WO2012023329A1 - Dispositif d'affichage - Google Patents

Dispositif d'affichage Download PDF

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Publication number
WO2012023329A1
WO2012023329A1 PCT/JP2011/062531 JP2011062531W WO2012023329A1 WO 2012023329 A1 WO2012023329 A1 WO 2012023329A1 JP 2011062531 W JP2011062531 W JP 2011062531W WO 2012023329 A1 WO2012023329 A1 WO 2012023329A1
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WIPO (PCT)
Prior art keywords
voltage
circuit
display device
scanning signal
signal line
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Application number
PCT/JP2011/062531
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English (en)
Japanese (ja)
Inventor
修司 西
業天　誠二郎
松田　英二
尚宏 山口
佐々木　修
卓也 鉢田
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シャープ株式会社
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Publication of WO2012023329A1 publication Critical patent/WO2012023329A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/56—Substrates having a particular shape, e.g. non-rectangular
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor

Definitions

  • the present invention relates to a display device, and more particularly, to a display device composed of a non-rectangular substrate.
  • FIG. 26 is a plan view showing a schematic configuration of a conventional general liquid crystal display device.
  • 27 is a cross-sectional view taken along the line CC of FIG.
  • this liquid crystal display device is commonly used to apply a voltage between an array substrate 7a, which is a glass substrate on which TFTs and pixel electrodes are formed in a matrix, and the pixel electrodes.
  • An IC Integrated
  • An IC 80 including various functional circuits for driving a counter substrate 7b which is a glass substrate on which electrodes are formed, and an array substrate 7a and the counter substrate 7b are bonded together via liquid crystal.
  • Circuit: integrated circuit 80 integrated circuit 80.
  • the IC 80 is mounted on the array substrate 7a by a COG (Chip On Glass) method.
  • COG Chip On Glass
  • a terminal portion 89 including a plurality of terminals for inputting / outputting various electric signals is formed on the array substrate 7a.
  • the liquid crystal panel is provided with a rectangular active area (effective display area) 90.
  • a scanning signal line (gate bus line), a video signal line (source bus line), and a pixel circuit unit Etc. are formed within the active area 90.
  • the shape of the whole glass substrate 7 is a rectangle.
  • a region indicated by reference numeral A1 indicates a region where the array substrate 7a and the counter substrate 7b are opposed to each other in the region where the array substrate 7a is formed.
  • a region indicated by reference numeral A2 indicates a region where the array substrate 7a and the counter substrate 7b are not opposed to each other in the region where the array substrate 7a is formed.
  • the area indicated by reference numeral A1 is referred to as “two-glass area”, and the area indicated by reference numeral A2 is referred to as “single-glass area”.
  • the two-glass region includes an active area (effective display region) 90 and a panel frame region 91 that is a region around the active area 90.
  • the single glass region is a region other than the double glass region (active area 90 and panel frame region 91), and is configured by a terminal portion region or a terminal portion region and a COG mounting region.
  • FIG. 28 is a block diagram showing a functional configuration of the IC 80 in the liquid crystal display device.
  • the IC 80 includes an input interface circuit 81 that receives various electric signals sent from the outside via a terminal unit 89, a display voltage generation circuit 82 that generates two or more voltages to be applied to the pixel electrodes, and various timing signals.
  • a video signal line drive circuit (source driver) 86 for driving lines and a memory circuit (frame memory or the like) 87 for holding image data are included.
  • Various signals generated by these circuits in the IC 80 are given to the two glass regions, and the liquid crystal panel is driven.
  • liquid crystal display device in which a part of the circuit in the IC 80 is monolithically formed in the panel frame region 91 of the two glass region.
  • a liquid crystal display device in which the scanning signal line driving circuit 85 and the video signal line driving circuit 86 are formed in the panel frame region 91 as shown in FIG. 29 is widely known.
  • FIG. 30 is a block diagram schematically showing a configuration in the active area 90 in the conventional general liquid crystal display device as described above.
  • the active area 90 includes a plurality (n) of scanning signal lines GL1 to GLn, a plurality (m) of video signal lines SL1 to SLm, and scanning signal lines GL1 to GLn.
  • a pixel circuit portion 900 provided corresponding to each intersection with the video signal lines SL1 to SLm and an auxiliary capacitance wiring CS for providing an auxiliary capacitance between the pixel electrodes in each pixel circuit portion 900 are formed. Yes.
  • the pixel circuit unit 900 is formed in a matrix in the active area 90.
  • Each pixel circuit unit 900 includes one pixel electrode and corresponds to one pixel.
  • FIG. 31 is a circuit diagram showing a configuration of the pixel circuit unit 900 in the liquid crystal display device.
  • Each pixel circuit unit 900 includes a TFT 901 having a gate electrode connected to the scanning signal line GL passing through the corresponding intersection and a source electrode connected to the video signal line SL passing through the intersection, and a drain electrode of the TFT 901.
  • a capacitor 904 and an auxiliary capacitor 905 formed by the pixel electrode 902 and the auxiliary capacitor line CS are included.
  • the liquid crystal capacitor 904 and the auxiliary capacitor 905 form a pixel capacitor CP.
  • the TFT 901 when the gate electrode of each TFT 901 receives an on-level scanning signal from the scanning signal line GL, the TFT 901 is turned on, and a voltage based on the video signal on the video signal line SL is passed through the TFT 901 to the pixel. The capacitor CP is charged. Thereafter, an off-level scanning signal is received from the scanning signal line GL, the TFT 901 is turned off, and the voltage charged in the pixel capacitor CP based on the video signal is held. The voltage held in the pixel capacitor CP is reflected in the display state of the pixel.
  • FIG. 32 is a signal waveform diagram for describing a driving method of the liquid crystal display device.
  • the scanning signal lines GL1 to GLn are sequentially supplied with on-level scanning signals row by row. Accordingly, the TFTs 901 in the pixel circuit unit 900 included in each row are sequentially turned on one row at a time.
  • Video signals corresponding to the display image are given to the video signal lines SL1 to SLm. As shown in FIG. 32, the video signal starts changing toward the target potential corresponding to the display image at the rising edge of the scanning signal.
  • FIG. 32 shows an example of waveforms of the video signal SL1 for the first column and the video signal SL2 for the second column when the target potentials in the first column and the second column are the same throughout the period shown in FIG. Is shown.
  • FIG. 33 is a plan view showing an example of a schematic configuration of a liquid crystal display device provided with such a display system. As shown in FIG. 33, in this liquid crystal display device, the glass substrate 8 is octagonal and the active area 90a is circular.
  • FIG. 34 is a block diagram schematically showing a configuration in the active area 90a in the liquid crystal display device. Unlike a liquid crystal display device having a rectangular active area 90 (see FIG. 30), the number of pixel circuit portions 900 increases in the row direction and the column direction from the end to the center.
  • one pixel circuit unit 900 is provided in the first and fifth columns, and three pixel circuit units 900 are provided in the second and fourth columns.
  • five pixel circuit units 900 are provided. Focusing on each row, one pixel circuit unit 900 is provided in the first row and the fifth row, and three pixel circuit units 900 are provided in the second row and the fourth row.
  • Five pixel circuit portions 900 are provided.
  • the number of scanning signal lines and the number of video signal lines are five, but in general, there are more scanning signal lines and video signal lines than five. Is provided.
  • there is a liquid crystal display device having a rectangular active area even when the glass substrate has a non-rectangular shape such as an octagon.
  • the configuration of the pixel circuit unit 900 is as shown in FIG. That is, also in the liquid crystal display device having the circular active area 90a, in each pixel circuit unit 900, when the gate electrode of each TFT 901 receives an on-level scanning signal from the scanning signal line GL, the TFT 901 is turned on. A voltage based on the video signal on the video signal line SL is charged to the pixel capacitor CP through the TFT 901. Thereafter, an off-level scanning signal is received from the scanning signal line GL, the TFT 901 is turned off, and the voltage charged in the pixel capacitor CP based on the video signal is held.
  • the voltage held in the pixel capacitor CP is reflected in the display state of the pixel.
  • monochrome binary display is performed.
  • the video signal line driving circuit 86 outputs a voltage for displaying the pixel in a white display state or a voltage for setting the pixel display state in a black display. Applied to the signal line SL.
  • Japanese Laid-Open Patent Publication No. 2008-216894 discloses a configuration including two scanning signal line driving circuits and two video signal line driving circuits for a liquid crystal display device having a circular or polygonal display region.
  • Japanese Laid-Open Patent Publication No. 2008-292959 and Japanese Special Publication No. 2005-528644 relate to a display device that includes a non-rectangular substrate and has a non-rectangular display area. A configuration with high density is disclosed.
  • 2006-276361 relates to a liquid crystal display device which is formed of a non-rectangular substrate and has an elliptical or circular display area, and a scanning signal line, a video signal line and a driver LSI are arranged at the outer edge of the display area
  • positioned in is disclosed.
  • Japanese Patent Publication No. 2008-502023, Japanese Unexamined Patent Publication No. 2009-122636, etc. also disclose inventions related to display devices composed of non-rectangular substrates.
  • Japanese Unexamined Patent Publication No. 2008-216894 Japanese Unexamined Patent Application Publication No. 2008-292995 Japanese Special Table 2005-528644 Japanese Unexamined Patent Publication No. 2006-276361 Japanese Special Table 2008-502023 Japanese Unexamined Patent Publication No. 2009-122636
  • the size of the single glass region must be increased as compared with the case where the rectangular glass substrate is adopted. There is. This will be described below.
  • an octagonal glass substrate as described above is to be adopted as a non-rectangular glass substrate, an octagonal glass substrate 8 is produced by cutting four corners of a rectangular glass substrate 7 of a predetermined size (see FIG. 35).
  • the size of the single glass region is constant, the non-rectangular glass substrate 8 is more single glass than the rectangular glass substrate 7. The size of the IC that can be mounted in the area is reduced.
  • the IC 80b mounted on the non-rectangular glass substrate 8 may not include all the circuits formed in the IC 80a when the rectangular glass substrate 7 is employed.
  • the shape of the IC in order to include all these circuits in the IC 80b, for example, the shape of the IC must be changed as shown in FIG. 37. Therefore, the size of the single glass region (the vertical size in FIG. 36) is increased. There is a need to. That is, the size of the single glass region when the non-rectangular glass substrate 8 is employed (L2 in FIG. 33) is the size of the single glass region when the rectangular glass substrate 7 is employed (L1 in FIG. 26). ).
  • an object of the present invention is to suppress the enlargement of a single glass region associated with the use of a non-rectangular substrate in a display device.
  • a first aspect of the present invention includes a two-glass region composed of an effective display region and a panel frame region that is a peripheral region of the effective display region, and a single-glass region that is an area outside the two-glass region.
  • a display device that includes a non-rectangular substrate and displays an image by changing a display state of pixels, A plurality of data signal lines; A plurality of scanning signal lines intersecting with the plurality of data signal lines; A data signal line driving circuit for applying a data signal corresponding to an image to be displayed to the plurality of data signal lines; A scanning signal line driving circuit for applying a scanning signal to the plurality of scanning signal lines; A plurality of pixel circuit portions each provided so as to correspond to an intersection of one of the plurality of data signal lines and one of the plurality of scanning signal lines; Each pixel circuit section A switch that is switched on / off based on a scanning signal applied to a scanning signal line passing through a corresponding intersection; A storage unit that takes in binary data based on the potential of a data signal applied to
  • a part of a panel driving circuit including a plurality of functional circuits for operating the pixel circuit portion is formed in the panel frame region.
  • the scanning signal line driving circuit and the data signal line driving circuit are formed in the panel frame region as a part of the panel driving circuit.
  • a timing signal generation circuit for generating a timing signal for controlling the operation timing of the scanning signal line drive circuit and the data signal line drive circuit is further formed in the panel frame region. It is characterized by that.
  • an input interface circuit for receiving an electric signal sent from the outside via a terminal portion provided in the one glass region is formed in the panel frame region.
  • a sixth aspect of the present invention is the fourth aspect of the present invention, As a part of the panel drive circuit, a display voltage generation circuit for generating the first voltage and the second voltage, and the first voltage or the second voltage of two electrodes included in the display element unit A counter voltage generation circuit for generating a voltage to be applied to an electrode arranged so as to face the electrode to which is applied is formed in the panel frame region.
  • a display voltage generation circuit for generating the first voltage and the second voltage, and the first voltage or the second voltage of two electrodes included in the display element unit
  • a counter voltage generation circuit for generating a voltage to be applied to an electrode arranged so as to face the electrode to which is applied is formed in the panel frame region.
  • All the functional circuits constituting the panel driving circuit are formed in the panel frame region.
  • the second aspect of the present invention it further comprises an external substrate provided with at least a part of a circuit excluding the functional circuit formed in the panel frame region among the plurality of functional circuits constituting the panel driving circuit.
  • the substrate has an octagonal shape.
  • the pixel circuit unit is provided with a storage unit capable of storing (holding) binary data (1-bit data). It is done.
  • the binary data is stored in the storage unit based on the potential of the data signal when the switch is on.
  • either the first voltage or the second voltage is selected by the voltage selection unit according to the value (logical value) of the binary data stored in the storage unit, and the voltage selected by the voltage selection unit is the pixel. It is reflected in the display state. In this way, the display state of the pixel is determined based on the data held in the storage unit in each pixel circuit unit.
  • a part of the panel drive circuit is formed in the panel frame region instead of in the single glass region IC. For this reason, it is possible to further reduce the size of the IC to be mounted on the single glass region. Thereby, in a display apparatus, expansion of the single glass area
  • substrate is suppressed effectively.
  • a part of the panel driving circuit and a storage unit are formed in the two-glass region (effective display region and panel frame region), the panel frame region and the outside are connected. Therefore, the number of terminals required for this can be reduced. Therefore, by adopting a non-rectangular substrate, a display device configured with a non-rectangular substrate can be realized without enlarging a single glass region even if there are restrictions on the shape and size of the terminal portion. Is possible.
  • the same effect as in the second aspect of the present invention is obtained.
  • the scanning signal lines are driven by a scanning signal line driving circuit in the panel frame region, and the data signal lines are driven by a data signal line driving circuit in the panel frame region. For this reason, it is possible to reduce the number of wirings between the IC and the panel frame region as compared with the configuration in which the scanning signal line driving circuit and the data signal line driving circuit are provided in the IC.
  • the size of the IC can be further reduced as compared with the third aspect of the present invention, and one sheet compared with the conventional display device configured with a rectangular substrate.
  • a display device formed of a non-rectangular substrate can be realized without enlarging the glass region.
  • the size of the IC can be further reduced as compared with the fourth aspect of the present invention, compared with the conventional display device configured with a rectangular substrate.
  • a display device composed of a non-rectangular substrate can be realized without enlarging the single glass region.
  • the size of the IC can be further reduced as compared with the fourth aspect of the present invention. It is possible to realize a display device configured with a non-rectangular substrate without enlarging a single glass region as compared with the conventional display device configured.
  • the size of the IC can be made smaller than that of the third aspect of the present invention, and it is configured by a rectangular substrate. Therefore, it is possible to realize a display device constituted by a non-rectangular substrate without enlarging the single glass region as compared with the conventional display device.
  • a display device constituted by a non-rectangular substrate in which the single glass region is significantly reduced. can be realized.
  • the size of the IC can be made smaller than that of the second aspect of the present invention, or it is not necessary to include the IC, and therefore, it is configured by a rectangular substrate.
  • a display device constituted by a non-rectangular substrate can be realized without enlarging a single glass region as compared with a conventional display device.
  • the same effect as that of the first aspect of the present invention can be obtained in the display device constituted by the octagonal substrate.
  • FIG. 3 is a circuit diagram illustrating a detailed configuration of a pixel circuit unit in the first embodiment. It is a signal waveform diagram for demonstrating the drive method in the said 1st Embodiment.
  • FIG. 6 is a signal waveform diagram for describing an operation when attention is paid to one pixel circuit unit in the first embodiment.
  • FIG. 9 is a diagram illustrating an internal state of the pixel circuit unit in a period T1 in FIG. 8 in the first embodiment.
  • FIG. 9 is a diagram showing an internal state of the pixel circuit unit in periods T2 and T4 in FIG. 8 in the first embodiment.
  • FIG. 9 is a diagram illustrating an internal state of the pixel circuit unit in a period T3 in FIG. 8 in the first embodiment.
  • FIG. 9 is a diagram illustrating an internal state of the pixel circuit unit at the end of a period T5 in FIG. 8 in the first embodiment.
  • FIG. 9 is a diagram illustrating an internal state of the pixel circuit unit in periods T6 and T8 in FIG.
  • FIG. 9 is a diagram illustrating an internal state of the pixel circuit unit in periods T7 and T9 in FIG. 8 in the first embodiment. It is a figure for demonstrating the effect in the said 1st Embodiment. It is a top view which shows schematic structure of the liquid crystal display device in the 1st modification of the said 1st Embodiment.
  • FIG. 10 is a block diagram showing a functional configuration of an IC in a first modification of the first embodiment. It is a top view which shows schematic structure of the liquid crystal display device in the 2nd modification of the said 1st Embodiment.
  • FIG. 2 is a plan view showing a schematic configuration of the liquid crystal display device according to the first embodiment of the present invention.
  • 3 is a cross-sectional view taken along line BB in FIG.
  • a common electrode for applying a voltage is formed between the array substrate 5a, which is a glass substrate on which TFTs, pixel electrodes, and the like are formed, and the pixel electrodes.
  • the counter substrate 5b which is a glass substrate, and the IC 20 including various functional circuits for driving a liquid crystal panel manufactured by bonding the array substrate 5a and the counter substrate 5b through liquid crystal. Yes.
  • the IC 20 is mounted on a single glass region on the array substrate 5a by the COG method. Further, on the array substrate 5a, a terminal portion 30 composed of a plurality of terminals for inputting / outputting various electric signals is formed. In the present embodiment, the entire shape of the glass substrate 5 is an octagon.
  • the liquid crystal panel is provided with a substantially circular active area (effective display area) 10 within which scanning signal lines (first scanning signal line and second scanning signal line), data A signal line, a pixel circuit portion, and the like are formed.
  • FIG. 4 is a block diagram schematically showing a configuration in the active area 10 in the present embodiment.
  • the active area 10 includes first scanning signal lines GL1 to GL5, second scanning signal lines GLB1 to GLB5, data signal lines DL1 to DL5, and a high-level DC power supply potential VDD.
  • a wiring and a plurality of pixel circuit portions 100 are formed. The plurality of pixel circuit units 100 are arranged so that an image having the shape of the active area 10 (circular in this embodiment) is displayed.
  • the number of pixel circuit units 100 increases from the end to the center in both the row direction and the column direction. ing. Specifically, focusing on each column, one pixel circuit unit 100 is provided in the first and fifth columns, and three pixel circuit units 100 are provided in the second and fourth columns. Five pixel circuit units 100 are provided in the third column. Focusing on each row, one pixel circuit unit 100 is provided in the first and fifth rows, three pixel circuit units 100 are provided in the second and fourth rows, and the third row has Five pixel circuit units 100 are provided. Each pixel circuit unit 100 has a built-in memory circuit capable of holding 1-bit data, as will be described later. In FIG. 4, for convenience of explanation, the number of first scanning signal lines, the number of second scanning signal lines, and the number of data signal lines are five, but the number is not limited.
  • FIG. 5 is a block diagram showing a functional configuration of the IC 20 in the present embodiment.
  • the IC 20 has an input interface circuit 21 that receives various electric signals sent from the outside via the terminal unit 30, and a display that generates voltages (white display voltage VLA and black display voltage VLB) to be applied to the pixel electrodes.
  • a voltage generation circuit 22 a timing generator (timing signal generation circuit) 23 for generating various timing signals, a counter voltage generation circuit 24 for generating a voltage (counter voltage) to be applied to the common electrode, and a scanning signal line ( A scanning signal line driving circuit 25 for driving the first scanning signal line and the second scanning signal line) and a data signal line driving circuit 26 for driving the data signal line are included.
  • a scanning signal line driving circuit 25 for driving the first scanning signal line and the second scanning signal line
  • a data signal line driving circuit 26 for driving the data signal line are included.
  • the IC 20 in this embodiment is not provided with a memory circuit for holding image data.
  • a panel drive circuit for operating the pixel circuit unit 100 with the display voltage generation circuit 22, the timing generator 23, the counter voltage generation circuit 24, the scanning signal line drive circuit 25, and the data signal line drive circuit 26. Is realized.
  • Various signals generated by the panel drive circuit in the IC 20 are given to the active area 10 via the panel frame region 11, and the liquid crystal panel is driven.
  • FIG. 1 is a diagram for explaining a schematic configuration of a pixel circuit unit 100 in the present embodiment.
  • a plurality of pixel circuit units 100 are arranged in the active area 10 provided in the two-glass region of the octagonal glass substrate 5.
  • Each pixel circuit unit 100 corresponds to one pixel, and includes a switch 110, a memory circuit 120, a liquid crystal driving voltage application circuit 130, and a display element unit 140, as shown in the lower part of FIG.
  • the display element unit 140 includes a liquid crystal, a pixel electrode that sandwiches the liquid crystal, and a common electrode.
  • a memory unit is realized by the memory circuit 120
  • a voltage selection unit is realized by the liquid crystal driving voltage application circuit 130.
  • the on / off state of the switch 110 is controlled based on scanning signals applied to the first scanning signal line GL and the second scanning signal line GLB.
  • binary data (1-bit data) is supplied to the memory circuit 120 based on the potential of the data signal applied to the data signal line DL when the switch 110 is on.
  • the memory circuit 120 holds the binary data received when the switch 110 is on until the switch 110 is turned on again.
  • the binary data held in the memory circuit 120 is given to the liquid crystal drive voltage application circuit 130.
  • the liquid crystal drive voltage application circuit 130 applies a display voltage (either the white display voltage VLA or the black display voltage VLB) to the liquid crystal based on the binary data value (logical value) given from the memory circuit 120. To do.
  • the scanning signal applied to the first scanning signal line GL is also referred to as “first scanning signal”, and the scanning signal applied to the second scanning signal line GLB is referred to as “second scanning signal”.
  • FIG. 6 is a circuit diagram showing a detailed configuration of the pixel circuit unit 100 in the present embodiment.
  • the switch 110 is a CMOS switch including a p-channel transistor 111 and an n-channel transistor 112.
  • the switch 110 is also referred to as “first switch SW1”.
  • the first switch SW1 is configured to be turned on when the first scanning signal GL is at a high level and the second scanning signal GLB is at a low level. That is, in the present embodiment, from the viewpoint of turning on the first switch SW1, the high level is the on level for the first scanning signal GL, and the low level is the on level for the second scanning signal GLB. It is.
  • the first switch SW1 is also configured so that the data signal line DL and the node 191 are electrically connected when in the on state. As described above, when the first scanning signal GL is at a high level and the second scanning signal GLB is at a low level, the first switch SW1 is turned on, and the potential of the data signal DL is applied to the node 191.
  • a configuration in which the first switch SW1 is realized only by an n-channel transistor or a configuration in which the first switch SW1 is realized only by a p-channel transistor may be employed. In this case, only one scanning signal line is provided for each row, and the on / off state of the first switch SW1 is controlled by one scanning signal applied to the scanning signal line.
  • the memory circuit 120 includes a CMOS switch SW2 including an n-channel transistor 121 and a p-channel transistor 122, a CMOS inverter INV1 including a p-channel transistor 123 and an n-channel transistor 124, a p-channel transistor 125, and an n-channel transistor 125.
  • a CMOS inverter INV2 including a channel type transistor 126 is included.
  • the CMOS switch SW2 is also referred to as “second switch SW2”
  • the CMOS inverter INV1 is also referred to as “first inverter INV1”
  • the CMOS inverter INV2 is also referred to as “second inverter INV2.” .
  • the second switch SW2 is configured to be turned on when the second scanning signal GLB is at a high level and the first scanning signal GL is at a low level.
  • the second switch SW2 is also configured so that the node 191 and the node 193 are electrically connected when in the ON state.
  • the input terminal is connected to the node 191 and the output terminal is connected to the node 192.
  • the second inverter INV2 the input terminal is connected to the node 192 and the output terminal is connected to the node 193.
  • the memory circuit 120 holds a value (logical value) based on the potential applied to the node 191 when the first switch SW1 is in the on state until the first switch SW1 is next in the on state. To work.
  • the liquid crystal drive voltage application circuit 130 includes a CMOS switch SW3 including a p-channel transistor 131 and an n-channel transistor 132, and a CMOS switch SW4 including a p-channel transistor 133 and an n-channel transistor 134. .
  • the CMOS switch SW3 is also referred to as “third switch SW3”, and the CMOS switch SW4 is also referred to as “fourth switch SW4”.
  • the third switch SW3 is configured to be turned on when the potential of the node 191 is at a high level and the potential of the node 192 is at a low level.
  • the third switch SW3 is also configured so that the white display voltage VLA is applied to the pixel electrode 142 when in the on state.
  • the fourth switch SW4 is configured to be turned on when the potential of the node 191 is low and the potential of the node 192 is high.
  • the fourth switch SW4 is also configured so that the black display voltage VLB is applied to the pixel electrode 142 when in the on state.
  • the display element unit 140 includes a liquid crystal 141, a pixel electrode 142, and a common electrode 143. A voltage is applied to the liquid crystal based on the voltage applied to the pixel electrode 142 and the voltage applied to the common electrode 143, and the liquid crystal applied voltage is reflected in the display state of the pixel.
  • the period during which the first scanning signal is set to the high level and the period during which the second scanning signal is set to the low level are the same.
  • the scanning signal line corresponding to each row is selected.
  • the first switch SW1 in the pixel circuit unit 100 included in each row is sequentially turned on row by row.
  • the data signals DL1 to DL5 the potential changes between a predetermined high level potential and a predetermined low level potential according to the display image.
  • the data signals DL1 to DL5 are output at the target potential (predetermined high level) at the rising edge of the scanning signal corresponding to the certain row. Or a predetermined low level potential).
  • the pixel circuit unit 100 included in each column binary data is held in the memory circuit 120 based on the potential of the data signal at the time when the first scanning signal falls and the second scanning signal rises. Then, a voltage is applied to the liquid crystal based on the value (logical value) of the binary data.
  • FIG. 7 shows an example of a waveform when the pixels in the first row are displayed in white and the pixels in the second and third rows are displayed in black during the period shown in FIG.
  • the scanning signal lines are sequentially selected row by row, but are not necessarily selected sequentially, and the pixel circuit unit 100 corresponding to the selected scanning signal line is not necessarily used. If the data signal to be written (stored) in (the memory circuit 120) is supplied to the data signal line, the scanning signal lines may be selected in any order.
  • FIG. 9 shows an internal state of the pixel circuit unit 100 in the period T1 of FIG.
  • FIG. 10 shows an internal state of the pixel circuit unit 100 in the periods T2 and T4 of FIG.
  • FIG. 11 shows an internal state of the pixel circuit unit 100 in the period T3 in FIG.
  • FIG. 12 shows the internal state of the pixel circuit unit 100 at the end of the period T5 in FIG.
  • FIG. 13 shows an internal state of the pixel circuit unit 100 in the periods T6 and T8 of FIG.
  • FIG. 14 shows an internal state of the pixel circuit unit 100 in the periods T7 and T9 in FIG.
  • the first switch SW1 is turned on and the second switch SW2 is turned off. Since the data signal DL is at a low level during this period, the potential of the node 191 is also at a low level. As a result, the potential of the node 192 becomes high level, and further, the potential of the node 193 becomes low level. In this way, binary data based on the data signal DL is stored in the memory circuit 120. Further, based on the potentials of the nodes 191 and 192, the third switch SW3 is turned off and the fourth switch SW4 is turned on.
  • the black display voltage VLB is applied to the pixel electrode 142.
  • the black display voltage VLB is at a low level.
  • the potential OUT of the pixel electrode 142 is at a low level.
  • the counter voltage VCOM is at a high level.
  • the display state of the pixels is black.
  • the first switch SW1 is turned off and the second switch SW2 is turned on.
  • the node 192 is connected to the output terminal of the first inverter INV1
  • the potential of the node 192 is reliably maintained at a high level during this period.
  • the node 193 is connected to the output terminal of the second inverter INV2
  • the potential of the node 193 is reliably maintained at a low level during this period. In this way, the potential of the node 193 is reliably maintained at a low level, and the second switch SW2 is turned on, so that the potential of the node 191 is also maintained at a low level.
  • the third switch SW3 is turned off and the fourth switch SW4 is turned on.
  • the black display voltage VLB is applied to the pixel electrode 142.
  • the potential OUT of the pixel electrode 142 is at a low level.
  • the counter voltage VCOM is at a high level.
  • the display state of the pixels is black. Note that in the period T4, the pixel display state is black display by the same operation as in the period T2.
  • the potentials of the nodes 191 and 193 are maintained at a low level and the potential of the node 192 is maintained at a high level by the same operation as in the period T2. For this reason, as in the periods T1 and T2, the third switch SW3 is turned off and the fourth switch SW4 is turned on. As a result, the black display voltage VLB is applied to the pixel electrode 142. Incidentally, during this period, the black display voltage VLB is at a high level. Accordingly, the potential OUT of the pixel electrode 142 is at a high level. During this period, the counter voltage VCOM is at a low level. Thus, in the period T3, the pixel display state is black.
  • the first switch SW1 is turned on and the second switch SW2 is turned off.
  • the data signal DL changes from the low level to the high level.
  • the potential of the node 191 also changes from the low level to the high level.
  • the potential of the node 192 becomes low level, and the potential of the node 193 becomes high level. In this way, the value (logical value) of the binary data stored in the memory circuit 120 is rewritten based on the data signal DL.
  • the third switch SW3 changes from the off state to the on state
  • the fourth switch SW4 changes from the on state to the off state.
  • the white display voltage VLA is applied to the pixel electrode 142.
  • the white display voltage VLA is at a low level.
  • the potential OUT of the pixel electrode 142 is at a low level.
  • the counter voltage VCOM is at a low level.
  • the display state of the pixels is white display.
  • the first switch SW1 is turned off and the second switch SW2 is turned on.
  • the potential of the node 192 is reliably maintained at a low level, and the potential of the node 193 is reliably maintained at a high level. Since the potential of the node 193 is reliably maintained at a high level and the second switch SW2 is turned on, the potential of the node 191 is also maintained at a high level.
  • the third switch SW3 is turned on and the fourth switch SW4 is turned off. As a result, the white display voltage VLA is applied to the pixel electrode 142.
  • the white display voltage VLA is at a low level
  • the potential OUT of the pixel electrode 142 is at a low level.
  • the counter voltage VCOM is at a low level.
  • the display state of the pixels is white display. Note that also in the period T8, the display state of the pixels is white by the same operation as in the period T6.
  • the potentials of the nodes 191 and 193 are maintained at a high level and the potential of the node 192 is maintained at a low level by the same operation as in the period T6.
  • the third switch SW3 is turned on and the fourth switch SW4 is turned off.
  • the white display voltage VLA is applied to the pixel electrode 142.
  • the white display voltage VLA is at a high level.
  • the potential OUT of the pixel electrode 142 is at a high level.
  • the counter voltage VCOM is at a high level.
  • the display state of the pixels is white display. Note that in the period T9 as well, the display state of the pixels is white by the same operation as in the period T7.
  • each pixel circuit unit 100 binary data is stored in the memory circuit 120 based on the potential of the data signal when the first switch SW1 is in the ON state.
  • a display voltage (either the white display voltage VLA or the black display voltage VLB) to be applied to the pixel electrode 142 is selected based on the binary data stored in the memory circuit 120. Is done. Then, based on the display voltage applied to the pixel electrode 142 and the voltage (counter voltage) applied to the common electrode 143, the display state of the pixel is white display or black display.
  • the pixel circuit unit 100 is provided with the memory circuit 120 that can hold binary data (1 bit data). Yes.
  • the binary data is held in the memory circuit 120 based on the potential of the data signal DL when the first switch SW1 is in the ON state.
  • either the white display voltage VLA or the black display voltage VLB is applied to the pixel electrode 142 in accordance with the value (logical value) of the binary data held in the memory circuit 120.
  • the display state of the pixel is determined based on the data held in the memory circuit 120 in each pixel circuit unit 100.
  • the size of the single glass region in this embodiment is larger than the size of the single glass region (L2 in FIG. 33) when an octagonal glass substrate is conventionally employed. It becomes small and becomes the same size as the size of one glass region (L1 in FIG. 26) when a rectangular glass substrate is adopted.
  • the panel drive circuit for operating the pixel circuit unit 100 is all formed in the IC 20 in the single glass region (see FIGS. 2 and 5). It is not limited.
  • the scanning signal line drive circuit 25 and the data signal line drive circuit 26 of the panel drive circuit may be formed monolithically in the panel frame region 11 on the array substrate instead of in the IC 20 ( First modification).
  • the IC 20 mounted on the single glass region on the array substrate does not include the scanning signal line driving circuit 25 and the data signal line driving circuit 26 as shown in FIG.
  • a voltage generation circuit 22, a timing generator 23, and a counter voltage generation circuit 24 are included.
  • the size of the IC 20 can be further reduced as compared with the first embodiment, and the enlargement of the single glass region accompanying the adoption of the octagonal substrate is effectively suppressed. .
  • the number of wirings between the IC 20 and the panel frame region 11 can be reduced as compared with the configuration in which the scanning signal line driving circuit 25 and the data signal line driving circuit 26 are provided in the IC 20. Further, since the memory circuit 120 is formed in the active area 10 and the scanning signal line driving circuit 25 and the data signal line driving circuit 26 are formed in the panel frame region 11, the panel frame region 11 is connected to the outside. It is possible to reduce the number of terminals required for the operation. For this reason, a liquid crystal display device composed of a non-rectangular glass substrate can be used without enlarging a single glass area even if the shape and size of the terminal portion are limited by adopting a non-rectangular glass substrate. It can be realized.
  • a display voltage generating circuit 22, a timing generator 23, and a counter voltage generating circuit 24 are provided on a panel frame on the array substrate.
  • the region 11 may be formed monolithically (second modification).
  • the timing generator 23 is formed in the panel frame region 11, or in addition to the scanning signal line driving circuit 25 and the data signal line driving circuit 26.
  • the input interface circuit 21 and the timing generator 23, in addition to the scanning signal line driving circuit 25 and the data signal line driving circuit 26, Can be configured to be formed in the panel frame region 11. With the configuration as described above, the size of the IC 20 can be further reduced.
  • the panel drive circuit formed in the panel frame region 11 is typically formed along the outer edge of the active area 10, as shown in FIGS. Thereby, the empty area in the panel frame area 11 is used without waste, and the single glass area can be effectively reduced.
  • the overall shape of the glass substrate 5 constituting the liquid crystal display device is an octagon (see FIG. 2), but the present invention is not limited to this. If the shape of the entire glass substrate 5 is non-rectangular, the present invention can be applied.
  • the present invention can also be applied to a liquid crystal display device or the like. Thereby, in the liquid crystal display device comprised not only in an octagon but a non-rectangular board
  • the shape of the active area 10 which is a region where an image is displayed, is circular (see FIG. 2), but the present invention is not limited to this. If the overall shape of the glass substrate 5 constituting the liquid crystal display device is a non-rectangular shape such as an octagon, the present invention can be applied to a liquid crystal display device in which the active area 10a has a rectangular shape as shown in FIG. Can be applied.
  • FIG. 22 is a plan view showing a schematic configuration of a liquid crystal display device according to the second embodiment of the present invention.
  • the input interface circuit 21, the display voltage generation circuit 22, the timing generator 23, the counter voltage generation circuit 24, the scanning signal line drive circuit 25, and the data signal line drive circuit. 26 is formed monolithically not in the IC 20 but in the panel frame region 11 on the array substrate. That is, all the circuits in the IC 20 shown in FIG. 5 are provided in the panel frame region 11 on the array substrate. For this reason, in this embodiment, the IC 20 is not provided in the single glass region on the array substrate.
  • Other configurations (the configuration in the active area 10, the configuration of the pixel circuit unit 100, etc.) and the driving method are the same as those in the first embodiment, and a description thereof will be omitted.
  • the liquid crystal display device configured with the octagonal glass substrate 5 an IC that has been conventionally mounted on a single glass region on the array substrate becomes unnecessary. For this reason, compared with the conventional structure, it becomes possible to make the size of one glass area
  • the overall shape of the glass substrate 5 is not limited to an octagon.
  • FIG. 23 is a plan view showing a schematic configuration of a liquid crystal display device according to a first modification of the second embodiment.
  • the scanning signal line drive circuit 25 and the data signal line drive circuit 26 are provided in the panel frame region 11, and the display voltage generation circuit 22, the timing generator 23, and the counter voltage generation circuit 24 are provided outside.
  • the display voltage generation circuit 22, the timing generator 23, and the counter voltage generation circuit 24 are formed on the flexible circuit board 6 attached in the vicinity of a single glass region.
  • the timing signal for controlling the operation of the scanning signal line drive circuit 25 and the data signal line drive circuit 26 the display voltage to be applied to the pixel electrode 142, and the counter voltage to be applied to the common electrode are externally connected to the terminal.
  • FIG. 24 is a plan view showing a schematic configuration of a liquid crystal display device according to a second modification of the second embodiment.
  • a display voltage generation circuit 22, a timing generator 23, a counter voltage generation circuit 24, a scanning signal line drive circuit 25, and a data signal line drive circuit 26 are provided in the panel frame region 11, and the display voltage generation circuit 22 is provided.
  • a signal for controlling the operation of the timing generator 23 and the counter voltage generation circuit 24 is given to the panel frame region 11 from the outside via the terminal portion 30.
  • the IC 20 since the IC 20 is not provided in the single glass region, it is possible to realize a liquid crystal display device including a non-rectangular glass substrate in which the single glass region is significantly reduced. Become.
  • a panel drive circuit as much as possible in an area (area indicated by reference numeral 40 in FIG. 25) between the (virtual) minimum rectangular area including the entire active area 10 and the outer edge of the active area 10,
  • the empty area in the panel frame area 11 is used without waste, and the single glass area can be effectively reduced.
  • liquid crystal display device has been described as an example, but the present invention is not limited to this.
  • the present invention can also be applied to other display devices such as organic EL (Electro Luminescence).

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

La présente invention se rapporte à un dispositif d'affichage caractérisé en ce qu'une extension d'une zone de cadre due à l'utilisation d'un substrat non rectangulaire est supprimée. Un dispositif d'affichage comprend un substrat de verre non rectangulaire (5), et chacune des unités de circuits de pixels (100) du dispositif d'affichage comprend : un commutateur (110) qui exécute une commutation entre l'état passant et l'état bloqué sur la base de signaux de balayage appliqués sur des lignes de signaux de balayage (une première ligne de signaux de balayage (GL) et une seconde ligne de signaux de balayage (GLB)) qui passent par des points de croisement correspondants; un circuit de mémoire (120) qui recherche et qui stocke des données binaires sur la base des potentiels de signaux de données appliqués sur une ligne de signaux de données (DL) quand le commutateur (110) est activé; un circuit d'application de tension de fonctionnement à cristaux liquides (130) qui sélectionne une tension pour l'affichage, cette tension correspondant à la valeur des données binaires stockées dans le circuit de mémoire (120); et un module d'éléments d'affichage (140) adapté pour amener la tension sélectionnée par le circuit d'application de tension de fonctionnement à cristaux liquides (130) à être reflétée dans l'état d'affichage du pixel.
PCT/JP2011/062531 2010-08-19 2011-05-31 Dispositif d'affichage WO2012023329A1 (fr)

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TWI782679B (zh) * 2021-08-27 2022-11-01 晶達光電股份有限公司 特殊尺寸液晶面板的製法及特殊尺寸液晶面板

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CN104599655A (zh) * 2015-02-05 2015-05-06 深圳市华星光电技术有限公司 非矩形显示器及其驱动方法
CN104599655B (zh) * 2015-02-05 2017-05-10 深圳市华星光电技术有限公司 非矩形显示器及其驱动方法
TWI782679B (zh) * 2021-08-27 2022-11-01 晶達光電股份有限公司 特殊尺寸液晶面板的製法及特殊尺寸液晶面板

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