WO2012015085A1 - Carte de circuit imprimé et son procédé de fabrication - Google Patents

Carte de circuit imprimé et son procédé de fabrication Download PDF

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Publication number
WO2012015085A1
WO2012015085A1 PCT/KR2010/005011 KR2010005011W WO2012015085A1 WO 2012015085 A1 WO2012015085 A1 WO 2012015085A1 KR 2010005011 W KR2010005011 W KR 2010005011W WO 2012015085 A1 WO2012015085 A1 WO 2012015085A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit pattern
chip
insulating layer
layer
metal layer
Prior art date
Application number
PCT/KR2010/005011
Other languages
English (en)
Inventor
Min Seok Lee
Hye Sun Yoon
Original Assignee
Lg Innotek Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lg Innotek Co., Ltd. filed Critical Lg Innotek Co., Ltd.
Priority to PCT/KR2010/005011 priority Critical patent/WO2012015085A1/fr
Publication of WO2012015085A1 publication Critical patent/WO2012015085A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Definitions

  • the disclosure relates to a printed circuit board and a method of manufacturing the same.
  • PCB printed circuit board
  • the manufacturing process for the embedded PCB includes a step of connecting a chip embedded in a PCB with circuit patterns of the PCB.
  • the chip may include a bare chip and a wafer level package (WLP) chip which is obtained by forming a redistribution layer on the bare chip.
  • WLP wafer level package
  • a connection terminal connected to an external circuit or an element is too small and a pitch between connection terminals is very narrow so connection to the circuit patterns is very difficult.
  • a redistribution layer is additionally formed on the bare chip.
  • the manufacturing process is complicated and product yield is lowered, so that the manufacturing cost is increased.
  • the embodiment provides a PCB having a novel structure and a method of manufacturing such a PCB.
  • the embodiment provides a PCB capable of connecting a chip to a circuit pattern through a simple process and a method of manufacturing such a PCB.
  • a method of manufacturing a printed circuit board includes preparing a carrier formed with a first metal layer; attaching a chip onto the first metal layer; connecting a connection terminal of the chip to the first metal layer by using a wire; forming a first insulating layer on the first metal layer and the chip and forming a second metal layer on the first insulating layer; removing the carrier; and forming a first circuit pattern including a connection circuit pattern and a second circuit pattern by selectively removing the first and second metal layers.
  • a printed circuit board includes a first circuit pattern including a connection circuit pattern; a chip on the first circuit pattern; a wire connecting a connection terminal of the chip to the connection circuit pattern; a first insulating layer on the chip and the first circuit pattern such that the chip is surrounded by the first insulating layer; and a second circuit pattern on the first insulating layer.
  • the embodiment can provide a PCB having a novel structure and a method of manufacturing such a PCB.
  • the embodiment can provide a PCB capable of effectively connecting a chip to a circuit pattern through a simple way by using a wire even if a connection terminal of the chip has a small size and the circuit pattern has a narrow pitch, and a method of manufacturing such a PCB.
  • FIGS. 1 to 11 are sectional views showing a printed circuit board and a method of manufacturing the same according to the embodiment.
  • a layer (or film), a region, a pattern, or a structure is referred to as being on or under another substrate, another layer (or film), another region, another pad, or another pattern, it can be directly or indirectly on the other substrate, layer (or film), region, pad, or pattern, or one or more intervening layers may also be present. Further, on or under of each layer is determined based on the drawing.
  • each layer shown in the drawings can be exaggerated, omitted or schematically drawn for the purpose of convenience or clarity.
  • the size of elements does not utterly reflect an actual size.
  • FIGS. 1 to 11 are sectional views showing a PCB and a method of manufacturing the same according to the embodiment.
  • the PCB shown in FIG. 11 is manufactured through the method according to the embodiment.
  • the PCB includes a first circuit pattern 80 having a connection circuit pattern 85, a chip 40 attached onto the first circuit pattern 80, a wire 25 connecting a connection terminal 41 of the chip 40 to the connection circuit pattern 85, a first insulating layer 50 formed on the chip 40 and the first circuit pattern 80, a second circuit pattern 81 formed on the first insulating layer 50, a first conductive via 71 formed through the first insulating layer 50 to electrically connect the first circuit pattern 80 to the second circuit pattern 81, a second insulating layer 90 formed on the first and second circuit patterns 80 and 81 and the first conductive via 71, a third circuit pattern 120 formed on the second insulating layer 90, and a second conductive via 110 for connecting the first and second circuit patterns 80 and 81 to a third circuit pattern 120.
  • connection circuit pattern 85 may include material identical to that of the first circuit pattern 80.
  • a position determination hole 21 can be formed in the first circuit pattern 80.
  • the position determination hole 21 may serve as a fiducial mark to detect an alignment position of the chip 40 and a bonding position of the wire 25.
  • the chip 40 may be aligned on an adhesive layer 30.
  • the adhesive layer 30 makes contact with at least one of the first circuit pattern 80 and the second insulating layer 90.
  • the adhesive layer 30 may have an area larger than that of the chip 40.
  • the chip 40 includes the connection terminal 41.
  • the connection terminal 41 is connected to the first circuit pattern 80 through the wire 25.
  • the wire 25 may have a curved shape or a parabolic shape. That is, the wire 25 is convex upward and connected to the first circuit pattern 80 while being spaced apart from the adhesive layer 30 on which the chip 40 is aligned.
  • the wire 25 extends by passing through the first insulating layer 50.
  • the wire 25 has a first part located above the chip 40, a second part located below the chip 40, and a third part located at a lateral side of the chip 40.
  • the wire 25 is surrounded by the first insulating layer 50.
  • At least a part of the second insulating layer 90 makes contact with the adhesive layer 30 and a part of the second insulating layer 90 is aligned in the first conductive via 71.
  • a carrier 10 formed thereon with a first metal layer 20 is prepared.
  • the first metal layer 20 includes at least one of Cu, Sn, Al, Ni, Au, or Ag.
  • the first metal layer 20 may be formed over the whole area of the carrier 10.
  • the first metal layer 20 can be formed on the carrier 10 through the sputtering, the plating or the stacking process.
  • the carrier 10 may include metal or resin.
  • the carrier 10 is formed by using material different from that of the first metal layer 20.
  • the first metal layer 20 is selectively removed to form the position determination hole 21.
  • the position determination hole 21 serves as a yardstick for determining the position of the first circuit pattern 80 and the connection circuit pattern 85 to be formed on the PCB and the attachment position of the chip 40. Details thereof will be described later with reference to the corresponding process.
  • a photoresist pattern (not shown) is formed on the first metal layer 20 and the first metal layer 20 is selectively etched by using the photoresist pattern as a mask.
  • the position determination hole 21 can be formed at an outer peripheral portion of the first metal layer 20.
  • the position determination hole 21 can be formed in the first circuit pattern 80 to be formed later.
  • the position determination hole 21 can be formed at the outer peripheral portion of the first circuit pattern 80.
  • the position of the position determination hole 21 can be variously changed according to the applications.
  • the adhesive layer 30 is formed on the first metal layer 20, and the chip 40 is attached onto the adhesive layer 30.
  • the adhesive layer 30 may have an area larger than that of the chip 40.
  • FIG. 3 shows the adhesive layer 30 locally formed on the first metal layer 20, the adhesive layer 30 may be formed over the whole area of the first metal layer 20, if necessary.
  • the adhesive layer 30 can be formed by using material having adhesive property, such as epoxy resin or phenol resin.
  • the chip 40 may include a bare chip, a WLP chip obtained by forming a redistribution layer on the bare chip, or various chips connectable to the external device through the wire bonding scheme.
  • the chip 40 includes the connection terminal 41 that electrically connects the chip 40 to the external circuit or the element.
  • the attachment position of the chip 40 may be determined based on the position determination hole 21.
  • the adhesive layer 30 is formed on the attachment position of the chip 40, which is previously designed based on the position determination hole 21, and then the chip 40 is attached onto the adhesive layer 30.
  • connection terminal 41 of the chip 40 is connected to the first metal layer 20 through the wire 25.
  • the bonding position of the wire 25 on the first metal layer 20 may be determined based on the position determination hole 21.
  • connection circuit pattern 85 The first meal layer 20 connected to the wire 25 is referred to as the connection circuit pattern 85, which will be described later in detail.
  • a conductive via is formed in an insulating layer between a chip and a circuit pattern in order to connect the chip to the circuit pattern.
  • the chip 40 may include the bare chip, the WLP chip obtained by forming the redistribution layer on the bare chip, or various chips connectable to the external device through the wire bonding scheme. If the bare chip serves as the chip 40, the pitch between the connection terminals 41 of the chip 40 is too narrow (about 150 ⁇ m or less) and the width of the connection terminal 41 is too small (about 100 ⁇ m or less), so it is difficult to form the conductive via to connect the chip 40 to the external circuit or the element.
  • the redistribution layer is formed on the bare chip through an additional process to connect the chip to the external circuit or the element although it may degrade the efficiency.
  • connection terminal 41 of the chip 40 is electrically connected to the first metal layer 20 through the wire 25, so the electric connection can be easily achieved even if the bare chip is used for the chip 40. That is, the additional processes to form the redistribution layer and the conductive via may be omitted, so that the manufacturing process is simplified and the efficiency is improved.
  • the wire 25 can be manufactured by using metal including at least one of Cu, Sn, Al, Ni, Au, or Ag.
  • the B-stage insulating layer 50 is prepared on the first metal layer 20 and the chip 40, and the second metal layer 60 is prepared on the first insulating layer 50.
  • the first insulating layer 50 surrounds the top surface of the first metal layer 20 and the chip 40 and includes a first layer 51 having the height corresponding to the height of the chip 40 and a second layer 52 covering the top surface of the chip 40 and the first layer 51.
  • a plurality of first and second layers 51 and 52 can be provided.
  • the first insulating layer 50 is formed by using material having adhesive and insulating properties.
  • the first insulating layer may include resin material, such as epoxy resin or phenol resin.
  • the first insulating layer 50 may include a prepreg, a polyimide film, or an ABF film. That is, the first insulating layer 50 may include various materials according to applications.
  • the second metal layer 60 can be formed by using metal including at least one of Cu, Sn, Al, Ni, Au, or Ag.
  • the B-stage first insulating layer 50 and the second metal layer 60 prepared on the B-stage first insulating layer 50 are pressed against the first metal layer 20 and the chip 40 by applying heat and pressure. Then, the first insulating layer 50 is cured by applying heat and ultraviolet ray to the first insulating layer 50.
  • the wire 25 can be formed on the chip 40 and the first metal layer 20 without being damaged when the second metal layer and the first insulating layer 50 are pressed against the first metal layer 20 and the chip 40.
  • the wire 25 extends by passing through the first insulating layer 50 to connect the connection terminal 41 of the chip 40 to the first metal layer 20.
  • the carrier 10 is removed, and the first conductive via 71 is formed through the first and second metal layers 20 and 60 and the first insulating layer 50.
  • the first conductive via 71 is formed to electrically activate the circuit patterns to be formed on the top surface and the bottom surface of the PCB.
  • a via hole 70 is formed through the first and second metal layers 20 and 60 and the first insulating layer 50 by a laser drilling process and a plating process is performed with respect to the via hole 70.
  • an electroless plating process is performed to form a seed layer and then an electroplating process is performed.
  • the first and second metal layers 20 and 60 are selectively removed to form the first and second circuit patterns 80 and 81.
  • the first circuit pattern 80 includes the connection circuit pattern 85.
  • a photoresist pattern (not shown) is formed on the first and second metal layers 20 and 60, and then the first and second metal layers 20 and 60 are etched by using the photoresist pattern as a mask.
  • the position of the first and second circuit patterns 80 and 81 and the connection circuit pattern 85 can be determined based on the position determination hole 21.
  • connection circuit pattern 85 is formed on a region to which the wire 25 is connected, so that the connection circuit pattern 85 is electrically connected to the connection terminal 41 of the chip 40 through the wire 25.
  • first and second circuit patterns 80 and 81 and the connection circuit pattern 85 are simultaneously formed by selectively removing the first metal layer 20, the manufacturing process can be simplified.
  • the second insulating layer 90 is formed on the first and second circuit patterns 80 and 81 and the first conductive via 71 and a third metal layer 100 is formed on the second insulating layer 90.
  • the second insulating layer 90 is formed by using material identical to that of the first insulating layer 50, so detailed description thereof will be omitted in order to avoid redundancy.
  • the B-stage second insulating layer 90 is prepared on the first and second circuit patterns 80 and 81 and the third metal layer 100 is prepared on the second insulating layer 90. Then, the B-stage second insulating layer 90 and the third metal layer 100 are pressed against the first and second circuit patterns 80 and 81 and the conductive via 71 by applying heat and pressure. After that, the second insulating layer 90 is cured.
  • the third metal layer 100 may include material identical to that of the first and second metal layers 20 and 60.
  • the second conductive via 110 can be formed to electrically connect the first and second circuit patterns 80 and 81 to the third metal layer 100.
  • a via hole (not shown) is formed through the second insulating layer 90 and a plating process is performed with respect to the via hole.
  • the third metal layer 100 is selectively removed to form the third circuit pattern 120.
  • the process for forming the third circuit pattern 120 is similar to the process for forming the first and second circuit patterns 80 and 81, so detailed description thereof will be omitted in order to avoid redundancy.
  • the process for forming the first and second insulating layers 50 and 90 among the first to third circuit patterns 80, 81 and 120 may be repeated or omitted depending on the circuits to be formed on the PCB.
  • this process can be variously modified within the scope of the embodiment.
  • solder mask and a solder ball can be formed on the third circuit pattern 120 to connect the PCB with other circuits, elements or substrates.
  • the embodiments are applicable to the PCB and the method of manufacturing the same.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L'invention concerne une carte de circuit imprimé et son procédé de fabrication. Le procédé consiste à préparer un support formé d'une première couche métallique ; à fixer une puce sur la première couche métallique ; à connecter une borne de connexion de la puce sur la première couche métallique en utilisant un fil ; à former une première couche isolante sur la première couche métallique et la puce et à former une seconde couche métallique sur la première couche isolante ; à retirer le support ; et à former un premier motif de circuit comprenant un motif de circuit de connexion et un deuxième motif de circuit en retirant sélectivement les première et seconde couches métalliques.
PCT/KR2010/005011 2010-07-30 2010-07-30 Carte de circuit imprimé et son procédé de fabrication WO2012015085A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/KR2010/005011 WO2012015085A1 (fr) 2010-07-30 2010-07-30 Carte de circuit imprimé et son procédé de fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/KR2010/005011 WO2012015085A1 (fr) 2010-07-30 2010-07-30 Carte de circuit imprimé et son procédé de fabrication

Publications (1)

Publication Number Publication Date
WO2012015085A1 true WO2012015085A1 (fr) 2012-02-02

Family

ID=45530276

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2010/005011 WO2012015085A1 (fr) 2010-07-30 2010-07-30 Carte de circuit imprimé et son procédé de fabrication

Country Status (1)

Country Link
WO (1) WO2012015085A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100722624B1 (ko) * 2005-09-12 2007-05-28 삼성전기주식회사 칩 내장형 인쇄회로기판의 제조방법
KR20080035974A (ko) * 2006-10-20 2008-04-24 신꼬오덴기 고교 가부시키가이샤 전자 부품이 탑재된 다층 배선 기판 및 그 제조 방법
US20080174978A1 (en) * 2006-12-19 2008-07-24 Shinko Electric Industries Co., Ltd. Electronic component built-in substrate and method of manufacturing electronic component built-in substrate
KR100874924B1 (ko) * 2007-05-15 2008-12-19 삼성전자주식회사 칩 삽입형 매개 기판 및 이를 이용한 반도체 패키지

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100722624B1 (ko) * 2005-09-12 2007-05-28 삼성전기주식회사 칩 내장형 인쇄회로기판의 제조방법
KR20080035974A (ko) * 2006-10-20 2008-04-24 신꼬오덴기 고교 가부시키가이샤 전자 부품이 탑재된 다층 배선 기판 및 그 제조 방법
US20080174978A1 (en) * 2006-12-19 2008-07-24 Shinko Electric Industries Co., Ltd. Electronic component built-in substrate and method of manufacturing electronic component built-in substrate
KR100874924B1 (ko) * 2007-05-15 2008-12-19 삼성전자주식회사 칩 삽입형 매개 기판 및 이를 이용한 반도체 패키지

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