WO2012013051A1 - 时钟与数据恢复系统、相位调整方法及鉴相器 - Google Patents
时钟与数据恢复系统、相位调整方法及鉴相器 Download PDFInfo
- Publication number
- WO2012013051A1 WO2012013051A1 PCT/CN2011/072954 CN2011072954W WO2012013051A1 WO 2012013051 A1 WO2012013051 A1 WO 2012013051A1 CN 2011072954 W CN2011072954 W CN 2011072954W WO 2012013051 A1 WO2012013051 A1 WO 2012013051A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- bias current
- current source
- amplitude
- gate
- source circuit
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000011084 recovery Methods 0.000 title claims abstract description 18
- 230000008878 coupling Effects 0.000 claims abstract description 10
- 238000010168 coupling process Methods 0.000 claims abstract description 10
- 238000005859 coupling reaction Methods 0.000 claims abstract description 10
- 238000003491 array Methods 0.000 claims description 7
- 230000003247 decreasing effect Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 12
- 230000003111 delayed effect Effects 0.000 description 4
- 230000003044 adaptive effect Effects 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000033228 biological regulation Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Definitions
- the present invention relates to a clock and data recovery system, and more particularly to a clock and data recovery system, a phase adjustment method, and a phase detector.
- FIG. 1 is a block diagram of a typical clock and data recovery system including a phase detector 102, a frequency discriminator 104, a charge pump (optional) & filter 103, and a Voltage Control Oscillator (VCO) 105.
- the discriminator 104 compares the reference clock with the clock signal output from the frequency divider 106, and the generated error signal generates a control voltage through the charge pump (optional) & filter 103 to oscillate the frequency of the VCO 105 at a preset operating frequency range.
- the phase detector 102 compares the phase relationship between the input data and the VCO feedback clock.
- the data recovery retimerlOl recovers the data to eliminate jitter and distortion generated during data transmission.
- the effective edge of the clock should be in the middle of the data to achieve optimal noise immunity, but in actual circuit implementation, the current source mismatch between the charge pump, the mismatch of each module in the loop, and the process Non-ideal conditions such as deviations, when the loop is locked, the effective edge of the clock is often not in the middle of the data.
- the loop is locked, there is a fixed phase difference between the clock and the data, which increases the bit error rate.
- the cause of the phase difference can be equivalent to the presence of a bias current source I in the charge pump (optional) & filter 103. Ffset , as shown in Figure 1.
- the bias current source With the change of the error signal and the reference signal of the phase detector 102, the bias current source equivalently charges (or discharges) the filter, causing the control voltage of the VCO to rise (or fall), thereby causing the clock generated by the VCO to deviate most. Good sample.
- One common implementation method is to implement phase adjustment in the phase detector. as shown in picture 2.
- FIG. 2 is a block diagram of a typical phase detector with a Hogge structure with phase adjustment.
- the output is Q1
- the data is passed through the delay unit D1 203 and the phase adjusting unit 204 to obtain the delayed data (DATA_D), and the two signals of Q1 and DATA-D are sent to the exclusive OR.
- the gate XOR205 generates an error signal (ERROR) representing the phase relationship between the clock and the data.
- the Q1 signal is delayed by half a clock cycle through the latch 202 to obtain a signal Q2, and the Q1 and Q2 signals are sent to the XOR 206 gate to generate and data.
- the associated reference signal (REFERENCE) is flipped, and the error signal and reference signal are fed to the charge pump (optional) & filter 103 to obtain the control voltage of the VCO, thereby controlling the clock phase of the VCO output.
- the phase adjustment unit 204 can directly delay the inversion effective edge of the data, thereby adjusting the pulse width of the ERROR signal to achieve the adjustment of the VCO output clock phase.
- Another method of phase adjustment is proposed by U.S. Patent No. 10,159,788.
- the fixed phase difference due to locking can be equivalent to the presence of a bias current source I in the filter 108 of FIG.
- FIG. 3 is a block diagram of the patent in which the circuitry of the frequency discrimination section is omitted.
- the patent incorporates a current source array 300 and a current sink array 350 at the VCO control voltage, i.e., filter 108, and the equivalent bias current is selected by PHASE-ADJUST[1:0] and PHASE-ADJUST[3:2].
- the ff set is offset by the current generated by the current source array 300 and/or the current sink array 350 to achieve an optimum sample.
- a disadvantage of this patent is that the switch array controlled by PHASE-ADJUST[1:0] and PHASE-ADJUST[3:2] is directly connected to the VCO control line, and the noise generated by the switch and/or externally introduced is very It is easy to couple into the VCO key module through parasitic capacitance or substrate, so that the output clock phase of the VCO is jittered.
- phase adjustment is discontinuous and, depending on the number of switch arrays used, this aspect makes the best sense in the true sense not easy to achieve, on the other hand the accuracy requirements of phase modulation The higher the value, the more pin resources you need to occupy.
- the present invention provides a phase detector comprising: a flip flop, a delay unit, a latch connected to the flip flop, and a first XOR gate connected to the flip flop and the delay unit a second exclusive OR gate connected to the flip flop and the latch, the phase detector is configured to receive the data signal and the clock signal, output an error signal representing a phase relationship between the clock signal and the data signal, and Referring to the data signal inversion related reference signal, wherein the first XOR gate is a current mode logic XOR gate, the first XOR gate comprises a first bias current source circuit, the first bias current source The circuit outputs an adjustable first bias current for controlling an amplitude of the error signal output by the first exclusive OR gate; and/or, the second exclusive OR gate is a current mode a logical exclusive OR gate, the second exclusive
- the first bias current source circuit or the second bias current source circuit includes: a plurality of parallel current sources, and a plurality of switch units, each of which controls a current source to be connected or disconnected.
- the phase detector further includes a continuous phase adjustment unit, wherein the first bias current source circuit and the second bias current source circuit are connected by a continuous phase adjustment unit, wherein: the first bias current source circuit comprises : 1 discrete current source 110, N discrete current sources 111 to I1N, 110 to I1N constitute N + 1 parallel branches of the first bias current source circuit; the second bias current source includes: 1 Discrete current sources 120, N discrete current sources 121 to I2N, 120 to I2N constitute N+1 parallel branches of the second bias current source circuit; and coupling switch arrays K1 to KN, wherein Kj controls discrete Current sources Ilj and I2j, and when Ilj is connected, I2j is disconnected, and when Ilj is disconnected, I2j is connected; the continuous phase adjusting unit is configured to output variable two-way current controlled by differential voltage
- the first XOR gate is configured to control the amplitude of the error signal as follows: when the clock signal leads or lags the data signal for a time T.
- the first bias current output by the first bias current source circuit is adjusted as follows to reduce or increase the amplitude of the error signal:
- Afc RR Rl *T/2 fc RR Rl *Toff set
- IE RR the first bias current before adjustment
- AI ERR is between the adjusted first bias current and the first bias current before adjustment
- T is the period of the clock signal
- R1 is the load resistance of the first bias current source circuit
- the second XOR gate is configured to control the amplitude of the reference signal as follows: When the clock signal leads or lags the data signal for a time T. In the case of ffset , the reference signal amplitude is kept unchanged; or the first XOR gate is set to control the amplitude of the error signal as follows: When the clock signal leads or lags the data signal for a time T. When ffset , keep the error signal amplitude unchanged;
- the second XOR gate is configured to control the amplitude of the reference signal as follows: When the clock signal leads or lags the data signal for a time T. In ffset , the second bias current output by the second bias current source circuit is adjusted as follows to increase or decrease the amplitude of the reference signal:
- AIREFR2*T/2 fc RR Rl *Toff set where AIREF is the difference between the adjusted second bias current and the second bias current before adjustment, and R2 is the second bias current source circuit Load resistance. among them,
- the first XOR gate is configured to control the amplitude of the error signal as follows: When the clock signal leads or lags the data signal for a time T. For ffset , adjust the first bias current as follows to reduce or increase the amplitude of the error signal:
- the second XOR gate is configured to control the amplitude of the reference signal as follows: When the clock signal leads or lags the data signal for a time T.
- the present invention also provides a clock and data recovery system, the clock and data recovery system comprising the above phase detector.
- the present invention also provides a phase adjustment method, which is applied to the above clock and data recovery system, the method comprising: adjusting a first XOR gate when a clock signal leads or lags behind a data signal A bias current and/or a second bias current of the second exclusive OR gate.
- the step of adjusting the first bias current of the first exclusive OR gate and/or the second bias current of the second exclusive OR gate comprises: when the clock signal leads or lags behind the data signal is T .
- AIREFR2*T/2 fc RR Rl *Toff set
- the AIREF is a difference between the adjusted second bias current and the second bias current before the adjustment
- R2 is a load resistance of the second bias current source circuit.
- the step of adjusting the first bias current of the first exclusive OR gate and/or the second bias current of the second exclusive OR gate comprises: when the clock signal leads or lags the data signal for a time T.
- adjust the first bias current as follows to reduce or increase the amplitude of the error signal:
- phase adjustment method and the phase detector provided by the invention can prevent the introduction of noise coupling to the VCO module, and at the same time can achieve the best sense in the true sense.
- FIG. 1 is a block diagram of a typical clock and data recovery system
- Figure 2 is a block diagram of a typical phase detector with a phase adjustment function of Hogge structure
- Figure 3 is a phase used in U.S. Patent No. 7,386,085 B2 Block diagram of the adjustment method
- Figure 4 is a block diagram of the phase adjustment scheme proposed by the present invention, the phase adjustment is in the XOR gate XOR
- Figure 5 is a typical current mode logic XOR gate XOR
- Figure 6 is an ideal case of the best data sample clock phase relationship and error signal ERROR and reference signal REFERENCE output waveform
- Figure 7 is the clock In the case of leading data, the phase adjustment method proposed by the present invention
- FIG. 1 is a block diagram of a typical clock and data recovery system
- Figure 2 is a block diagram of a typical phase detector with a phase adjustment function of Hogge structure
- Figure 3 is a phase used in U.S. Patent No. 7,386,085 B2 Block diagram of the adjustment method
- FIG. 8 is another phase adjustment method proposed by the present invention in the case of clock leading data
- FIG. 9 is the case when the clock is backward corresponding to FIG.
- Figure 10 is a diagram showing the clock backward data corresponding to Figure 8
- Figure 11 is a block diagram of a discrete phase adjustment circuit based on the switch array proposed by the invention for the above two adjustment methods
- Figure 12 is a diagram of the present invention A circuit block diagram that allows continuous phase adjustment.
- the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the features in the embodiments and the embodiments in the present application may be arbitrarily combined with each other.
- the core idea of the invention is to: implement a phase adjustment function in the XOR gate of the phase detector. Since the phase adjustment is far from the VCO critical modules, there is no noise coupling.
- the invention provides a phase detector, as shown in FIG. Mainly based on the Hogge phase detector, the phase adjustment function is implemented at two XOR gates XOR404 and XOR405. As shown in FIG.
- the phase detector of the present invention includes: a flip flop 401, a delay unit 402, a latch 403, a first XOR gate 404, and a second XOR gate 405, a first XOR gate 404 and / or the second XOR gate 405 is a current mode logic XOR gate, wherein: the data is outputted as Q1 after being triggered by the falling edge of the D flip-flop 401, and the data is passed through the delay unit 402 to obtain the delayed data DATA_D, Q1 and DATA—D two signals are sent to the XOR gate XOR404 to generate an error signal ERROR representing the phase relationship between the clock and the data.
- the & filter 103 obtains the control voltage of the VCO, thereby controlling the clock phase of the VCO output.
- the first XOR gate 404 includes a first bias current source circuit that outputs an adjustable first bias current for controlling the amplitude of the error signal output by the first XOR gate 404;
- the diOR gate 405 includes a second bias current source circuit that outputs an adjustable second bias current for controlling the amplitude of the reference signal output by the second exclusive OR gate.
- the first XOR gate 404 and the second XOR gate 405 may both be current mode logic XOR gates including adjustable bias current source circuits, or only one of them may be a current including an adjustable bias current source circuit.
- the modulo XOR gate, and the other is an XOR gate that includes a bias current source circuit with no current regulation. See Figure 5 for the results of the current mode logic XOR gate.
- Figure 5 is an XOR500 of the current mode logic whose output is an exclusive OR of the two input signals.
- the amplitude of the output signal (single-ended) is determined by the product of the current source I bias 501 and the resistor R502. Since the phase adjustment acts in the phase detector and away from the VCO module, noise can be introduced into the VCO.
- the working principle of the circuit shown in Figure 5 is as follows: When the input terminals A and B are both high or low at the same time, there are always M5, M2 or M6, M3 turned on at the same time, so that the output terminal OUT is pulled low, and there is always Ml When it is not the same as M5 and M6 and M4, the output terminals OUT-N are pulled high, so the circuit output is low when the inputs are the same.
- a and B are different, for example, A is high and B is low.
- FIG. 6 shows the phase relationship of the clock data in the ideal case and the output waveform of the error signal ERROR and the reference signal REFERENCE, where I ERR and IRE F are the bias generated by the bias current source that generates the error signal and the reference signal, respectively. Current, at this time There is no fixed phase difference in H. As shown by 701 in Fig. 7, the time at which the clock leads the data is T.
- Ffset Equivalent deviation current source I. Ffset produces a bias voltage of one in one cycle.
- FFSRT * (T/2-T. ffsrt )
- the present invention proposes two methods to eliminate this part of the deviation in the XOR gate.
- the first method is shown as 702 in Figure 7,
- the amplitude of the error signal can be reduced while ensuring that the amplitude of the reference signal is constant, so that the following relationship is satisfied, that is, the first bias current is adjusted to satisfy the following formula:
- Ioffset*(T/2- Toffset) can be equivalent by IR * T ff Set , and the average value of the voltage of this part can also be equivalent by adjusting the amplitude of the error signal to produce AI R * T/2, which is in the entire phase-locked loop.
- CONT When the loop is locked, it should be a constant, denoted by CONT.
- AI err represents the current after the phase adjustment of the first bias current source circuit minus the current before the phase adjustment, that is, the current change amount before and after the phase adjustment, R1 represents the load current of the first bias current source circuit, and I is adjusted.
- the first first bias current, T is the period of the clock signal.
- the second method is as shown by 802 in Fig. 8.
- the magnitude of the error signal reduction and the increase of the reference signal may be different, and it is necessary to ensure that the average value of the voltage amplitude reduced by the error signal minus the average of the increased voltage amplitude of the reference signal is equal to I.
- the error signal amplitude can be kept constant, the amplitude of the reference signal is reduced, and the second bias current is adjusted as follows:
- AI is the difference between the adjusted second bias current and the second bias current before adjustment
- R2 is the load resistance of the second bias current source circuit.
- the error signal and the reference signal are respectively increased and decreased by the same amplitude, so that the following relationship is satisfied:
- the bias current source circuit in the first XOR gate and/or the second XOR gate can be implemented based on the following circuit: the bias current source circuit includes a plurality of parallel current sources, and a plurality of switching units, each The switching unit controls the connection or disconnection of a current source.
- the bias current source circuit includes a plurality of parallel current sources, and a plurality of switching units, each The switching unit controls the connection or disconnection of a current source.
- FIG. 11 is a block diagram of a discrete array phase adjustment circuit based on a switch array proposed by the invention for the above two adjustment methods.
- the method can also be used to generate a bias current source IRE F of the exclusive OR gate XOR of the reference signal, or a bias current source 1 ⁇ 23 ⁇ 4 that is applied to the exclusive OR gate XOR of the error signal and an exclusive OR gate generating the reference signal.
- the bias current source IRE F of XOR achieves the purpose of phase adjustment. The higher the accuracy required for this configuration, the more switch arrays are required.
- the present invention further proposes another implementation of the first bias current source circuit and the second bias current source circuit as follows:
- the first bias current source circuit includes: one discrete current source 110, N discrete current sources 111 to I1N, 110 to I1N constituting N + 1 parallel branches of the first bias current source circuit;
- the two bias current sources include: 1 discrete current source 120, N discrete current sources 121 to
- I2N, 120 to I2N constitute N+1 parallel branches of the second bias current source circuit; coupling switch arrays to KN, wherein Kj controls discrete current sources Ilj and I2j, and when Ilj is connected, I2j is off When I1 is off, I2j is connected; the first bias current source circuit and the second bias current source circuit are connected by a continuous phase adjustment unit for outputting a differential voltage control Variable two currents, one of which acts as a parallel branch of the first bias current source circuit and the other serves as a parallel branch of the second bias current source circuit, the two currents being equal in magnitude In the opposite direction, controlling the first bias current and the second bias current to produce equal and opposite changes in direction.
- Kj controls discrete current sources Ilj and I2j, and when Ilj is connected, I2j is off When I1 is off, I2j is connected
- the first bias current source circuit and the second bias current source circuit are connected by a continuous phase adjustment unit for outputting a differential voltage control Variable two currents, one of which acts as
- FIG. 12 mainly includes a coupling switch array 1201 and a continuous phase adjustment unit 1202.
- the coupling switch array 1201 controls the discrete current sources 1 and 1 in I ERR and IRE F.
- the specific operation requires that the coupled switch array 1201 can control the discrete current in the right IRE F when the discrete current source 1 01 in the left side is turned on.
- Source 01 is turned off, otherwise, when the discrete current source 01 in the left I ERR is off, the dispersion in the right IRE F
- the current source 01 is turned on.
- the same requirements apply to discrete current sources on both sides. This can ensure that the second phase adjustment method proposed by the present invention is satisfied, and the phase is coarsely adjusted.
- the continuous phase adjustment unit 1202 is a push-pull current current mirror.
- VI and V2 differentially control the current Iss flowing through the two branches, and then generate two differential current outputs on I OT — adj and I ref — ac3 ⁇ 4 through the two outer mirror tubes, so that I ER] ⁇ o
- the IRE F achieves an equal and inverse change in current so that the amplitude of the error signal and the reference signal can change in the opposite direction. Since the following two pairs of mirror tubes are matched, the following relation (6) is satisfied, and I OT — adj and I REF — adj are controlled by the differential control voltages VI and V2, and successive and equal amounts are generated in opposite directions.
- the change so that the above circuit can achieve continuous adjustment of the error signal and the reference signal amplitude, thereby ensuring that the second phase adjustment method proposed by the present invention is satisfied, and the phase is continuously adjusted.
- the differential control voltages VI and V2 can be generated by an external circuit or by an internal adaptive method of the chip, for example, by detecting and judging the bit error rate of the recovered data to generate a pair of differential control voltages.
- the continuous phase adjustment unit shown in FIG. 12 is only an example, and other circuits capable of generating two currents of equal magnitude and opposite directions are also protected by the present invention.
- the tunable bias current source circuit shown in FIG. 11 and FIG. 12 is only an example, which is not limited by the present invention.
- Other configurations of tunable bias current sources are also within the scope of the present invention. ⁇ With the adjustment method shown in Figure 12, the number of required switch arrays can be effectively reduced, and the true best sample can be achieved. It is also possible to make the best adaptive sample, ie clock and data recovery.
- the system generates a control signal by judging the bit error rate of the recovered data, and adjusts VI and V2 in FIG. 12 to achieve the best sample, so that the bit error rate of the recovered data reaches the required range.
- the present invention also provides a clock and data recovery system including the phase detector of the present invention.
- the present invention also provides a phase adjustment method, which is applied to the clock and data recovery system of the present invention, the method comprising: The first bias current of the first exclusive OR gate and/or the second bias current of the second exclusive OR gate are adjusted when the clock signal leads or lags behind the data signal.
- the adjusting step includes: when the clock signal leads or lags behind the data signal
- AJERURI * ⁇ /2 fc RR Rl *Toff set
- IE RR is the first bias current before adjustment
- AI ERR is the difference between the adjusted first bias current and the first bias current before adjustment Value
- T is the period of the clock signal
- R1 is the load resistance of the first bias current source circuit
- AIREFR2*T/2 fc RR Rl *Toff Set
- AIREF is the difference between the adjusted second bias current and the second bias current before adjustment
- R2 is the second bias current source circuit Load resistance.
- the adjusting step includes: when the clock signal leads or lags behind the data signal T. For ffset , adjust the first bias current as follows to reduce or increase the amplitude of the error signal:
- phase adjustment method and phase detector proposed by the present invention can prevent noise coupling from being introduced to the VCO module, and at the same time, can achieve the best sense in the true sense.
- the present invention can effectively reduce the number of switch arrays required, so that the bit error rate of the recovered data reaches the required range.
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/575,595 US8624630B2 (en) | 2010-07-26 | 2011-04-18 | Clock and data recovery system, phase adjusting method, and phasedetector |
EP11811753.0A EP2515441B1 (en) | 2010-07-26 | 2011-04-18 | Clock and data recovery system, phase adjusting method, and phasedetector |
AU2011285387A AU2011285387B2 (en) | 2010-07-26 | 2011-04-18 | Clock and data recovery system, phase adjusting method, and phasedetector |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201010245170.8 | 2010-07-26 | ||
CN2010102451708A CN102347765B (zh) | 2010-07-26 | 2010-07-26 | 一种时钟与数据恢复系统、相位调整方法及鉴相器 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2012013051A1 true WO2012013051A1 (zh) | 2012-02-02 |
Family
ID=45529393
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2011/072954 WO2012013051A1 (zh) | 2010-07-26 | 2011-04-18 | 时钟与数据恢复系统、相位调整方法及鉴相器 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8624630B2 (zh) |
EP (1) | EP2515441B1 (zh) |
CN (1) | CN102347765B (zh) |
AU (1) | AU2011285387B2 (zh) |
WO (1) | WO2012013051A1 (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102843130B (zh) * | 2012-09-18 | 2014-10-08 | 北京大学 | 基于cml逻辑的相位检测器 |
JP2014140100A (ja) * | 2013-01-21 | 2014-07-31 | Sony Corp | 位相比較回路及びデータ受信装置 |
CN103762945A (zh) * | 2014-01-20 | 2014-04-30 | 复旦大学 | 一种相位可调的精确正交压控振荡器电路 |
US9288019B2 (en) * | 2014-07-03 | 2016-03-15 | Intel Corporation | Apparatuses, methods, and systems for jitter equalization and phase error detection |
CN108390675B (zh) * | 2018-05-15 | 2024-02-02 | 南京德睿智芯电子科技有限公司 | 一种异或门鉴相器 |
CN111371430B (zh) * | 2018-12-26 | 2023-08-08 | 深圳市中兴微电子技术有限公司 | 一种矢量合成移相器和矢量合成移相方法 |
CN113364278B (zh) * | 2020-04-08 | 2022-07-12 | 澜起电子科技(昆山)有限公司 | 开关电流源电路及开关电流源快速建立方法 |
CN112202426B (zh) * | 2020-10-16 | 2024-05-10 | 中国科学院微电子研究所 | 应用于多速率的高线性度的相位插值器及采用其的电路 |
CN116027842B (zh) * | 2023-03-24 | 2023-06-23 | 长鑫存储技术有限公司 | 功率控制电路、存储器及电子设备 |
CN117254894B (zh) * | 2023-11-20 | 2024-03-19 | 西安智多晶微电子有限公司 | 自动校正高速串行信号采样相位的方法、装置及电子设备 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5799048A (en) * | 1996-04-17 | 1998-08-25 | Sun Microsystems, Inc. | Phase detector for clock synchronization and recovery |
US20020021470A1 (en) * | 2000-02-17 | 2002-02-21 | Jafar Savoj | Linear half-rate phase detector and clock and data recovery circuit |
US6509801B1 (en) * | 2001-06-29 | 2003-01-21 | Sierra Monolithics, Inc. | Multi-gigabit-per-sec clock recovery apparatus and method for optical communications |
US7386085B2 (en) | 2002-05-30 | 2008-06-10 | Broadcom Corporation | Method and apparatus for high speed signal recovery |
US7409027B1 (en) * | 2002-06-14 | 2008-08-05 | Cypress Semiconductor Corp. | System and method for recovering a clock using a reduced rate linear phase detector and voltage controlled oscillator |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6538475B1 (en) * | 2000-03-15 | 2003-03-25 | Intel Corporation | Phase detector |
US7092474B2 (en) * | 2001-09-18 | 2006-08-15 | Broadcom Corporation | Linear phase detector for high-speed clock and data recovery |
US7286625B2 (en) * | 2003-02-07 | 2007-10-23 | The Regents Of The University Of California | High-speed clock and data recovery circuit |
US7057418B1 (en) * | 2004-04-13 | 2006-06-06 | Applied Micro Circuits Corporation | High speed linear half-rate phase detector |
JP4081067B2 (ja) * | 2004-11-08 | 2008-04-23 | 富士通株式会社 | 位相比較器及び位相比較器を有する半導体装置 |
US7609798B2 (en) * | 2004-12-29 | 2009-10-27 | Silicon Laboratories Inc. | Calibrating a phase detector and analog-to-digital converter offset and gain |
US7173494B2 (en) * | 2005-01-20 | 2007-02-06 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method and system for operating a feedback system for a voltage controlled oscillator that involves correcting for offset related to the feedback system |
CN101572527A (zh) * | 2009-06-09 | 2009-11-04 | 中国人民解放军国防科学技术大学 | 高速高抖动容限的随机数据线性鉴相器电路 |
-
2010
- 2010-07-26 CN CN2010102451708A patent/CN102347765B/zh active Active
-
2011
- 2011-04-18 WO PCT/CN2011/072954 patent/WO2012013051A1/zh active Application Filing
- 2011-04-18 EP EP11811753.0A patent/EP2515441B1/en active Active
- 2011-04-18 US US13/575,595 patent/US8624630B2/en active Active
- 2011-04-18 AU AU2011285387A patent/AU2011285387B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5799048A (en) * | 1996-04-17 | 1998-08-25 | Sun Microsystems, Inc. | Phase detector for clock synchronization and recovery |
US20020021470A1 (en) * | 2000-02-17 | 2002-02-21 | Jafar Savoj | Linear half-rate phase detector and clock and data recovery circuit |
US6509801B1 (en) * | 2001-06-29 | 2003-01-21 | Sierra Monolithics, Inc. | Multi-gigabit-per-sec clock recovery apparatus and method for optical communications |
US7386085B2 (en) | 2002-05-30 | 2008-06-10 | Broadcom Corporation | Method and apparatus for high speed signal recovery |
US7409027B1 (en) * | 2002-06-14 | 2008-08-05 | Cypress Semiconductor Corp. | System and method for recovering a clock using a reduced rate linear phase detector and voltage controlled oscillator |
Non-Patent Citations (1)
Title |
---|
See also references of EP2515441A4 |
Also Published As
Publication number | Publication date |
---|---|
AU2011285387B2 (en) | 2013-09-19 |
US20120293226A1 (en) | 2012-11-22 |
US8624630B2 (en) | 2014-01-07 |
CN102347765A (zh) | 2012-02-08 |
CN102347765B (zh) | 2013-10-16 |
EP2515441B1 (en) | 2017-11-22 |
AU2011285387A1 (en) | 2012-08-23 |
EP2515441A1 (en) | 2012-10-24 |
EP2515441A4 (en) | 2015-01-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2012013051A1 (zh) | 时钟与数据恢复系统、相位调整方法及鉴相器 | |
US7276977B2 (en) | Circuits and methods for reducing static phase offset using commutating phase detectors | |
US7542533B2 (en) | Apparatus and method for calibrating the frequency of a clock and data recovery circuit | |
US6181210B1 (en) | Low offset and low glitch energy charge pump for PLL-based timing recovery systems | |
US7719329B1 (en) | Phase-locked loop fast lock circuit and method | |
US20030091139A1 (en) | System and method for adjusting phase offsets | |
US7312666B2 (en) | PLL circuit configured to distribute its loop control signal to CDR circuits | |
US5734301A (en) | Dual phase-locked loop clock synthesizer | |
US8019022B2 (en) | Jitter-tolerance-enhanced CDR using a GDCO-based phase detector | |
US10277389B2 (en) | Phase detectors for clock and data recovery | |
CN104539285A (zh) | 数据时钟恢复电路 | |
US10623005B2 (en) | PLL circuit and CDR apparatus | |
US7285995B2 (en) | Charge pump | |
US20080191787A1 (en) | Charge Pump with Cascode Biasing | |
CN101414784A (zh) | 电荷泵 | |
US7386085B2 (en) | Method and apparatus for high speed signal recovery | |
US6275097B1 (en) | Differential charge pump with low voltage common mode feedback circuit | |
KR100317679B1 (ko) | 링 발진기 출력파형간의 위상 오프셋을 보정하기 위한자기 보정회로 및 방법 | |
US6721380B2 (en) | Fully differential CMOS phase-locked loop | |
US7283602B2 (en) | Half-rate clock and data recovery circuit | |
US7409027B1 (en) | System and method for recovering a clock using a reduced rate linear phase detector and voltage controlled oscillator | |
US11115030B2 (en) | Method and circuits for charge pump devices of phase-locked loops | |
US20040170245A1 (en) | Fully differential CMOS phase-locked loop | |
US20040257162A1 (en) | Charge pump for eliminating dc mismatches at common drian nodes | |
US20020172299A1 (en) | Data width corrector |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 11811753 Country of ref document: EP Kind code of ref document: A1 |
|
REEP | Request for entry into the european phase |
Ref document number: 2011811753 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2011811753 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13575595 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2011285387 Country of ref document: AU |
|
ENP | Entry into the national phase |
Ref document number: 2011285387 Country of ref document: AU Date of ref document: 20110418 Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |