WO2012012994A1 - Dispositif à architecture de gestion de châssis unifiée et son procédé de commande de gestion - Google Patents

Dispositif à architecture de gestion de châssis unifiée et son procédé de commande de gestion Download PDF

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Publication number
WO2012012994A1
WO2012012994A1 PCT/CN2010/079281 CN2010079281W WO2012012994A1 WO 2012012994 A1 WO2012012994 A1 WO 2012012994A1 CN 2010079281 W CN2010079281 W CN 2010079281W WO 2012012994 A1 WO2012012994 A1 WO 2012012994A1
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Prior art keywords
logic unit
board
cpu
control board
main control
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PCT/CN2010/079281
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English (en)
Chinese (zh)
Inventor
乔海龙
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中兴通讯股份有限公司
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Publication of WO2012012994A1 publication Critical patent/WO2012012994A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip

Definitions

  • the present invention relates to the field of communications, and in particular to a device having a unified machine 11 management architecture and a management control method thereof.
  • BACKGROUND OF THE INVENTION Machine-framed devices are widely used in the fields of electronics, communications, and machinery.
  • the device is based on a chassis, and multiple slots are provided on the chassis for each unit device in the device, such as a service ticket.
  • the board access, the unified machine 411 management architecture is managed by the machine 411 management board, and the service board in the machine 411 is managed.
  • the subrack management board is the main control board, and the other managed service boards are controlled. board. In the current communication equipment, the services running on the controlled board usually need to be managed and maintained.
  • the CPU runs software to process and communicate with the main control board.
  • the main control board and the controlled board communicate according to a certain protocol, as shown in Figure 1.
  • the initialization and configuration of the control board is completed by the CPU of the board.
  • the control boards of different services have different CPU requirements. For example, boards such as E1 or Ethernet have low requirements for CPU management and maintenance.
  • the above design mainly has two points to consider: First, the design is simple, there are a large number of general circuit support; Second, the efficiency is high, the development and debugging of each controlled board can be carried out in parallel. However, in today's increasingly fierce competition in the communications industry, cost will be an important factor in the vitality of the product market. The cost of a CPU on a controlled board cannot be ignored. At the same time, maintaining multiple codes on the software also adds cost and complexity.
  • the main technical problem to be solved by the present invention is to provide a device with a unified chassis management architecture and a management control method thereof, which can reduce the management control cost of a device having a unified chassis management architecture.
  • a device having a unified chassis management architecture including a main control board and a control board, the main control board a CPU and a first logic unit connected to the CPU, the controlled board includes a second logic unit, a clock module, and an application module, where the second logic unit communicates with the first logic of the main control board through a communication interface Units are coupled to communicate with the first logic unit to effect signal interaction with the CPU; the second logic unit is coupled to the application module via a control interface for control by the CPU The application module is managed and controlled; the clock module is configured to complete clock distribution of the second logic unit and the application module by reading a preset configuration word pre-stored in the memory.
  • the signal communicated between the first logic unit and the second logic unit includes a clock signal, a data signal, and an enable signal.
  • the control interface of the second logic unit includes a serial bus interface, a parallel bus interface, a serial bus interface, and other control interfaces than the parallel bus interface.
  • the serial bus interface includes an I2C serial interface, an SPI serial interface, and an SMI serial interface;
  • the parallel bus interface includes a LOCAL BUS interface; the other control interface Includes state control interface.
  • the main control board is one, and the controlled boards are multiple, and the communication interfaces of the main control board and each controlled board have respective addresses and respective Independent read and write unit.
  • the first logic unit and the second logic unit are an FPGA or an EPLD.
  • the present invention also provides a management control method for any device with a unified chassis management architecture, including: initializing configuration of a controlled board by a CPU in a main control board, and CPU and a controlled board in the main control board The second logical unit performs data interaction to manage and control the controlled board.
  • the CPU in the main control board includes a power-on process before initializing the configuration of the controlled board, where the power-on process includes: controlled power-on, clock module read configuration Word, generate the required clock, distribute to the second logic The unit and the application module; the second logic unit is started, and the board status information of the board is obtained after the power is successfully sent, and the board status information and the initialization request are sent to the main control board.
  • the power-on process includes: controlled power-on, clock module read configuration Word, generate the required clock, distribute to the second logic The unit and the application module; the second logic unit is started, and the board status information of the board is obtained after the power is successfully sent, and the board status information and the initialization request are sent to the main control board.
  • the CPU in the main control board performs data interaction with the second logic unit of the controlled board to manage and control the controlled board, including a data uplink process, and the data uplink process
  • the second logic unit acquires the status information of the board, encapsulates the information into the frame, and sends the frame to the first logic unit after the verification; the frame includes the frame type, the data type, the data, and the school-risk information; After the unit successfully checks the received frame, the CPU in the main control board is notified to read and the frame type and data type are processed accordingly.
  • the CPU in the main control board performs data interaction with the second logic unit of the controlled board to manage and control the controlled board, including a data downlink process, and the data downlink process
  • the method includes: the CPU in the main control board encapsulates the data into a frame, and the first logic unit sends the frame to the second logic unit after the frame is diagnosed and failed; and the second logical unit succeeds in the received frame. - Performing a corresponding operation according to the frame; the second logic unit acquires a return result or a status indication of the application module to determine whether the operation is successful.
  • FIG. 1 is a general-purpose main control board communication architecture
  • FIG. 3 is a flowchart of a data communication process according to an embodiment of the present invention
  • Fig. 4 is a schematic view showing a concrete implementation of an application example of the present invention.
  • BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be further described in detail by way of specific embodiments with reference to the accompanying drawings.
  • the main idea of the present invention is to implement controlled by a logic unit, such as an FPGA (Field Programmable Logic 'J) or other 1 unit (Erasable Programmable Logic Device).
  • the management of the board controls the production and maintenance costs of the product.
  • the implementation program mainly includes: a device having a unified chassis management architecture, including a main control board and a control board, where the main control board includes a CPU and a first logic unit connected to the CPU, the control board a second logic unit, a clock module, and an application module, where the second logic unit is connected to the first logic unit of the main control board through a communication interface to communicate with the first logic unit to implement the CPU Inter-signal interaction; the second logic unit is connected to the application module through a control interface, and is configured to manage and control the application module under control of the CPU; the clock module is configured to read The preset configuration words pre-stored in the memory complete the clock distribution of the second logic unit and the application module. As shown in FIG. 2, in the example of FIG.
  • the first logic unit and the second logic unit are both FPGAs
  • the controlled board replaces the CPU with the cost of the FPGA to complete various services and configurations of the controlled board.
  • Management and control The main control board sends a control command to the controlled board, and the protocol is unpacked by the controlled board FPGA, and the control operation is completed.
  • the control and management of the controlled board is unified on the main control board and encapsulated by the CPU software of the main control board.
  • the CPU software in the main control board reads and writes the FPGA on the main control board to complete the control operation command and data transmission and reception.
  • the protocol package of the main control board is completed by the CPU software in the main control board, and distributed to each control board slot through the main control board FPGA.
  • the communication interface between the main control board and the controlled board (between the first logic unit and the second logic unit) can reduce the signal line of the interface between the main control board and the controlled board on the backplane by using the high-speed serial bus.
  • the controlled board FPGA mainly completes the parsing of the protocol and performs corresponding operations according to the pre-established protocol. The specific operations are implemented according to different types of controlled board services.
  • the interface between the main control board and the controlled board mainly has the following signal lines: Clock line: High-speed clock signal to ensure the data rate; Data line: Pass the communication data of the main control board, select half-duplex and duplex mode Single root One-way line to save the trace or 2 to the two-way line to ensure real-time; enable line: enable signal, used to control the path between the gated main control board.
  • the CPU-less controlled board of the FPGA in the embodiment of the present invention mainly has the following differences: 1.
  • the application module of the controlled board (for example, a service module for performing service processing or A storage module for storage, etc., that is, a module other than the FPGA and the clock module that can implement an application function, is unchanged, and the FPGA replaces the control interface of the CPU.
  • These interfaces include: Serial bus interface: such as I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), SMI (Serial Management Interface) Such as the commonly used serial interface, of course, can also be other serial interfaces; Parallel bus interface: such as LOCAL BUS interface, of course, can also be other parallel interfaces, including custom interfaces; Other control interfaces: such as state control interfaces .
  • the clock with the CPU controlled board is configured and managed by the CPU, as shown in Figure 1.
  • clock distribution is no longer controlled by the CPU, but is done by the clock module reading a predetermined configuration word in the EEPROM (Electrically Erasable Read Only Memory), as shown in Figure 2.
  • EEPROM Electrically Erasable Read Only Memory
  • the software interface encapsulation and configuration of a part of the application module of the controlled board is handed over to the CPU software of the main control board for packaging.
  • the communication interface between the main control board FPGA and each controlled board FPGA has its own independent read and write operation unit, and each interface has its own address.
  • the CPU in the main control board directly encapsulates the data frame structure of the interface of the controlled board application module, including the protocol type, data type, and data transfer to the main control board FPGA.
  • the main control board FPGA performs verification and encapsulates the data into a unified The frame structure is sent to the controlled board.
  • the controlled board FPGA completes simple interface conversion according to the protocol type delivered by the main control board, and directly generates the corresponding interface timing by the data frame already encapsulated by the main control board, and completes communication with the application module.
  • the FPGA of the controlled board only adds the received data and information to the protocol frame of the protocol type and is reported to the main control board.
  • the device of the embodiment of the invention has a management control method corresponding to the original controlled board management control. Differently, the method mainly includes: initializing the configuration of the controlled board by the CPU in the main control board, and performing data interaction between the CPU in the main control board and the second logic unit of the controlled board to manage and control the controlled board. As shown in FIG.
  • the process of the management control method includes a power-on process, a data uplink process, and a data downlink process, which are respectively described below.
  • the specific process of the power-on process of the control board includes: Step A. The controlled board power, the on-board clock module reads the configuration word through the EEPROM, generates the clock required by the board, and distributes the clock to each module. , including FPGA (second logic unit) and other modules (such as multiple application modules shown in Figure 2). Step B. The FPGA is started, and the FPGA is downloaded from the SPI Flash on the board to complete the startup configuration of the FPGA. Step C.
  • the controlled board FPGA obtains the status information of the board and sends the status information to the main board. Board status information and initialization request.
  • the initialization request of the CPU-controlled board in the main control board completes the initial configuration of the controlled board.
  • the uplink process of data communication includes: Step D.
  • the controlled board FPGA obtains the status information of the board, such as some board registration information, etc.
  • Step E The controlled board FPGA encapsulates the data into the defined frame structure and is in the frame. The header is attached to the frame type and the data type, and the frame is sent to the main control board through the interface between the main control board and the controlled board after the verification; Step F.
  • the main control board FPGA After the main control board FPGA receives the frame, after the verification succeeds Notify the controlled board that the FPGA receives successfully, otherwise it returns a failure.
  • the main control board FPGA notifies the CPU on the main control board, and the CPU reads the frame received by the FPGA, and judges the type of data and service according to the frame type and the frame data, and further processing and operations are performed by the CPU software.
  • the downlink process of data communication includes: Step G.
  • the CPU software in the main control board directly encapsulates the processed data into a data frame structure to be transmitted, and the main control board FPGA only applies the data to the insurance and adds the school-risk information. And then packaged into a frame and sent to the controlled board FPGA; Step H.
  • the controlled board FPGA After the controlled board FPGA receives the data, and the verification succeeds, the main control board is notified to deliver successfully. Otherwise the return fails.
  • the controlled board FPGA judges the further operation of the FPGA according to the parameters and types defined in the received data frame header. Step I.
  • the controlled board FPGA determines the operation type, completes the specific operation, such as completing the control of a certain module or
  • the data in the received frame is directly sent to each module according to the type of operation to generate the corresponding interface timing (such as SPI).
  • Step J The controlled board FPGA obtains the return result of each module (some write operations to the module may not need to return a result) or status indication to indicate whether an operation is successful. If necessary, report the result to the main control board according to the procedure in step DF.
  • Step K The main control board initiates the FPGA update command, according to the process of step G-H, delivers
  • Step L After the FPGA response command is confirmed, the main control board sends the FPGA update data to the controlled board through step G.
  • the controlled board FPGA writes the data to the flash through the SPI port according to step H, and returns the result to the main control board.
  • Step M After receiving the control board update success message, the main control board resets the controlled board and repeats the operation of step AC. If the result of the failure is returned, repeat the operation of step KM.
  • FIG. 4 is an application example of an Ethernet switch-based control board in an embodiment of the present invention.
  • the main control board includes a CPU and an FPGA module 107 (first logic unit); the controlled board mainly includes a clock module 101 (including an EEPROM storing a preset configuration word), and an FPGA module 102 (second Logic unit), SPI Flash (flash) 103, switch module 108, PHY (Physical Layer) module 109, EEPROM and sensor module 111.
  • the switch module 108, the PHY (Physical Layer) module 109, the EEPROM and the sensor module 111 in FIG. 4 are the aforementioned application modules, and are used to implement application functions such as Ethernet switching, storage, and sensing. Communication between the main control board and the controlled board is through the communication interface 106.
  • the FPGA module 102 interacts with the clock module 101 through the SPI interface 106, interacts with the interaction module 108 through the SMI control interface 107, interacts with the module 111 such as the EEPROM and the sensor through the I2C interface 112, and performs SMI control between the switch module 108 and the PHY module 109.
  • Interface 110 interacts.
  • the FPGA module 102 includes a control module 104 and an interface module 105.
  • the data communication interface 106 of the main control board and the control board is a serial bus, including data, time Clock and enable signal lines. In order to save the backplane routing, it is compatible with other serial management buses with CPU-controlled boards (such as the IPMI (Intelligent Platform Management Interface) bus), which can support the intermixing of multiple types of boards.
  • IPMI Intelligent Platform Management Interface
  • the data communication interface 106 takes an I2C serial bus as an example, and its data bit width is 48 bits (different applications, data bit width may be different), the first 12 bits are communication protocol information and control information, the last 32 bits are data information, and the last 4 bits are School - dangerous position.
  • the controlled-board FPGA sets the data line to indicate that the reception was successful, otherwise it fails, and notifies the CPU that an error is returned.
  • the clock module 101 reads the configuration word through the EEPROM on the board to complete the configuration of the clock module. After the clock configuration is completed, the clock is distributed to each module, including the FPGA module 102, the switch module 108, and the PHY (Physical Layer) module 109.
  • the FPGA module 102 loads the FPGA program through the SPI Flash module 103 on the board under the operating clock.
  • the controlled board FPGA module 102 starts to work.
  • the control module 104 acquires the state of the board, and combines the data into a 32-bit frame, plus a 12-bit frame header (including data type, service type, start/end, etc.), and finally adds The upper 4 bits of the verification result is sent to the main control board FPGA module 107 through the interface module 105.
  • the main control board FPGA module 107 receives the data and notifies the CPU to process it.
  • the CPU reads 44 bits of data (the parity bit has been removed), and determines the type of the data as the power-on information and the initialization request according to a predefined protocol.
  • the CPU in the main control board After the CPU in the main control board registers the information and status of the controlled board, the CPU sends a configuration command to the controlled board through the FPGA module 107.
  • the data frame sent by the FPGA is completely generated by the CPU software, which can minimize the complexity of the logic unit, further reduce the resource occupancy rate, and improve the efficiency of the debugging application. Taking the switching chip operation management of the switching module 108 as an example, the process of one downlink communication is described.
  • the CPU in the main control board determines the frame type sent by the FPGA module 107, and generates the frame type of the switch chip configuration, including the 12-bit frame header (frame type, operation type, etc.) and the standard SMI management frame structure (32 bits).
  • a 48-bit data frame is generated, which is sent to the interface module 105 of the controlled-board FPGA module 102 through the communication interface 106 between the main control boards.
  • the interface module 105 extracts protocol information according to the first 12 bits of the received frame.
  • the interface module 105 determines that the operation of the switch module 108 is to be performed, and directly sends the SMI interface timing of the data generation of the last 32 bits to the switch module 108, and directly returns a success message according to the corresponding state of the module.
  • the content of the message is performed according to the uplink communication flow.
  • the controlled board FPGA directly or indirectly encapsulates the return result (32bits) or status information of the switching module 108 into a 32-bit data frame, adds the frame header protocol of the uplink communication, and performs verification, and then puts 48-bit frame data into the frame.
  • the data is sent to the main control board FPGA while waiting for the communication interface 106 between the main control boards to be idle. Number of work received
  • the CPU reads the data and hands it to the CPU software to process the data. This completes a communication handshake and data transfer between the main control boards.
  • the configuration and communication of the switching module 108 are completed in sequence.
  • the processing of other modules on the board is similar to the above steps. The difference is that the data frame encapsulation of the CPU in the main control board and the conversion of the interface timing between the application modules by the FPGA interface module 105 are different.
  • the control module 104 in the FPGA module 102 can perform simple single board control tasks.
  • the management control of the CPU of the main control board and the control of the single board of the FPGA of the controlled board are roughly classified according to the complexity.
  • the CPU of the main control board completes the configuration related to the initialization of each controlled board; and the command operation and data processing
  • controlled board FPGAs can handle the operation and processing, such as simple processing of interrupts, monitoring and reporting of application module status information, etc., by the controlled board FPGA; Operations and processing that are not strong and complex are handled by the CPU of the main control board.
  • a compatible version with CPU and FPGA can be designed for debugging convenience.
  • FPGA debugging is performed according to the above method flow. At this point, FPGA debugging only focuses on communication and processing. In the later stage, the parameters of the previous commissioning will be carried out. When the system is stable, external circuits such as the CPU can be removed during production. The invention also satisfies the requirements of production testing, and is also compatible with hybrid insertion multiplexing of CPU boards. Compared with the prior art, the present invention uses a low-cost FPGA instead of a CPU to manage and control the controlled board.
  • the FPGA has relatively low resource requirements, and as the price advantage of the FPGA increases, the current high-speed digital In the circuit, FPGAs are used more and more widely, and FPGAs are generally used on the single boards, so the cost pressure is controlled.
  • the CPU-free solution can reduce a large number of CPU peripherals and circuits, reducing the complexity of the hardware. And cost;
  • the FPGA is replaced by the FPGA software to control the controlled board, which improves the stability and reliability of the board, and also saves a lot of CPU software expenses.
  • the present invention can be applied to an application scenario in which multiple boards that need to be managed and maintained are used, and the application scenario is richer and has better versatility.

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Abstract

L'invention porte sur un dispositif à architecture de gestion de châssis unifiée et sur son procédé de commande de gestion. Le dispositif comprend une carte de commande maître et une carte commandée. La carte de commande maître comprend une unité centrale (CPU) et une première unité logique connectée à la CPU. La carte commandée comprend une seconde unité logique, un module d'horloge et un module d'application. La seconde unité logique se connecte à la première unité logique de la carte de commande maître afin de communiquer avec la première unité logique par l'intermédiaire d'une interface de communication, de manière à réaliser une interaction par signaux avec la CPU. La seconde unité logique, qui se connecte au module d'application par l'intermédiaire d'une interface de commande, est utilisée pour gérer et commander le module d'application sous la commande de la CPU. Le module d'horloge est utilisé pour effectuer la distribution d'horloge pour la seconde unité logique et le module d'application par lecture d'un mot de configuration préréglé préalablement stocké dans une mémoire.
PCT/CN2010/079281 2010-07-30 2010-11-30 Dispositif à architecture de gestion de châssis unifiée et son procédé de commande de gestion WO2012012994A1 (fr)

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CN2010102415858A CN102346501A (zh) 2010-07-30 2010-07-30 一种具有统一机框管理架构的设备及其管理控制方法

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017032112A1 (fr) * 2015-08-26 2017-03-02 中兴通讯股份有限公司 Procédé pour communiquer avec une carte dépourvue de cpu, et dispositif de communication
CN108304338A (zh) * 2017-12-20 2018-07-20 深圳比特微电子科技有限公司 多单板管理方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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CN111385133A (zh) * 2018-12-29 2020-07-07 中兴通讯股份有限公司 资源管理方法及系统
CN112506848A (zh) * 2020-12-03 2021-03-16 中国电子科技集团公司第三十研究所 基于配置的信息交互控制模型及方法
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1665154A (zh) * 2004-03-04 2005-09-07 中兴通讯股份有限公司 一种嵌入式系统带内复位的方法及其装置
CN1848103A (zh) * 2005-04-12 2006-10-18 华为技术有限公司 实现中央控制单元对单板集中控制的方法和系统
CN101631345A (zh) * 2009-08-13 2010-01-20 中兴通讯股份有限公司 单板运行状态的监控方法及装置
CN101741593A (zh) * 2008-11-19 2010-06-16 华为技术有限公司 一种动态加载业务板的方法和动态加载系统

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1154046C (zh) * 2001-04-06 2004-06-16 华为技术有限公司 一种检测单板在位的方法
CN101446805A (zh) * 2007-11-27 2009-06-03 飞跃中科（台州）数控系统有限公司 家用电脑绣花机及在家用电脑绣花机上输入数据的方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1665154A (zh) * 2004-03-04 2005-09-07 中兴通讯股份有限公司 一种嵌入式系统带内复位的方法及其装置
CN1848103A (zh) * 2005-04-12 2006-10-18 华为技术有限公司 实现中央控制单元对单板集中控制的方法和系统
CN101741593A (zh) * 2008-11-19 2010-06-16 华为技术有限公司 一种动态加载业务板的方法和动态加载系统
CN101631345A (zh) * 2009-08-13 2010-01-20 中兴通讯股份有限公司 单板运行状态的监控方法及装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017032112A1 (fr) * 2015-08-26 2017-03-02 中兴通讯股份有限公司 Procédé pour communiquer avec une carte dépourvue de cpu, et dispositif de communication
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