WO2012012994A1

WO2012012994A1 - Device with unified shelf management architecture and management control method thereof

Info

Publication number: WO2012012994A1
Application number: PCT/CN2010/079281
Authority: WO
Inventors: 乔海龙
Original assignee: 中兴通讯股份有限公司
Priority date: 2010-07-30
Filing date: 2010-11-30
Publication date: 2012-02-02
Also published as: CN102346501A

Abstract

A device with a unified shelf management architecture and a management control method thereof are provided. The device includes a master control board and a controlled board. The master control board comprises a Central Processing Unit (CPU) and a first logic unit connected with the CPU. The controlled board comprises a second logic unit, a clock module, and an application module. The second logic unit connects with the first logic unit of the master control board to communicate with the first logic unit via a communication interface, so as to realize the signal interaction with the CPU. The second logic unit, which connects with the application module via a control interface, is used for managing and controlling the application module under the control of the CPU. The clock module is used for completing the clock distribution for the second logic unit and the application module by reading a preset configuration word pre-stored in a memory.

Description

The present invention relates to the field of communications, and in particular to a device having a unified machine 11 management architecture and a management control method thereof. BACKGROUND OF THE INVENTION Machine-framed devices are widely used in the fields of electronics, communications, and machinery. The device is based on a chassis, and multiple slots are provided on the chassis for each unit device in the device, such as a service ticket. The board access, the unified machine 411 management architecture, is managed by the machine 411 management board, and the service board in the machine 411 is managed. The subrack management board is the main control board, and the other managed service boards are controlled. board. In the current communication equipment, the services running on the controlled board usually need to be managed and maintained. Generally, the CPU runs software to process and communicate with the main control board. The main control board and the controlled board communicate according to a certain protocol, as shown in Figure 1. The initialization and configuration of the control board is completed by the CPU of the board. The control boards of different services have different CPU requirements. For example, boards such as E1 or Ethernet have low requirements for CPU management and maintenance. The above design mainly has two points to consider: First, the design is simple, there are a large number of general circuit support; Second, the efficiency is high, the development and debugging of each controlled board can be carried out in parallel. However, in today's increasingly fierce competition in the communications industry, cost will be an important factor in the vitality of the product market. The cost of a CPU on a controlled board cannot be ignored. At the same time, maintaining multiple codes on the software also adds cost and complexity. If the same processing is performed on the controlled boards of all services, unnecessary waste and complexity will be caused. SUMMARY OF THE INVENTION The main technical problem to be solved by the present invention is to provide a device with a unified chassis management architecture and a management control method thereof, which can reduce the management control cost of a device having a unified chassis management architecture. In order to solve the above technical problem, the present invention uses the following technical solutions: A device having a unified chassis management architecture, including a main control board and a control board, the main control board a CPU and a first logic unit connected to the CPU, the controlled board includes a second logic unit, a clock module, and an application module, where the second logic unit communicates with the first logic of the main control board through a communication interface Units are coupled to communicate with the first logic unit to effect signal interaction with the CPU; the second logic unit is coupled to the application module via a control interface for control by the CPU The application module is managed and controlled; the clock module is configured to complete clock distribution of the second logic unit and the application module by reading a preset configuration word pre-stored in the memory. In an embodiment of the device of the present invention, the signal communicated between the first logic unit and the second logic unit includes a clock signal, a data signal, and an enable signal. In an embodiment of the device of the present invention, the control interface of the second logic unit includes a serial bus interface, a parallel bus interface, a serial bus interface, and other control interfaces than the parallel bus interface. In an embodiment of the device of the present invention, the serial bus interface includes an I2C serial interface, an SPI serial interface, and an SMI serial interface; the parallel bus interface includes a LOCAL BUS interface; the other control interface Includes state control interface. In an embodiment of the device of the present invention, the main control board is one, and the controlled boards are multiple, and the communication interfaces of the main control board and each controlled board have respective addresses and respective Independent read and write unit. In an embodiment of the device of the present invention, the first logic unit and the second logic unit are an FPGA or an EPLD. The present invention also provides a management control method for any device with a unified chassis management architecture, including: initializing configuration of a controlled board by a CPU in a main control board, and CPU and a controlled board in the main control board The second logical unit performs data interaction to manage and control the controlled board. In an embodiment of the method, the CPU in the main control board includes a power-on process before initializing the configuration of the controlled board, where the power-on process includes: controlled power-on, clock module read configuration Word, generate the required clock, distribute to the second logic The unit and the application module; the second logic unit is started, and the board status information of the board is obtained after the power is successfully sent, and the board status information and the initialization request are sent to the main control board. In an embodiment of the method of the present invention, the CPU in the main control board performs data interaction with the second logic unit of the controlled board to manage and control the controlled board, including a data uplink process, and the data uplink process The second logic unit acquires the status information of the board, encapsulates the information into the frame, and sends the frame to the first logic unit after the verification; the frame includes the frame type, the data type, the data, and the school-risk information; After the unit successfully checks the received frame, the CPU in the main control board is notified to read and the frame type and data type are processed accordingly. In an embodiment of the method of the present invention, the CPU in the main control board performs data interaction with the second logic unit of the controlled board to manage and control the controlled board, including a data downlink process, and the data downlink process The method includes: the CPU in the main control board encapsulates the data into a frame, and the first logic unit sends the frame to the second logic unit after the frame is diagnosed and failed; and the second logical unit succeeds in the received frame. - Performing a corresponding operation according to the frame; the second logic unit acquires a return result or a status indication of the application module to determine whether the operation is successful. The beneficial effects of the present invention are: by setting a second logic unit in the controlled board, communicating with the first logic unit of the main control board and performing signal interaction with the CPU in the main control board, under the control of the CPU of the main control board The management control of the controlled board application module is realized, thereby realizing the CPUless of the controlled board and reducing the cost of the controlled board, thereby reducing the management control cost of the equipment with the unified chassis management architecture as a whole. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a general-purpose main control board communication architecture;

3 is a flowchart of a data communication process according to an embodiment of the present invention; Fig. 4 is a schematic view showing a concrete implementation of an application example of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be further described in detail by way of specific embodiments with reference to the accompanying drawings. The main idea of the present invention is to implement controlled by a logic unit, such as an FPGA (Field Programmable Logic 'J) or other 1 unit (Erasable Programmable Logic Device). The management of the board controls the production and maintenance costs of the product. The implementation program mainly includes: a device having a unified chassis management architecture, including a main control board and a control board, where the main control board includes a CPU and a first logic unit connected to the CPU, the control board a second logic unit, a clock module, and an application module, where the second logic unit is connected to the first logic unit of the main control board through a communication interface to communicate with the first logic unit to implement the CPU Inter-signal interaction; the second logic unit is connected to the application module through a control interface, and is configured to manage and control the application module under control of the CPU; the clock module is configured to read The preset configuration words pre-stored in the memory complete the clock distribution of the second logic unit and the application module. As shown in FIG. 2, in the example of FIG. 2, the first logic unit and the second logic unit are both FPGAs, and the controlled board replaces the CPU with the cost of the FPGA to complete various services and configurations of the controlled board. Management and control. The main control board sends a control command to the controlled board, and the protocol is unpacked by the controlled board FPGA, and the control operation is completed. The control and management of the controlled board is unified on the main control board and encapsulated by the CPU software of the main control board. The CPU software in the main control board reads and writes the FPGA on the main control board to complete the control operation command and data transmission and reception. To ensure that the main control board can operate multiple control boards at the same time, the protocol package of the main control board is completed by the CPU software in the main control board, and distributed to each control board slot through the main control board FPGA. The communication interface between the main control board and the controlled board (between the first logic unit and the second logic unit) can reduce the signal line of the interface between the main control board and the controlled board on the backplane by using the high-speed serial bus. The controlled board FPGA mainly completes the parsing of the protocol and performs corresponding operations according to the pre-established protocol. The specific operations are implemented according to different types of controlled board services. The interface between the main control board and the controlled board mainly has the following signal lines: Clock line: High-speed clock signal to ensure the data rate; Data line: Pass the communication data of the main control board, select half-duplex and duplex mode Single root One-way line to save the trace or 2 to the two-way line to ensure real-time; enable line: enable signal, used to control the path between the gated main control board. Compared with the original CPU-controlled board, the CPU-less controlled board of the FPGA in the embodiment of the present invention mainly has the following differences: 1. After replacing the CPU, the application module of the controlled board (for example, a service module for performing service processing or A storage module for storage, etc., that is, a module other than the FPGA and the clock module that can implement an application function, is unchanged, and the FPGA replaces the control interface of the CPU. These interfaces include: Serial bus interface: such as I2C (Inter-Integrated Circuit), SPI (Serial Peripheral Interface), SMI (Serial Management Interface) Such as the commonly used serial interface, of course, can also be other serial interfaces; Parallel bus interface: such as LOCAL BUS interface, of course, can also be other parallel interfaces, including custom interfaces; Other control interfaces: such as state control interfaces .

After the FPGA replaces the CPU, it completes the conversion of these interface protocols and implements some simple monitoring and processing tasks, such as status monitoring and simple interrupt processing tasks, as shown in Figure 2.

2. The clock with the CPU controlled board is configured and managed by the CPU, as shown in Figure 1. In a CPU-free board, clock distribution is no longer controlled by the CPU, but is done by the clock module reading a predetermined configuration word in the EEPROM (Electrically Erasable Read Only Memory), as shown in Figure 2.

3. The software interface encapsulation and configuration of a part of the application module of the controlled board is handed over to the CPU software of the main control board for packaging. The communication interface between the main control board FPGA and each controlled board FPGA has its own independent read and write operation unit, and each interface has its own address. The CPU in the main control board directly encapsulates the data frame structure of the interface of the controlled board application module, including the protocol type, data type, and data transfer to the main control board FPGA. The main control board FPGA performs verification and encapsulates the data into a unified The frame structure is sent to the controlled board. The controlled board FPGA completes simple interface conversion according to the protocol type delivered by the main control board, and directly generates the corresponding interface timing by the data frame already encapsulated by the main control board, and completes communication with the application module. When the data is reported, the FPGA of the controlled board only adds the received data and information to the protocol frame of the protocol type and is reported to the main control board. The device of the embodiment of the invention has a management control method corresponding to the original controlled board management control. Differently, the method mainly includes: initializing the configuration of the controlled board by the CPU in the main control board, and performing data interaction between the CPU in the main control board and the second logic unit of the controlled board to manage and control the controlled board. As shown in FIG. 3, the process of the management control method includes a power-on process, a data uplink process, and a data downlink process, which are respectively described below. In the embodiment of the present invention, the specific process of the power-on process of the control board includes: Step A. The controlled board power, the on-board clock module reads the configuration word through the EEPROM, generates the clock required by the board, and distributes the clock to each module. , including FPGA (second logic unit) and other modules (such as multiple application modules shown in Figure 2). Step B. The FPGA is started, and the FPGA is downloaded from the SPI Flash on the board to complete the startup configuration of the FPGA. Step C. After the power is successfully applied, the controlled board FPGA obtains the status information of the board and sends the status information to the main board. Board status information and initialization request. The initialization request of the CPU-controlled board in the main control board completes the initial configuration of the controlled board. The uplink process of data communication includes: Step D. The controlled board FPGA obtains the status information of the board, such as some board registration information, etc. Step E. The controlled board FPGA encapsulates the data into the defined frame structure and is in the frame. The header is attached to the frame type and the data type, and the frame is sent to the main control board through the interface between the main control board and the controlled board after the verification; Step F. After the main control board FPGA receives the frame, after the verification succeeds Notify the controlled board that the FPGA receives successfully, otherwise it returns a failure. The main control board FPGA notifies the CPU on the main control board, and the CPU reads the frame received by the FPGA, and judges the type of data and service according to the frame type and the frame data, and further processing and operations are performed by the CPU software. The downlink process of data communication includes: Step G. The CPU software in the main control board directly encapsulates the processed data into a data frame structure to be transmitted, and the main control board FPGA only applies the data to the insurance and adds the school-risk information. And then packaged into a frame and sent to the controlled board FPGA; Step H. After the controlled board FPGA receives the data, and the verification succeeds, the main control board is notified to deliver successfully. Otherwise the return fails. The controlled board FPGA judges the further operation of the FPGA according to the parameters and types defined in the received data frame header. Step I. The controlled board FPGA determines the operation type, completes the specific operation, such as completing the control of a certain module or The data in the received frame is directly sent to each module according to the type of operation to generate the corresponding interface timing (such as SPI). Step J. The controlled board FPGA obtains the return result of each module (some write operations to the module may not need to return a result) or status indication to indicate whether an operation is successful. If necessary, report the result to the main control board according to the procedure in step DF.

FPGA version online update process: Step K. The main control board initiates the FPGA update command, according to the process of step G-H, delivers

The FPGA update command. Step L. After the FPGA response command is confirmed, the main control board sends the FPGA update data to the controlled board through step G. The controlled board FPGA writes the data to the flash through the SPI port according to step H, and returns the result to the main control board. Step M. After receiving the control board update success message, the main control board resets the controlled board and repeats the operation of step AC. If the result of the failure is returned, repeat the operation of step KM. As shown in FIG. 4, FIG. 4 is an application example of an Ethernet switch-based control board in an embodiment of the present invention. In this application example, the main control board includes a CPU and an FPGA module 107 (first logic unit); the controlled board mainly includes a clock module 101 (including an EEPROM storing a preset configuration word), and an FPGA module 102 (second Logic unit), SPI Flash (flash) 103, switch module 108, PHY (Physical Layer) module 109, EEPROM and sensor module 111. The switch module 108, the PHY (Physical Layer) module 109, the EEPROM and the sensor module 111 in FIG. 4 are the aforementioned application modules, and are used to implement application functions such as Ethernet switching, storage, and sensing. Communication between the main control board and the controlled board is through the communication interface 106. The FPGA module 102 interacts with the clock module 101 through the SPI interface 106, interacts with the interaction module 108 through the SMI control interface 107, interacts with the module 111 such as the EEPROM and the sensor through the I2C interface 112, and performs SMI control between the switch module 108 and the PHY module 109. Interface 110 interacts. The FPGA module 102 includes a control module 104 and an interface module 105. The data communication interface 106 of the main control board and the control board is a serial bus, including data, time Clock and enable signal lines. In order to save the backplane routing, it is compatible with other serial management buses with CPU-controlled boards (such as the IPMI (Intelligent Platform Management Interface) bus), which can support the intermixing of multiple types of boards. The data communication interface 106 takes an I2C serial bus as an example, and its data bit width is 48 bits (different applications, data bit width may be different), the first 12 bits are communication protocol information and control information, the last 32 bits are data information, and the last 4 bits are School - dangerous position. On the 49th clock cycle, the controlled-board FPGA sets the data line to indicate that the reception was successful, otherwise it fails, and notifies the CPU that an error is returned. After the board is powered on, the clock module 101 reads the configuration word through the EEPROM on the board to complete the configuration of the clock module. After the clock configuration is completed, the clock is distributed to each module, including the FPGA module 102, the switch module 108, and the PHY (Physical Layer) module 109. The FPGA module 102 loads the FPGA program through the SPI Flash module 103 on the board under the operating clock. The controlled board FPGA module 102 starts to work. First, the control module 104 acquires the state of the board, and combines the data into a 32-bit frame, plus a 12-bit frame header (including data type, service type, start/end, etc.), and finally adds The upper 4 bits of the verification result is sent to the main control board FPGA module 107 through the interface module 105. The main control board FPGA module 107 receives the data and notifies the CPU to process it. The CPU reads 44 bits of data (the parity bit has been removed), and determines the type of the data as the power-on information and the initialization request according to a predefined protocol. After the CPU in the main control board registers the information and status of the controlled board, the CPU sends a configuration command to the controlled board through the FPGA module 107. The data frame sent by the FPGA is completely generated by the CPU software, which can minimize the complexity of the logic unit, further reduce the resource occupancy rate, and improve the efficiency of the debugging application. Taking the switching chip operation management of the switching module 108 as an example, the process of one downlink communication is described. The CPU in the main control board determines the frame type sent by the FPGA module 107, and generates the frame type of the switch chip configuration, including the 12-bit frame header (frame type, operation type, etc.) and the standard SMI management frame structure (32 bits). After the FPGA module 107 performs verification, a 48-bit data frame is generated, which is sent to the interface module 105 of the controlled-board FPGA module 102 through the communication interface 106 between the main control boards. The interface module 105 extracts protocol information according to the first 12 bits of the received frame. The interface module 105 determines that the operation of the switch module 108 is to be performed, and directly sends the SMI interface timing of the data generation of the last 32 bits to the switch module 108, and directly returns a success message according to the corresponding state of the module. The content of the message is performed according to the uplink communication flow. The controlled board FPGA directly or indirectly encapsulates the return result (32bits) or status information of the switching module 108 into a 32-bit data frame, adds the frame header protocol of the uplink communication, and performs verification, and then puts 48-bit frame data into the frame. In the send buffer, the data is sent to the main control board FPGA while waiting for the communication interface 106 between the main control boards to be idle. Number of work received After that, the CPU reads the data and hands it to the CPU software to process the data. This completes a communication handshake and data transfer between the main control boards. According to the above steps, the configuration and communication of the switching module 108 are completed in sequence. The processing of other modules on the board is similar to the above steps. The difference is that the data frame encapsulation of the CPU in the main control board and the conversion of the interface timing between the application modules by the FPGA interface module 105 are different.

The control module 104 in the FPGA module 102 can perform simple single board control tasks. The management control of the CPU of the main control board and the control of the single board of the FPGA of the controlled board are roughly classified according to the complexity. Generally, the CPU of the main control board completes the configuration related to the initialization of each controlled board; and the command operation and data processing For real-time, low-complexity, controlled board FPGAs can handle the operation and processing, such as simple processing of interrupts, monitoring and reporting of application module status information, etc., by the controlled board FPGA; Operations and processing that are not strong and complex are handled by the CPU of the main control board. In the early stage of implementation, a compatible version with CPU and FPGA can be designed for debugging convenience. After the configuration and application debugging of each module are stabilized in the early stage of board debugging, FPGA debugging is performed according to the above method flow. At this point, FPGA debugging only focuses on communication and processing. In the later stage, the parameters of the previous commissioning will be carried out. When the system is stable, external circuits such as the CPU can be removed during production. The invention also satisfies the requirements of production testing, and is also compatible with hybrid insertion multiplexing of CPU boards. Compared with the prior art, the present invention uses a low-cost FPGA instead of a CPU to manage and control the controlled board. The FPGA has relatively low resource requirements, and as the price advantage of the FPGA increases, the current high-speed digital In the circuit, FPGAs are used more and more widely, and FPGAs are generally used on the single boards, so the cost pressure is controlled. In addition, the CPU-free solution can reduce a large number of CPU peripherals and circuits, reducing the complexity of the hardware. And cost; At the same time, the FPGA is replaced by the FPGA software to control the controlled board, which improves the stability and reliability of the board, and also saves a lot of CPU software expenses. The present invention can be applied to an application scenario in which multiple boards that need to be managed and maintained are used, and the application scenario is richer and has better versatility. The interface between the FPGA of the main control board and each controlled board can be processed in parallel, which improves the processing performance of the system. The above is a further detailed description of the present invention in connection with the specific embodiments, and the specific implementation of the invention is not limited to the description. Common to the technical field to which the present invention pertains The skilled person can make a simple deduction or replacement without departing from the inventive concept, and should be regarded as belonging to the protection scope of the present invention.

Claims

Claim

A device having a unified chassis management architecture, including a main control board and a control board, wherein the main control board includes a CPU and a first logic unit connected to the CPU, and the control board a second logic unit, a clock module, and an application module, where the second logic unit is connected to the first logic unit of the main control board through a communication interface to communicate with the first logic unit to implement the CPU The second logic unit is connected to the application module through a control interface, and is configured to manage and control the application module under the control of the CPU; the clock module is configured to read The preset configuration words pre-stored in the memory complete the clock distribution of the second logic unit and the application module.

2. The device according to claim 1, wherein the signal communicated between the first logic unit and the second logic unit comprises a clock signal, a data signal, and an enable signal.

3. The device according to claim 1, wherein the control interface of the second logic unit comprises a serial bus interface, a parallel bus interface, a serial bus interface, and other control interfaces than the parallel bus interface.

4. The device of claim 3, wherein the serial bus interface comprises an I2C serial interface, an SPI serial interface, an SMI serial interface; the parallel bus interface comprises a LOCAL BUS interface; The control interface includes a state control interface.

The device according to claim 1, wherein the main control board is one, and the controlled boards are multiple, and the communication interface between the main control board and each controlled board has a respective address. And separate read and write units.

The device according to any one of claims 1-5, wherein the first logic unit and the second logic unit are both an FPGA or an EPLD.

The management control method of the device with a unified chassis management architecture according to any one of claims 1-5, comprising: initializing configuration of the controlled board by the CPU in the main control board, and The CPU in the control board interacts with the second logic unit of the controlled board to manage and control the controlled board. The method of claim 7, wherein the CPU in the main control board includes a power-on process before initializing the configuration of the controlled board, where the power-on process includes: controlled power-on, clock module read configuration The words, generate the required clocks, and distribute them to the second logic unit and the application module. The second logic unit starts, and obtains the board status information of the board after the power is successfully sent, and sends the board status information and the initialization request to the main control board. . The method of claim 7, wherein the CPU in the main control board performs data interaction with the second logic unit of the controlled board to manage and control the controlled board, including a data uplink process, and the data uplink process The second logic unit acquires the status information of the board, encapsulates the information into the frame, and sends the frame to the first logic unit after the verification; the frame includes the frame type, the data type, the data, and the school-risk information; After the unit successfully checks the received frame, the CPU in the main control board is notified to read and perform corresponding processing according to the frame type and data type. The method of claim 7, wherein the CPU in the main control board performs data interaction with the second logic unit of the controlled board to manage and control the controlled board, including a data downlink process, and the data downlink process The method includes: the CPU in the main control board encapsulates the data into a frame, the first logic unit sends the frame to the second logic unit after the frame is diagnosed, and the second logic unit performs the calibration on the received frame. The main control board is informed, and the corresponding operation is performed according to the frame or sent to the corresponding application module for processing; the second logic unit acquires a return result or a status indication of the application module, and determines whether the operation is successful.