WO2015131516A1 - Procédé de raccordement réparti pour bus de gestion de plates-formes intelligentes et châssis atca - Google Patents

Procédé de raccordement réparti pour bus de gestion de plates-formes intelligentes et châssis atca Download PDF

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Publication number
WO2015131516A1
WO2015131516A1 PCT/CN2014/086972 CN2014086972W WO2015131516A1 WO 2015131516 A1 WO2015131516 A1 WO 2015131516A1 CN 2014086972 W CN2014086972 W CN 2014086972W WO 2015131516 A1 WO2015131516 A1 WO 2015131516A1
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Prior art keywords
ipmi
bmc
data
ipmc
board
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PCT/CN2014/086972
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English (en)
Chinese (zh)
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刘斌涛
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中兴通讯股份有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices

Definitions

  • the present invention relates to the field of computers, and in particular, to a distributed intelligent platform management bus (Intelligent Platform Management BUS, IPMB for short) connection method and an advanced telecom computing platform (ATCA) chassis.
  • a distributed intelligent platform management bus Intelligent Platform Management BUS, IPMB for short
  • IPMB Intelligent Platform Management BUS
  • ATCA advanced telecom computing platform
  • the ATCA standard began with the CompactPCI standard, a new generation of mainstream industrial computing technology widely used in telecommunications, aerospace, industrial control, medical equipment, intelligent transportation, military equipment and other fields.
  • IPMI Intelligent Platform Management Interface
  • BMC baseboard management controller
  • IPMC intelligent platform management controller
  • the IPMC is distributed on the board of the system to manage, monitor, and control the power supply voltage, temperature sensor, and fan speed on the board.
  • the baseboard management controller connects the boards through the intelligent platform management bus (IPMB), and provides the IPMC management communication channel of the baseboard management controller to other boards.
  • IPMB communication bus uses the I2C signal line (including one data line SDA and one clock line SCL).
  • the ATCA specification requires that the board have two IPMB bus interfaces, called IPMB-A and IPMB-B, respectively. It is IPMB-0.
  • IPMB connection mode is mainly implemented in a dual bus or dual star configuration mode to ensure the stability of the system.
  • the active and standby BMCs provide two IPMB bus interfaces IPMB-A and IPMB-B respectively, and the IPMC nodes on the peripheral boards simultaneously provide two I2C interfaces to be mounted on the two IPMB buses.
  • the primary BMC acts as the master device of the I2C bus, and manages the IPMC on the peripheral board node and the IPMC on the standby BMC.
  • the standby BMC becomes the master of the I2C bus, replacing the faulty BMC to complete the system management function.
  • the IPMB dual bus connection has the following disadvantages: the hardware signal abnormality (SCL or SDA is low) of the I2C signal of any IPMC or BMC node will clamp the entire I2C bus (normal data cannot be performed). Sending and receiving), all IPMC nodes cannot communicate through the I2C bus signal; in addition, the position of the I2C faulty board cannot be located.
  • SCL or SDA hardware signal abnormality
  • the I2C switch is mainly controlled to switch the I2C channel, and the BMC processor and the I2C switch are connected through an I2C bus.
  • the prior art discloses an improvement on the star IPMB bus structure.
  • the processor of the active and standby BMC respectively provides an IPMB bus to form an independent IPMB bus through the I2C switch to manage the IPMC node.
  • This centralized data management method cannot control the device environment in a timely manner. Especially when the management slot increases and the amount of data increases, the feedback delay of the chassis information becomes more serious.
  • the I2C bus will still be clamped, causing the BMC to lose control of the bus.
  • the present invention has been proposed to provide a distributed intelligent platform management bus IPMB connection method and an ATCA chassis that overcome the above problems.
  • the embodiment of the present invention provides a distributed intelligent platform management bus IPMB connection method, which is used in an ATCA chassis of an advanced telecommunication computing architecture, wherein an ATCA board with a plurality of slots is provided with an ATCA board inserted in a slot.
  • Each ATCA board includes two main control boards and at least one node board.
  • Each node board is provided with an intelligent platform management controller IPMC, and the baseboard management controller BMC is integrated on two main control boards, including : Set the intelligent platform management interface IPMI on each main control board.
  • the BMC on each main control board performs point-to-point star connection through IPMI and IPMC of each node board and IPMI on the other main control board.
  • the BMC exchanges data with the IPMC nodes of the peripheral board through IPMI.
  • the BMC and IPMI exchange data through the local bus.
  • IPMI exchanges data with each IPMC node of the peripheral board through the independently distributed I2C-based multi-channel IPMB bus.
  • IPMI provides The total number of I2C-based multi-channel IPMB buses corresponds to the number of peripheral boards.
  • the BMCs on the two main control boards are the primary BMC and the standby BMC respectively, and an IPMB bus is disposed between the primary BMC and the standby BMC.
  • an IPMB bus is disposed between the primary BMC and the standby BMC.
  • the data exchange between the BMC and the IPMC node of the peripheral board through the IPMI specifically includes: the BMC performs logical operations of reading data and writing data to the IPMI through the local bus; wherein, when the BMC actively writes data to the IPMC, the IPMI is in the host mode; When the data is actively written to the BMC, the IPMI is in the slave mode.
  • the default working mode of the IPMI is the slave receive mode. After receiving a packet in the slave receive mode, the slave exits the slave. Mode, waiting for the BMC to determine its working mode; IPMI performs data conversion between the local bus interface and the I2C interface, and data transmission between the I2C interface and the IPMC.
  • the logic operation of the BMC to read data and write data to the IPMI through the local bus specifically includes: the BMC writing data to the IPMI through the local bus includes the following processing: writing data to the write data buffer register in the IPMI, and writing a data in the BMC
  • the write enable of the write data buffer register is actively closed, and the sending task is handed over to the IPMI.
  • the write enable of the write data buffer register is enabled, and the BMC software is opened.
  • BMC reads data to IPMI through the local bus, including the following processing: After receiving the reception interrupt reported by the local bus channel, the BMC reads the length register in the IPMI to obtain the length of the data packet to be fetched, and then The contents of the packet are read out in bytes in the data register in IPMI until the length register and the data register are read out.
  • the method further includes: IPMI statistics the status of the data packet exchanged between the BMC and the IPMC and reporting.
  • the embodiment of the present invention further provides an ATCA chassis of an advanced telecommunication computing architecture, which includes: an ATCA board with a plurality of slots in the ATCA frame, and an ATCA board inserted in the slot, each ATCA board including two mains
  • the control board and at least one node board, each node board is provided with an intelligent platform management controller IPMC
  • the baseboard management controller BMC is integrated on two main control boards, and each main control board is provided with an intelligent platform management interface.
  • IPMI IPMI
  • the BMC on each main control board performs point-to-point star connection with IPMC of each node board and IPMI of another main control board through IPMI.
  • the BMC exchanges data with the IPMC node of the peripheral board through IPMI.
  • BMC and IPMI exchange data through local bus.
  • IPMI exchanges data with each IPMC node of peripheral board through independent distributed I2C-based multi-channel IPMB bus.
  • the total number of I2C-based multi-channel IPMB bus provided by IPMI and peripheral board The
  • the BMCs on the two main control boards are the primary BMC and the standby BMC respectively, and an IPMB bus is disposed between the primary BMC and the standby BMC.
  • an IPMB bus is disposed between the primary BMC and the standby BMC.
  • the BMC is specifically configured to: perform logical operations of reading data and writing data to the IPMI through the local bus; the IPMI is specifically configured to: perform data conversion between the local bus interface and the I2C interface, and data between the I2C interface and the IPMC.
  • Transmission, in which the BMC actively writes data to the IPMC the IPMI is in the host mode; when the IPMC actively writes data to the BMC, the IPMI is in the slave mode, the default working mode of the IPMI is the slave receiving mode, and the IPMI is received in the slave receiving mode. After completing a packet, it exits the slave receive mode and waits for the BMC to determine its mode of operation.
  • the BMC is specifically configured to: write data to the write data cache register in the IPMI, and after the BMC writes an IPMB communication protocol data packet, actively close the write enable of the write data cache register, and hand the send task to the IPMI.
  • the IPMI After receiving the receiving interrupt reported by the local bus channel, read the length register in the IPMI, obtain the length of the data packet to be fetched, and read the contents of the data packet in bytes from the data register in the IPMI until the length The register and data register are read out; the IPMI is specifically set to: After the IPMB communication protocol packet is sent, the write enable of the write data buffer register is enabled, and the BMC software continues to write data for transmission.
  • the IPMI is further configured to: report the status of the data packet exchanged between the BMC and the IPMC and report the status.
  • the distributed IPMB connection method solves the problem that the IPMB communication bandwidth is narrow and the single IPMC node is faulty, which causes the chassis management function to be in the prior art.
  • each The IPMB bus is independent. Any IPMB bus failure will not cause the whole frame management system to fail and improve the reliability of the system.
  • the chassis management controller can process each IPMB bus in parallel to improve system data response and processing speed.
  • FIG. 1 is a schematic diagram of an implementation of an IPCA dual bus connection architecture of an ATCA chassis in the prior art
  • FIG. 2 is a schematic diagram of an implementation of an IPMB dual-star connection architecture of an improved ATCA chassis in the prior art
  • FIG. 3 is a flowchart of a method for connecting a distributed intelligent platform management bus IPMB according to an embodiment of the present invention
  • FIG. 4 is a schematic diagram of a distributed IPMB connection architecture in an ATCA chassis according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a 24-way IPMB interface provided by IPMI according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a state transition in the real-time IPMI interface of the present invention.
  • the present invention provides a distributed intelligent platform management bus IPMB connection method and an ATCA chassis, in order to solve the problem that the IPMB communication bandwidth is narrow and the single IPMC node is faulty in the prior art.
  • a distributed IPMB bus connection method is implemented, and an Intelligent Platform Management Interface (IPMI) device is integrated in the Baseboard Management Controller (BMC) node, and the BMC software is provided to provide a distributed IPMB bus channel management ATCA rack.
  • IPMI Intelligent Platform Management Interface
  • the BMC node and the IPMI device exchange data through the parallel bus channel; IPMI provides independent IPMB bus channel and IPMC node of the peripheral board to realize data exchange, so that the data of the peripherally distributed IPMC node can be processed in parallel at the BMC node. Faster system response. Further, the design of independent communication of each channel can avoid the failure of a certain node to affect the management of the entire chassis.
  • the embodiment of the present invention further provides an ATCA chassis of an advanced telecommunication computing architecture, which includes an ATCA frame having multiple slots and an ATCA board inserted in the slot.
  • the ATCA board includes two main control boards. And at least one node board, the ATCA board has an intelligent platform management controller IPMC, wherein the baseboard management controller BMC is integrated on two main control boards respectively, and the BMC of each main control board passes the IPMI interface and each The IPMC of the node board and the IPMI of the other main control board are point-to-point star connections.
  • the IPMI on the main control board provides independent I2C signals to complete the distributed connection of the IPMB management bus.
  • an active/standby baseboard management controller (BMC) is included for overall system management control; and an intelligent platform management controller (IPMC) is provided, which is configured to manage real-time monitoring information such as temperature and voltage of the control system node; Includes Intelligent Platform Management Bus (IPMB), set to provide protocol specifications for communication between BMC and IPMC.
  • IPMB Intelligent Platform Management Bus
  • the invention also provides a connection between the BMC and the IPMC.
  • the channel between the BMC and the IPMC is distributed through an Intelligent Platform Management Interface (IPMI), providing independent IPMB channels to manage IPMC nodes on the peripheral board.
  • IPMI Intelligent Platform Management Interface
  • Data is transmitted between the IPMI and the BMC via the parallel bus.
  • a distributed intelligent platform management bus IPMB connection method for an advanced telecommunications computing architecture ATCA chassis, wherein an ATCA frame having multiple slots is disposed in a slot.
  • the ATCA board, each ATCA board includes two main control boards and at least one node board.
  • Each node board is provided with an intelligent platform management controller IPMC, and the baseboard management controller BMC is integrated in two main control boards.
  • the BMCs on the two main control boards are respectively the primary BMC and the standby BMC, and an IPMB bus is disposed between the primary BMC and the standby BMC, and one of them is used as the primary BM. The other is used as an IPMC node.
  • the standby BMC switches to the primary BMC.
  • FIG. 3 is a flowchart of a method for a distributed intelligent platform management bus IPMB connection according to an embodiment of the present invention. As shown in FIG. 3, a distributed intelligent platform management bus IPMB connection method according to an embodiment of the present invention includes the following processing:
  • Step 301 Set an intelligent platform management interface IPMI on each main control board, and the BMC on each main control board performs a point-to-point star through the IPMI and the IPMC of each node board and the IPMI on the other main control board. connection;
  • Step 302 The BMC exchanges data with the IPMC node of the peripheral board through the IPMI, wherein the BMC and the IPMI exchange data through the local bus, and the IPMI exchanges data with each IPMC node of the peripheral board through the independently distributed I2C-based multiple IPMB bus.
  • the total number of I2C-based multi-channel IPMB buses provided by IPMI corresponds to the number of peripheral boards.
  • step 302 the BMC exchanges data with the IPMC node of the peripheral board through the IPMI, including:
  • Step 1 The BMC performs logical operations of reading data and writing data to the IPMI through the local bus.
  • the IPMI is in the host mode.
  • the IPMC actively writes data to the BMC, the IPMI is in the slave mode, IPMI.
  • the default working mode is the slave receiving mode. After receiving a packet in the slave receiving mode, it exits the slave receiving mode and waits for the BMC to determine its working mode.
  • the logical operation of the BMC to read data and write data to the IPMI through the local bus specifically includes:
  • the BMC writes data to the IPMI through the local bus, including the following processing: writing data to the write data buffer register in the IPMI, and actively writing off the write enable of the write data buffer register after the BMC writes an IPMB communication protocol data packet, and will send The task is handed over to IPMI. After IPMI sends the IPMB communication protocol packet, the write enable of the write data buffer register is enabled, and the BMC software continues to write data for transmission.
  • the BMC reads data to the IPMI through the local bus, including the following processing: after receiving the receiving interrupt reported by the local bus channel, the BMC reads the length register in the IPMI, obtains the length of the data packet to be fetched, and then takes the data register from the IPMI. The contents of the packet are read out in bytes until the length and data registers are read out.
  • Step 2 IPMI performs data conversion between the local bus interface and the I2C interface, and data transmission between the I2C interface and the IPMC.
  • the IPMI can also count the status of the data packet exchanged between the BMC and the IPMC and report the status.
  • FIG. 4 is a schematic diagram of a distributed IPMB connection architecture of an ATCA chassis according to an embodiment of the present invention, as shown in FIG. 4, including: an active and standby baseboard management controller (BMC), an intelligent platform management interface (IPMI), and an intelligent platform management. Controller (IPMC).
  • BMC active and standby baseboard management controller
  • IPMI intelligent platform management interface
  • IPMC intelligent platform management. Controller
  • the BMC implements the conversion between the user data and the IPMB protocol package, and completes the management and control of the monitoring information of the peripheral nodes of the rack.
  • the IPMI module implements data conversion between the LOCAL BUS interface (1 bus in Figure 5) and the I2C interface, and data transfer between the I2C interface and the I2C device (2 bus in Figure 5).
  • IPMI connects the BMC node to the IPMC node.
  • the communication between the BMC and the IPMC includes: the BMC actively writes data to the IPMC and the IPMC actively writes data to the BMC.
  • the IPMI When the BMC actively writes data to the IPMC, the IPMI is in the host mode; when the IPMC actively writes data to the BMC, the IPMI acts as the slave mode.
  • the default working mode of IPMI should be the slave receiving mode.
  • the current method is to exit the slave receive mode after receiving a packet in the slave receive mode.
  • the BMC performs the logical operation of reading and writing data through the Local Bus and the IPMI internal cache, and interacts with the internal information of the IPMI through the Local Bus module in the IPMI device, including parameter configuration, state information acquisition, and communication with the I2C bus.
  • the operation of the BMC to send data to the send buffer (Master Write) process the BMC software completes writing data to the write data buffer register in the channel, and after writing an IPMB communication protocol data packet, actively closes the write cache write enable register.
  • the BMC software completes the operation of writing a complete packet to the IPMI device.
  • the write enable of the data cache register will be enabled, and the BMC software can continue to write data for transmission.
  • the BMC reads the data from the receive buffer (Slave Receive) process: the BMC software finds that the channel receives the receive interrupt, and determines that the type is the receive interrupt.
  • the BMC reads the length register to get the length of the data packet to be fetched, and then from the data register. The contents of the data packet are read out in bytes until the length register and the data register are read out. After the length register and the data register are read empty, if a register is empty and a register is not empty, it will be regarded as an exception. Abnormal interruption.
  • the functions that the IPMI interface needs to implement include: implementing an independent distributed multi-channel I2C function, adopting an LVTTL level, and a clock frequency of 100 KHz; implementing a function of initiating a master sender mode (Master Write); The main receiving mode (Master Read) function; realizes the response initiated by the master device, implements the slave mode (Slave Receive) function; implements the Local Bus interface with the host CPU; realizes the conversion of the Local Bus and the multi-channel I2C interface; Implement the necessary statistical functions and provide software monitoring and receiving packet status.
  • the primary BMC and the IPMC of each node board are connected by an I2C signal (one SDA data line and one SCL clock line) provided by the IPMI interface.
  • the total number of I2C signal channels provided by IPMI corresponds to the number of peripheral node boards, and an additional IPMI interface is connected to the standby BMC.
  • the I2C signals between the channels are independent of each other, and the BMC can simultaneously communicate with any peripheral node board in point-to-point.
  • the I2C topology of the standby master is the same as that of the active master.
  • the primary backup state is negotiated between the primary BMC and the standby BMC through the I2C channel provided by the IPMI.
  • the status of the active and standby is not fixed.
  • the two BMCs compete for the active and standby states to obtain the primary BMC management system function.
  • the other BMC is in the system as the managed node. If the current primary BMC fails, the negotiation is in the standby state and is in the managed node.
  • the current standby BMC becomes the active state and completes the system management function.
  • the distributed IPMB bus implemented in the form of an IPMI interface is completely independent of each bus, and the BMC software can synchronously process the data reported by the peripheral IPMC node. At the same time, the interface is easy to expand, and only needs to modify the logic of IPMI to flexibly support different numbers of IPMC nodes.
  • FIG. 5 is a schematic diagram of an IPMI interface provided by IPMI according to an embodiment of the present invention. As shown in FIG. 5, a 24-way IPMB bus provided by an IPMI interface controls each IPMC node independently. You can monitor the 23 slots of the service board and provide one way to the main control board node.
  • Each IPMB bus provided by IPMI has the same state machine scheduling.
  • 6 is a schematic diagram of a state transition in the real-time IPMI interface of the present invention. As shown in FIG. 6, after the BMC enables the IPMI dispatcher, the IPMI dispatcher enters the slave state from the idle state to the slave state, and the slave receives the state. The priority is higher. If the IPMC as the host has data transmission, the state machine enters the slave receiving processing flow, and the user receives a packet or slows down. When the memory is full, it will enter the slave receive wait mode. If there is data transmission, it will automatically jump to the host send process; that is, the scheduler runs in the slave state by default, and the BMC software only needs to send data. Write to the send buffer, the transmission timing is handled by the IPMI dispatcher.
  • IPMI In the host transmit mode state, IPMI is in the host mode of the I2C protocol, and the IPMC is in the slave mode of the I2C protocol.
  • the BMC caches the data in the Master Transmit buffer (MTB) through the Local Bus interface.
  • MTB Master Transmit buffer
  • IPMI transmits the data to the IPMC, and the BMC can monitor the transmission process through the I2CSTAT provided by IPMI.
  • IPMI In the slave receive mode state, when the IPMC has data to report to the IPMI, the IPMC is in the host mode of the I2C protocol, and the IPMI is in the slave mode of the I2C protocol. IPMI receives the data sent from the IPMC. After receiving a packet, it writes the received length into the buffer and notifies the BMC to read it. The design in IPMI allows multiple packets to exist simultaneously in the data cache for each channel.
  • the length cache When the data cache is empty, the length cache must be empty; when the length buffer is empty, the data cache must also be empty, otherwise it is regarded as an error and the user is notified.
  • the default working state of the IPMI state machine is the slave receiving mode. Therefore, when the IPMC has data to report, it responds preferentially. If the IPMC always has data reported, the state machine will always work in the slave receive mode, and the slave receive mode has the highest priority. If the BMC sends data to the IPMI, the state machine waits for the opportunity to switch to the host transmit mode.
  • each IPMB bus is independent, and any IPMB bus failure does not cause a failure of the entire frame management system.
  • the chassis management controller can process each IPMB bus in parallel to improve system data response and processing speed.
  • an advanced telecommunications computing architecture ATCA chassis includes: an ATCA framework having multiple slots.
  • An ATCA board is inserted in the slot.
  • Each ATCA board includes two main control boards and at least one node board.
  • Each node board is provided with an intelligent platform management controller IPMC and a baseboard management controller BMC. They are integrated on two main control boards.
  • Each main control board is equipped with an intelligent platform management interface IPMI.
  • the BMC on each main control board passes IPMI and IPMC of each node board, and IPMI on the other main control board. For point-to-point star connection, BMC exchanges data with IPMC nodes of the peripheral board through IPMI.
  • IPMI passes independent distributed I2C-based multi-channel IPMB.
  • the line exchanges data with each IPMC node of the peripheral board.
  • the total number of I2C-based multiple IPMB buses provided by IPMI corresponds to the number of peripheral boards.
  • the BMCs on the two main control boards are the primary BMC and the standby BMC respectively, and an IPMB bus is disposed between the primary BMC and the standby BMC.
  • an IPMB bus is disposed between the primary BMC and the standby BMC.
  • the BMC is specifically configured to: perform logical operations of reading data and writing data to the IPMI through the local bus;
  • the IPMI is specifically configured to: perform data conversion between the local bus interface and the I2C interface, and data transmission between the I2C interface and the IPMC.
  • the IPMI When the BMC actively writes data to the IPMC, the IPMI is in the host mode; the IPMC actively writes data to the BMC.
  • IPMI When IPMI is in slave mode, IPMI's default mode of operation is slave receive mode. After receiving a packet in slave receive mode, IPMI exits slave receive mode and waits for BMC to determine its mode of operation.
  • the BMC is specifically configured to: write data to the write data cache register in the IPMI, and after the BMC writes an IPMB communication protocol data packet, actively close the write enable of the write data cache register, and hand the transmission task to the IPMI.
  • the length register in the IPMI is read, the length of the data packet to be fetched is obtained, and the contents of the data packet are read out from the data register in the IPMI until the length register. And the data register is read empty;
  • the IPMI is specifically set to: After the IPMB communication protocol packet is sent, the write enable of the write data buffer register is enabled, and the BMC software continues to write data for transmission.
  • the IPMI is further configured to: report the status of the data packet exchanged between the BMC and the IPMC and report the status.
  • FIG. 4 it includes: an active and standby baseboard management controller (BMC), an intelligent platform management interface (IPMI), and an intelligent platform management controller (IPMC).
  • BMC baseboard management controller
  • IPMI intelligent platform management interface
  • IPMC intelligent platform management controller
  • the BMC implements the conversion between the user data and the IPMB protocol package, and completes the management and control of the monitoring information of the peripheral nodes of the rack.
  • the IPMI module implements data conversion between the LOCAL BUS interface (1 bus in Figure 5) and the I2C interface, and data transfer between the I2C interface and the I2C device (2 bus in Figure 5).
  • IPMI connects the BMC node to the IPMC node.
  • the communication between the BMC and the IPMC includes: the BMC actively writes data to the IPMC and the IPMC actively writes data to the BMC.
  • the IPMI When the BMC actively writes data to the IPMC, the IPMI is in the host mode; when the IPMC actively writes data to the BMC, the IPMI acts as the slave mode.
  • the default working mode of IPMI should be the slave receiving mode.
  • the BMC performs the logical operation of reading and writing data through the Local Bus and the IPMI internal cache, and interacts with the internal information of the IPMI through the Local Bus module in the IPMI device, including parameter configuration, state information acquisition, and communication with the I2C bus.
  • the operation of the BMC to send data to the send buffer (Master Write) process the BMC software completes writing data to the write data buffer register in the channel, and after writing an IPMB communication protocol data packet, actively closes the write cache write enable register.
  • the BMC software completes the operation of writing a complete packet to the IPMI device.
  • the write enable of the data cache register will be enabled, and the BMC software can continue to write data for transmission.
  • the BMC reads the data from the receive buffer (Slave Receive) process: the BMC software finds that the channel receives the receive interrupt, and determines that the type is the receive interrupt.
  • the BMC reads the length register to get the length of the data packet to be fetched, and then from the data register. The contents of the data packet are read out in bytes until the length register and the data register are read out. After the length register and the data register are read empty, if a register is empty and a register is not empty, it will be regarded as an exception. Abnormal interruption.
  • the functions that the IPMI interface needs to implement include: implementing an independent distributed multi-channel I2C function, adopting an LVTTL level, and a clock frequency of 100 KHz; implementing a function of initiating a master sender mode (Master Write); The main receiving mode (Master Read) function; realizes the response initiated by the master device, implements the slave mode (Slave Receive) function; implements the Local Bus interface with the host CPU; realizes the conversion of the Local Bus and the multi-channel I2C interface; Implement the necessary statistical functions and provide software monitoring and receiving packet status.
  • the primary BMC and the IPMC of each node board are connected by an I2C signal (one SDA data line and one SCL clock line) provided by the IPMI interface.
  • the total number of I2C signal channels provided by IPMI corresponds to the number of peripheral node boards, and an additional IPMI interface is connected to the standby BMC.
  • the I2C signals between the channels are independent of each other, and the BMC can simultaneously communicate with any peripheral node board in point-to-point.
  • the I2C topology of the standby master is the same as that of the active master.
  • the primary backup state is negotiated between the primary BMC and the standby BMC through the I2C channel provided by the IPMI.
  • the status of the active and standby is not fixed.
  • the two BMCs compete for the active and standby states to obtain the primary BMC management system function.
  • the other BMC is in the system as the managed node. If the current primary BMC fails, Then, the negotiation is in the standby state and is in the managed node; the current standby BMC becomes the active state, and the system management function is completed.
  • the distributed IPMB bus implemented in the form of an IPMI interface is completely independent of each bus, and the BMC software can synchronously process the data reported by the peripheral IPMC node. At the same time, the interface is easy to expand, and only needs to modify the logic of IPMI to flexibly support different numbers of IPMC nodes.
  • FIG. 5 is a schematic diagram of an IPMI interface provided by IPMI according to an embodiment of the present invention. As shown in FIG. 5, a 24-way IPMB bus provided by an IPMI interface controls each IPMC node independently. You can monitor the 23 slots of the service board and provide one way to the main control board node.
  • Each IPMB bus provided by IPMI has the same state machine scheduling.
  • 6 is a schematic diagram of a state transition in the real-time IPMI interface of the present invention. As shown in FIG. 6, after the BMC enables the IPMI dispatcher, the IPMI dispatcher enters the slave state from the idle state to the slave state, and the slave receives the state. The priority is higher. If the IPMC as the host has data transmission, the state machine enters the slave receiving processing flow. When the user receives a packet or the buffer is full, it will enter the slave receiving standby mode. Data transmission will automatically jump to the host sending process; that is, the dispatcher defaults to the receiving state, the BMC software only needs to write the sending data to the sending buffer, and the sending timing is handled by the IPMI dispatcher.
  • IPMI In the host transmit mode state, IPMI is in the host mode of the I2C protocol, and the IPMC is in the slave mode of the I2C protocol.
  • the BMC caches the data in the Master Transmit buffer (MTB) through the Local Bus interface.
  • MTB Master Transmit buffer
  • IPMI transmits the data to the IPMC, and the BMC can monitor the transmission process through the I2CSTAT provided by IPMI.
  • IPMI In the slave receive mode state, when the IPMC has data to report to the IPMI, the IPMC is in the host mode of the I2C protocol, and the IPMI is in the slave mode of the I2C protocol. IPMI receives the data sent from the IPMC. After receiving a packet, it writes the received length into the buffer and notifies the BMC to read it. The design in IPMI allows multiple packets to exist simultaneously in the data cache for each channel.
  • the length cache When the data cache is empty, the length cache must be empty; when the length buffer is empty, the data cache must also be empty, otherwise it is regarded as an error and the user is notified.
  • the default working state of the IPMI state machine is the slave receiving mode. Therefore, when the IPMC has data to report, it responds preferentially. If the IPMC always has data reported, the state machine will always work in the slave receive mode, and the slave receive mode has the highest priority. If the BMC sends data to the IPMI, the state machine waits for the opportunity to switch to the host transmit mode.
  • each IPMB bus is independent, and any IPMB bus failure does not cause a failure of the entire frame management system.
  • the chassis management controller can process each IPMB bus in parallel to improve system data response and processing speed.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
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Abstract

L'invention concerne un procédé de raccordement réparti pour bus de gestion de plates-formes intelligentes (IPMB) et un châssis ATCA. Le châssis ATCA doté d'une pluralité d'emplacements est muni de cartes ATCA insérées dans les emplacements. Chaque carte ATCA comporte deux cartes principales de commande et au moins une carte de nœud, chaque carte de nœud portant un IPMC; un BMC est intégré respectivement sur les deux cartes principales de commande, et une IPMI est disposée sur chaque carte principale de commande; le BMC sur chaque carte principale de commande est en liaison en étoile de point à point avec l'IPMC sur chaque carte de nœud et l'IPMI sur l'autre carte principale de commande; le BMC échange des données avec le nœud IPMC d'une carte périphérique via l'IPMI; le BMC échange des données avec l'IPMI via le bus local, et l'IPMI échange des données avec chaque nœud IPMC de la carte périphérique via des bus IPMB répartis indépendamment à trajets multiples basés sur I2C, le nombre total des bus IPMB à trajets multiples basés sur I2C mis en place par l'IPMI correspondant au nombre des cartes périphériques.
PCT/CN2014/086972 2014-03-07 2014-09-19 Procédé de raccordement réparti pour bus de gestion de plates-formes intelligentes et châssis atca WO2015131516A1 (fr)

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