CN110312999B - 基于软件配置/策略分发的PCIe盘阵列的动态划分 - Google Patents
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Abstract
本公开涉及用于基于软件配置/策略分发对PCIe盘阵列进行动态划分的方法和系统。在一个实施例中,至少一个PCIe交换机具有可操作地连接到相应CPU的输入端口以及至少一个输出端口。复用器连接在至少一个PCIe交换机的(一个或多个)输出端口与PCIe盘阵列(例如NVMe SSD)之间,并且被配置为在第一配置下将PCIe盘阵列连接到一个x4端口模式或两个x2端口模式下的单个PCIe交换机,或者在第二配置下将PCIe盘阵列连接到x2端口模式下的两个PCIe交换机。该复用器可以在运行时在第一配置和第二配置之间动态地切换。切换可以例如响应于NVMe SSD的热插拔或策略改变而发生。
Description
技术领域
本公开总地涉及通信领域,并且更具体地涉及用于基于软件配置/策略分发对外围组件互连快速(PCIe)盘阵列进行动态划分的方法和系统。
背景技术
在数据中心存储解决方案中的PCIe盘阵列中增加使用固态驱动器(SSD)不仅大大减少了输入/输出(I/O)等待时间,而且还能够通过在无需大量盘机箱的情况下提供高得多的I/O性能来缓解I/O瓶颈。然而,鉴于性能的极大提升,网络控制器和其他网络设备的性能因此已经在处理大量增加的I/O流量方面远远落后。
为了处理控制器瓶颈,已经开发了NVMe(非易失性存储器快速)接口,其由于中央处理单元CPU和SSD之间的直接PCIe连接(这导致线性可扩展的带宽和等待时间的相当大的减少)而获得胜过传统的SAS/SATA接口(SAS=串行连接SCSI;SATA=串行高级技术附件)的很大优势。然而,另一方面,当前的NVMe实现与CPU太紧密耦合,使得SSD的故障转移可能引起问题。为了放松CPU和SSD之间的现有技术紧密耦合,存储解决方案已经涉及PCIe交换机,其不仅在本地扩展了有限的CPU PCIe带宽,而且还隔离SSD故障问题,代价是增加的CPU到SSD等待时间。
为了处理I/O性能的网络瓶颈,超融合已成为数据中心基础设施的新趋势。与传统的集中存储(诸如SAN(存储区域网络),其中主机经由网络访问作为整体的存储池)相比,超融合基本上是通过在本地将计算和存储组件集成在一起作为节点并将节点聚合成集群来实现的分布式存储平台。超融合充分利用节点内的本地化I/O操作,这显著卸载网络流量。然而,由于分布式存储要求(诸如数据副本和同步),在节点到节点网络上仍有高流量。
附图说明
为了提供对本公开以及其特征和优点的更全面的理解,结合附图参考以下描述,其中相似的参考标号表示相似的部分,其中:
图1A至1E示出了简化示意图,其示出了根据本公开的一些实施例的用于通过PCIe交换机连接CPU和NVMe SSD的基本拓扑;
图2是示出根据本公开的一些实施例的用于通过具有CPU级和交换机级冗余的PCIe交换机连接多个CPU和NVMe SSD的另一基本拓扑的简化示意图;
图3示出了根据本公开的一些实施例的动态可配置的NVMe SSD接口架构;
图4示出了图3的可动态配置的NVMe SSD接口架构的简化结构;
图5示意性地示出了表1中列出的NVMe SSD的可能的工作状态转换;
图6示意性地示出了用于热添加NVMe SSD的处理流程;
图7示意性地示出了用于热移除NVMe SSD的处理流程;并且
图8示意性地示出了用于动态修改SSD配置策略的处理流程。
具体实施方式
在独立权利要求中阐述了本发明的各方面,并且在从属权利要求中阐述了优选特征。一个方面的特征可以单独应用于每个方面或者与其他方面组合应用。
本公开的各种实施例涉及基于软件配置/策略分发来动态地划分PCIe盘阵列。基本思想是以在交换机SW0、SW1的下游端口与非易失性存储器快速(NVMe)固态驱动器(SSD)之间连接的复用器的形式提供冗余的PCIe链路,其可以根据检测到的交换机或SSD故障状态和/或应用策略/要求来动态地切换。如本文所使用的,在本公开的上下文中,术语“在运行时”和“动态地”描述了例如在切换所影响的过程正在进行的同时(而不是作为静态预定义的某事物的结果)发展或发生的活动或事件。更具体而言,术语“热插拔”、“热添加”和“热移除”是指诸如所描述的NVMe SSD之类的计算机硬件的“运行时”替换。
在本公开的一个方面,提出了一种装置,其具有:至少一个PCIe交换机,该PCIe交换机具有可操作地连接到相应CPU的输入端口和至少一个输出端口;和至少一个复用器,该复用器被连接在至少一个PCIe交换机的输出端口与PCIe盘阵列之间,并被配置为在第一配置下将PCIe盘阵列连接到一个x4端口模式或两个x2端口模式下的单个PCIe交换机,或者在第二配置下将PCIe盘阵列连接到x2端口模式下的两个PCIe交换机,并在运行时在第一配置和第二配置之间动态地切换。标记“x2”指示2通道配置(2个物理端口-x2端口模式),其中“x4”指示4通道配置(4个物理端口=x4端口模式)。端口可以用光纤来实现。
在实施例中,第一配置和第二配置之间的切换可以响应于PCIe盘阵列的配置策略的改变而发生。
在另一个实施例中,第一配置和第二配置之间的切换可以响应于PCIe盘阵列的意外添加(热添加)而发生。
在又一个实施例中,第一配置和第二配置之间的切换可以响应于NVMe SSD的意外移除(热移除)而发生。
在另一个实施例中,第一配置和第二配置之间的切换可以基于预定的时序要求而顺序地发生。
在又一个实施例中,当在第一PCIe交换机处检测到数据流量拥塞时,至少一个复用器被配置为将一部分数据流量从第一PCIe交换机重定向到第二PCIe交换机,以便传输到PCIe盘阵列。
在又一个实施例中,当在x4端口模式下操作时,至少一个复用器被配置为在检测到第一PCIe交换机的故障时将所有数据流量从第一PCIe交换机迁移到第二PCIe交换机,以便传输到PCIe盘阵列。
在又一个实施例中,PCIe盘阵列可以是NVMe SSD。
在又一个实施例中,该装置可以包括控制逻辑设备,该控制逻辑设备可操作地连接到至少一个PCIe交换机和至少一个复用器,并且被配置为监视PCIe盘阵列信息和PCIe盘配置策略执行。
在又一个实施例中,控制逻辑设备可以为了通信而连接到管理平台,该管理平台管理控制逻辑设备的策略。
在本公开的另一方面,提出了一种用于在将CPU连接到NVMe SSD的配置之间动态切换的方法。该方法包括在第一配置下将PCIe盘阵列连接到一个x4端口或两个x2端口模式下的单个PCIe交换机的输出端口,或者在第二配置下将PCIe盘阵列连接到x2端口模式下的两个PCIe交换机的输出端口,以及在运行时在第一配置与第二配置之间动态地切换。
在一个实施例中,可以通过插入在PCIe盘阵列和PCIe盘阵列之间的至少一个复用器来动态地切换PCIe盘阵列。
在另一个实施例中,可以响应于PCIe盘阵列的配置策略的改变、PCIe盘阵列的意外添加(热添加)、NVMe SSD的意外移除(热移除)或其组合而动态地切换PCIe盘阵列。
在又一个实施例中,当在第一PCIe交换机处检测到数据流量拥塞时,可以将一部分数据流量从第一PCIe交换机重定向到第二PCIe交换机,以便传输到PCIe盘阵列。
在又一个实施例中,当在x4端口模式下操作时,在检测到第一PCIe交换机的故障时可以将所有数据流量迁移到第二PCIe交换机,以便传输到PCIe盘阵列。
在又一个实施例中,动态切换可以包括利用可操作地连接到至少一个PCIe交换机和至少一个复用器配置的控制逻辑设备来管理PCIe盘阵列的信息和至少一个复用器的状态信息。
如本领域技术人员将认识到的,可以通过计算机程序来控制本公开的各方面,特别是与PCIe盘阵列的动态划分的各个方面有关的功能。因此,本公开的其他方面涉及用于执行根据本文描述的各种实施例的方法的系统、计算机程序、机制和构件。这样的系统、计算机程序、机制和构件可以被包括在各种网络设备中,例如,管理平台和管理程序。计算机程序可以例如被下载(更新)到现有的网络设备和系统(例如,到现有的路由器、交换机、各种控制节点等),或者在这些设备和系统的制造时被存储。
在又一方面,本申请涉及一种或多种非暂时性计算机可读存储介质,其编码有软件,该软件包括计算机可执行指令并且当由计算机的处理器执行时可操作来执行根据本文描述的各种实施例的方法。
在又一方面,本申请涉及一种包括多个计算机的系统,每个计算机以一对一的对应关系连接到第一切换构件,第二切换构件的每个输入连接到每个第一切换构件的输出并且第二切换构件的输出连接到存储构件,其中第二切换构件被配置成在运行时将存储构件动态地连接到第一切换构件的输出。
本公开的附加特征和优点将在接着的描述中阐述,并且部分地将从描述中显而易见,或者可以通过实践本文公开的原理来学习。借助于在所附权利要求中特别指出的仪器和组合,可以实现和获得本公开的特征和优点。本公开的这些和其他特征从以下描述和所附权利要求将变得更加明显,或者可以通过实践本文阐述的原理来容易地学习。
外围组件互连快速(PCIe)架构的概述
一个互连结构架构包括外围组件互连快速(PCIe)架构。PCIe的主要目标是使来自不同供应商的组件和设备能够在开放式架构中互操作,该开放式架构跨越多个细分市场;客户端(台式和移动),服务器(标准和企业),以及嵌入式和通信设备。PCIe是为各种各样未来的计算和通信平台定义的高性能通用I/O互连。一些PCIe属性(诸如其使用模型、加载-存储架构、以及软件接口)已通过其修订版得到维护,而先前的并行总线实现已被高度可扩展的完全串行接口替代。较新版本的PCIe利用点对点互连、基于交换的技术和分组化协议的进展来提供新水平的性能和特征。电源管理、服务质量(QoS)、热抽换/热插拔支持、数据完整性和错误处理是PCI Express所支持的一些高级特征。
然而,不利的是,许多具有单个x4NMVe SSD的传统的基于交换的技术不具有高可靠存储产品中所需的交换机级冗余。为了克服该点,设计了双x2端口NVMe SSD,其可以连接到2个交换机以获得冗余。交换机与SSD之间的连接在所有传统方法中都是固定的,并且不允许基于策略在运行时在双端口模式和单端口模式之间切换。在本公开的各种实施例中提出并说明的设计试图减轻这些缺点。
图1(a)至1(c)示出了用于经由插入的PCIe交换机来连接CPU和NVMe SSD的基本拓扑。图1(a)示出了仅具有单个CPU和单个交换机SW0的拓扑。对于更大数量的SSD,可以要么以如图1(b)所示的具有两个交换机SW0、SW1(其各自的输入连接到单个CPU)的并行布置来扩展这些拓扑,要么以如图1(c)所示的具有两层交换机(其中上层的交换机SW0的输入连接到单个CPU,并且下层的交换机SW1、SW2、...SWn连接在交换机SW0与NVMe SSD之间)的级联布置来扩展这些拓扑。在图1(a)至(c)的所有这三种拓扑中,SSD在x4PCIe模式下操作,并且CPU与SSD之间的连接是固定的或硬连线的,这使这些拓扑失去灵活性并降低了该类存储解决方案的可靠性。
可以通过对示例性交换机SW0和SW1的MR-IOV(多根I/O虚拟化)特征和NVMe SSD的双端口特征进行组合来实现CPU级冗余(CPU冗余),其中两个CPU将被连接到图1(a)中的拓扑的交换机SW0的上游(US)端口,从而允许将每个CPU切换到任何NVMe SSD。该拓扑在图1(d)中示出。同时,如图1(e)所示,可以实现交换机级冗余,其中每个交换机SW0和SW1的下游(DS)端口可以连接到任何NVMe SSD。这将被称为交换机冗余。根据应用和CPU的I/O带宽要求,两个交换机SW0和SW1可以在主动/主动或主动/被动模式下工作。CPU冗余和交换机冗余可以被有利地组合以在CPU级和在交换机级两者提供双冗余,其在图2中用CPU0和CPU1以及交换机SW0和SW1示出。
如上所述,上述拓扑具有CPU冗余或交换机冗余或两者兼有,而不迫使NMVe SSD在双2x端口模式下工作以促进冗余连接。还存在如下情况:需要灵活性来在运行时在双端口模式和单端口模式之间切换NVMe SSD。所提出的设计试图实现在不限制可以在存储系统中使用的SSD类型的情况下提供冗余。
可切换NVMe SSD接口架构的示例实施例
图3中示出了所提出的NVMe SSD接口架构300的顶层设计。考虑到冗余和交换机端口资源之间的权衡,双交换机设计可能是最佳选择。基本思想是在交换机SW0、SW1与NVMeSSD之间提供冗余的PCIe链路,其可以根据检测到的交换机或SSD故障状态和/或应用策略/要求进行切换。该设计具有总共四个不同的组件,即:交换机;在这里示例性地示出为FPGA(现场可编程门阵列)的硬件控制逻辑设备;在8639驱动器背板连接器处连接的NVMe SSD;以及上层管理平台,诸如本示例中的Cisco UCSM(统一计算系统管理器)。
8639驱动器背板连接器是68引脚连接器,并被设计为支持PCI Express以及热抽换和热移除,在有和没有先前系统通知(意外热移除)两种情况下都支持。
数据平面中的PCIe信号(双箭头)及其在时钟平面中的参考时钟(虚线)、控制平面中的边带信号(包括双端口使能DUALPORTEN#/接口检测IFDET#/热抽换检测PRSNT#/PCIe设备复位PERST#/电力使能PWREN)对于促进所有SSD操作时序控制是必要的,并被指派给8639连接器上的特定引脚。控制平面信号直接或间接地在FPGA上连接到Expander_SWl和Expander_SW2。信号EN是使能信号。
本公开仅解决交换机SW0、SW1的下游端口与NVMe SSD之间的数据平面中的流量。对于交换机SW0、SW1的上游端口与一个或多个CPU之间的连接,可以使用图1所示的拓扑和图2所示的冗余拓扑中的任何一种。换句话说,下游端口与NVMe SSD的连接性不受上游端口的拓扑的影响。将会理解,所示出的CPU、交换机和NVMe SSD的数量仅仅是示例,并且可以使用可以以所描述的方式互连和寻址的任何数量的这种设备。
硬件控制逻辑设备(在本文中也简称为FPGA)处理所有控制逻辑,诸如SSD信息收集和报告、策略执行以及可选的指示灯(LED)管理。管理平台在管理程序和FPGA之间进行接口,收集SSD信息,并以策略的形式提供应用要求。
将FPGA连接到管理平台的虚拟通道可以经由多种方式(例如以太网)实现。为了支持NVMe的单端口模式和双端口模式两者,系统必须能够在运行时修改交换机SW0、SW1的下游端口的分叉。在本公开的上下文中,术语“在运行时”描述了动态地(即,在切换所影响的过程正在进行的同时,而不是静态预定义的某事物的结果)发展或发生的活动或事件。更具体而言,术语“热插拔”是指诸如所描述的NVMe SSD之类的计算机硬件的“运行时”替换。这是通过发送用来切换ASIC(专用集成电路)本身的重新配置命令(MRPC=PMC PCIe交换机中的多播远程过程调用命令)来实现的。交换机SW0、SW1与2:1PCIe复用器(PCIe MUX)的连接在PCIe端口切换的下游实现,以便不管是单个x4SSD被附接还是双x2SSD被附接都获得冗余。该运行时切换基于策略或软件配置。
表1中总结了双交换机冗余情况的所有有效SSD配置。
表1
在图3所示的NVMe SSD接口架构300的顶部设计图中,两个CPU(CPU0和CPU1)各自连接到交换机SW0、SW1的相应上游(US)端口。注意,CPU0和SW1之间以及CPU1和SW0之间没有连接。每个交换机的下游(DS)端口为了数据传送而连接到两个2:1PCIe复用器(MUX)310、312中的每一个MUX的相应输入端口,即,每个CPU可以将数据传送到MUX 310、312中的每一个和从MUX 310、312中的每一个接收数据。DUALPORTEN#被禁用(低=0),使得NVMe SSD在x2模式下操作。在图3中,MUX 310、312中的每一个MUX的输入端口在x2模式下连接到8639连接器上的相应PCIe端子(即,PCIe[1:0]和PCIe[3:2]),并从那里连接到未示出的NVMe SSD。可能的数据链路取决于交换机选择,并且x2模式下的相应工作状态在表1中列为W1-W4。
注意,图3中未示出FPGA的所有组件,并且对于未在图3中未示出的任何组件,参考图4。
为了更容易理解图3中的NVMe SSD接口架构300的顶部设计图,现在参考图4所示的示例性系统400,其仅使用单个复用器410。将假设DUALPORTEN#被启用(高=1),使得与8639连接器上的端子PCIe[3:0]连接的未示出的NVMe SSD在x4模式(x4PCIe)下操作。然后,数据平面中的流量可以只在表1中的工作状态W5和工作状态W6之间切换。在该示例中仅使用一个MUX 410。交换机选择信号SW_SEL_0和SW_SEL_1两者都被选择性地施加到MUX 410。图4中所示的两个LED(红色LED;蓝色LED)是状态指示器,并且与系统400的操作无关。
图4中所示的I2C GPIO扩展器是可以经由I2C接口(I2C=集成电路间)使用的通用输入/输出(GPIO)扩展器,并允许多于一个设备连接到计算机上的单个端口。
在第一工作状态W5下,REF_CLK_P0在8639连接器的引出线处被启用(=1),而REF_CLK_P1被禁用(未使用)。FPGA上的I2C GPIO扩展器SW0为高=1,而FPGA上的I2C GPIO扩展器SW1为低=0。在工作状态W5下SW_SEL_0和SW_SEL_1两者都为低(=0)的情况下,8639连接器上的4端口(x4)PCIe[3:0]通过交换机SW0而连接到NVMe SSD。PE_RST_P0是信令SW0,而PE_RST_P1在图4中未被连接,因为在该配置中未使用第二2:1RST MUX。同样地,由于在工作状态W5下SW1未被寻址,因此在图4中也未使用图3的第二2:1PCIe MUX 312和第二2:1CLKMUX。上述x4工作状态W5的情况基本上相当于工作状态W1,其中SW_SEL_0=SW_SEL_1=0并且DUALPORTEN#被禁用。
在第二工作状态W6下,REF_CLK_P0在8639连接器的引出线处被启用,而REF_CLK_P1被禁用(未使用)。FPGA上的I2C GPIO扩展器SW0为高=1,而FPGA上的I2C GPIO扩展器SW1为低=0。在工作状态W6下SW_SEL_0和SW_SEL_1两者都为高(=1)的情况下,8639连接器上的4端口(x4)PCIe[3:0]通过交换机SW1而连接到NVMe SSD。PE_RST_P0是信令SW1,而PE_RST_P1在图4中未被连接,因为如上所述在该配置中未使用第二2:1RST Mux。同样地,由于在工作状态W6下SW0未被寻址,因此在图4中也未使用图3的第二2:1PCIe Mux和第二2:1CLKMux。上述x4工作状态W5的情况基本上相当于工作状态W1,其中SW_SEL_0=SW_SEL_1=0并且DUALPORTEN#被禁用。总而言之,来自SW0的x4PCIe总线和来自SW1的x4PCIe总线经由2:1PCI2Mux选择性地(但从不同时地)连接到在PCIe[3:0]引脚处在连接器8639处端接的x4PCIe总线,并最终连接到NVMe SSD(未示出)。
如上面参考图3提到,其他四个有效工作状态W1-W4都采用两个x2端口而不是单个x4端口。工作状态W1和W2由于它们与工作状态W5和W6的类似性已经在上面得到讨论。对于工作状态W3和W4,Ref_CLK_P0和Ref_CLK_P1两者均为高,并且SW_SEL_0或SW_SEL_1为高,而另一个为低。这选择来自SW0的端口1和来自SW1的端口2用于工作状态W5,以及来自SW0的端口2和来自SW1的端口1用于工作状态W5。在图5中示意性地示出这些工作状态W1-W6之间的切换。
示例性工作状态转换
在图5所示的所有可能的工作状态转换当中,以下三个示例旨在展示该设计的一些益处。
示例1:从工作状态_W5到工作状态_W1的转换
考虑到从高带宽单流到较低带宽多流的不同应用I/O操作样式,存储虚拟化平台需要提供它们之间进行切换的灵活性,并且从工作状态_W5到工作状态_Wl的转换促进虚拟化堆栈充分利用SSD的高并行I/O操作能力。
示例2:从工作状态_W5到工作状态_W3的转换
可以利用该转换来实现交换机级流量卸载。在其中SW0的上游端口正在遭受流量堵塞的一种场景下,其下游SSD的一半然后可以被重定向到SW1,从而显著提高整体I/O数据流速度。该转换提供了平衡存储负载的可能性。
示例3:从工作状态_W5到工作状态_W6的转换
该转换的最常见应用场景是交换机故障转移。例如,假设SW0已发生故障。然后,可以通过将往返SW0的下游端口的所有流量迁移到SW1来避免数据丢失。由于该冗余在x4单端口模式下实现,因此不会由于双端口操作而发生I/O性能损失。
另一应用可以应用于一种交换机布置,其中图2中的每个交换机连接到单个CPU,即,CPU0和SW1之间以及CPU1和SW0之间的连接将不存在。在需要将大量冷数据(即,很少被访问的数据)从CPU0传输到CPU1的情况下,例如当新节点被添加到当前分布式存储网络中时,需要将用户数据的副本从当前节点传递到该新节点。传统的解决方案将涉及两个CPU(CPU0,CPU1)之间的通信网络,从而产生重流量负载。利用例如在图3中示出的上述示例性设计,CPU0可以首先将所有所需数据克隆到一个NVMe SSD上,然后将该NVMe SSD整体迁移到CPU1。换句话说,利用CPU内部带宽(在一个节点内制作克隆SSD),从而节省了CPU间网络带宽成本。
现在将参考图6所示的过程流程图来描述NVMe SSD的热添加期间的操作。
FPGA和交换机初始化
在任何热插拔之前,必须给系统通电并加载固件。在NVMe SSD可以被成功检测和配置之前,FPGA将禁用交换机SW0、SW1与NVMe SSD之间的所有I2C GPIO扩展器接口。
交换机SW0、SW1需要在初始化期间启用动态分叉和动态划分特征。交换机还应当为物理下游(DS)端口保留足够数量的逻辑P2P(PCIe到PCIe)网桥。对于每个堆栈,然后将以x2粒度配置所有DS端口。当向下分发策略时,可以通过配置命令来组合2个x2端口以作为1个x4端口工作。在枚举期间,将为每个逻辑P2P网桥指派其自己的主/辅/从属总线编号。这是根复合体(root complex)的任务,根复合体将处理器和存储器子系统连接到由一个或多个交换机设备组成的PCI Express交换结构。
对于与图1中的拓扑(c)的布置类似的级联交换机,顶层SW执行枚举。在本公开的上下文中,所公开的过程仅涉及直接与NVMe SSD接口的底部交换机。
意外SSD热添加
图6示意性地示出了用于热添加NVMe SSD的过程600。过程600在610处开始。FPGA在612处首先感测指示新插入的NVMe SSD的IFDET#的切换。由该切换触发,FPGA然后将轮询SSD E2PROM内容并将内容报告给管理平台。
通常,用户将经由管理平台为该SSD指派一个特定的应用策略,管理平台向FPGA提供最新的策略。这可以是缺省的配置策略或例如由用户响应于应用更新而更新的配置策略。
FPGA需要根据策略配置图3和图4中的所有MUX设备。只有在已经成功执行所有配置之后,才将启用I2C GPIO扩展器接口。
在614处,交换机读取断言的IFDET#和SSD的DUALPORTEN#。然后,在步骤616处,交换机将如在图3的示例中那样将分叉配置为x2,或者如在图4的示例中那样将分叉配置为x4,与DUALPORTEN#信号状态相称。此后,在618处,交换机给SSD通电,取消断言PERST#,并启动PCIe链路训练过程以进入正常操作模式。
意外SSD热移除
图7示出了用于意外SSD热移除的过程800。当在步骤714处启动SSD移除时,在716处向FPGA报告取消断言的IFDET#信号的丢失,这将在718处自动禁用通向交换机的I2CGPIO扩展器接口。在720处检测到链路丢失将在722处清理SSD配置空间,之后可以在724处执行由SSD的供应商指定的完整热移除过程。也可以通过PCIe链路的丢失来触发热移除。当热移除过程结束时,交换机在726处向FPGA发送热移除完成标志。
SSD配置策略的动态修改
可以根据改变的应用要求在运行时修改SSD配置策略。现在将参考图8中的流程图描述相关联的过程800。
在812处,基于应用更新来更新SSD的配置策略。具体而言,这通过执行图7中描述的热移除过程的至少一些步骤来完成(参见图7中的过程700),但是实际上将不必在物理上移除NVMe SSD,这意味着PCIe链路可能仍然是活动的。然后,交换机在816处在热移除过程完成时通知FPGA,并设置标志。在一个示例中,交换机可以在热移除过程期间激活闪烁灯(未示出),然后在热移除过程终止时停止闪烁。热移除过程的细节不是本公开的一部分,并且通常由交换机的供应商规定。在818处,在接收到热移除完成信号之后,FPGA将根据新策略(参见表1)来配置更新的DUALPORTEN#和SW_SEL_0/1信号。当重新配置完成时,FPGA将断言FPGA_CONFG_DONE信号。然后,交换机可以在820处重新分叉其下游端口并重新训练PCIe链路。当热添加SSD时(参见图6中的过程600),不需要执行过程800。
所公开的实施例代表一种整合的解决方案,该解决方案用于在运行时以x2端口粒度灵活地和动态地修改NVMe SSD与PCIe交换机之间的连接。根据本公开的一些实施例,一个NVMe SSD可以连接到一个x4端口模式/两个x2端口模式下的单个交换机,或者连接到x2端口模式下的两个交换机。然后可以动态地切换这些不同的连接场景,而无需管理员干预。
通过(在双端口和单端口之间)切换NVMe SSD工作模式并基于特定时序要求顺序地改编交换机的下游划分策略来实现该灵活性。
利用该灵活性,虚拟化堆栈现在获得了多一级的自由度来以更加平衡和有效的方式调度其I/O流量。除此之外,交换机级冗余在单端口模式下在本地实现,而没有由于双端口操作而导致的I/O性能损失代价。
总之,这些示例性实施例可以提供至少以下优点:
a)通过支持不同的基于策略的面向应用的存储I/O操作来提高灵活性。
b)通过动态平衡交换机之间的I/O流量来提高性能。
c)通过提供交换机级冗余来提高可靠性。
d)通过将所需数据从一个CPU克隆到一个NVMe SSD上并且此后将这些数据从NVMeSSD迁移到另一个CPU来减少CPU间流量负载。
总之,本公开涉及用于基于软件配置/策略分发对PCIe盘阵列进行动态划分的方法和系统。在一个实施例中,至少一个PCIe交换机具有可操作地连接到相应CPU的输入端口和至少一个输出端口。复用器连接在至少一个PCIe交换机的一个或多个输出端口与PCIe盘阵列(例如NVMe SSD)之间,并且被配置为在第一配置下将PCIe盘阵列连接到一个x4端口或两个x2端口模式下的单个PCIe交换机,或者在第二配置下将PCIe盘阵列连接到x2端口模式下的两个PCIe交换机。该复用器可以在运行时在第一配置和第二配置之间动态地切换。切换可以例如响应于NVMe SSD的热插拔或策略改变而发生。
上述的方法、硬件、软件、固件或代码的实施例可以经由在可由处理元件执行的机器可访问、机器可读、计算机可访问或计算机可读的介质上存储的指令或代码来实现。非暂时性机器可访问/可读介质包括以机器(诸如计算机或电子系统)可读的形式提供(即,存储和/或传输)信息的任何机制。例如,非暂时性机器可访问介质包括:随机存取存储器(RAM),诸如静态RAM(SRAM)或动态RAM(DRAM);ROM;磁性或光学存储介质;闪存设备;电存储设备;光存储设备;声学存储设备;用于保持从暂时(传播的)信号(例如,载波、红外信号、数字信号)接收的信息的其他形式的存储设备;等等,它们将被与可以从其接收信息的非暂时性介质区分开。
用于给执行本发明的实施例的逻辑编程的指令可以存储在系统中的存储器内,诸如DRAM、缓存、闪存或其他存储装置。另外,可以经由网络或通过其他计算机可读介质来分发指令。因此,机器可读介质可以包括用于以机器(例如,计算机)可读的形式存储或传输信息的任何机制,但不限于:软盘,光盘,光盘只读存储器(CD-ROM),和磁光盘,只读存储器(ROM),随机存取存储器(RAM),可擦除可编程只读存储器(EPROM),电可擦除可编程只读存储器(EEPROM),磁卡或光卡,闪存,或者用于经由电、光、声或其他形式的传播信号(例如,载波、红外信号、数字信号等)通过因特网传输信息的有形机器可读存储装置。因此,计算机可读介质包括适合于以机器(例如,计算机)可读的形式存储或传输电子指令或信息的任何类型的有形机器可读介质。
贯穿本说明书对“一个实施例”或“实施例”的引用意味着结合该实施例描述的特定特征、结构或特性被包括在本发明的至少一个实施例中。因此,短语“在一个实施例中”或“在实施例中”在贯穿本说明书的各个地方的出现不一定都指的是同一实施例。另外,特定特征、结构或特性可以在一个或多个实施例中以任何合适的方式组合。
在前述说明书中,已经参考特定示例性实施例给出了详细描述。然而,将会显而易见的是,在不脱离如在所附权利要求中阐述的本发明的更广泛的精神和范围的情况下,可以对其进行各种修改和改变。因此,说明书和附图将被以说明性意义而非限制性意义看待。另外,实施例和其他示例性语言的前述使用不一定指代相同的实施例或相同的示例,而是可以指代不同且独特的实施例,以及可能相同的实施例。
还应该强调的是,尽管在所附的从属权利要求中单独列出了某些特征,但是这些特征可以在单个实施例中彼此组合,除非被明确排除或在逻辑上不可能。
Claims (19)
1.一种用于对PCIe(外围组件互连快速)盘阵列进行划分的装置,包括:
至少一个PCIe(外围组件互连快速)交换机,其具有可操作地连接到相应CPU的输入端口并具有至少一个输出端口;和
至少一个复用器,其连接在所述至少一个PCIe交换机的所述至少一个输出端口与PCIe盘阵列之间,并被配置为在第一配置下将所述PCIe盘阵列连接到一个x4端口模式或两个x2端口模式下的单个PCIe交换机,或者在第二配置下将所述PCIe盘阵列连接到x2端口模式下的两个PCIe交换机,并被配置为在运行时在所述第一配置与所述第二配置之间动态地切换,
其中,在所述第一配置与所述第二配置之间的切换响应于PCIe盘阵列在运行时的意外添加(热添加)和/或PCIe盘阵列在运行时的意外移除(热移除)而发生。
2.如权利要求1所述的装置,其中,在所述第一配置与所述第二配置之间的切换响应于所述PCIe盘阵列的配置策略的改变而发生。
3.如权利要求1所述的装置,其中,在所述第一配置与所述第二配置之间的切换基于预定的时序要求而顺序地发生。
4.如权利要求1至3中任一项所述的装置,其中,当在第一PCIe交换机处检测到数据流量拥塞时,所述至少一个复用器被配置为将一部分数据流量从所述第一PCIe交换机重定向到第二PCIe交换机,以进行去往/来自所述PCIe盘阵列的传输。
5.如权利要求1至3中任一项所述的装置,其中,当在x4端口模式下操作时,所述至少一个复用器被配置为在检测到第一PCIe交换机的故障时将所有数据流量从所述第一PCIe交换机迁移到第二PCIe交换机,以进行去往/来自所述PCIe盘阵列的传输。
6.如权利要求1至3中任一项所述的装置,其中,所述PCIe盘阵列包括非易失性存储器快速固态驱动器(NVMe SSD)。
7.如权利要求1至3中任一项所述的装置,还包括:控制逻辑设备,其可操作地连接到至少一个PCIe交换机和所述至少一个复用器,并且被配置为监视PCIe盘阵列信息和PCIe盘配置策略执行。
8.如权利要求7所述的装置,其中,所述控制逻辑设备被连接来与管理平台通信,所述管理平台管理所述控制逻辑设备的策略。
9.一种用于对PCIe(外围组件互连快速)盘阵列进行划分的方法,包括:
将至少一个复用器在代表第一配置的单x4端口模式或双x2端口模式下连接在所述PCIe盘阵列与单个PCIe交换机的输出端口之间,以及在代表第二配置的x2端口模式下连接到两个PCIe交换机的相应输出端口,和
在运行时利用所述至少一个复用器在所述第一配置与所述第二配置之间动态地切换,
其中,在所述第一配置与所述第二配置之间的动态切换响应于PCIe盘阵列在运行时的意外添加(热添加)或PCIe盘阵列在运行时的意外移除(热移除)或这两者而发生。
10.如权利要求9所述的方法,其中,所述PCIe盘阵列包括非易失性存储器快速固态驱动器(NVMe SSD)。
11.如权利要求9或10所述的方法,其中,在所述第一配置与所述第二配置之间的动态切换响应于所述PCIe盘阵列的配置策略的改变而发生。
12.如权利要求9或10所述的方法,还包括:当在第一PCIe交换机处检测到数据流量拥塞时,将一部分数据流量从所述第一PCIe交换机重定向到第二PCIe交换机,以进行去往/来自所述PCIe盘阵列的传输。
13.如权利要求9或10所述的方法,还包括:当在x4端口模式下操作时,在检测到第一PCIe交换机的故障时将所有数据流量迁移到第二PCIe交换机,以进行去往/来自所述PCIe盘阵列的传输。
14.如权利要求9或10所述的方法,其中,动态切换包括:利用可操作地连接到至少一个PCIe交换机和至少一个复用器配置的控制逻辑设备来管理所述PCIe盘阵列的信息和所述至少一个复用器的状态信息。
15.一种计算机程序,体现在非暂时性计算机可读介质中并且包括程序指令,所述程序指令在被加载到计算机存储器中并由处理器执行时使所述处理器进行以下操作:
在第一配置和第二配置之间切换至少一个复用器,所述至少一个复用器连接在PCIe(外围组件互连快速)盘阵列与一个或多个PCIe交换机的一个或多个输出端口之间,其中所述至少一个复用器在所述第一配置下将所述PCIe盘阵列连接到一个x4端口模式或两个x2端口模式下的单个PCIe交换机的输出端口,或者在所述第二配置下将所述PCIe盘阵列连接到x2端口模式下的两个PCIe交换机的输出端口,
其中,所述至少一个复用器在运行时在所述第一配置和所述第二配置之间动态地切换,
其中,动态切换响应于以下各项而发生:PCIe盘阵列在运行时的意外添加(热添加)、PCIe盘阵列在运行时的意外移除(热移除)、所述PCIe盘阵列的配置策略的改变、或其组合。
16.如权利要求15所述的计算机程序,其中,所述计算机程序使控制逻辑设备传送所述PCIe盘阵列和所述至少一个复用器的状态信息。
17.一种用于对PCIe(外围组件互连快速)盘阵列进行划分的装置,包括:
用于下述操作的构件:将至少一个复用器在代表第一配置的单x4端口模式或双x2端口模式下连接在所述PCIe盘阵列与单个PCIe交换机的输出端口之间以及在代表第二配置的x2端口模式下连接到两个PCIe交换机的相应输出端口,和
用于在运行时利用所述至少一个复用器在所述第一配置与所述第二配置之间动态地切换的构件,
其中,在所述第一配置与所述第二配置之间的切换响应于PCIe盘阵列在运行时的意外添加(热添加)和/或PCIe盘阵列在运行时的意外移除(热移除)而发生。
18.根据权利要求17所述的装置,还包括用于实施根据权利要求10至14中任一项所述的方法的构件。
19.一种计算机程序、计算机程序产品或计算机可读介质,其包括指令,所述指令当由计算机执行时使该计算机执行权利要求9至14中任一项所述的方法的步骤。
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