WO2012008346A1 - Input device and method for manufacturing same - Google Patents

Input device and method for manufacturing same Download PDF

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Publication number
WO2012008346A1
WO2012008346A1 PCT/JP2011/065511 JP2011065511W WO2012008346A1 WO 2012008346 A1 WO2012008346 A1 WO 2012008346A1 JP 2011065511 W JP2011065511 W JP 2011065511W WO 2012008346 A1 WO2012008346 A1 WO 2012008346A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
wiring
alloy
wiring portion
input device
Prior art date
Application number
PCT/JP2011/065511
Other languages
French (fr)
Japanese (ja)
Inventor
秀幸 橋本
清 佐藤
雅弘 頓所
一聡 五十嵐
Original Assignee
アルプス電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by アルプス電気株式会社 filed Critical アルプス電気株式会社
Priority to CN201180019161.XA priority Critical patent/CN102870072B/en
Priority to JP2011552252A priority patent/JP5039859B2/en
Priority to KR1020127019504A priority patent/KR101227288B1/en
Publication of WO2012008346A1 publication Critical patent/WO2012008346A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C22C9/06—Alloys based on copper with nickel or cobalt as the next major constituent
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/047—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using sets of wires, e.g. crossed wires
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0445—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Definitions

  • the present invention relates to an input device capable of detecting an input coordinate position, and more particularly to the structure of a wiring unit.
  • the following patent document discloses an invention related to an input device (touch panel).
  • the input device is provided with a pair of opposing substrates, and the respective substrates are joined via an adhesive layer.
  • An electrode portion is formed in the input area of each substrate, and when the operator operates the surface of the input device with a finger or an input pen, for example, the operation position can be detected based on a change in capacitance. .
  • the wiring part electrically connected to the electrode part formed in the input area is routed.
  • the wiring portion is formed of, for example, a Cu single layer.
  • Cu is excellent in electrical characteristics and can reduce the cost of materials at low cost.
  • the wiring portion is formed of a Cu single layer, corrosion such as oxidation progresses, and a change with time of the wiring resistance becomes large, and there is a problem that a stable wiring resistance can not be obtained.
  • the surface of the wiring portion is covered with, for example, an optical transparent adhesive layer (OCA).
  • OCA optical transparent adhesive layer
  • Patent Document 1 describes that a protective layer is formed on the surface of the wiring layer (see column [0041] of Patent Document 1), but even if the protective layer is formed, the material cost is kept as low as possible. It is necessary. In addition, if different etching solutions are used for the wiring layer and the protective layer, and two etching solutions are required, the manufacturing cost increases and the manufacturing process becomes complicated.
  • the present invention is intended to solve the above-described conventional problems, and in particular, it is an object of the present invention to provide an input device capable of reducing the change with time of wiring resistance by improving the structure of the wiring portion.
  • Another object of the present invention is to provide a method of manufacturing an input device in which the amount of recession due to side etching can be reduced and the etchant can be a single solution.
  • the input device in the present invention is A substrate, an electrode portion provided in an input area on the surface of the substrate, and a wiring portion electrically connected to the electrode portion in a non-input area on the surface of the substrate located outside the input area Equipped with a substrate
  • the wiring portion is characterized by comprising: a wiring main layer formed of Cu; and a surface protection layer formed on the surface of the wiring main layer and made of a Cu alloy having a thickness smaller than that of the wiring main layer. It is said that.
  • the surface protective layer is preferably formed of a CuNi alloy.
  • the Ni composition ratio in the CuNi alloy is preferably in the range of 5 wt% to 35 wt%.
  • the Ni composition ratio is more preferably in the range of 15 wt% to 25 wt%.
  • the maximum amount of recession due to side etching can be reduced, the etching rate can be relatively increased, the processing time can be shortened, and the productivity can be improved.
  • the surface of the said wiring part is preferably applicable to the structure currently covered by the optical transparent adhesive layer.
  • the configuration of the wiring portion of the present invention in the state where the surface of the wiring portion is covered with the optical transparent adhesive layer, corrosion such as oxidation can be appropriately suppressed, and the change with time of the wiring resistance can be effectively suppressed. .
  • the method of manufacturing the input device according to the present invention is It has a base material, an electrode part provided in an input area on the surface of the base material, and a wiring part electrically connected to the electrode part in a non-input area on the surface of the substrate located outside the input area.
  • Equipped with a substrate Forming a Cu layer on the surface of the base material in the non-input area, and forming a Cu alloy layer thinner than the Cu layer on the surface of the Cu layer; Forming a mask layer for forming the wiring portion on the surface of the Cu alloy layer;
  • the Cu alloy layer and the Cu layer not covered by the mask layer are continuously removed by wet etching, and a wiring main layer formed of Cu and a surface protection formed of Cu alloy on the surface of the wiring main layer Forming the wiring portion comprising a layer; Removing the mask layer; It is characterized by having.
  • the amount of receding due to side etching is formed as a Cu single layer by forming the wiring portion in a laminated structure of the wiring main layer made of Cu and the surface protection layer made of Cu alloy. It can be smaller than in the case. Further, in the present invention, at the time of wet etching, the Cu alloy layer and the Cu layer can be continuously etched by the etching solution of one solution, the manufacturing cost can be suppressed, and complication of the manufacturing process can be suppressed.
  • the Cu layer is formed on the entire surface of the conductive layer, and a Cu alloy layer is further formed on the entire surface of the Cu layer; Forming the wiring portion composed of the wiring main layer made of Cu and a surface protection layer made of a Cu alloy in the non-input area by wet etching; Leaving the conductive layer formed in the input region in the shape of the electrode portion and leaving the conductive layer formed in the non-input region under the wiring portion to remove the unnecessary conductive layer; It is preferable to have Thus, the electrode portion and the wiring portion can be formed simply and in a predetermined pattern.
  • the Cu alloy layer is preferably formed of a CuNi alloy layer.
  • the Ni composition ratio in the CuNi alloy is preferably in the range of 5 wt% to 35 wt%. Furthermore, the Ni composition ratio is more preferably in the range of 15 wt% to 25 wt%.
  • the input device of the present invention it is possible to suppress the corrosion such as oxidation with respect to the wiring portion, and to suppress the change with time of the wiring resistance to a smaller level as compared to the conventional case where the wiring portion is formed of a Cu single layer. Moreover, material cost can be held down by forming the surface protective layer of a Cu alloy.
  • the amount of recession due to side etching can be reduced by forming the wiring portion in a laminated structure of the wiring main layer made of Cu and the surface protection layer made of Cu alloy. Moreover, when performing a wet etching process with respect to a Cu alloy layer and a Cu layer, it can etch continuously with the etching liquid of one solution, can suppress a manufacturing cost, and can suppress complication of a manufacturing process. .
  • FIG. 2 is a partially enlarged longitudinal cross-sectional view of the input device shown in FIG.
  • a partial longitudinal sectional view of the input device in another embodiment different from FIG. 5 (a) and 5 (b) are process drawings showing a method of manufacturing a wiring part in the present embodiment
  • FIG. 5 (c) is a partially enlarged longitudinal sectional view for explaining the amount of recession due to side etching
  • Explanatory drawing partially expanded longitudinal cross-sectional view for demonstrating a side etching in the prior art example which formed the wiring part by Cu single layer.
  • Top view of experimental sample, 7 is a graph showing the relationship between the test time and the resistance ratio in the conventional example in which the wiring portion is formed of a single Cu layer, using the experimental sample of FIG. 7;
  • FIG. 8 is a graph showing the relationship between the test time and the resistance ratio in an embodiment in which the wiring portion is formed of a Cu layer / CuNi layer, using the experimental sample of FIG. 7;
  • FIG. 8 is a graph showing the relationship between the Ni composition ratio and the resistance ratio in an embodiment in which the wiring portion is formed of a Cu layer / CuNi layer using the experimental sample of FIG.
  • FIG. 1 is an exploded perspective view of the input device 10 according to the present embodiment.
  • FIG. 2 is a partially enlarged vertical cross-sectional view of the input device shown in FIG. 1 in an assembled state, cut along the line AA and viewed from the arrow direction.
  • FIG. 3 is a partially enlarged vertical sectional view of the wiring portion in the present embodiment.
  • the input device 10 is configured to have a top plate 20, an upper substrate 21, a lower substrate 22, a flexible printed substrate 23, and the like.
  • the top plate 20 is formed of a plastic or glass substrate.
  • a decorative layer 18 is provided on the lower surface 20 b of the top plate 20, and as shown in FIG. 1, a colored non-transparent non-input area surrounding the periphery of the transparent input area 11 and the input area 11. It is divided into twelve.
  • the non-input area 12 is formed in a frame shape.
  • a lower electrode portion 14 formed of a transparent conductive layer such as ITO (Indium Tin Oxide) is formed on the surface of the lower base 24.
  • each lower electrode portion 14 extends along, for example, the X1-X2 direction of the XY plane, and a plurality of lower electrode portions 14 are arranged at intervals in the Y1-Y2 direction (see FIG. 1). In 1, only a part of the lower electrode portion 14 is shown).
  • the wiring lower layer 28 (see FIGS. 2 and 3) formed integrally with the lower electrode portion 14 and extending to the non-input area 12 and formed of the transparent conductive layer is a surface of the lower base 24. Is formed.
  • wiring portions 16 electrically connected to the lower electrode portions 14 as sensor portions formed in the input area 11 are routed. It is done.
  • the wiring sections 16 are respectively routed from the X1 side area and the X2 side area of the non-input area 12, and the tip of each wiring section 16 constitutes a connection section 17 in the Y2 side area of the non-input area 12.
  • the wiring portion 16 is formed on the wiring lower layer 28 extending integrally with the lower electrode portion 14.
  • the wiring portion 16 may be formed directly on the surface of the lower base material 24, the manufacturing process can be simplified by forming the wiring portion 16 so as to overlap on the wiring lower layer 28. Stability can be appropriately improved.
  • the wiring lower layer 28 is located under the wiring portion 16 and is not left on the surface of the lower base 24 between the wiring portions 16. Therefore, adjacent wiring parts 16 do not short circuit via the wiring lower layer 28.
  • the lower substrate 24 is made of a resin or glass such as translucent polyethylene terephthalate.
  • the lower base 24 can have a form in which a coat layer made of an insulating material such as polyester resin or epoxy resin is formed on the front and back of the resin base.
  • the upper electrode portion 13 formed of a transparent conductive layer such as ITO (Indium Tin Oxide) is formed on the surface of the upper base 25.
  • each upper electrode portion 13 extends along, for example, the Y1-Y2 direction of the XY plane, and a plurality of upper electrode portions 13 are arranged at intervals in the X1-X2 direction (see FIG. 1). In 1, only a part of the upper electrode portion 13 is shown).
  • the upper electrode portions 13 and the lower electrode portions 14 formed in the input region 11 in this manner are orthogonal to each other.
  • a wiring portion (not shown) electrically connected to each upper electrode portion 13 is routed around the non-input area 12.
  • a wiring lower layer formed integrally with the non-input area 12 from the upper electrode portion 13 and formed of the transparent conductive layer is formed.
  • the tip of each wiring portion formed on the upper substrate 21 constitutes a connection portion 15 shown in FIG.
  • the upper base material 25 is made of a resin or glass such as light transmitting polyethylene terephthalate.
  • the upper base material 25 can be made into the form by which the coat layer which consists of insulating materials, such as a polyester resin and an epoxy resin, was formed in front and back of a resin base material.
  • OCA optically transparent adhesive layer
  • the top plate 20 and the upper substrate 21 are joined via an optical transparent adhesive layer (OCA) 27.
  • OCA optical transparent adhesive layer
  • the lower substrate 22 and the upper substrate 21 are joined by the optically transparent adhesive layer 26 in a state where the respective electrode portions 13 and 14 of the lower substrate 22 and the upper substrate 21 face upward (to the top plate 20).
  • the lower substrate 22 and the upper substrate are in a state in which one of the electrode parts is directed downward (opposite to the top plate 20) or in a state in which both the electrodes 13 and 14 are directed downward. 21 may be joined.
  • the upper electrode part 13 may be formed in the upper surface 50a of one base material 50, and the lower electrode part 14 may be formed in the lower surface 50b.
  • the same members as those in FIG. 2 are denoted by the same reference numerals.
  • FIG. 3 shows an enlarged longitudinal sectional view of the wiring portion 16 which is cut along the line B--B of FIG. 1 and viewed from the arrow direction. Although only two wiring portions 16 are shown in FIGS. 1 and 3, in practice, about ten wiring portions 16 are provided in the non-input area 12 on the X1 side and the X2 side.
  • each wiring part 16 is formed on each wiring lower layer 28 which consists of a transparent conductive layer (ITO etc.) of a wiring pattern shape.
  • ITO transparent conductive layer
  • each wiring portion 16 is formed of a laminated structure of a wiring main layer 29 made of Cu and a surface protection layer 30 made of a Cu alloy formed on the surface (upper surface) 29 a of the wiring main layer 29. Ru.
  • the film thickness H1 of the wiring main layer 29 is about 100 to 150 nm
  • the film thickness H2 of the surface protective layer 30 is about 15 to 30 nm
  • the surface protective layer 30 is thinner than the wiring main layer 29.
  • the surface protective layer 30 is preferably formed of a CuNi alloy.
  • the Ni composition ratio in the CuNi alloy is preferably in the range of 5 wt% to 35 wt%, and more preferably in the range of 15 wt% to 25 wt%.
  • the entire surface of the wiring portion 16 is covered with the antirust film 38.
  • the material of the rustproof film 38 is not particularly limited.
  • benzotriazole can be used.
  • the rustproof film 38 may not be formed.
  • each wiring portion 16 is about 20 to 100 ⁇ m, and the distance T2 between each wiring portion 16 is about 20 to 100 ⁇ m.
  • a thin film is formed by sputtering or the like instead of printing and forming.
  • Each wiring portion 16 is formed in a fine pattern using a lithography technique.
  • FIG. 5 is a process chart showing a method of manufacturing the wiring portion 16 of the present embodiment. Each drawing shows a partially enlarged longitudinal sectional view in the manufacturing process.
  • a transparent conductive layer 34 such as ITO (Indium Tin Oxide) is formed on the entire surface of the lower substrate 24 by a sputtering method or a vapor deposition method.
  • transparent indicates a state in which the visible light transmittance is 80% or more. Furthermore, it is preferable that the haze value is 6 or less.
  • a Cu layer 31 is formed on the entire surface of the transparent conductive layer 34 by a sputtering method or a vapor deposition method.
  • the Cu layer 31 is more conductive than the transparent conductive layer 34.
  • a Cu alloy layer 32 is formed on the entire surface of the Cu layer 31 by a sputtering method or a vapor deposition method. At this time, the Cu alloy layer 32 is formed thinner than the Cu layer 31.
  • a resist layer is coated on the upper surface of the Cu alloy layer 32, and exposed and developed to leave a plurality of wiring pattern shapes in the non-input area 12 using the resist layer 35 as a mask layer.
  • the Cu alloy layer 32 and the Cu layer 31 not covered with the resist layer 35 are continuously removed by wet etching.
  • an etching solution containing ammonium persulfate can be used as the etching solution. And in this embodiment, it is possible to etch appropriately both Cu alloy layer 32 and Cu layer 31 with this etching solution of one solution.
  • the remaining Cu layer 31 is a wiring main layer 29 constituting most of the wiring portion 16, and the remaining Cu alloy layer 32 is a surface protection layer 30 constituting a surface layer of the wiring portion 16.
  • the width dimension of the wiring portion 16 is smaller than the width dimension of the resist layer 35 when the side surface 16a of the wiring portion 16 is affected by the side etching in the wet etching process of FIG.
  • the influence of side etching can be reduced compared to the conventional case, and hence the maximum amount of retraction T3 by side etching can be reduced, and controllability at the time of wet etching is excellent.
  • the transparent conductive layer 34b not covered with the resist layer 35 is removed, and a transparent conductive layer 34a having a wiring pattern substantially the same shape as the wiring portion 16 under the wiring portion 16 is removed. As a wiring lower layer 28. Then, the resist layer 35 is removed. Further, after that, an anticorrosive film 38 (see FIG. 3) may be applied to the surface of each wiring portion 16 by dip or the like.
  • the transparent conductive layer 34 is also formed on the entire surface of the input area 11, leaving the transparent conductive layer 34 on the input area 11 as the lower electrode portion 14 shown in FIG.
  • the unnecessary unnecessary transparent conductive layer 34 is removed.
  • the step of forming the lower electrode portion 14 and the step of leaving the transparent conductive layer 34a as the wiring lower layer 28 under the wiring portion 16 may be other than the method described above, and are not particularly limited. That is, in FIG.
  • the unnecessary transparent conductive layer 34b located between the wiring portions 16 is removed using the resist layer (mask layer) 35 for forming the wiring portions 16, but, for example, Then, the resist layer 35 is removed, and subsequently, a resist layer composed of a wiring pattern and an electrode pattern is formed on the transparent conductive layer 34 on each of the wiring portions 16 and on the input region 11, and the transparent layer not covered by the resist layer
  • the formation of the lower electrode portion 14 and the formation of the wiring lower layer 28 in the form of a wiring pattern located under each wiring portion 16 can be simultaneously performed.
  • the upper substrate 21 can also be formed by the same manufacturing method as that shown in FIG. Then, the lower substrate 22 and the upper substrate 21 are joined via the optically transparent adhesive layer (OCA) 26, and further, the upper substrate 21 and the top plate 20 are joined via the optically transparent adhesive layer (OCA) 27. Do.
  • the wiring portion 16 (not shown) formed on the upper substrate 21 can also be formed in a similar laminated structure.
  • the wiring portion is formed of a laminated structure of the wiring main layer 29 made of Cu and the surface protection layer 30 made of a Cu alloy formed on the surface 29 a of the wiring main layer 29.
  • the wiring portion 16 is formed in a laminated structure in which the surface protective layer 30 of Cu alloy is provided on the surface of the wiring main layer 29 of Cu. Therefore, corrosion such as oxidation can be suppressed, and as a result, it is possible to suppress the change with time of the wiring resistance to a small value.
  • the wiring portion 16 has a laminated structure of the wiring main layer 29 made of Cu and the surface protection layer 30 made of a Cu alloy, so that the amount of recession due to side etching is achieved. It can be made smaller than forming a wiring part by Cu single layer, and the controllability to side etching can be improved.
  • FIG. 6 shows a conventional example in which the wiring portion 37 is formed of a Cu single layer.
  • a resist layer 35 which is a mask layer is provided on the wiring portion 37.
  • the surface 37a of the wiring portion 37 is easily corroded by oxidation or the like under the influence of heat treatment or the like applied in the manufacturing process.
  • the surface 37a is discolored due to oxidation or the like, and the width dimension of the discoloring is larger than that of the present embodiment. Therefore, when the wet etching process is performed, the vicinity of the surface 37a of the wiring portion 37 located below the resist layer 35 is largely removed, and the amount of recession of the side surface 37b of the wiring portion 37 due to side etching becomes very large. Therefore, the adhesion to the resist layer 35 is also poor. In the worst case, the resist layer 35 was peeled off in the middle of the manufacturing process, and the wiring portion 37 could not be stably formed. Thus, in the conventional configuration, the controllability to the side etching is very bad.
  • the surface protection layer 30 made of a Cu alloy on the surface of the wiring portion 16 by providing the surface protection layer 30 made of a Cu alloy on the surface of the wiring portion 16, the occurrence of corrosion such as oxidation on the surface of the wiring portion 16 can be suppressed.
  • the maximum receding amount T3 can be effectively reduced compared to the conventional example of FIG. Controllability of side etching can be enhanced.
  • the Cu alloy layer 32 and the Cu layer 31 not covered with the resist layer 35 can be continuously wet-etched by the etching solution of one solution, the manufacturing cost can be suppressed, and the manufacturing process becomes complicated. Can be suppressed.
  • the surface protection layer 30 made of a Cu alloy is preferably formed of a CuNi alloy, and the Ni composition ratio is preferably 5 wt% to 35 wt%.
  • the Ni composition ratio is more preferably in the range of 15 wt% to 25 wt%. Thereby, the change with time of the wiring resistance can be effectively suppressed.
  • the maximum amount of recession due to side etching can be reduced, the etching rate can be relatively increased, processing time can be shortened, and productivity can be improved.
  • the etching rate of the CuNi alloy layer 32 can be increased when an etching solution containing ammonium persulfate is used, which is more effective.
  • the Cu alloy layer 32 and the Cu layer 31 can be continuously wet-etched by the etchant of one solution.
  • the film thickness H1 of the wiring main layer 29 of Cu is formed larger than the film thickness H2 of the surface protective layer 30 of Cu alloy.
  • the electrical characteristics of the wiring portion 16 can be made substantially equal to that of the conventional wiring portion formed of a Cu single layer, and the material cost can be suppressed to the same low price as that of the conventional example of a Cu single layer.
  • connection parts 15 and 17 shown in FIG. 1 are also parts integrally formed with the wiring part, they are formed in a laminated structure shown in FIG. Then, the connection portions 15 and 17 are exposed and crimped to the flexible printed circuit board 23.
  • the connection portions 15 and 17 are formed in a laminated structure of the wiring main layer 29 made of Cu and the surface protection layer 30 made of Cu alloy, and the surface protection layer 30 becomes a pressure contact surface with the flexible printed circuit 23. ing. According to the present embodiment, the pressure bonding strength between each of the connection portions 15 and 17 and the flexible printed circuit 23 can be kept good.
  • all the wiring portions formed on the lower substrate 22 and the upper substrate 21 be formed in a laminated structure of the wiring main layer 29 made of Cu and the surface protective layer 30 made of a Cu alloy. May be formed in a form other than the laminated structure shown in FIG.
  • the wiring structure of the present embodiment is not limited to the capacitance type input device.
  • the test sample shown in FIG. 7 was formed.
  • the reference numeral 40 denotes a wiring portion
  • the reference numeral 41 denotes a test pad
  • the reference numeral 42 denotes an optically transparent adhesive layer (OCA).
  • OCA optically transparent adhesive layer
  • the wiring portion 40 is formed of a Cu single layer.
  • the wiring portion 40 has a laminated structure of a Cu layer and a CuNi layer.
  • the Ni composition ratio of the CuNi alloy is 15 wt%.
  • the film thickness of the Cu layer was 150 nm, and the film thickness of the CuNi alloy layer was 20 nm.
  • the wiring width of the wiring portion 40 shown in FIG. 7 is 50 ⁇ m, and the wiring length is 30 mm.
  • the temperature is 60 ° C.
  • the humidity is 95%, before the start of the test
  • 65 After the time, 130, 240, 300, and 500 hours, the wiring resistance of the wiring portion 40 was measured.
  • FIG. 8 shows an experimental result of the conventional example in which the wiring portion 40 is formed of a Cu single layer.
  • the ordinate represents the wiring resistance before the start of the test (test time: 0 hours) as the initial resistance, and the wiring resistance at each test time is indicated by the electrical resistance change rate (%).
  • the electrical resistance change rate (%) is represented by (wiring resistance at each test time-initial resistance) / initial resistance.
  • the wiring resistance (the rate of change in electrical resistance (%)) may increase rapidly as the test time becomes longer. all right.
  • FIG. 9 shows experimental results of an example in which the wiring portion 40 is formed in a laminated structure of Cu layer / CuNi layer.
  • shaft made resistance value before a test start (test time: 0 hour) an initial stage resistance, and showed the wiring resistance in each test time by the electrical resistance change rate (%).
  • the electrical resistance change rate %.
  • the second optically transparent adhesive layer is used, as shown in FIG.
  • the Ni composition ratio of the CuNi alloy was changed to measure the wiring resistance.
  • the wiring resistances before the test start (test time: 0 hours) of the wiring parts 40 including CuNi layers having different Ni composition ratios are respectively taken as initial resistances, and each wiring part when the test time becomes 500 hours
  • the wiring resistance of 40 was shown by the electrical resistance change rate (%).
  • the Ni composition ratio As shown in FIG. 10, it is understood that when the Ni composition ratio is 35 wt% or less, the electrical resistance change rate (%) is almost stable in the range of 32% to 25%, and the fluctuation of the wiring resistance can be suppressed low.
  • the wiring resistance resistance ratio
  • the Ni composition ratio of the CuNi alloy is preferably in the range of 5 wt% to 35 wt%.
  • an ITO film is formed on a Si substrate, a Cu layer having a thickness of 150 nm is further formed by sputtering on the ITO film, and a CuNi layer having a thickness of 20 nm is further sputtered on the surface of the Cu layer. Formed. Subsequently, the etching rate was measured using an etching solution containing ammonium persulfate. In the experiment, the Ni composition ratio of the CuNi alloy was varied within the range of 0 wt% to 50 wt%, and the relationship between each Ni composition ratio and the etching rate was examined. The experimental results are shown in FIG.
  • a resist layer (mask layer) having a wiring width of 30 ⁇ m and an interval between wiring parts of 30 ⁇ m is formed by photolithography technology, and the CuNi alloy layer and Cu layer not covered with the resist layer are ammonium persulfate And a resist layer (mask layer) having a wiring width of 50 ⁇ m and an interval of each wiring portion of 50 ⁇ m by photolithography technology, and covered with the resist layer.
  • An experimental sample 2 was formed by wet etching a CuNi alloy layer and a Cu layer with an etchant containing ammonium persulfate.
  • the maximum amount of recession of the side etching was measured.
  • the maximum retraction amount is indicated by the maximum recess amount from the position of the side edge of the resist layer shown in FIG. 5C and FIG. 6 to the side surface on one side of the wiring portion.
  • the experimental results are shown in FIG. As shown in FIG. 12, it was found that as the Ni composition ratio of the CuNi alloy layer increases, the maximum amount of retraction in side etching gradually decreases.
  • FIG. 13 shows an experimental result of measuring the discolored width dimension of the surface of the wiring portion in the above-described Experimental Sample 1 and Experimental Sample 2. As shown in FIG. 13, it was found that the width dimension of the color change can be gradually reduced as the Ni composition ratio increases. The discoloration is caused by surface oxidation and the like.
  • the wiring portion has a laminated structure of a Cu layer and a CuNi alloy layer, and the preferable range of the Ni composition ratio of the CuNi alloy layer is 5 wt% to 35 wt% Within the range.
  • the change with time of the wiring resistance can be kept small (see FIGS. 9 and 10), and the etching rate of the CuNi alloy layer can be made as large as that of the Cu layer (see FIG. 11).
  • the width of the color change due to oxidation or the like formed can be reduced (see FIG. 13), and the maximum amount of retraction by side etching can be effectively reduced (see FIG. 12).
  • the more preferable range of the Ni composition ratio is in the range of 15 wt% to 25 wt%.
  • the surface protection effect that is, corrosion due to oxidation or the like was substantially equivalent to that of the example in which Cu / CuNi was used.
  • the wet etching process it is necessary to etch the NiFe layer and the Cu layer using different etching solutions, which requires two solutions, and the maximum amount of recession due to side etching is also Cu / CuNi. It turned out that it is easy to fluctuate compared with an example, and controllability to side etching is bad.
  • the etching solution is completed with one solution, the surface protection effect is bad, and further, the maximum amount of receding by side etching is larger than that in the example of Cu / CuNi. It turned out that the controllability to side etching is bad.
  • the wiring portion in a laminated structure of a Cu layer and a CuNi layer, which is excellent in the surface protection effect and the controllability of side etching, and further requires only one etching solution to facilitate the manufacturing process. It turned out that it can hold down low.

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Abstract

Provided is an input device which has an improved wiring unit structure and can reduce changes in wiring resistance that occur over time. The input device is provided with a base plate comprising: a substrate; an electrode unit provided in an input region of a substrate surface; and a wiring unit electrically connected to the electrode unit in a non-input region of the substrate surface positioned outside of the input region. The wiring unit (16) is constructed from: a main wiring layer (29) that is formed from Cu; and a surface protective layer (30) that is formed on a surface (29a) of the main wiring layer (29) and comprises a Cu alloy having a film thickness that is thinner than that of the main wiring layer (29).

Description

入力装置及びその製造方法INPUT DEVICE AND METHOD FOR MANUFACTURING THE SAME
　本発明は、入力座標位置を検出可能な入力装置に係り、特に配線部の構造に関する。 The present invention relates to an input device capable of detecting an input coordinate position, and more particularly to the structure of a wiring unit.
　下記特許文献には入力装置（タッチパネル）に関する発明が開示されている。入力装置には、対向する一対の基板が設けられ、各基板間が粘着層を介して接合されている。各基板の入力領域には電極部が形成されており、操作者が指や入力ペンで入力装置の表面を操作すると、例えば、静電容量変化に基づいて操作位置を検出できるようになっている。各基板の入力領域の周囲に位置する非入力領域には、入力領域に形成された電極部に電気的に接続された配線部が引き回される。 The following patent document discloses an invention related to an input device (touch panel). The input device is provided with a pair of opposing substrates, and the respective substrates are joined via an adhesive layer. An electrode portion is formed in the input area of each substrate, and when the operator operates the surface of the input device with a finger or an input pen, for example, the operation position can be detected based on a change in capacitance. . In the non-input area located around the input area of each substrate, the wiring part electrically connected to the electrode part formed in the input area is routed.
　各特許文献に記載されているように、配線部は、例えば、Ｃｕ単層で形成されていた。Ｃｕは電気的特性に優れ、また材料原価を安く抑えることが出来る。 As described in each patent document, the wiring portion is formed of, for example, a Cu single layer. Cu is excellent in electrical characteristics and can reduce the cost of materials at low cost.
　しかしながら、配線部をＣｕ単層で形成すると、酸化等の腐食が進行して、配線抵抗の経時変化が大きくなり、安定した配線抵抗を得ることが出来ない問題があった。配線部の表面は、例えば、光学透明粘着層（ＯＣＡ）で覆われている。しかしながら、光学透明粘着層で配線部の表面を覆っても完全に酸化等の腐食を食い止めることはできず、また光学透明粘着層中に含まれる物質によっても酸化の進行や膜変質が生じて、結局、安定した配線抵抗を得ることが出来なかった。 However, when the wiring portion is formed of a Cu single layer, corrosion such as oxidation progresses, and a change with time of the wiring resistance becomes large, and there is a problem that a stable wiring resistance can not be obtained. The surface of the wiring portion is covered with, for example, an optical transparent adhesive layer (OCA). However, even if the surface of the wiring portion is covered with the optically transparent adhesive layer, corrosion such as oxidation can not be completely prevented, and the progress of oxidation and film deterioration occur depending on the substance contained in the optically transparent adhesive layer, After all, stable wiring resistance could not be obtained.
　また配線部をＣｕ単層で形成した場合、製造工程でのウエットエッチング処理時、サイドエッチングによる後退量が大きくなることがわかった。このため、安定して所定の配線抵抗を有する配線部を形成することができなかった。 In addition, it was found that when the wiring portion is formed of a single Cu layer, the amount of recession due to side etching is increased at the time of the wet etching process in the manufacturing process. Therefore, it has been impossible to stably form a wiring portion having a predetermined wiring resistance.
　また特許文献１には配線層の表面に保護層を形成することが記載されているが（特許文献１の［００４１］欄等）、保護層を形成しても、できる限り材料原価を安く抑えることが必要である。また配線層と保護層の夫々に対して異なるエッチング液を用い、二液のエッチング液が必要となれば、製造コストの上昇、更には製造工程の煩雑化が問題となる。 In addition, Patent Document 1 describes that a protective layer is formed on the surface of the wiring layer (see column [0041] of Patent Document 1), but even if the protective layer is formed, the material cost is kept as low as possible. It is necessary. In addition, if different etching solutions are used for the wiring layer and the protective layer, and two etching solutions are required, the manufacturing cost increases and the manufacturing process becomes complicated.
特開２００８－６５７４８号公報JP 2008-65748 A 特開昭６３－１１３５８５号公報JP 63-113585 特開２００７－１８２２６号公報JP 2007-18226 A
　そこで本発明は上記従来の課題を解決するためのものであり、特に、配線部の構造を改良して、配線抵抗の経時変化が小さくできる入力装置を提供することを目的としている。 Accordingly, the present invention is intended to solve the above-described conventional problems, and in particular, it is an object of the present invention to provide an input device capable of reducing the change with time of wiring resistance by improving the structure of the wiring portion.
　更に本発明は、サイドエッチングによる後退量を小さくでき、またエッチング液が一液で足りる入力装置の製造方法を提供することを目的としている。 Another object of the present invention is to provide a method of manufacturing an input device in which the amount of recession due to side etching can be reduced and the etchant can be a single solution.
　本発明における入力装置は、
　基材と、基材表面の入力領域に設けられた電極部と、前記入力領域の外側に位置する前記基材表面の非入力領域にて前記電極部と電気的に接続された配線部とを有する基板を備え、
　前記配線部はＣｕで形成された配線主体層と、前記配線主体層の表面に形成され、前記配線主体層よりも薄い膜厚のＣｕ合金からなる表面保護層と、で構成されることを特徴とするものである。 The input device in the present invention is
A substrate, an electrode portion provided in an input area on the surface of the substrate, and a wiring portion electrically connected to the electrode portion in a non-input area on the surface of the substrate located outside the input area Equipped with a substrate
The wiring portion is characterized by comprising: a wiring main layer formed of Cu; and a surface protection layer formed on the surface of the wiring main layer and made of a Cu alloy having a thickness smaller than that of the wiring main layer. It is said that.
　これにより、配線部に対して酸化等の腐食を抑制でき、配線部がＣｕ単層で形成されていた従来に比べて配線抵抗の経時変化を小さく抑えることができる。また表面保護層をＣｕ合金で形成することで、材料原価を低く抑えることができる。 As a result, corrosion such as oxidation can be suppressed with respect to the wiring portion, and the change with time of the wiring resistance can be suppressed to a small level as compared to the conventional case where the wiring portion is formed of a Cu single layer. Moreover, material cost can be held down by forming the surface protective layer of a Cu alloy.
　本発明では、前記表面保護層は、ＣｕＮｉ合金で形成されることが好ましい。このとき、ＣｕＮｉ合金中に占めるＮｉ組成比は、５ｗｔ％～３５ｗｔ％の範囲内であることが好ましい。これにより、より効果的に、配線抵抗の経時変化を小さくでき、安定した配線抵抗を有する配線部を構成することが出来る。また、Ｎｉ組成比は、１５ｗｔ％～２５ｗｔ％の範囲内であることがより好ましい。これにより、より効果的に、配線抵抗の経時変化を小さく抑えることができる。またサイドエッチングによる最大後退量を小さくでき、更に、エッチングレートを比較的大きくでき、加工時間を短縮し、生産性を向上させることができる。 In the present invention, the surface protective layer is preferably formed of a CuNi alloy. At this time, the Ni composition ratio in the CuNi alloy is preferably in the range of 5 wt% to 35 wt%. As a result, the change with time of the wiring resistance can be more effectively reduced, and a wiring portion having stable wiring resistance can be configured. Further, the Ni composition ratio is more preferably in the range of 15 wt% to 25 wt%. Thereby, the change with time of the wiring resistance can be suppressed more effectively. Further, the maximum amount of recession due to side etching can be reduced, the etching rate can be relatively increased, the processing time can be shortened, and the productivity can be improved.
　また本発明では、前記配線部の表面が光学透明粘着層で覆われている構成に好ましく適用できる。本発明の配線部の構成によれば、配線部の表面を光学透明粘着層で覆った状態において、酸化等の腐食を適切に抑制でき、配線抵抗の経時変化を効果的に抑制することができる。 Moreover, in this invention, the surface of the said wiring part is preferably applicable to the structure currently covered by the optical transparent adhesive layer. According to the configuration of the wiring portion of the present invention, in the state where the surface of the wiring portion is covered with the optical transparent adhesive layer, corrosion such as oxidation can be appropriately suppressed, and the change with time of the wiring resistance can be effectively suppressed. .
　また本発明における入力装置の製造方法は、
　基材と、基材表面の入力領域に設けられた電極部と、前記入力領域の外側に位置する前記基板表面の非入力領域にて前記電極部と電気的に接続された配線部とを有する基板を備え、
　前記非入力領域の基材表面に、Ｃｕ層を形成し、前記Ｃｕ層の表面に、前記Ｃｕ層よりも膜厚の薄いＣｕ合金層を形成する工程、
　Ｃｕ合金層の表面に前記配線部を形成するためのマスク層を形成する工程、
　前記マスク層に覆われていないＣｕ合金層及びＣｕ層を連続してウエットエッチングにて除去し、Ｃｕで形成された配線主体層と、前記配線主体層の表面にＣｕ合金で形成された表面保護層とからなる前記配線部を形成する工程、
　前記マスク層を除去する工程、
　を有することを特徴とするものである。 The method of manufacturing the input device according to the present invention is
It has a base material, an electrode part provided in an input area on the surface of the base material, and a wiring part electrically connected to the electrode part in a non-input area on the surface of the substrate located outside the input area. Equipped with a substrate
Forming a Cu layer on the surface of the base material in the non-input area, and forming a Cu alloy layer thinner than the Cu layer on the surface of the Cu layer;
Forming a mask layer for forming the wiring portion on the surface of the Cu alloy layer;
The Cu alloy layer and the Cu layer not covered by the mask layer are continuously removed by wet etching, and a wiring main layer formed of Cu and a surface protection formed of Cu alloy on the surface of the wiring main layer Forming the wiring portion comprising a layer;
Removing the mask layer;
It is characterized by having.
　本発明の製造方法によれば、配線部を、Ｃｕから成る配線主体層と、Ｃｕ合金から成る表面保護層との積層構造とすることで、サイドエッチングによる後退量を、Ｃｕ単層で形成する場合に比べて小さくできる。また、本発明では、ウエットエッチング時、Ｃｕ合金層及びＣｕ層を一液のエッチング液により連続してエッチングすることができ、製造コストを抑制でき、製造工程の煩雑化を抑制することができる。 According to the manufacturing method of the present invention, the amount of receding due to side etching is formed as a Cu single layer by forming the wiring portion in a laminated structure of the wiring main layer made of Cu and the surface protection layer made of Cu alloy. It can be smaller than in the case. Further, in the present invention, at the time of wet etching, the Cu alloy layer and the Cu layer can be continuously etched by the etching solution of one solution, the manufacturing cost can be suppressed, and complication of the manufacturing process can be suppressed.
　また本発明では、基材表面の全体に導電層を形成した後、前記導電層の表面全体に前記Ｃｕ層を形成し、更に前記Ｃｕ層の表面全体にＣｕ合金層を形成する工程、
　ウエットエッチングにより、前記非入力領域に、Ｃｕからなる前記配線主体層と、Ｃｕ合金からなる表面保護層とで構成される前記配線部を形成する工程、
　前記入力領域に形成された前記導電層を前記電極部の形状に残すとともに、前記非入力領域に形成された前記導電層を前記配線部下に残し、不要な前記導電層を除去する工程、
　を有することが好ましい。これにより、電極部、及び配線部を簡単且つ所定のパターン形状で形成することができる。 In the present invention, after a conductive layer is formed on the entire surface of the substrate, the Cu layer is formed on the entire surface of the conductive layer, and a Cu alloy layer is further formed on the entire surface of the Cu layer;
Forming the wiring portion composed of the wiring main layer made of Cu and a surface protection layer made of a Cu alloy in the non-input area by wet etching;
Leaving the conductive layer formed in the input region in the shape of the electrode portion and leaving the conductive layer formed in the non-input region under the wiring portion to remove the unnecessary conductive layer;
It is preferable to have Thus, the electrode portion and the wiring portion can be formed simply and in a predetermined pattern.
　また本発明では、前記Ｃｕ合金層を、ＣｕＮｉ合金層で形成することが好ましい。このとき、ＣｕＮｉ合金中に占めるＮｉ組成比を、５ｗｔ％～３５ｗｔ％の範囲内とすることが好ましい。更に、Ｎｉ組成比を、１５ｗｔ％～２５ｗｔ％の範囲内とすることがより好ましい。これにより、Ｃｕ層をエッチング可能なエッチング液を用いて、ＣｕＮｉ合金層をエッチングした際に、エッチングレートが極端に小さくなるのを抑制でき、Ｃｕ層とＣｕＮｉ合金層を一液のエッチング液にて、適切にエッチング処理することが出来る。また、製造過程における酸化等の腐食を抑制でき、サイドエッチングによる後退量を効果的に小さくすることが可能になる。 Further, in the present invention, the Cu alloy layer is preferably formed of a CuNi alloy layer. At this time, the Ni composition ratio in the CuNi alloy is preferably in the range of 5 wt% to 35 wt%. Furthermore, the Ni composition ratio is more preferably in the range of 15 wt% to 25 wt%. As a result, when the CuNi alloy layer is etched using an etching solution capable of etching the Cu layer, the etching rate can be prevented from becoming extremely small, and the Cu layer and the CuNi alloy layer can be etched using a single etching solution. And can be etched appropriately. In addition, corrosion such as oxidation in the manufacturing process can be suppressed, and the amount of recession due to side etching can be effectively reduced.
　本発明の入力装置によれば、配線部に対して酸化等の腐食を抑制し、配線部がＣｕ単層で形成されていた従来に比べて配線抵抗の経時変化を小さく抑えることができる。また表面保護層をＣｕ合金で形成することで、材料原価を低く抑えることができる。 According to the input device of the present invention, it is possible to suppress the corrosion such as oxidation with respect to the wiring portion, and to suppress the change with time of the wiring resistance to a smaller level as compared to the conventional case where the wiring portion is formed of a Cu single layer. Moreover, material cost can be held down by forming the surface protective layer of a Cu alloy.
　また本発明の入力装置の製造方法によれば、配線部を、Ｃｕから成る配線主体層と、Ｃｕ合金から成る表面保護層との積層構造とすることで、サイドエッチングによる後退量を小さくできる。また、Ｃｕ合金層及びＣｕ層に対してウエットエッチング処理を行うとき、一液のエッチング液により連続してエッチングすることができ、製造コストを抑制でき、製造工程の煩雑化を抑制することができる。 Further, according to the method of manufacturing the input device of the present invention, the amount of recession due to side etching can be reduced by forming the wiring portion in a laminated structure of the wiring main layer made of Cu and the surface protection layer made of Cu alloy. Moreover, when performing a wet etching process with respect to a Cu alloy layer and a Cu layer, it can etch continuously with the etching liquid of one solution, can suppress a manufacturing cost, and can suppress complication of a manufacturing process. .
本実施形態の入力装置の分解斜視図、An exploded perspective view of the input device of the present embodiment; 図１に示す入力装置を組み立てた状態とし、Ａ－Ａ線に沿って切断し矢印方向から見た部分拡大縦断面図、FIG. 2 is a partially enlarged longitudinal cross-sectional view of the input device shown in FIG. 本実施形態における配線部の部分拡大縦断面図、A partially enlarged longitudinal sectional view of a wiring portion in the present embodiment; 図２とは別の実施形態における入力装置の部分縦断面図、A partial longitudinal sectional view of the input device in another embodiment different from FIG. 図５（ａ）（ｂ）は、本実施形態における配線部の製造方法を示す工程図であり、図５（ｃ）はサイドエッチングによる後退量を説明するための部分拡大縦断面図、5 (a) and 5 (b) are process drawings showing a method of manufacturing a wiring part in the present embodiment, and FIG. 5 (c) is a partially enlarged longitudinal sectional view for explaining the amount of recession due to side etching; 配線部をＣｕ単層で形成した従来例において、サイドエッチングを説明するための説明図（部分拡大縦断面図）、Explanatory drawing (partially expanded longitudinal cross-sectional view) for demonstrating a side etching in the prior art example which formed the wiring part by Cu single layer. 実験サンプルの平面図、Top view of experimental sample, 図７の実験サンプルを用いて、配線部をＣｕ単層で形成した従来例における試験時間と抵抗比との関係を示すグラフ、7 is a graph showing the relationship between the test time and the resistance ratio in the conventional example in which the wiring portion is formed of a single Cu layer, using the experimental sample of FIG. 7; 図７の実験サンプルを用いて、配線部をＣｕ層／ＣｕＮｉ層で形成した実施例における試験時間と抵抗比との関係を示すグラフ、FIG. 8 is a graph showing the relationship between the test time and the resistance ratio in an embodiment in which the wiring portion is formed of a Cu layer / CuNi layer, using the experimental sample of FIG. 7; 図７の実験サンプルを用い、配線部をＣｕ層／ＣｕＮｉ層で形成した実施例において、Ｎｉ組成比と抵抗比との関係を示すグラフ、FIG. 8 is a graph showing the relationship between the Ni composition ratio and the resistance ratio in an embodiment in which the wiring portion is formed of a Cu layer / CuNi layer using the experimental sample of FIG. 7; ＣｕＮｉ合金のＮｉ組成比とエッチングレートとの関係を示すグラフ、Graph showing relationship between Ni composition ratio of CuNi alloy and etching rate, 配線部をＣｕ層／ＣｕＮｉ層で形成して、ウエットエッチングを施した際のＮｉ組成比とサイドエッチングによる後退量との関係を示すグラフ、A graph showing the relationship between the Ni composition ratio and the amount of recession due to side etching when the wiring portion is formed of Cu layer / CuNi layer and wet etching is performed. 配線部をＣｕ層／ＣｕＮｉ層で形成して、ウエットエッチングを施した際のＮｉ組成比と、配線部の表面に形成された酸化膜の幅寸法との関係を示すグラフ、A graph showing the relationship between the Ni composition ratio when the wiring part is formed of Cu layer / CuNi layer and wet etching is performed, and the width dimension of the oxide film formed on the surface of the wiring part. Ｃｕ／ＮｉＦｅ、Ｃｕ／ＣｕＮｉ、Ｃｕ／ＭｏＮｂに対して、表面保護効果、エッチング液、サイドエッチングの制御性について評価した表。The table | surface which evaluated the surface protection effect, the control property of an etching liquid, and the side etching with respect to Cu / NiFe, Cu / CuNi, and Cu / MoNb.
　図１は本実施形態の入力装置１０の分解斜視図である。図２は、図１に示す入力装置を組み立てた状態とし、Ａ－Ａ線に沿って切断し矢印方向から見た部分拡大縦断面図である。図３は本実施形態における配線部の部分拡大縦断面図である。 FIG. 1 is an exploded perspective view of the input device 10 according to the present embodiment. FIG. 2 is a partially enlarged vertical cross-sectional view of the input device shown in FIG. 1 in an assembled state, cut along the line AA and viewed from the arrow direction. FIG. 3 is a partially enlarged vertical sectional view of the wiring portion in the present embodiment.
　図１に示すように入力装置１０は、天板２０、上部基板２１、下部基板２２、及びフレキシブルプリント基板２３等を有して構成される。 As shown in FIG. 1, the input device 10 is configured to have a top plate 20, an upper substrate 21, a lower substrate 22, a flexible printed substrate 23, and the like.
　天板２０は、プラスチックやガラス基材で形成される。天板２０の下面２０ｂには、加飾層１８が設けられ、図１に示すように、透光性の入力領域１１と入力領域１１の周囲を囲む着色された非透光性の非入力領域１２とに区分けされている。例えば、非入力領域１２は額縁状で形成される。 The top plate 20 is formed of a plastic or glass substrate. A decorative layer 18 is provided on the lower surface 20 b of the top plate 20, and as shown in FIG. 1, a colored non-transparent non-input area surrounding the periphery of the transparent input area 11 and the input area 11. It is divided into twelve. For example, the non-input area 12 is formed in a frame shape.
　図２に示すように下部基板２２には、下部基材２４の表面にＩＴＯ（Indium Tin Oxide）等の透明導電層からなる下部電極部１４が形成されている。 As shown in FIG. 2, on the lower substrate 22, a lower electrode portion 14 formed of a transparent conductive layer such as ITO (Indium Tin Oxide) is formed on the surface of the lower base 24.
　図１に示すように、入力領域１１には、複数本の下部電極部１４が所定のパターン形状にて形成される。図１では、各下部電極部１４は、Ｘ－Ｙ平面の例えばＸ１－Ｘ２方向に沿って延出し、且つ複数の各下部電極部１４がＹ１－Ｙ２方向に間隔を空けて配置される（図１では、下部電極部１４の一部のみ図示した）。 As shown in FIG. 1, a plurality of lower electrode portions 14 are formed in a predetermined pattern shape in the input area 11. In FIG. 1, each lower electrode portion 14 extends along, for example, the X1-X2 direction of the XY plane, and a plurality of lower electrode portions 14 are arranged at intervals in the Y1-Y2 direction (see FIG. 1). In 1, only a part of the lower electrode portion 14 is shown).
　本実施形態では、下部電極部１４から一体となって非入力領域１２に延出し、前記透明導電層で形成されて成る配線下部層２８（図２，図３参照）が下部基材２４の表面に形成されている。 In this embodiment, the wiring lower layer 28 (see FIGS. 2 and 3) formed integrally with the lower electrode portion 14 and extending to the non-input area 12 and formed of the transparent conductive layer is a surface of the lower base 24. Is formed.
　図１に示すように、入力領域１１の周囲を取り囲む非入力領域１２には、入力領域１１に形成されたセンサ部としての各下部電極部１４に電気的に接続される配線部１６が引き回されている。配線部１６は、非入力領域１２のＸ１側領域及びＸ２側領域から夫々、引き回され、各配線部１６の先端は非入力領域１２のＹ２側領域で接続部１７を構成している。 As shown in FIG. 1, in the non-input area 12 surrounding the periphery of the input area 11, wiring portions 16 electrically connected to the lower electrode portions 14 as sensor portions formed in the input area 11 are routed. It is done. The wiring sections 16 are respectively routed from the X1 side area and the X2 side area of the non-input area 12, and the tip of each wiring section 16 constitutes a connection section 17 in the Y2 side area of the non-input area 12.
　図２，図３に示すように、配線部１６は、下部電極部１４と一体となって延出する配線下部層２８上に形成されている。なお配線部１６は下部基材２４の表面に直接形成されてもよいが、配線部１６を配線下部層２８上に重ねて形成することで、製造工程を簡単にでき、また配線部１６の電気的安定性を適切に向上させることができる。なお、配線下部層２８は、配線部１６の下に位置して各配線部１６の間の下部基材２４表面には残されていない。よって、隣接する配線部１６同士が、前記配線下部層２８を介して短絡することはない。 As shown in FIGS. 2 and 3, the wiring portion 16 is formed on the wiring lower layer 28 extending integrally with the lower electrode portion 14. Although the wiring portion 16 may be formed directly on the surface of the lower base material 24, the manufacturing process can be simplified by forming the wiring portion 16 so as to overlap on the wiring lower layer 28. Stability can be appropriately improved. The wiring lower layer 28 is located under the wiring portion 16 and is not left on the surface of the lower base 24 between the wiring portions 16. Therefore, adjacent wiring parts 16 do not short circuit via the wiring lower layer 28.
　下部基材２４は、透光性のポリエチレンテレフタレート等の樹脂やガラスで構成される。下部基材２４は、樹脂基材の表裏面にポリエステル樹脂やエポキシ樹脂等の絶縁材料から成るコート層が形成された形態とすることが出来る。 The lower substrate 24 is made of a resin or glass such as translucent polyethylene terephthalate. The lower base 24 can have a form in which a coat layer made of an insulating material such as polyester resin or epoxy resin is formed on the front and back of the resin base.
　図２に示すように上部基板２１には、上部基材２５の表面にＩＴＯ（Indium Tin Oxide）等の透明導電層からなる上部電極部１３が形成されている。 As shown in FIG. 2, on the upper substrate 21, the upper electrode portion 13 formed of a transparent conductive layer such as ITO (Indium Tin Oxide) is formed on the surface of the upper base 25.
　図１に示すように、入力領域１１には、複数本の上部電極部１３が所定のパターン形状にて形成される。図１では、各上部電極部１３は、Ｘ－Ｙ平面の例えばＹ１－Ｙ２方向に沿って延出し、且つ複数の各上部電極部１３がＸ１－Ｘ２方向に間隔を空けて配置される（図１では、上部電極部１３の一部のみ図示した）。 As shown in FIG. 1, a plurality of upper electrode portions 13 are formed in a predetermined pattern shape in the input area 11. In FIG. 1, each upper electrode portion 13 extends along, for example, the Y1-Y2 direction of the XY plane, and a plurality of upper electrode portions 13 are arranged at intervals in the X1-X2 direction (see FIG. 1). In 1, only a part of the upper electrode portion 13 is shown).
　このように入力領域１１に形成された各上部電極部１３と各下部電極部１４とは直交している。 The upper electrode portions 13 and the lower electrode portions 14 formed in the input region 11 in this manner are orthogonal to each other.
　本実施形態では、各上部電極部１３と電気的に接続される配線部（図示しない）が非入力領域１２に引き回されている。前記配線部の下には、上部電極部１３から一体となって非入力領域１２に延出し、前記透明導電層で形成されて成る配線下部層が形成されている。 In the present embodiment, a wiring portion (not shown) electrically connected to each upper electrode portion 13 is routed around the non-input area 12. Below the wiring portion, a wiring lower layer formed integrally with the non-input area 12 from the upper electrode portion 13 and formed of the transparent conductive layer is formed.
　上部基板２１に形成された各配線部の先端は、図１に示す接続部１５を構成している。
　上部基材２５は、透光性のポリエチレンテレフタレート等の樹脂やガラスで構成される。上部基材２５は、樹脂基材の表裏面にポリエステル樹脂やエポキシ樹脂等の絶縁材料から成るコート層が形成された形態とすることが出来る。 The tip of each wiring portion formed on the upper substrate 21 constitutes a connection portion 15 shown in FIG.
The upper base material 25 is made of a resin or glass such as light transmitting polyethylene terephthalate. The upper base material 25 can be made into the form by which the coat layer which consists of insulating materials, such as a polyester resin and an epoxy resin, was formed in front and back of a resin base material.
　図２に示すように、下部基板２２と上部基板２１間が光学透明接着層（ＯＣＡ）２６を介して接合されている。 As shown in FIG. 2, the lower substrate 22 and the upper substrate 21 are bonded via an optically transparent adhesive layer (OCA) 26.
　また図２に示すように、天板２０と上部基板２１の間は、光学透明接着層（ＯＣＡ）２７を介して接合されている。 Further, as shown in FIG. 2, the top plate 20 and the upper substrate 21 are joined via an optical transparent adhesive layer (OCA) 27.
　図２では、下部基板２２及び上部基板２１の各電極部１３，１４を夫々、上方（天板２０側）に向けた状態で、下部基板２２と上部基板２１間を光学透明粘着層２６により接合しているが、一方の電極部を、下方（天板２０側とは反対側）に向けた状態、あるいは、両方の電極１３，１４を、下方に向けた状態として、下部基板２２と上部基板２１間を接合してもよい。 In FIG. 2, the lower substrate 22 and the upper substrate 21 are joined by the optically transparent adhesive layer 26 in a state where the respective electrode portions 13 and 14 of the lower substrate 22 and the upper substrate 21 face upward (to the top plate 20). However, the lower substrate 22 and the upper substrate are in a state in which one of the electrode parts is directed downward (opposite to the top plate 20) or in a state in which both the electrodes 13 and 14 are directed downward. 21 may be joined.
　または図４に示すように、一つの基材５０の上面５０ａに、上部電極部１３を形成し、下面５０ｂに、下部電極部１４を形成した形態であってもよい。なお図４では、図２と同じ部材に同じ符号を付した。 Or as shown in FIG. 4, the upper electrode part 13 may be formed in the upper surface 50a of one base material 50, and the lower electrode part 14 may be formed in the lower surface 50b. In FIG. 4, the same members as those in FIG. 2 are denoted by the same reference numerals.
　図１，図２に示す入力装置１０では、入力領域１１の表面に指Ｆを接触させると、下部電極部１４及び上部電極部１３を備えた入力領域１１での静電容量が変化することで、指Ｆの接触位置を検出することが可能になっている。 In the input device 10 shown in FIGS. 1 and 2, when the finger F is brought into contact with the surface of the input area 11, the capacitance in the input area 11 including the lower electrode portion 14 and the upper electrode portion 13 changes. , And the touch position of the finger F can be detected.
　図３は、図１のＢ－Ｂ線に沿って切断し矢印方向から見たときに現れる配線部１６の拡大縦断面図を示す。図１，図３には２本の配線部１６しか図示していないが、実際にはＸ１側及びＸ２側の夫々の非入力領域１２に配線部１６が、１０本程度設けられる。 FIG. 3 shows an enlarged longitudinal sectional view of the wiring portion 16 which is cut along the line B--B of FIG. 1 and viewed from the arrow direction. Although only two wiring portions 16 are shown in FIGS. 1 and 3, in practice, about ten wiring portions 16 are provided in the non-input area 12 on the X1 side and the X2 side.
　図３に示すように、各配線部１６は、配線パターン形状の透明導電層（ＩＴＯ等）から成る各配線下部層２８上に形成される。 As shown in FIG. 3, each wiring part 16 is formed on each wiring lower layer 28 which consists of a transparent conductive layer (ITO etc.) of a wiring pattern shape.
　図３に示すように各配線部１６は、Ｃｕから成る配線主体層２９と、配線主体層２９の表面（上面）２９ａに形成されたＣｕ合金から成る表面保護層３０との積層構造で形成される。 As shown in FIG. 3, each wiring portion 16 is formed of a laminated structure of a wiring main layer 29 made of Cu and a surface protection layer 30 made of a Cu alloy formed on the surface (upper surface) 29 a of the wiring main layer 29. Ru.
　配線主体層２９の膜厚Ｈ１は、１００～１５０ｎｍ程度、表面保護層３０の膜厚Ｈ２は、１５～３０ｎｍ程度であり、表面保護層３０は配線主体層２９よりも薄く形成される。 The film thickness H1 of the wiring main layer 29 is about 100 to 150 nm, the film thickness H2 of the surface protective layer 30 is about 15 to 30 nm, and the surface protective layer 30 is thinner than the wiring main layer 29.
　表面保護層３０はＣｕＮｉ合金で形成されることが好ましい。このとき、ＣｕＮｉ合金中に占めるＮｉ組成比は、５ｗｔ％～３５ｗｔ％の範囲内であることが好ましく、より好ましくは１５ｗｔ％～２５ｗｔ％の範囲内である。 The surface protective layer 30 is preferably formed of a CuNi alloy. At this time, the Ni composition ratio in the CuNi alloy is preferably in the range of 5 wt% to 35 wt%, and more preferably in the range of 15 wt% to 25 wt%.
　図３に示す実施形態では、配線部１６の表面全体が、防錆膜３８で覆われている。防錆膜３８の材質は特に限定されるものでない。例えばベンゾトリアゾールを用いることができる。また防錆膜３８は形成されなくてもよい。 In the embodiment shown in FIG. 3, the entire surface of the wiring portion 16 is covered with the antirust film 38. The material of the rustproof film 38 is not particularly limited. For example, benzotriazole can be used. Further, the rustproof film 38 may not be formed.
　各配線部１６の幅寸法Ｔ１は、２０～１００μｍ程度であり、各配線部１６間の間隔Ｔ２は、２０～１００μｍ程度である。このように、複数の配線部１６を限られた非入力領域１２内で、狭いピッチで形成しなければいけないため、印刷成形等でなく、本実施形態では、スパッタ法等で薄膜形成し、フォトリソグラフィ技術を用いて各配線部１６を微細なパターンで形成する。 The width dimension T1 of each wiring portion 16 is about 20 to 100 μm, and the distance T2 between each wiring portion 16 is about 20 to 100 μm. As described above, since a plurality of wiring portions 16 must be formed with a narrow pitch in the limited non-input area 12, in the present embodiment, a thin film is formed by sputtering or the like instead of printing and forming. Each wiring portion 16 is formed in a fine pattern using a lithography technique.
　図５は本実施形態の配線部１６の製造方法を示す工程図である。各図は製造工程における部分拡大縦断面図を示す。 FIG. 5 is a process chart showing a method of manufacturing the wiring portion 16 of the present embodiment. Each drawing shows a partially enlarged longitudinal sectional view in the manufacturing process.
　図５（ａ）の工程では、下部基材２４の表面全体にＩＴＯ（Indium Tin Oxide）等の透明導電層３４をスパッタ法や蒸着法により形成する。ここで、「透明」とは可視光線透過率が８０％以上の状態を指す。更にヘイズ値が６以下であることが好適である。 In the process of FIG. 5A, a transparent conductive layer 34 such as ITO (Indium Tin Oxide) is formed on the entire surface of the lower substrate 24 by a sputtering method or a vapor deposition method. Here, "transparent" indicates a state in which the visible light transmittance is 80% or more. Furthermore, it is preferable that the haze value is 6 or less.
　次に、透明導電層３４上の全面にＣｕ層３１をスパッタ法や蒸着法で成膜する。Ｃｕ層３１は、透明導電層３４よりも導電性に優れている。更にＣｕ層３１上の全面にＣｕ合金層３２をスパッタ法や蒸着法で成膜する。このときＣｕ合金層３２をＣｕ層３１より薄い膜厚で形成する。 Next, a Cu layer 31 is formed on the entire surface of the transparent conductive layer 34 by a sputtering method or a vapor deposition method. The Cu layer 31 is more conductive than the transparent conductive layer 34. Further, a Cu alloy layer 32 is formed on the entire surface of the Cu layer 31 by a sputtering method or a vapor deposition method. At this time, the Cu alloy layer 32 is formed thinner than the Cu layer 31.
　次に、Ｃｕ合金層３２の上面にレジスト層を塗布し、露光現像により、非入力領域１２に、前記レジスト層３５をマスク層として、複数の配線パターン形状で残す。 Next, a resist layer is coated on the upper surface of the Cu alloy layer 32, and exposed and developed to leave a plurality of wiring pattern shapes in the non-input area 12 using the resist layer 35 as a mask layer.
　次に図５（ｂ）の工程では、レジスト層３５に覆われていないＣｕ合金層３２及びＣｕ層３１をウエットエッチングにより連続して除去する。 Next, in the step of FIG. 5B, the Cu alloy layer 32 and the Cu layer 31 not covered with the resist layer 35 are continuously removed by wet etching.
　本実施形態では、エッチング液として過硫酸アンモニウムを含むエッチング液を用いることが出来る。そして本実施形態では、この一液のエッチング液でＣｕ合金層３２及びＣｕ層３１の双方を適切にエッチングすることが可能になっている。 In the present embodiment, an etching solution containing ammonium persulfate can be used as the etching solution. And in this embodiment, it is possible to etch appropriately both Cu alloy layer 32 and Cu layer 31 with this etching solution of one solution.
　残されたＣｕ層３１は、配線部１６の大部分を構成する配線主体層２９であり、残されたＣｕ合金層３２は配線部１６の表面層を構成する表面保護層３０である。 The remaining Cu layer 31 is a wiring main layer 29 constituting most of the wiring portion 16, and the remaining Cu alloy layer 32 is a surface protection layer 30 constituting a surface layer of the wiring portion 16.
　図５（ｃ）に示すように、図５（ｂ）のウエットエッチング工程により配線部１６の側面１６ａがサイドエッチングの影響を受けると配線部１６の幅寸法がレジスト層３５の幅寸法よりも小さくなるが、本実施形態ではサイドエッチングの影響を従来に比べて小さくでき、よってサイドエッチングによる最大後退量Ｔ３を小さくでき、ウエットエッチング時の制御性に優れる。 As shown in FIG. 5C, the width dimension of the wiring portion 16 is smaller than the width dimension of the resist layer 35 when the side surface 16a of the wiring portion 16 is affected by the side etching in the wet etching process of FIG. However, in the present embodiment, the influence of side etching can be reduced compared to the conventional case, and hence the maximum amount of retraction T3 by side etching can be reduced, and controllability at the time of wet etching is excellent.
　更に図５（ｂ）の工程では、レジスト層３５に覆われていない透明導電層３４ｂを除去して、配線部１６の下に、配線部１６とほぼ同形状の配線パターンからなる透明導電層３４ａを配線下部層２８として残す。そして前記レジスト層３５を除去する。また、その後に、各配線部１６の表面に防錆膜３８（図３参照）をディップ等で塗布してもよい。 Furthermore, in the process of FIG. 5B, the transparent conductive layer 34b not covered with the resist layer 35 is removed, and a transparent conductive layer 34a having a wiring pattern substantially the same shape as the wiring portion 16 under the wiring portion 16 is removed. As a wiring lower layer 28. Then, the resist layer 35 is removed. Further, after that, an anticorrosive film 38 (see FIG. 3) may be applied to the surface of each wiring portion 16 by dip or the like.
　図５（ａ）の工程で、透明導電層３４は、入力領域１１上の全面にも形成されており、入力領域１１上の透明導電層３４を、図１に示す下部電極部１４として残し、それ以外の不要な透明導電層３４を除去する。下部電極部１４を形成する工程や、配線部１６下に透明導電層３４ａを配線下部層２８として残す工程は、上記した方法以外であってもよく特に限定されるものではない。すなわち図５（ｂ）では、配線部１６を形成するためのレジスト層（マスク層）３５を利用して、各配線部１６間に位置する不要な透明導電層３４ｂを除去したが、例えば、一旦、レジスト層３５を除去し、続いて、各配線部１６上から入力領域１１上の透明導電層３４上に配線パターン及び電極パターンからなるレジスト層を形成し、前記レジスト層に覆われていない透明導電層３４を除去することで、下部電極部１４の形成と、各配線部１６下に位置する配線パターン形状の配線下部層２８の形成とを同時に行なうことが可能になる。 In the process of FIG. 5A, the transparent conductive layer 34 is also formed on the entire surface of the input area 11, leaving the transparent conductive layer 34 on the input area 11 as the lower electrode portion 14 shown in FIG. The unnecessary unnecessary transparent conductive layer 34 is removed. The step of forming the lower electrode portion 14 and the step of leaving the transparent conductive layer 34a as the wiring lower layer 28 under the wiring portion 16 may be other than the method described above, and are not particularly limited. That is, in FIG. 5B, the unnecessary transparent conductive layer 34b located between the wiring portions 16 is removed using the resist layer (mask layer) 35 for forming the wiring portions 16, but, for example, Then, the resist layer 35 is removed, and subsequently, a resist layer composed of a wiring pattern and an electrode pattern is formed on the transparent conductive layer 34 on each of the wiring portions 16 and on the input region 11, and the transparent layer not covered by the resist layer By removing the conductive layer 34, the formation of the lower electrode portion 14 and the formation of the wiring lower layer 28 in the form of a wiring pattern located under each wiring portion 16 can be simultaneously performed.
　上部基板２１においても図５と同様の製造方法により形成することができる。そして、下部基板２２と上部基板２１間を光学透明粘着層（ＯＣＡ）２６を介して接合し、更に、上部基板２１と天板２０との間を光学透明粘着層（ＯＣＡ）２７を介して接合する。 The upper substrate 21 can also be formed by the same manufacturing method as that shown in FIG. Then, the lower substrate 22 and the upper substrate 21 are joined via the optically transparent adhesive layer (OCA) 26, and further, the upper substrate 21 and the top plate 20 are joined via the optically transparent adhesive layer (OCA) 27. Do.
　上記では、配線部１６の構造について説明したが、上部基板２１に形成される配線部（図示しない）についても同様の積層構造で形成することができる。 Although the structure of the wiring portion 16 has been described above, the wiring portion (not shown) formed on the upper substrate 21 can also be formed in a similar laminated structure.
　本実施形態では、配線部が、Ｃｕから成る配線主体層２９と、配線主体層２９の表面２９ａに形成されたＣｕ合金からなる表面保護層３０との積層構造で形成される。配線部がＣｕ単層で形成されていた従来では、表面に酸化膜が形成されやすく、また配線部の表面が光学透明粘着層で覆われていても酸化等の腐食を抑えることができず、配線抵抗の経時変化が大きくなる問題があったが、本実施形態のように、Ｃｕの配線主体層２９の表面にＣｕ合金の表面保護層３０を設けた積層構造で配線部１６を形成することで、酸化等の腐食を抑制でき、この結果、配線抵抗の経時変化を小さく抑えることが可能である。 In the present embodiment, the wiring portion is formed of a laminated structure of the wiring main layer 29 made of Cu and the surface protection layer 30 made of a Cu alloy formed on the surface 29 a of the wiring main layer 29. In the conventional case where the wiring portion is formed of a Cu single layer, an oxide film is easily formed on the surface, and even if the surface of the wiring portion is covered with the optical transparent adhesive layer, corrosion such as oxidation can not be suppressed. Although there is a problem that the change with time of the wiring resistance becomes large, as in the present embodiment, the wiring portion 16 is formed in a laminated structure in which the surface protective layer 30 of Cu alloy is provided on the surface of the wiring main layer 29 of Cu. Therefore, corrosion such as oxidation can be suppressed, and as a result, it is possible to suppress the change with time of the wiring resistance to a small value.
　また本実施形態における入力装置１０の製造方法では、配線部１６を、Ｃｕから成る配線主体層２９と、Ｃｕ合金から成る表面保護層３０との積層構造とすることで、サイドエッチングによる後退量をＣｕ単層で配線部を形成するよりも小さくでき、サイドエッチングに対する制御性を高めることができる。図６は、配線部３７をＣｕ単層で形成した従来例を示す。図６では、配線部３７の上にマスク層であるレジスト層３５が設けられている。図６に示す従来例の場合、製造過程で施される熱処理等の影響を受けて、配線部３７の表面３７ａが酸化等で腐食しやすい。後述する実験でも表面３７ａが酸化等で変色し、その変色の幅寸法が本実施形態に比べて大きくなることが確認されている。このため、ウエットエッチング処理を行うと、レジスト層３５下に位置する配線部３７の表面３７ａ付近が大幅に除去され、配線部３７の側面３７ｂのサイドエッチングによる後退量が非常に大きくなってしまう。よってレジスト層３５との密着性も悪い。最悪の場合、レジスト層３５が製造過程の途中で剥がれてしまい、配線部３７を安定して形成できなかった。このように従来の構成では、サイドエッチングに対する制御性が非常に悪かった。 Further, in the method of manufacturing the input device 10 according to the present embodiment, the wiring portion 16 has a laminated structure of the wiring main layer 29 made of Cu and the surface protection layer 30 made of a Cu alloy, so that the amount of recession due to side etching is achieved. It can be made smaller than forming a wiring part by Cu single layer, and the controllability to side etching can be improved. FIG. 6 shows a conventional example in which the wiring portion 37 is formed of a Cu single layer. In FIG. 6, a resist layer 35 which is a mask layer is provided on the wiring portion 37. In the case of the conventional example shown in FIG. 6, the surface 37a of the wiring portion 37 is easily corroded by oxidation or the like under the influence of heat treatment or the like applied in the manufacturing process. Also in the experiment described later, it is confirmed that the surface 37a is discolored due to oxidation or the like, and the width dimension of the discoloring is larger than that of the present embodiment. Therefore, when the wet etching process is performed, the vicinity of the surface 37a of the wiring portion 37 located below the resist layer 35 is largely removed, and the amount of recession of the side surface 37b of the wiring portion 37 due to side etching becomes very large. Therefore, the adhesion to the resist layer 35 is also poor. In the worst case, the resist layer 35 was peeled off in the middle of the manufacturing process, and the wiring portion 37 could not be stably formed. Thus, in the conventional configuration, the controllability to the side etching is very bad.
　これに対して本実施形態では、Ｃｕ合金から成る表面保護層３０を配線部１６の表面に設けたことで、配線部１６の表面に酸化等の腐食が生じるのを抑制でき、この結果、図５（ｃ）に示すように多少、サイドエッチングの影響を受けても、その最大後退量Ｔ３を、Ｃｕ単層で配線部３７を形成した図６の従来例に比べて効果的に小さくでき、サイドエッチングに対する制御性を高めることができる。 On the other hand, in the present embodiment, by providing the surface protection layer 30 made of a Cu alloy on the surface of the wiring portion 16, the occurrence of corrosion such as oxidation on the surface of the wiring portion 16 can be suppressed. As shown in FIG. 5 (c), even under the influence of side etching, the maximum receding amount T3 can be effectively reduced compared to the conventional example of FIG. Controllability of side etching can be enhanced.
　また本実施形態では、レジスト層３５に覆われていないＣｕ合金層３２及びＣｕ層３１を一液のエッチング液により連続してウエットエッチングすることができ、製造コストを抑制でき、製造工程の煩雑化を抑制することができる。 Further, in the present embodiment, the Cu alloy layer 32 and the Cu layer 31 not covered with the resist layer 35 can be continuously wet-etched by the etching solution of one solution, the manufacturing cost can be suppressed, and the manufacturing process becomes complicated. Can be suppressed.
　本実施形態では、Ｃｕ合金から成る表面保護層３０は、ＣｕＮｉ合金で形成されることが好ましく、Ｎｉ組成比は、５ｗｔ％～３５ｗｔ％であることが好適である。これにより配線抵抗の経時変化を小さくでき、またサイドエッチングによる最大後退量Ｔ３をより効果的に小さくできる。したがって所定の配線抵抗を有する配線部１６を安定して形成することができる。Ｎｉ組成比は１５ｗｔ％～２５ｗｔ％の範囲内であることがより好適である。これにより、効果的に、配線抵抗の経時変化を小さく抑えることができる。また、サイドエッチングによる最大後退量を小さくでき、更に、エッチングレートを比較的大きくでき、加工時間を短縮し、生産性を向上させることができる。 In the present embodiment, the surface protection layer 30 made of a Cu alloy is preferably formed of a CuNi alloy, and the Ni composition ratio is preferably 5 wt% to 35 wt%. As a result, the change with time of the wiring resistance can be reduced, and the maximum amount of retraction T3 by side etching can be reduced more effectively. Therefore, the wiring portion 16 having a predetermined wiring resistance can be stably formed. The Ni composition ratio is more preferably in the range of 15 wt% to 25 wt%. Thereby, the change with time of the wiring resistance can be effectively suppressed. In addition, the maximum amount of recession due to side etching can be reduced, the etching rate can be relatively increased, processing time can be shortened, and productivity can be improved.
　また入力装置の製造方法において、ＣｕＮｉ合金のＮｉ組成比を２５ｗｔ％以下とすることで、過硫酸アンモニウムを含むエッチング液を用いた場合に、ＣｕＮｉ合金層３２のエッチングレートを大きくでき、より効果的に、Ｃｕ合金層３２及びＣｕ層３１を一液のエッチング液により連続してウエットエッチングすることができる。 Further, by setting the Ni composition ratio of the CuNi alloy to 25 wt% or less in the method of manufacturing the input device, the etching rate of the CuNi alloy layer 32 can be increased when an etching solution containing ammonium persulfate is used, which is more effective. The Cu alloy layer 32 and the Cu layer 31 can be continuously wet-etched by the etchant of one solution.
　本実施形態では、Ｃｕからなる配線主体層２９の膜厚Ｈ１が、Ｃｕ合金からなる表面保護層３０の膜厚Ｈ２よりも大きく形成されている。これにより配線部１６の電気的特性は、Ｃｕ単層で形成された従来の配線部とほぼ同等にでき、また材料原価もＣｕ単層の従来例とほぼ同等に安く抑えることが出来る。 In the present embodiment, the film thickness H1 of the wiring main layer 29 of Cu is formed larger than the film thickness H2 of the surface protective layer 30 of Cu alloy. As a result, the electrical characteristics of the wiring portion 16 can be made substantially equal to that of the conventional wiring portion formed of a Cu single layer, and the material cost can be suppressed to the same low price as that of the conventional example of a Cu single layer.
　また、図１に示す接続部１５，１７も配線部と一体に形成された部分であるから図３に示す積層構造で形成される。そして、露出して各接続部１５，１７が、フレキシブルプリント基板２３と圧着される。本実施形態では、接続部１５，１７が、Ｃｕから成る配線主体層２９とＣｕ合金から成る表面保護層３０の積層構造で形成され、表面保護層３０がフレキシブルプリント基板２３との圧着面となっている。本実施形態によれば、各接続部１５，１７とフレキシブルプリント基板２３との圧着強度を良好に保つことが出来る。 Further, since the connection parts 15 and 17 shown in FIG. 1 are also parts integrally formed with the wiring part, they are formed in a laminated structure shown in FIG. Then, the connection portions 15 and 17 are exposed and crimped to the flexible printed circuit board 23. In the present embodiment, the connection portions 15 and 17 are formed in a laminated structure of the wiring main layer 29 made of Cu and the surface protection layer 30 made of Cu alloy, and the surface protection layer 30 becomes a pressure contact surface with the flexible printed circuit 23. ing. According to the present embodiment, the pressure bonding strength between each of the connection portions 15 and 17 and the flexible printed circuit 23 can be kept good.
　下部基板２２及び上部基板２１に形成される全ての配線部が、Ｃｕから成る配線主体層２９とＣｕ合金から成る表面保護層３０の積層構造で形成されることが好ましいが、一部の配線部が図３に示す積層構造以外の形態で形成されてもよい。 It is preferable that all the wiring portions formed on the lower substrate 22 and the upper substrate 21 be formed in a laminated structure of the wiring main layer 29 made of Cu and the surface protective layer 30 made of a Cu alloy. May be formed in a form other than the laminated structure shown in FIG.
　図１の入力装置１０は静電容量式であったが、本実施形態の配線構造は静電容量式の入力装置に限定されるものでない。 Although the input device 10 of FIG. 1 is a capacitance type, the wiring structure of the present embodiment is not limited to the capacitance type input device.
　図７に示す試験サンプルを形成した。符号４０が配線部、符号４１がテストパッド、符号４２が光学透明粘着層（ＯＣＡ）である。配線部４０の表面が光学透明粘着層４２で覆われている。 The test sample shown in FIG. 7 was formed. The reference numeral 40 denotes a wiring portion, the reference numeral 41 denotes a test pad, and the reference numeral 42 denotes an optically transparent adhesive layer (OCA). The surface of the wiring portion 40 is covered with the optically transparent adhesive layer 42.
　従来例では、配線部４０をＣｕ単層で形成した。また実施例では、配線部４０をＣｕ層とＣｕＮｉ層の積層構造とした。ＣｕＮｉ合金のＮｉ組成比を１５ｗｔ％とした。Ｃｕ層の膜厚を１５０ｎｍ、ＣｕＮｉ合金層の膜厚を２０ｎｍとした。また図７に示す配線部４０の配線幅を５０μｍ、配線長さを３０ｍｍとした。 In the conventional example, the wiring portion 40 is formed of a Cu single layer. In the embodiment, the wiring portion 40 has a laminated structure of a Cu layer and a CuNi layer. The Ni composition ratio of the CuNi alloy is 15 wt%. The film thickness of the Cu layer was 150 nm, and the film thickness of the CuNi alloy layer was 20 nm. The wiring width of the wiring portion 40 shown in FIG. 7 is 50 μm, and the wiring length is 30 mm.
　実験では、光学透明粘着層４２として種類の異なる第１の光学透明粘着層と第２の光学透明粘着層を使用し、温度が６０℃、湿度が９５％の条件下で、試験開始前、６５時間後、１３０時間後、２４０時間後、３００時間後、５００時間後の配線部４０の配線抵抗を測定した。 In the experiment, different types of the first optical transparent adhesive layer and the second optical transparent adhesive layer are used as the optical transparent adhesive layer 42, and the temperature is 60 ° C., the humidity is 95%, before the start of the test, 65 After the time, 130, 240, 300, and 500 hours, the wiring resistance of the wiring portion 40 was measured.
　図８は、配線部４０をＣｕ単層で形成した従来例の実験結果である。なお、縦軸は、試験開始前（試験時間：０時間）の配線抵抗を初期抵抗とし、各試験時間における配線抵抗を電気抵抗変化率（％）で示した。電気抵抗変化率（％）は、（各試験時間での配線抵抗－初期抵抗）／初期抵抗で示される。図８に示すように、第２の光学透明粘着層を配線部４０に重ねて実験を行うと、配線抵抗（電気抵抗変化率（％））は、試験時間が長くなるほど急激に上昇することがわかった。 FIG. 8 shows an experimental result of the conventional example in which the wiring portion 40 is formed of a Cu single layer. The ordinate represents the wiring resistance before the start of the test (test time: 0 hours) as the initial resistance, and the wiring resistance at each test time is indicated by the electrical resistance change rate (%). The electrical resistance change rate (%) is represented by (wiring resistance at each test time-initial resistance) / initial resistance. As shown in FIG. 8, when an experiment is performed by overlapping the second optical transparent adhesive layer on the wiring portion 40, the wiring resistance (the rate of change in electrical resistance (%)) may increase rapidly as the test time becomes longer. all right.
　図９は、配線部４０を、Ｃｕ層／ＣｕＮｉ層の積層構造で形成した実施例の実験結果である。なお、縦軸は、試験開始前（試験時間：０時間）の抵抗値を初期抵抗とし、各試験時間における配線抵抗を電気抵抗変化率（％）で示した。図９に示すように、第１の光学透明粘着層及び第２の光学透明粘着層のどちらを使用した場合でも、配線抵抗（電気抵抗変化率（％））の上昇を小さく抑えることができるとわかった。特に、第２の光学透明粘着層を用いた場合、図８に示すように従来例では急激な配線抵抗の上昇が見られたが本実施例によれば、効果的に電気抵抗変化率（％）の上昇を抑制できることがわかった。また第１の光学透明粘着層を用いた場合でも、図８の従来例に比べて電気抵抗変化率（％）の上昇を抑制することができるとわかった。第１の光学透明粘着層は、第２の光学透明粘着層よりも値段が高い。よって製造コストを抑制するには第２の光学透明粘着層を用いることが好ましいが、本実施例によれば、第２の光学透明粘着層を用いても十分に配線抵抗の経時変化を抑制でき、製造コストを抑制することが可能になる。 FIG. 9 shows experimental results of an example in which the wiring portion 40 is formed in a laminated structure of Cu layer / CuNi layer. In addition, the vertical axis | shaft made resistance value before a test start (test time: 0 hour) an initial stage resistance, and showed the wiring resistance in each test time by the electrical resistance change rate (%). As shown in FIG. 9, it is possible to suppress the increase in the wiring resistance (the rate of change in electrical resistance (%)) to a small value regardless of which of the first optical transparent adhesive layer and the second optical transparent adhesive layer is used. all right. In particular, when the second optically transparent adhesive layer is used, as shown in FIG. 8, a sharp increase in wiring resistance was observed in the conventional example, but according to this embodiment, the rate of change in electrical resistance (%) is effectively It turned out that the rise of) can be suppressed. In addition, even when the first optically transparent adhesive layer was used, it was found that the increase in the rate of change in electrical resistance (%) can be suppressed as compared with the conventional example of FIG. The first optically clear adhesive layer is more expensive than the second optically clear adhesive layer. Therefore, it is preferable to use the second optically transparent adhesive layer in order to suppress the manufacturing cost, but according to this example, even if the second optically transparent adhesive layer is used, it is possible to sufficiently suppress the change in wiring resistance with time. , It becomes possible to control the manufacturing cost.
　次に、配線部４０を、Ｃｕ層／ＣｕＮｉ層の積層構造で形成した実施例において、ＣｕＮｉ合金のＮｉ組成比を変化させて、配線抵抗を測定した。 Next, in the example in which the wiring portion 40 was formed with a laminated structure of Cu layer / CuNi layer, the Ni composition ratio of the CuNi alloy was changed to measure the wiring resistance.
　実験では、異なるＮｉ組成比のＣｕＮｉ層を含む各配線部４０の試験開始前（試験時間：０時間）の配線抵抗を夫々、初期抵抗とし、試験時間が５００時間となったときの各配線部４０の配線抵抗を電気抵抗変化率（％）で示した。 In the experiment, the wiring resistances before the test start (test time: 0 hours) of the wiring parts 40 including CuNi layers having different Ni composition ratios are respectively taken as initial resistances, and each wiring part when the test time becomes 500 hours The wiring resistance of 40 was shown by the electrical resistance change rate (%).
　図１０に示すように、Ｎｉ組成比を３５ｗｔ％以下とすると、電気抵抗変化率（％）が３２％～２５％の範囲内でほぼ安定し、配線抵抗の変動を低く抑えることができるとわかった。ただし、Ｎｉ組成比が少ないと、やや配線抵抗（抵抗比）が上昇しやすい傾向が見られるため、ＣｕＮｉ合金のＮｉ組成比は、５ｗｔ％～３５ｗｔ％の範囲が好ましいとした。 As shown in FIG. 10, it is understood that when the Ni composition ratio is 35 wt% or less, the electrical resistance change rate (%) is almost stable in the range of 32% to 25%, and the fluctuation of the wiring resistance can be suppressed low. The However, when the Ni composition ratio is low, the wiring resistance (resistance ratio) tends to increase slightly, so the Ni composition ratio of the CuNi alloy is preferably in the range of 5 wt% to 35 wt%.
　次に、Ｓｉ基板上にＩＴＯ膜を成膜し、さらにＩＴＯ膜上に膜厚が１５０ｎｍのＣｕ層をスパッタにて形成し、更にＣｕ層の表面に、膜厚が２０ｎｍのＣｕＮｉ層をスパッタ法にて形成した。続いて、過硫酸アンモニウムを含むエッチング液を用いてエッチングレートを測定した。実験では、ＣｕＮｉ合金のＮｉ組成比を０ｗｔ％～５０ｗｔ％の範囲内で変動させて、各Ｎｉ組成比とエッチングレートとの関係について調べた。その実験結果が図１１に示されている。 Next, an ITO film is formed on a Si substrate, a Cu layer having a thickness of 150 nm is further formed by sputtering on the ITO film, and a CuNi layer having a thickness of 20 nm is further sputtered on the surface of the Cu layer. Formed. Subsequently, the etching rate was measured using an etching solution containing ammonium persulfate. In the experiment, the Ni composition ratio of the CuNi alloy was varied within the range of 0 wt% to 50 wt%, and the relationship between each Ni composition ratio and the etching rate was examined. The experimental results are shown in FIG.
　図１１に示すように、エッチングレートはＮｉ組成比が約１０ｗｔ％より大きくなると徐々に小さくなり、Ｎｉ組成比が５０ｗｔ％になるとエッチングレートが非常に小さくなることがわかった。この結果、Ｎｉ組成比が高すぎると、過硫酸アンモニウムを含むエッチング液では、ＣｕＮｉ合金層を適切にエッチングできず、エッチング液が２液必要になることがわかった。 As shown in FIG. 11, it was found that the etching rate gradually decreased as the Ni composition ratio became larger than about 10 wt%, and the etching rate became very small as the Ni composition ratio became 50 wt%. As a result, it was found that when the Ni composition ratio is too high, the etching solution containing ammonium persulfate can not properly etch the CuNi alloy layer, and two etching solutions are required.
　続いて、図５（ｂ）のように不要な部分をＣｕＮｉ合金層及びＣｕ層をウエットエッチングで除去したときにおけるＣｕＮｉ合金層のＮｉ組成比とサイドエッチングの最大後退量との関係を調べた。 Subsequently, as shown in FIG. 5B, when the unnecessary portion was removed by wet etching the CuNi alloy layer and the Cu layer, the relationship between the Ni composition ratio of the CuNi alloy layer and the maximum amount of receding side etching was investigated.
　実験では、フォトリソグラフィ技術により、配線幅が３０μｍ、各配線部の間隔が３０μｍとなるレジスト層（マスク層）を形成して、前記レジスト層に覆われていないＣｕＮｉ合金層及びＣｕ層を過硫酸アンモニウムを含むエッチング液によりウエットエッチングした実験サンプル１と、フォトリソグラフィ技術により、配線幅が５０μｍ、各配線部の間隔が５０μｍとなるレジスト層（マスク層）を形成して、前記レジスト層に覆われていないＣｕＮｉ合金層及びＣｕ層を過硫酸アンモニウムを含むエッチング液によりウエットエッチングした実験サンプル２とを形成した。 In the experiment, a resist layer (mask layer) having a wiring width of 30 μm and an interval between wiring parts of 30 μm is formed by photolithography technology, and the CuNi alloy layer and Cu layer not covered with the resist layer are ammonium persulfate And a resist layer (mask layer) having a wiring width of 50 μm and an interval of each wiring portion of 50 μm by photolithography technology, and covered with the resist layer. An experimental sample 2 was formed by wet etching a CuNi alloy layer and a Cu layer with an etchant containing ammonium persulfate.
　そして、サイドエッチングの最大後退量を測定した。最大後退量は、図５（ｃ）や図６に示すレジスト層の側縁部の位置から配線部の片側の側面までの最大凹み量で示した。その実験結果が図１２に示されている。図１２に示すように、ＣｕＮｉ合金層のＮｉ組成比が大きくなると、徐々にサイドエッチングにおける最大後退量が小さくなることがわかった。 Then, the maximum amount of recession of the side etching was measured. The maximum retraction amount is indicated by the maximum recess amount from the position of the side edge of the resist layer shown in FIG. 5C and FIG. 6 to the side surface on one side of the wiring portion. The experimental results are shown in FIG. As shown in FIG. 12, it was found that as the Ni composition ratio of the CuNi alloy layer increases, the maximum amount of retraction in side etching gradually decreases.
　図１３は、上記した実験サンプル１及び実験サンプル２において、配線部の表面の変色した幅寸法を測定した実験結果である。図１３に示すように、Ｎｉ組成比が大きくなると徐々に変色の幅寸法を小さくできることがわかった。変色は表面の酸化等で生じたものである。 FIG. 13 shows an experimental result of measuring the discolored width dimension of the surface of the wiring portion in the above-described Experimental Sample 1 and Experimental Sample 2. As shown in FIG. 13, it was found that the width dimension of the color change can be gradually reduced as the Ni composition ratio increases. The discoloration is caused by surface oxidation and the like.
　図８ないし図１３に示す実験結果に基づいて、本実施例では、配線部を、Ｃｕ層とＣｕＮｉ合金層の積層構造とし、ＣｕＮｉ合金層のＮｉ組成比の好ましい範囲を５ｗｔ％～３５ｗｔ％の範囲内とした。これにより、配線抵抗の経時変化を小さく抑えることができ（図９，図１０参照）、また、ＣｕＮｉ合金層のエッチングレートをＣｕ層と同程度に大きくでき（図１１参照）、配線部の表面に形成される酸化等による変色の幅を小さく抑えることができ（図１３参照）、サイドエッチングによる最大後退量を効果的に小さくできる(図１２参照)。またＮｉ組成比のより好ましい範囲を１５ｗｔ％～２５ｗｔ％の範囲内とした。これにより、より効果的に、配線抵抗の経時変化を小さく抑えることができ、サイドエッチングによる最大後退量を小さくできる。更に、エッチングレートを比較的大きくでき、加工時間を短縮し、生産性を向上させることができる。 Based on the experimental results shown in FIGS. 8 to 13, in this example, the wiring portion has a laminated structure of a Cu layer and a CuNi alloy layer, and the preferable range of the Ni composition ratio of the CuNi alloy layer is 5 wt% to 35 wt% Within the range. Thereby, the change with time of the wiring resistance can be kept small (see FIGS. 9 and 10), and the etching rate of the CuNi alloy layer can be made as large as that of the Cu layer (see FIG. 11). The width of the color change due to oxidation or the like formed can be reduced (see FIG. 13), and the maximum amount of retraction by side etching can be effectively reduced (see FIG. 12). Further, the more preferable range of the Ni composition ratio is in the range of 15 wt% to 25 wt%. As a result, the change with time of the wiring resistance can be suppressed more effectively, and the maximum amount of recession due to side etching can be reduced. Furthermore, the etching rate can be made relatively large, the processing time can be shortened, and the productivity can be improved.
　次に、Ｃｕ／ＣｕＮｉ以外の積層構造で配線部を形成した場合について実験を行った。実験では、表面保護効果を測定し、更にエッチング液、配線部のサイドエッチングの制御性について調べた。その実験結果が図１４に示されている。 Next, experiments were conducted on the case where the wiring portion was formed with a laminated structure other than Cu / CuNi. In the experiment, the surface protection effect was measured, and the controllability of the etching liquid and the side etching of the wiring portion was further examined. The experimental results are shown in FIG.
　図１４に示すように、配線部をＣｕ／ＮｉＦｅとした場合、表面保護効果、すなわち酸化等による腐食については、Ｃｕ／ＣｕＮｉとした実施例とほぼ同等であった。しかしながら、ウエットエッチング工程にて、ＮｉＦｅ層とＣｕ層とを別々のエッチング液を用いてエッチングしなければならず２液が必要になり、またサイドエッチングによる最大後退量も、Ｃｕ／ＣｕＮｉとした実施例に比べて変動しやすく、サイドエッチングに対する制御性が悪いことがわかった。また、配線部をＣｕ／ＭｏＮｂとした場合、エッチング液は１液で済んだが、表面保護効果が悪く、更に、サイドエッチングによる最大後退量も、Ｃｕ／ＣｕＮｉとした実施例に比べて大きくなり、サイドエッチングに対する制御性が悪いことがわかった。 As shown in FIG. 14, in the case where the wiring portion is Cu / NiFe, the surface protection effect, that is, corrosion due to oxidation or the like was substantially equivalent to that of the example in which Cu / CuNi was used. However, in the wet etching process, it is necessary to etch the NiFe layer and the Cu layer using different etching solutions, which requires two solutions, and the maximum amount of recession due to side etching is also Cu / CuNi. It turned out that it is easy to fluctuate compared with an example, and controllability to side etching is bad. In addition, when the wiring part is Cu / MoNb, although the etching solution is completed with one solution, the surface protection effect is bad, and further, the maximum amount of receding by side etching is larger than that in the example of Cu / CuNi. It turned out that the controllability to side etching is bad.
　以上により配線部をＣｕ層と、ＣｕＮｉ層との積層構造で形成することが表面保護効果やサイドエッチングの制御性に優れ、更にエッチング液を１液で済み、製造工程を容易にでき、製造コストを低く抑えることができるとわかった。 As described above, it is possible to form the wiring portion in a laminated structure of a Cu layer and a CuNi layer, which is excellent in the surface protection effect and the controllability of side etching, and further requires only one etching solution to facilitate the manufacturing process. It turned out that it can hold down low.
１０　入力装置
１１　入力領域
１２　非入力領域
１３　上部電極部
１４　下部電極部
１５、１７　接続部
１６　配線部
２０　天板
２１　上部基板
２２　下部基板
２３　フレキシブルプリント基板
２４　下部基材
２６、２７　光学透明粘着層
２８　配線下部層
２９　配線主体層
３０　表面保護層
３１　Ｃｕ層
３２　Ｃｕ合金層
３４　透明導電層
３５　レジスト層 REFERENCE SIGNS LIST 10 input device 11 input area 12 non-input area 13 upper electrode portion 14 lower electrode portion 15, 17 connection portion 16 wiring portion 20 top plate 21 upper substrate 22 lower substrate 23 flexible printed substrate 24 lower substrate 26, 27 optically transparent adhesive layer 28 wiring lower layer 29 wiring main layer 30 surface protective layer 31 Cu layer 32 Cu alloy layer 34 transparent conductive layer 35 resist layer

Claims (10)

  1. 　基材と、基材表面の入力領域に設けられた電極部と、前記入力領域の外側に位置する前記基材表面の非入力領域にて前記電極部と電気的に接続された配線部とを有する基板を備え、
    　前記配線部はＣｕから成る配線主体層と、前記配線主体層の表面に形成され、前記配線主体層よりも薄い膜厚のＣｕ合金からなる表面保護層と、で構成されることを特徴とする入力装置。     A substrate, an electrode portion provided in an input area on the surface of the substrate, and a wiring portion electrically connected to the electrode portion in a non-input area on the surface of the substrate located outside the input area Equipped with a substrate
    The wiring portion is characterized by comprising: a wiring main layer made of Cu; and a surface protection layer formed on the surface of the wiring main layer and made of a Cu alloy having a thickness smaller than that of the wiring main layer. Input device.
  2. 　前記表面保護層は、ＣｕＮｉ合金で形成される請求項１記載の入力装置。 The input device according to claim 1, wherein the surface protection layer is formed of a CuNi alloy.
  3. 　ＣｕＮｉ合金中に占めるＮｉ組成比は、５ｗｔ％～３５ｗｔ％の範囲内である請求項２記載の入力装置。 The input device according to claim 2, wherein the Ni composition ratio in the CuNi alloy is in the range of 5 wt% to 35 wt%.
  4. 　Ｎｉ組成比は、１５ｗｔ％～２５ｗｔ％の範囲内である請求項３記載の入力装置。 The input device according to claim 3, wherein the composition ratio of Ni is in the range of 15 wt% to 25 wt%.
  5. 　前記配線部の表面は光学透明粘着層で覆われている請求項１ないし４のいずれか１項に記載の入力装置。 The input device according to any one of claims 1 to 4, wherein the surface of the wiring portion is covered with an optical transparent adhesive layer.
  6. 　基材と、基材表面の入力領域に設けられた電極部と、前記入力領域の外側に位置する前記基板表面の非入力領域にて前記電極部と電気的に接続された配線部とを有する基板を備え、
    　前記非入力領域の基材表面に、Ｃｕ層を形成し、前記Ｃｕ層の表面に、前記Ｃｕ層よりも膜厚の薄いＣｕ合金層を形成する工程、
    　Ｃｕ合金層の表面に前記配線部を形成するためのマスク層を形成する工程、
    　前記マスク層に覆われていないＣｕ合金層及びＣｕ層を連続してウエットエッチングにて除去し、Ｃｕで形成された配線主体層と、前記配線主体層の表面にＣｕ合金で形成された表面保護層とからなる前記配線部を形成する工程、
    　前記マスク層を除去する工程、
    　を有することを特徴とする入力装置の製造方法。     It has a base material, an electrode part provided in an input area on the surface of the base material, and a wiring part electrically connected to the electrode part in a non-input area on the surface of the substrate located outside the input area. Equipped with a substrate
    Forming a Cu layer on the surface of the base material in the non-input area, and forming a Cu alloy layer thinner than the Cu layer on the surface of the Cu layer;
    Forming a mask layer for forming the wiring portion on the surface of the Cu alloy layer;
    The Cu alloy layer and the Cu layer not covered by the mask layer are continuously removed by wet etching, and a wiring main layer formed of Cu and a surface protection formed of Cu alloy on the surface of the wiring main layer Forming the wiring portion comprising a layer;
    Removing the mask layer;
    A method of manufacturing an input device, comprising:
  7. 　基材表面の全体に導電層を形成した後、前記導電層の表面全体に前記Ｃｕ層を形成し、更に前記Ｃｕ層の表面全体にＣｕ合金層を形成する工程、
    　ウエットエッチングにより、前記非入力領域に、Ｃｕからなる前記配線主体層と、Ｃｕ合金からなる表面保護層とで構成される前記配線部を形成する工程、
    　前記入力領域に形成された前記導電層を前記電極部の形状に残すとともに、前記非入力領域に形成された前記導電層を前記配線部下に残し、不要な前記導電層を除去する工程、
    　を有する請求項６記載の入力装置の製造方法。     Forming a conductive layer on the entire surface of the substrate, forming the Cu layer on the entire surface of the conductive layer, and further forming a Cu alloy layer on the entire surface of the Cu layer;
    Forming the wiring portion composed of the wiring main layer made of Cu and a surface protection layer made of a Cu alloy in the non-input area by wet etching;
    Leaving the conductive layer formed in the input region in the shape of the electrode portion and leaving the conductive layer formed in the non-input region under the wiring portion to remove the unnecessary conductive layer;
    The manufacturing method of the input device of Claim 6 which has these.
  8. 　前記Ｃｕ合金層を、ＣｕＮｉ合金層で形成する請求項６又は７に記載の入力装置の製造方法。 The method of manufacturing an input device according to claim 6, wherein the Cu alloy layer is formed of a CuNi alloy layer.
  9. 　ＣｕＮｉ合金中に占めるＮｉ組成比を、５ｗｔ％～３５ｗｔ％の範囲内とする請求項８記載の入力装置の製造方法。 9. The method of manufacturing an input device according to claim 8, wherein the Ni composition ratio in the CuNi alloy is in the range of 5 wt% to 35 wt%.
  10. 　Ｎｉ組成比を、１５ｗｔ％～２５ｗｔ％の範囲内とする請求項９記載の入力装置の製造方法。 The method for manufacturing an input device according to claim 9, wherein the Ni composition ratio is in the range of 15 wt% to 25 wt%.
PCT/JP2011/065511 2010-07-14 2011-07-06 Input device and method for manufacturing same WO2012008346A1 (en)

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