WO2012006869A1 - 电阻型存储器及其制备方法 - Google Patents

电阻型存储器及其制备方法 Download PDF

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Publication number
WO2012006869A1
WO2012006869A1 PCT/CN2011/001162 CN2011001162W WO2012006869A1 WO 2012006869 A1 WO2012006869 A1 WO 2012006869A1 CN 2011001162 W CN2011001162 W CN 2011001162W WO 2012006869 A1 WO2012006869 A1 WO 2012006869A1
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dielectric layer
layer
lower electrode
copper
resistive memory
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French (fr)
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林殷茵
杨玲明
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Fudan University
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Fudan University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/028—Formation of switching materials, e.g. deposition of layers by conversion of electrode material, e.g. oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the invention belongs to the field of memory technology, and specifically relates to a resistive memory
  • the resistive memory reversibly converts the storage medium between the high resistance state (HRS) and the low resistance state (LRS) state by the action of the electrical signal, thereby realizing the storage function.
  • the metal oxide semiconductor material is a storage medium material used for a resistive memory, for example, copper telluride (CuxO, 1 ⁇ ⁇ ⁇ 2 ), tungsten oxide (WOx, K x ⁇ 3 ), titanium Telluride and the like.
  • the first is to form a metal oxide layer as a storage medium layer directly by thin film deposition on the lower electrode; the second is to directly use the metal as a lower electrode, The lower electrode is then oxidized and self-aligned to form a metal oxide layer as a storage medium layer.
  • the second method which has the characteristics of self-alignment and process process, is widely used.
  • the storage characteristics of the storage medium layer formed by oxidation are greatly affected by the uniformity of the metal layer, and the better the bonding property of the metal layer is, the characteristics of the formed metal oxide layer are more consistent, and the resistance type memory is uniform. The better the sex.
  • the metal layer is usually patterned in the dielectric layer, and when the metal layer is formed in the dielectric layer, it is usually necessary to form a diffusion barrier layer to form a metal layer, usually, with a shield.
  • the characteristics of the metal layer in the vicinity of the boundary region of the layer are large compared to the characteristics of the metal layer in the central portion of the metal layer, for example, the grain size is different and the crystal orientation is different.
  • the metal oxide layer is formed by self-aligned oxidation of the metal layer, since the characteristics of the metal layer in the same pattern are largely different, the difference in characteristics of the memory medium layer formed by oxidation is also large.
  • FIG. 1 is a schematic structural view of a prior art CuxO resistive memory.
  • a top view of the resistive memory and a C-C cross-sectional view thereof are shown in FIG.
  • the CuxO resistive memory is generally integrated in the back end copper interconnect structure, that is, the copper lead or the copper plug in the copper interconnect structure is used as the lower electrode to further oxidize to form the storage medium layer.
  • 10 is an interlayer dielectric layer for forming a certain layer of copper leads
  • 11 is an etch stop layer
  • 13 is a caper layer
  • 21 is a diffusion barrier of a copper lead
  • 22 is copper.
  • the seed layer in the lead, 23 is the copper lead in the middle region.
  • the general characteristics of the central region 23 of the copper lead and the seed layer 22 of the copper lead edge region are significantly different, and the grain size and crystal orientation may be different, and the copper lead is deuterated.
  • the central region and the edge region are oxidized at different speeds and the like, the storage characteristics of the CuxO storage medium layer 30 formed by oxidation are not uniform.
  • the cap layer 12 When oxidizing, the cap layer 12 is generally exposed to expose the copper lead for oxidation, but since the feature size is smaller and smaller, the width of the copper lead itself (the left and right direction shown in the figure) is also smaller and smaller, if Only for the patterned oxidation of the central region 23, the opening size of the cap layer 12 must be relatively small, which greatly increases the cost of the process; and, when oxidized, the oxide film also partially diffuses to both sides; therefore, if not concentrated The metal layer is exposed to a smaller size in the central portion, and the CuxO storage medium layer 30 (the dotted line frame area in FIG.
  • layer 30 1) formed on the seed layer 22 and the CuxO storage medium formed on the central portion 23 for the same memory cell
  • the performance of layer 30 is different; for a plurality of memory cells, a CuxO memory dielectric layer of some memory cells may be formed on the central region 23, and a CuxO memory dielectric layer of some memory cells may also be formed on the seed layer 22. Therefore, this resistive memory has a large problem in terms of consistency.
  • an object of the present invention is to improve the consistency of a resistive memory
  • a resistive memory comprising: a lower electrode that is patternedly formed in the first dielectric layer;
  • a second dielectric layer formed on the lower electrode and the first mesa layer, wherein the second dielectric layer is provided with an opening for patterning and exposing the lower electrode;
  • a sidewall formed in the opening of the second dielectric layer for covering an interface region between the lower electrode and the first dielectric layer to expose only a central region of the lower electrode to be partially or completely exposed ;
  • a storage medium layer formed by deuterating the second dielectric layer and the sidewall; and an upper electrode.
  • the resistive memory is integrated in a copper interconnect structure, the storage medium layer being a CuxO memory dielectric layer, wherein 1 ⁇ ⁇ 2.
  • the lower electrode may be a copper lead, or the lower electrode may be a copper plug.
  • the boundary region between the lower electrode and the first shield layer includes a diffusion barrier layer and a copper seed layer.
  • the central portion of the lower electrode is a copper lead region formed by electroplating
  • the first dielectric layer may be an interconnect dielectric layer, and the second dielectric layer may be a capping layer.
  • the first dielectric layer may also be an interlayer dielectric layer, and the second dielectric layer may also be an etch stop layer.
  • the copper interconnect structure is a copper interconnect structure below a 65 nm process node.
  • the sidewall is formed by first depositing a layer of dielectric film to cover the opening, and then etching.
  • the oxidation can be plasma oxidation, thermal oxidation or wet deuteration.
  • a memory comprising a memory array comprising a plurality of the above-described resistive memories arranged in rows and columns.
  • the technical effect of the present invention is to provide a sidewall, which covers the boundary region between the lower electrode and the first dielectric layer, and exposes only the central region of the lower electrode, so that the central region of the lower electrode is self- Aligning the oxide to form the storage medium layer is advantageous for improving the uniformity of the resistive memory.
  • the reliability problem caused by the formation of the storage medium layer due to the boundary region of the lower electrode can be avoided, and the reliability is high.
  • the resistive memory Arrays also help to improve the consistency between multiple resistive memories.
  • the size of the resistive memory is reduced, which is beneficial to improve its storage performance. Attached sleep instructions
  • 1 is a schematic structural view of a prior art CuxO resistive memory
  • FIG. 6 is a schematic structural view of a resistive memory according to an embodiment of the present invention.
  • This reference drawing is a schematic representation of an idealized embodiment of the invention, and the illustrated embodiment of the invention should not be considered limited to the particular shapes of the regions shown in the figures, but rather to include the resulting shapes, such as manufacturing variations. .
  • the curve obtained by dry etching usually has the characteristics of bending or squeezing, but in the illustration of the embodiment of the present invention, it is represented by a rectangle, and the representation in the figure is schematic, but this should not be considered as limiting the present invention.
  • the scope is a schematic representation of an idealized embodiment of the invention, and the illustrated embodiment of the invention should not be considered limited to the particular shapes of the regions shown in the figures, but rather to include the resulting shapes, such as manufacturing variations.
  • the curve obtained by dry etching usually has the characteristics of bending or squeezing, but in the illustration of the embodiment of the present invention, it is represented by a rectangle, and the representation in the figure is schematic, but this should not be considered as limiting the present invention.
  • the scope is a schematic representation
  • FIG. 6 is a schematic structural diagram of a resistive memory according to an embodiment of the invention.
  • a top view of the resistive memory of this embodiment and its AA cross-sectional view are shown in FIG.
  • a resistive memory is integrated in a copper interconnect structure. More specifically, a resistive memory is formed on a copper lead of a copper interconnect structure (ie, a copper lead is used as a resistor).
  • the lower electrode of the type of memory is self-aligned to form a CuxO storage medium layer thereon.
  • the specific number of layers of the copper lead is not limited by the present invention, and for example, it may be the first layer or the third layer or the like. Generally, the copper lead is formed by patterning.
  • the copper lead is formed in the interconnect dielectric layer 10 in a damascene process, and the etch stop layer 11 is under the interconnect dielectric layer 10.
  • the etching is terminated.
  • the interconnect dielectric 10 may be a dielectric material such as Si0 2 or Si 3 N 4 , or may be FSG, USG, or the like.
  • the interconnect dielectric layer 10 when metal wiring is formed in the interconnect dielectric layer 10, it is necessary to prevent metal atoms from diffusing into the interconnect dielectric layer 10, thereby affecting the performance of the interconnect dielectric layer 10.
  • copper metal it is particularly necessary to prevent copper diffusion. Therefore, when a copper lead is formed in a conventional damascene process, a diffusion barrier layer 21 is first formed in the trench, and then formed on the diffusion barrier layer 21 before electroplating to form a copper lead. The copper seed layer 22 is then plated with the central region copper layer 23 to form copper leads. Therefore, the copper lead actually includes the diffusion barrier layer 21, the copper seed layer 22, and the central region copper layer 23.
  • the diffusion barrier layer 21, the copper seed layer 22, and the central region copper layer 23 are sequentially distributed from the edge to the middle of the trench.
  • the diffusion barrier layer 21 may be a TaN, Ta/TaN composite layer or a Ti/TiN composite layer, or other conductive materials that function in the same manner, such as TiSiN, WNx, WNxCy, Ru, TiZr/TiZrN, and the like.
  • the specific material of the diffusion barrier layer 21 is not limited by the embodiments of the present invention and evolves as the process technology advances.
  • the copper seed layer 22 is generally formed by thin film deposition such as sputtering, and its thickness is relatively small as compared with the copper layer 23 in the middle portion (the scale shown in the figure is schematic, the schematic is), the central region copper layer 23 formed by electroplating growth. Therefore, the copper seed layer 22 and the middle region copper layer 23 in the edge region of the trench are both copper materials, but the preparation process is different, so some physical properties are significantly different, for example, the relative grain size of the central region copper layer 23 Larger, crystal orientations, etc. will also vary, all of which affect the speed of the subsequent self-aligned deuteration process, the film properties of the formed CuxO storage medium layer, and the like.
  • a portion between the central region copper layer 23 and the interconnect dielectric layer 10 is defined as a boundary region between the copper wiring and the interconnect dielectric layer 10, and the central region copper layer 23 is surrounded by the boundary region.
  • It may include different conductive materials such as the diffusion barrier layer 21, and includes a copper metal material having physical properties different from that of the central region copper layer 23.
  • the metal in the trench (or in the hole) of the shield layer has a diffusion barrier. Even if there is no diffusion barrier, the metal is at the boundary between the meso layer and the metal layer due to the difference in interface properties.
  • the physical properties of the layers are significantly different. Therefore, for all the metal lower electrodes formed in the dielectric layer, we can distinguish them into the junction area and the middle area.
  • the physical structure and characteristics of the lower electrode in the middle area are relatively more consistent, and the junction area is relatively more physical. A junction area that changes and has inconsistent characteristics.
  • the resistive memory further includes a cap layer 12 that can be used to prevent electromigration of the upper surface of the copper leads in a copper interconnect structure.
  • the cap layer 205 is also an insulating dielectric layer, and may specifically be Si 3 N 4 , SiON, SiCN, SiC, SiO 2 or a composite layer containing one of them.
  • An opening as shown is formed on the cap layer 12 to pattern the exposed copper leads.
  • the size of the process features continues to decrease, the size of the copper interconnect structure is also scaled down, and the width of the copper leads (the size in the left and right directions in the figure) is also decreasing.
  • the size of the opening is required to be smaller, so that the composition is more demanded, for example, the precision of photolithography is required to be greatly improved, and thus the light may be greatly increased.
  • the cost of engraving the composition For example, if the copper lead has a width dimension of 90 nm and the central region copper 30 has a width dimension of 45 nm, it is relatively easy to form a 90 nm-sized opening under the existing lithography technique for forming the copper interconnect structure.
  • the resistive memory of the present invention is more suitable for Small-sized process generation structures, for example, in copper interconnect structures below the 65-nm process node).
  • the opening is also formed on the cap layer 12 including the copper lead, but it is ingenious in that it further includes the side wall 40 formed on the edge of the opening of the cap layer 12, according to The specific size of the interface area and the size of the opening, the width dimension of the side wall 40 is designed such that the side wall 40 can substantially cover the copper lead of the interface area, for example, covering the copper seed layer 22, so that the size of the mouth is small, only part or All of the central region copper 30 is exposed; the central region copper 30 has a relatively uniform physical structure and uniform performance, so that the CuxO storage medium layer 30 formed thereon is also self-aligned.
  • the size of the opening is reduced, and the storage of the resistive memory is achieved. The size of the medium is reduced, which is advantageous for reducing the size of the resistive memory and improving the storage performance.
  • the storage medium layer 30 is typically formed by plasma oxidation, but the particular method of oxidation and thickness are not limited by the embodiments of the present invention.
  • Mt's During the process, the exposed copper leads may be laterally oxidized, thereby forming a part of the storage medium layer under the sidewall 40. If the copper lead forming the portion of the storage medium layer is the copper seed layer 23, the storage medium layer may also be caused.
  • the storage characteristics of 30 are inconsistent. In order to avoid this as much as possible, the width dimension of the side wall 40 can be appropriately increased, and only a part of the central portion copper 30 is exposed, so that the storage medium layer 30 can be formed by the central region copper 30.
  • the resistive memory further includes an upper electrode 50 formed on the memory dielectric layer 30, and the upper electrode 50 may be TaN, Ta, TiN, Ti, Cu, Al, Ni or Co, etc.
  • the specific materials are not limited by the embodiments of the present invention.
  • the upper electrode 50 is formed in a hole formed by the side wall 40.
  • FIGS. 2 to 6 are views showing a process of forming a resistive memory of the embodiment shown in Fig. 6. The preparation process of the resistive memory will be described in detail below with reference to Figs. 2 to 2 .
  • a structure is provided before forming a cap layer in a copper interconnect structure, and a copper lead is formed in a trench of the interconnect dielectric layer 10 by damascene, specifically, A CVD (Chemical Vapor Deposition) or PVD (Physical Vapor Deposition) deposition in the trench forms a diffusion barrier layer 21, and then PVD is deposited to form a copper seed layer 22, which is then electroplated to form a copper region in the middle region of the copper layer 23b trench.
  • the width is defined as D1, and therefore, the width of the copper lead is also D1.
  • the metal lower electrode formed in the dielectric layer 10 we can distinguish it as the boundary region and the middle region, and the boundary region is the diffusion barrier layer 21 and the copper seed.
  • the central region is the copper layer 23 in the middle region, and the physical structure and characteristics of the lower electrode in the central region are relatively more uniform, and the boundary region is a relatively more and more uneven interface region. Therefore, in the invention, efforts are made to self-align the storage medium of the resistive memory to the central region copper layer 23, thereby making the characteristics of the storage medium more uniform and the characteristics of the memory more uniform.
  • the dielectric layer 10 and the copper leads are CVD grown to form the cap layer 12, and an opening 121 is patterned on the cap layer 12 to expose the copper leads.
  • An opening 121 is formed on the cap layer 12 by a photolithography and etching step.
  • the size D2 of the opening 121 may be substantially equal to the width dimension D1 of the copper lead.
  • the dimension D2 of the opening 121 is slightly smaller than the width dimension D1 of the copper lead.
  • most of the junction areas are exposed by openings.
  • the specific selection of the size D2 can be selected according to the width dimension D1 of the copper lead and the process of the photolithography. If it is difficult to lithographically form an opening pattern smaller than the D1 size, the opening pattern of the D1 size can be formed.
  • the side wall 40 is formed at the edge of the opening 121 of the cap layer 12.
  • the sidewall 40 is formed by first depositing a dielectric film layer covering the opening 121 and then etching.
  • the specific forming method of the sidewall is known to those skilled in the art and will not be described in detail herein.
  • the thickness of the dielectric film layer deposited thereon determines the width dimension of the sidewall 40, that is, the size D3 of the opening 41 in the sidewall 40, and the size of the original opening 121 is reduced due to the presence of the sidewall.
  • the area exposed by the copper leads is smaller and concentrated in the more central area.
  • the opening 41 of the dimension D3 partially exposes the copper layer 23 in the central portion of the copper lead, ready for the next oxidation.
  • the size D3 of the opening 41 can be selected according to factors such as the size of the central region copper layer 23, the area of the storage medium layer, and the like, for example, D3 is 10-100 nm smaller than D1.
  • the specific material of the side wall 40 may be a shield layer such as Si0 2 or Si 3 N 4 .
  • self-aligned oxidation forms a CuxO memory shield layer 30, and the size of the CuxO memory dielectric layer 30 is determined by the size D3 of the opening 41.
  • it may be plasma oxidation, thermal deuteration, or chemical wet deuteration, or may be a mixture of plasma oxidation and thermal oxidation.
  • Specific oxidation methods and oxidation conditions are well known to those skilled in the art, and
  • the central region copper 30 has the same physical structure and uniform performance
  • the CuxO storage shield layer 30 formed on the self-aligned layer also has the same performance.
  • the memory performance between them is more uniform.
  • the deposited metal layer forms the upper electrode 50.
  • a metal layer is first deposited by CVD in the opening 41, and then the upper electrode 50 is formed by chemical mechanical polishing (CMP).
  • resistive memory of the embodiment shown in Fig. 6 is formed.
  • the manufacturing process of the subsequent copper interconnect process is well known to those skilled in the art and will not be described again here.
  • FIG. 7 is a schematic structural view of a resistive memory according to still another embodiment of the present invention.
  • the resistive memory is integrated in the copper interconnect structure, but is not formed in the copper lead of the embodiment shown in FIG. 6. Upper, but formed on the copper plug of the copper interconnect structure.
  • the copper plug including the diffusion barrier layer 21, the copper seed layer 22, and the central region copper layer 23 is formed on the interlayer dielectric layer (IMD).
  • IMD interlayer dielectric layer
  • 1 is an upper etch stop layer 15 over the interlayer dielectric layer (IMD) 14, and a second etch stop layer 11 under the interlayer dielectric layer (IMD) 14.
  • a circular opening is formed in the first etch stop layer 15 to expose the copper plug, and similarly, the area of the circular opening is reduced by forming the side wall 40 (the circular opening diameter is reduced to D4) Only the central region copper layer 23 is partially or completely exposed and self-aligned.
  • the CuxO resistive memory structure with the side wall structure can also be applied to other resistive memories to improve the consistency, such as tungsten oxide resistive memory, titanium oxide resistive memory, etc.
  • each of the resistive memories in the array is formed by self-aligned oxidation of the central portion of the lower electrode, so that the consistency of the memory array is good.
  • the memory of the present invention can be formed by further integrating the peripheral circuits of the resistive memory by the memory array.
  • the peripheral circuit is known to those skilled in the art and will not be described in detail herein.

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Abstract

提供了一种电阻型存储器及其制备方法。该电阻型存储器包括：下电极，其被构图地形成于第一介质层（10）中；第二介质层（12），形成于下电极和第一介质层上；形成于第二介质层的开口（121）中的边墙（40），用于覆盖下电极与第一介质层的交界区域以仅使下电极的中部区域被部分地或全部地暴露；以第二介质层和边墙为掩膜氧化形成的存储介质层（30）；以及上电极（50）。该电阻型存储器的一致性好、可靠性高，并且单元尺寸小、有利于提高存储特性。

Description

电阻型存储器及其制备方法
技术领城
本发明属于存储器技术领域， 具体^及一种电阻型存储器
( Resistive Memory )及其制备方法. 背景技术
作为 Flash存储器的未来替换技术之一， 电阻型存储器由于其高密 度、 低成本、 可突破工艺技术代发展限制的等特点引起广泛关注。 电 阻型存储器通过电信号的作用， 使存储介质在高电阻状态 （High Resistance State, HRS )和^氐电阻（ Low Resistance State, LRS )状态之 间可逆转换， 从而实现存储功能。 其中金属氧化物半导体材料是电阻 型存储器所使用的一种存储介质材料， 例如， 铜的氡化物 （CuxO, 1 < χ < 2 ) , 钨的氧化物 ( WOx, K x < 3 ) 、 钛的氡化物等。
金属氧化物的制备基本有以下两种方法： 第一种是， 直接在下电 极上通过薄膜沉积的方法形成作为存储介质层的金属氧化物层； 第二 种是， 直接 该种金属作为下电极， 然后对该下电极进行氧化自对准 形成作为存储介质层的金属氧化物层.其中第二种方法，具有自对准、 工艺过程筒单的特点而被广泛使用。
在第二种方法中， 氧化形成的存储介质层的存储特性受金属层的 均匀性影响较大， 金属层均勾性越好， 所形成的金属氧化物层特性更 一致， 电阻型存储器的一致性越好。
但是，在形成下电极时，金属层通常是被构图地形成在介质层中， 而金属层在形成于介质层中时， 通常需要先形成扩散阻挡层等才能形 成金属层， 通常， 与介盾层的交界区域附近的金属层的特性相比于金 属层中部区域的金属层的特性， 其差异较大， 例如， 晶粒尺寸不同、 晶向不同。 以该金属层自对准氧化形成金属氧化物层时， 由于同一构 图中的金属层的特性差异较大， 因此， 其氧化形成的存储介质层的特 性差异也较大。特别是随着尺寸不断按比例缩小，对于每个存储单元， 难以保证自对准于金属层的中部区域氧化形成存储介质层； 从而， 对 于很多个存储单元， 更难以保"^所有都自对准于金属层的中部区域氧 化形成存储介质层。 因此， 这种方法形成电阻型存储器时， 其存储器 的一致性受到挑战 β
以下具体以 CuxO电阻型存储器为例说明以上的问题，
图 1所示为现有技术的 CuxO电阻型存储器的结构示意图。 图 1 中示出了电阻型存储器的俯视图及其 C-C截面图。现有技术中， CuxO 电阻型存储器一般是集成于后端铜互连结构中， 即以铜互连结构中铜 引线或者铜栓塞作为下电极， 进一步氧化形成存储介质层。 如图 1所 示， 10为用于形成某一层铜引线的层间介质层， 11 为刻蚀终止层， 13为盖帽层 ( Caper Layer ) , 21为铜引线的扩散阻挡层， 22为铜引 线中的籽晶层， 23为中部区域的铜引线。 铜引线的中部区域 23和铜 引线边沿区域的籽晶层 22 (即与介质层的交界区域）一般特性是明显 不同的， 晶粒尺寸和晶向等会有所差异， 以该铜引线氡化时， 中部区 域与边缘区域的氧化的速度等会有所差异， 氧化形成的 CuxO存储介 质层 30的存储特性也不会均勾。 在进行氧化时， 一般是对盖帽层 12 开孔暴露铜引线以氧化， 但是， 由于特征尺寸越来越小， 铜引线本身 的宽度 （图中所示的左右方向）也越来越小， 如果仅对中部区域 23 暴露构图氧化， 盖帽层 12 开孔尺寸必须相对很小， 其会大大增加工 艺的成本； 并且， 在氧化时， 氧化薄膜也会部分地向两边扩散生长； 因此， 如果不集中于中部区域更小尺寸地暴露该金属层， 对于同一存 储单元， 形成于籽晶层 22上的 CuxO存储介质层 30 (图 1 中的虚线 框区域） 和形成于中部区域 23上的 CuxO存储介质层 30的性能是不 同的； 对于多个存储单元， 有的存储单元的 CuxO存储介质层可能是 形成在中部区域 23上，有的存储单元的 CuxO存储介质层可能还形成 在籽晶层 22上； 因此， 该电阻型存储器会在一致性方面存在较大的 问题。
同样， 对于被构图地形成在介质层中其它下电极材料（例如钨）， 同样存在以上问题。 明内睿
针对以上所述问题， 本发明的目的在于， 提高电阻型存储存储器 的一致性；
为实现以上目的或者其它目的， 本发明提供以下技术方案： 按照本发明的一方面， 提供一种电阻型存储器， 其包括： 下电极， 其被构图地形成于第一介质层中；
第二介质层， 形成于所述下电极和第一介庸层上， 所述第二介质 层中设置有用于构图暴露所述下电极的开口；
形成于所迷第二介质层的开口中的边墙， 其用于覆盖所述下电极 与所述笫一介质层的交界区域以仅使所述下电极的中部区域被部分 地或全部地暴露；
以所述第二介质层和边墻为掩膜氡化形成的存储介质层； 以及 上电极。
在本发明所提供的电阻型存储器的一个实施例中， 所迷电阻型存 储器集成于铜互连结构中， 所述存储介质层为 CuxO存储介质层， 其 中 1 < χ 2。
在上述的电阻型存储器中， 所述下电极可以为铜引线， 或所述下 电极可以为铜栓塞。
在上述的电阻型存储器中， 所述下电极与所迷第一介盾层的交界 区域包括扩散阻挡层和铜籽晶层。
在上述的电阻型存储器中， 所述下电极的中部区域为电镀生成的 铜引线区域，
在上述的电阻型存储器中， 所述第一介盾层可以为互连线介质 层， 所述第二介质层可以为盖帽层。 所述第一介盾层也可以为层间介 质层， 所述第二介质层也可以为刻蚀终止层。
在上述的电阻型存储器中， 较佳地， 所迷铜互连结构为 65 纳米 工艺节点以下的铜互连结构。
按照本发明的又一方面， 提供一种制备上述电阻型存储器的方 法， 其包括以下步骤：
提供被构图地形成于第一介凓层中的下电极；
在所述下电极和第一介质层上覆盖形成第二介质层；
在所述第二介盾层上形成暴露所述下电极的开口；
在所迷开口中形成用于覆盖所述下电极与所述第一介盾层的交 界区域以仅使所述下电极的中部区域被部分地或全部地仅暴露的边 墻；
以所述第二介质层和边墙为掩膜氧化形成存储介质层；
沉积上电极。 具体地， 所述边墻是通过先沉积一层介质薄膜层覆盖所述开口、 然后再刻蚀形成。所述氧化可以为等离子氧化、热氧化或者湿法氡化。
按照本发明的再一方面还提供一种存储器， 包括存储阵列， 所述 存储阵列包括按行和列的形式排列的多个以上所述的电阻型存储器。
本发明的技术效果是， 通过设置边墻， 其覆盖所述下电极与所述 第一介质层的交界区域、 并仅暴露所述下电极的中部区域， 从而以所 述下电极的中部区域自对准氧化形成存储介质层， 有利于提高电阻型 存储器的一致性， 同时， 也可以避免因下电极的交界区域被氧化形成 存储介质层时导致的可靠性问题，可靠性高.对于电阻型存储器阵列， 也有利于提高多个电阻型存储器之间的一致性。 同时， 电阻型存储器 的尺寸得以缩小， 有利于提高其存储性能。 附困说明
从结合附图的以下详细说明中， 将会使本发明的上述和其它目的 及优点更加完全清楚，其中，相同或相似的要素采用相同的标号表示。
图 1是现有技术的 CuxO电阻型存储器的结构示意图；
图 2至图 6是形成图 6所示实施例电阻型存储器的制备过程图； 图 6是按照本发明一实施例提供的电阻型存储器的结构示意图； 图 7是按照本发明又一实施例的电阻型存储器的结构示意图。 具体实施方式
在、下文中结合图示在参考实施例中更完全地描迷本发明， 本发明 提供优选实施例，但不应该被认为仅限于在此阐述的实施例。在图中， 为了清楚放大了层和区域的厚度， 但作为示意图不应该被认为严格反 映了几何尺寸的比例关系。
此参考图是本发明的理想化实施例的示意图， 本发明所示的实 施例不应该被认为仅限于图中所示的区域的特定形状， 而是包括所得 到的形状， 比如制造引起的偏差。 例如干法刻蚀得到的曲线通常具有 弯曲或囫润的特点， 但在本发明实施例图示中， 均以矩形表示， 图中 的表示是示意性的， 但这不应该被认为限制本发明的范围。
图 6所示为按照本发明一实施例提供的电阻型存储器的结构示意 图。 图 6中示出了该实施例电阻型存储器的俯视图及其 A-A截面图。 如图 6所示， 在该实施例中， 以电阻型存储器集成于铜互连结构中为 例， 更具体地， 电阻型存储器形成于铜互连结构的铜引线上（即以铜 引线作为电阻型存储器的下电极， 在其上面自对准氡化形成 CuxO存 储介质层） 。 铜引线的具体所在的层数不受本发明限制， 例如， 其可 以为第一层或者第三层等。 通常地， 铜引线是以一定形状构图形成， 在该实施例中， 铜引线以大马士革工艺形成于互连线介质层 10 中， 互连线介质层 10之下为刻蚀终止层 11 ,其用于在对层间介质层 10构 图刻蚀形成沟槽（Trench )时、 起终止刻蚀作用， 互连线介质 10可以 为 Si02、 Si3N4等介质材料， 还可以为 FSG、 USG等 low-k材料， 或 者还可以为其它起到同样作用的材料。
通常地， 在互连线介质层 10 中形成金属连线时， 需要防止金属 原子扩散至互连线介质层 10中， 从而影响互连线介质层 10的性能。 具体地， 对于铜金属， 尤其需要防止铜扩散， 因此， 以常规大马士革 工艺形成铜引线时， 先在沟槽中形成扩散阻挡层 21， 然后在电镀形成 铜引线之前， 在扩散阻挡层 21上形成铜籽晶层 22, 然后再电镀中部 区域铜层 23， 从而形成铜引线。 因此， 铜引线实际上是包括扩散阻挡 层 21、 铜籽晶层 22以及中部区域铜层 23， 扩散阻挡层 21、 铜籽晶层 22、 中部区域铜层 23 由沟槽的边沿至中部依次分布。 其中， 扩散阻 挡层 21可以为 TaN、 Ta/TaN复合层或是 Ti/TiN复合层， 或是其它起 到同样作用的导电材料， 如 TiSiN、 WNx、 WNxCy、 Ru、 TiZr/TiZrN 等。 扩散阻挡层 21 的具体材料不受本发明实施例限制， 并随着工艺 技术代的进步而演变。 铜籽晶层 22—般是通过溅射等薄膜沉积的办 法形成， 其厚度相对于中部区域铜层 23 —般比较小 （图中所示尺寸 比例尸、是示意性的） ， 中部区域铜层 23 通过电镀生长形成。 因此， 沟槽边沿区域的铜籽晶层 22和中部区域铜层 23虽然都是铜材料， 但 是制备工艺不同， 因此某些物理特性是明显不同的， 例如， 中部区域 铜层 23 相对晶粒尺寸更大， 晶向等也会有所差异， 这些都影响后续 自对准氡化过程的速度、 形成的 CuxO存储介质层的薄膜性能等。 因 此， 在该实施例中， 将中部区域铜层 23与互连线介质层 10之间的部 分定义为铜引线与互连线介质层 10的交界区域， 中部区域铜层 23被 交界区域所包围， 可能包括犷散阻挡层 21 等不同的导电材料， 并包 括物理特性不同于中部区域铜层 23 的铜金属材料。 对于其它形成于 介盾层的沟槽中 （或孔洞中） 的金属， 大部分都存在扩散阻挡层， 即 使不存在扩散阻挡层， 也会由于界面特性差异， 在介庸层与金属层的 交界处， 其金属层的物理特性是明显有所差异的。 因此， 对于所有形 成于介质层中的金属下电极， 我们可以将其区分为交界区域和中部区 域， 中部区域的下电极的物理结构和特性相对更为一致， 交界区域是 相对更为物理结构多变且特性不一致的交界区域。
继续如图 6所示，该电阻型存储器还包括盖帽层（Cap Layer ) 12, 在铜互连结构中，其可以用来防止铜引线上表面的电迁移。盖帽层 205 也为绝缘介质层， 具体可以为 Si3N4、 SiON、 SiCN、 SiC、 Si02或者 包含其中之一的复合层。 盖帽层 12上形成如图所示的开口， 从而构 图暴露了铜引线。 随着工艺特征尺寸的不断减小， 铜互连结构的尺寸 也按比例缩小， 铜引线的宽度（图中左右方向的尺寸）也不断减小。 如果直接在盖帽层 12上开口仅暴露部分中部区域铜 30， 该开口的尺 寸要求更小， 因此对构图的要求更高， 例如， 要求光刻的精度大大提 高， 因此， 可能会大大加大光刻构图的成本。 例如， 如果铜引线的宽 度尺寸是 90纳米， 中部区域铜 30的宽度尺寸是 45纳米， 在现有形 成该铜互连结构的光刻技术代下， 形成 90納米尺寸的开口是比较容 易的， 但是如果要形成 45 纳米的开口， 则要采用更为先进的光刻技 术代， 而光刻技术的提高， 是需要很大的设备成本以及技术要求（因 此， 本发明的电阻型存储更适应于小尺寸工艺代的结构中， 例如， 65 纳米工艺节点以下的铜互连结构中） 。 因此， 在该发明中， 同样现有 技术一样， 同样是在盖帽层 12上形成开口包括铜引线， 但其巧妙之 处在于， 还包括形成于盖帽层 12的开口的边沿的边墙 40, 根据交界 区域的具体尺寸以及开口的尺寸， 设计边墙 40 的宽度尺寸， 从而边 墻 40可以基本覆盖交界区域的铜引线， 例如覆盖铜籽晶层 22， 这样 幵口的尺寸变小， 仅部分或者全部暴露中部区域铜 30; 中部区域铜 30相对物理结构均匀、 性能一致， 因此在其上自对准形成的 CuxO存 储介质层 30也性能一致 另外， 由于开口的尺寸减小， 电阻型存储 器的存储介质的尺寸减小， 有利于减小电阻型存储器的尺寸， 提高存 储性能。
继续如图 6所示， 存储介质层 30通常是通过等离子氧化形成， 但是其具体氧化方法以及厚度不受本发明是实施例限制。 在! Mt的过 程中， 暴露的铜引线可能会横向氧化、 从而在边墻 40 下也形成部分 存储介质层， 如果形成该部分存储介质层的铜引线为铜籽晶层 23， 则 也可能会造成存储介质层 30 的存储特性不一致。 为尽可能避免这种 情况， 可以适当增加边墻 40的宽度尺寸， 仅使部分中部区域铜 30暴 露， 这样， 可以保证存储介质层 30都是以中部区域铜 30氡化形成。
继续如图 6 所示， 该电阻型存储器还包括形成于存储介质层 30 之上的上电极 50， 上电极 50可以为是 TaN、 Ta、 TiN、 Ti、 Cu、 Al、 Ni或者 Co等， 其具体材料不受本发明实施例限制。 在该实施例中， 上电极 50形成于边墙 40所包围形成的孔洞中
图 6中仅示出了铜互连结构中的形成电阻型存储器的部分， 其它 部分的铜互连结构为本领域技术人员所公知， 因此不在图中示出并一 一赘迷。
图 2至图 6所示为形成图 6所示实施例电阻型存储器的制备过程 图。 以下结合图 2至图 所示对该电阻型存储器的制备过程作详细说 明。
首先， 如图 2所示， 提供在铜互连结构中形成铜引线后、 形成盖 帽层之前的结构， 铜引线通过镶嵌形成于互连线介质层 10的沟槽中， 具体地， 先通过在沟槽中 CVD (化学气相淀积） 或 PVD (物理气相 淀积）沉积形成扩散阻挡层 21 , 然后 PVD沉积形成铜籽晶层 22， 再 然后电镀生长形成铜引线的中部区域铜层 23b沟槽的宽度定义为 D1 , 因此，铜引线的宽度也为 D1 ,对于形成于介质层 10中的金属下电极， 我们可以将其区分为交界区域和中部区域，交界区域为扩散阻挡层 21 和铜籽晶层 22， 中部区域即为中部区域铜层 23， 中部区域的下电极 的物理结构和特性相对更为均勾， 交界区域是相对更为物理结构多变 且不均匀的交界区域。 因此， 在该发明中， 努力使电阻型存储器的存 储介质自对准于中部区域铜层 23 而形成， 从而使存储介质的特性更 一致， 存储器的特性从而更加一致。
进一步， 如图 3所示， 介质层 10和铜引线上 CVD生长形成盖帽 层 12, 并在盖帽层 12上构图形成开口 121以暴露铜引线。 盖帽层 12 上通过光刻、 刻蚀步骤形成开口 121 , 开口 121的尺寸 D2可以基本 等于铜引线的宽度尺寸 Dl， 在该实施例中， 开口 121的尺寸 D2稍小 于铜引线的宽度尺寸 Dl， 但还是有大部分的交界区域被开口暴露。 尺寸 D2的具体选择可以根据铜引线的宽度尺寸 D1 以及光刻的工艺 奈件选择， 如果难以光刻形成小于 D1 尺寸的开口图形， 则形求 D1 尺寸的开口图形即可。
进一步， 如图 4所示， 在盖帽层 12的开口 121的边沿形成边墙 40。 具体地， 边墻 40是通过先沉积一层介质薄膜层覆盖开口 121、 然 后再刻蚀形成， 边墙的具体形成方法为本领域技术人员所公知， 在此 不再详述。 其所沉积的介质薄膜层的厚度决定了边墻 40的宽度尺寸， 也即决定了边墙 40中的开口 41的尺寸 D3, 由于边墙的存在， 将原 有的开口 121的尺寸缩小， 从而铜引线所暴露的区域更缩小并集中于 更中部区域。 在该实施例中， 尺寸 D3的开口 41部分地暴露铜引线的 中部区域铜层 23， 准备进行下一步的氧化。 开口 41的尺寸 D3可以 根据中部区域铜层 23 的尺寸、 存储介质层的面积等因素选择决定， 例如， D3相对于 D1小 10-100纳米。边墻 40的具体材料可以为 Si02、 Si3N4等介盾层。
进一步， 如图 5所示， 以盖帽层 12和边墻 40为掩膜， 自对准氧 化形成 CuxO存储介盾层 30, CuxO存储介质层 30的尺寸由开口 41 的尺寸 D3所决定。 具体地， 可以为等离子体氧化、 热氡化、 或者化 学湿法氡化， 也可以为等离子氧化和热氧化的混合进行， 具体的氧化 方法以及氧化条件为本领域技术人员所公知， 在此不再详述， 由于， 中部区域铜 30相对物理结构均勾、 性能一致， 因此在其上自对准形 成的 CuxO存储介盾层 30也性能一致。并且,对于同时形成的多个电 阻型存储器， 相互之间的存储器性能也更为一致。
进一步，如图 6所示，沉积金属层形成上电极 50。在该实施例中， 先在开口 41中 CVD沉积金属层， 然后通过化学机械研磨（CMP )成 型该上电极 50。
至此， 图 6所示实施例的电阻型存储器形成。 后续的铜互连工艺 的制造过程为本领域技术人员所公知， 在此不再附作赘述，
图 7 所示为按照本发明又一实施例的电阻型存储器的结构示意 图， 在该实施例中， 电阻型存储器集成于铜互连结构中， 但是不是形 成于图 6所示实施例的铜引线上，而是形成于铜互连结构的铜栓塞上。 相比于图 6所示的电阻型存储器，其主要区别是，包括扩散阻挡层 21、 铜籽晶层 22、 中部区域铜层 23的铜栓塞形成于层间介质层 （IMD ) 1 中， 层间介质层 （IMD ) 14之上为第一刻蚀终止层 15， 层间介质 层 （IMD ) 14 之下为第二刻蚀终止层 11。 其中， 在该实施例中， 第 一刻蚀终止层 15 中形成圆形开口暴露铜栓塞， 同样地， 然后在通过 形成边墻 40以缩小圆形开口的面积 （圆形开口直径被缩小为 D4 ) , 仅使中部区域铜层 23部分地或全部地暴露并被自对准氧化。
以上实施例中虽然仅以 CuxO电阻型存储器作具体说明。 但是以 上带边墻结构的 CuxO电阻型存储器结构的同样可以类推应用于其它 电阻型存储器以提高一致性， 例如氧化钨电阻型存储器、 氧化钛电阻 型存储器等，
通过以上多个实施例的电阻型存储器按行和列的排列方式形成 存储阵列时， 阵列中的各个电阻型存储器均通过下电极的中部区域自 对准氧化形成， 因此， 存储阵列的一致性好。 通过该存储阵列进一步 结合电阻型存储器的外围电路， 可以形成本发明的存储器。 该外围电 路为本领域技术人负所悉知， 在此不作详迷。
以上例子主要说明了本发明的电阻型存储器及其制备方法， 尽管 只对其中一些本发明的实施方式进行了描述， 但是本领域普通技术人 员应当了解， 本发明可以在不偏离其主旨与范围内以许多其它的形式 实施。因此，所展示的例子与实施方式被视为示意性的而非限制性的， 在不脱离如所附各权利要求所定义的本发明精神及范围的情况下， 本 发明可能涵盖各种的修改与替换。

Claims

^ ^ ^ ^
1. 一种电阻型存储器， 其特征在于， 包括：
下电极, 其被构图地形成于第一介质层中；
第二介质层， 形成于所述下电极和第一介质层上， 所述第二介质 层中设置有用于构图暴露所述下电极的开口；
形成于所述第二介质层的开口中的边墙， 其用于覆盖所述下电极 与所述第一介质层的交界区域以仅使所述下电极的中部区域被部分 地或全部地暴露；
以所述第二介质层和边墙为掩膜氧化形成的存储介质层； 以及 上电极，
2. 如权利要求 1所述的电阻型存储器， 其特征在于， 所迷电阻型 存储器集成于铜互连结构中， 所迷存储介质层为 CuxO存储介质层， 其中 1 < x < 2。
3. 如权利要求 2所述的电阻型存储器， 其特征在于， 所述下电极 为铜引线， 或者所述下电极为铜栓塞。
4. 如权利要求 3所述的电阻型存储器， 其特征在于， 所述下电极 与所述第一介质层的交界区域包括扩散阻挡层和铜籽晶层。
5. 如权利要求 3所述的电阻型存储器， 其特征在于， 所述下电极 的中部区域为电镀生成的铜引线区域。
6. 如权利要求 2所述的电阻型存储器， 其特征在于， 所述第一介 质层为互连线介质层， 所述第二介质层为盖帽层。
7. 如权利要求 3所述的电阻型存储器， 其特征在于， 所述第一介 质层为层间介质层， 所迷笫二介质层为刻蚀终止层。
8. 如权利要求 2所述的电阻型存储器， 其特征在于， 所迷铜互连 结构为 65纳米工艺节点以下的铜互连结构。
9. 一种制备如权利要求 1 所述电阻型存储器的方法， 其特征在 于， 包括以下步骤：
提供被构图地形成于第一介质层中的下电极;
在所述下电极和第一介质层上覆盖形成第二介质层；
在所述笫二介质层上形成暴露所述下电极的开口； 在所述开口中形成用于覆盖所述下电极与所述第一介质层的交 界区域以仅使所述下电极的中部区域被部分地或全部地暴露的边墙； 以所述第二介质层和边墻为掩¾氧化形成存储介质层； 以及 沉积上电极。
10. 如权利要求 9所述的方法， 其特征在于， 所述边墦是通过先 沉积一层介质薄膜层覆盖所述开口、 然后再刻蚀形成。
11. 如权利要求 9所述的方法， 其特征在于， 所述氧化为等离子 氧化、 热氧化、 或者湿法氡化。
12. 一种存储器， 包括存储阵列， 其特征在于， 所迷存储阵列包 括按行和列的形式排列的多个如权利要求 1所述的电阻型存储器。
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