WO2011148446A1 - レベルシフタおよびそれを備えた半導体集積回路 - Google Patents
レベルシフタおよびそれを備えた半導体集積回路 Download PDFInfo
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- WO2011148446A1 WO2011148446A1 PCT/JP2010/007111 JP2010007111W WO2011148446A1 WO 2011148446 A1 WO2011148446 A1 WO 2011148446A1 JP 2010007111 W JP2010007111 W JP 2010007111W WO 2011148446 A1 WO2011148446 A1 WO 2011148446A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
- H03K5/023—Shaping pulses by amplifying using field effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/35613—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit the input circuit having a differential configuration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
- H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/02—Shaping pulses by amplifying
Definitions
- the present invention relates to a level shifter mounted on a semiconductor integrated circuit having different power supply voltages, and more particularly to a level shifter suitable for a semiconductor integrated circuit having transistors having different breakdown voltages and threshold voltages and manufactured by a fine process.
- the power supply voltage (I / O voltage) of an interface portion including many analog circuits is about 2.5 V or 3.3 V
- the power supply voltage (core voltage) of a digital circuit is 1.1 V.
- the voltage reduction is progressing to the extent. That is, recent semiconductor integrated circuits generally have different power supply voltages. Therefore, a level shifter is required for converting a low voltage amplitude signal output from a core operating at a low voltage into a high voltage amplitude and transmitting it to a circuit operating at a high voltage.
- a low voltage amplitude input pulse signal is logically inverted in an inverter circuit operating at a low voltage, and two voltage level shifters operating in opposite directions are complemented by a low voltage amplitude consisting of the input signal and output signal of the inverter circuit.
- the DC component of the low-voltage amplitude input pulse signal is cut, and the input and output are short-circuited.
- the signal biased by the inverter circuit is input to the gates of the Pch transistor and the Nch transistor constituting the inverter circuit that operates at a high voltage (for example, see Patent Document 2).
- JP 2004-40262 A Japanese Patent Laid-Open No. 2003-110419
- a circuit including a transistor having a low withstand voltage and a low threshold voltage (about 0.3 to 0.4 V) among transistors operating at a low voltage has a channel direction, that is, from the viewpoint of preventing transistor characteristic deterioration.
- the arrangement of the drain, gate, and source must be aligned in the same direction.
- an inverter circuit that logically inverts an input pulse signal having a low voltage amplitude is composed of a low withstand voltage / low threshold voltage transistor similar to a transistor used in a digital circuit. receive. Therefore, when the circuit pattern of the level shifter is rectangular, even if there is an empty area in the semiconductor integrated circuit that can be arranged by rotating the circuit pattern by 90 °, such a rotational arrangement cannot be performed. Free space cannot be used effectively.
- the level shifter does not operate correctly even if the inverter circuit is configured with a high threshold voltage transistor that is not subject to placement restrictions instead of the low threshold voltage transistor. Therefore, in order to make effective use of the empty area of the semiconductor integrated circuit, it is necessary to prepare another circuit pattern configured by rotating the channel direction of the low threshold voltage transistor by 90 ° for the level shifter. This will increase the design man-hours.
- the low threshold voltage transistor has a problem that the leakage current is relatively large and a characteristic that deteriorates over time due to kickback from a high voltage power supply.
- the characteristic deterioration of the low voltage circuit directly affects the high speed operability of the level shifter.
- the level shifter disclosed in Patent Document 2 is configured without using a low threshold voltage transistor, and therefore, problems such as an arrangement limitation problem, a leakage current, and aged deterioration of characteristics hardly occur.
- problems such as an arrangement limitation problem, a leakage current, and aged deterioration of characteristics hardly occur.
- the circuit scale increases because a capacitive element for cutting the DC component of the input pulse signal having a low voltage amplitude is required.
- the bias voltage is generated by short-circuiting the input / output of the inverter circuit that operates at a high voltage, there is a problem that the through current always flows through the inverter circuit and the consumption current increases.
- an object of the present invention is to provide a level shifter that can be freely arranged in a fine process, has a small circuit scale and power consumption, and is less likely to deteriorate over time.
- a level shifter that converts a low voltage amplitude input pulse signal into a high voltage amplitude includes a low voltage circuit that generates a low voltage amplitude complementary pulse signal from the input pulse signal, and a high voltage amplitude pulse signal based on the complementary pulse signal.
- a high voltage circuit for generating the low voltage circuit is composed of a high threshold voltage transistor, and is connected between a plurality of cascaded inverter circuits and at least one input / output of the plurality of inverter circuits, and operates as a resistor when conducting. And a resistive switch circuit.
- the resistive switch circuit when the resistive switch circuit is turned on, at least one inverter circuit in the low voltage circuit operates as an amplifier circuit, and an input pulse signal having a low voltage amplitude is converted to a threshold value of the inverter circuit configured by a high threshold voltage transistor. It can be amplified to the extent that the voltage is reached. Therefore, even if the inverter circuit in the low voltage circuit is composed of a high threshold voltage transistor, the level shifter can convert the input pulse signal having a low voltage amplitude into a high voltage amplitude.
- the low voltage circuit may have a plurality of resistive switch circuits.
- the plurality of resistive switch circuits may be controllable independently of each other.
- the level shifter is configured without using the low threshold voltage transistor, it is possible to avoid the arrangement restriction in the fine process.
- the capacitive element for cutting the DC component of the input pulse signal is not used, the circuit scale of the level shifter can be reduced.
- the high threshold voltage transistor is used, the leakage current is reduced, and the deterioration over time due to the kickback from the high voltage power source is also reduced.
- FIG. 1 is a circuit configuration diagram of the level shifter according to the first embodiment.
- FIG. 2 is a circuit configuration diagram of an inverter circuit in the low voltage circuit.
- FIG. 3 is a diagram illustrating a modification of the low voltage circuit.
- FIG. 4 is a circuit configuration diagram of the level shifter according to the second embodiment.
- FIG. 5 is a diagram illustrating an arrangement example of the level shifter on the semiconductor integrated circuit.
- FIG. 1 shows a circuit configuration of a level shifter according to the first embodiment.
- the level shifter according to the present embodiment includes a low voltage circuit 10 that generates a low voltage amplitude complementary pulse signal OUT_L from a low voltage amplitude input pulse signal IN_L, and a high voltage pulse signal OUT_H that generates a high voltage amplitude pulse signal OUT_H based on the signal OUT_L.
- Voltage circuit 20 is a low voltage circuit 10 that generates a low voltage amplitude complementary pulse signal OUT_L from a low voltage amplitude input pulse signal IN_L, and a high voltage pulse signal OUT_H that generates a high voltage amplitude pulse signal OUT_H based on the signal OUT_L.
- the inverter circuit 11 includes a Pch transistor 111 and an Nch transistor 112 connected in series between a low voltage power supply VDDL and a low voltage ground VSSL. Note that these transistors are high threshold voltage transistors that are not subject to arrangement restrictions.
- a resistive switch circuit 12 is connected between the input and output of the inverter circuit 11 in the previous stage.
- the resistive switch circuit 12 is switching-controlled by the control signal CTL and operates as a resistor when it is turned on.
- the resistive switch circuit 12 can be composed of a switch element 121 and a resistance element 122 connected in series as shown, and can also be composed of a Pch or Nch transistor having a channel resistance at the time of turn-on, a transfer gate, or the like.
- the transistors constituting the resistive switch circuit 12 are also high threshold voltage transistors that are not subject to arrangement restrictions.
- the high voltage ground VSSH is connected to the sources of the Nch transistors 21 and 22, and the signal OUT_L is connected to the gate.
- the sources of the Pch transistors 23 and 24 are connected to the high voltage power supply VDDH.
- the drains of the Nch transistors 21 and 22 and the drains of the Pch transistors 23 and 24 are connected to each other, and the drains of the Nch transistors 22 and 21 and the gates of the Pch transistors 23 and 24 are connected to each other.
- a signal OUT_H is obtained by logically inverting the voltage at the connection point between the Pch transistor 24 and the Nch transistor 22.
- the operation of the level shifter configured as described above will be described.
- the signal IN_L is at L level
- the input and output of the subsequent inverter circuit 11 are at H level and L level, respectively, and the Nch transistor 21 is turned on.
- the Pch transistor 24 having the high voltage ground VSSH applied to the gate is turned on, and the voltage at the connection point between the Pch transistor 24 and the Nch transistor 22 becomes the high voltage power supply VDDH, that is, the H level.
- the signal OUT_H is fixed at the L level that is the logical inversion of the connection point between the Pch transistor 24 and the Nch transistor 22.
- the signal IN_L has the same voltage amplitude as that of the low voltage power supply, that is, the H level
- each inverter circuit and each transistor operate in the reverse manner, and the signal OUT_H is determined to be the H level.
- the resistive switch circuit 12 is turned on when the signal IN_L transits. Since the resistive switch circuit 12 behaves as a resistor when conducting, the circuit portion including the inverter circuit 11 and the resistive switch circuit 12 in the previous stage operates as an amplifier circuit. As a result, the signal IN_L is amplified to the extent that it reaches the threshold voltage of the subsequent inverter circuit 11 and is input to the subsequent inverter circuit 11. Therefore, even if the inverter circuit 11 is composed of a high threshold voltage transistor, the level shifter can convert the input pulse signal IN_L having a low voltage amplitude into a high voltage amplitude.
- the resistive switch circuit 12 When the resistive switch circuit 12 is turned on, a current flows from the low voltage power supply or the ground to the input side circuit (not shown) of the signal IN_L via the resistive switch circuit 12, but the resistance of the resistive switch circuit 12 By ensuring a sufficiently large value, the current can be made small enough to be ignored.
- the number of inverter circuits 11 constituting the low voltage circuit 10 is not limited to two.
- the number of resistive switch circuits 12 is not limited to one.
- the low voltage circuit 10 can be configured as shown in FIG. In other words, any configuration may be used as long as a number of inverter circuits 11 are connected in cascade and the complementary pulse signal OUT_L is output from the input pulse signal IN_L.
- the resistive switch circuit 12 only needs to be connected between the input and output of at least one inverter circuit 11. When there are a plurality of resistive switch circuits 12, they may be controlled in the same way by a common control signal CTL, or may be controlled independently of each other.
- Whether or not the resistive switch circuit 12 is to be conducted and how many are to be conducted may be determined according to the frequency of the signal IN_L and the input impedance of the high voltage circuit 20. That is, when the frequency of the signal IN_L is high or the input impedance of the high voltage circuit 20 is large, many resistive switch circuits 12 are turned on to increase the amplification capability. On the other hand, when the frequency of the signal IN_L is low or the input impedance of the high voltage circuit 20 is small, the number of the resistive switch circuits 12 to be conducted is reduced, and in some cases, all the resistive switch circuits 12 are made non-conductive. May be.
- FIG. 4 shows a circuit configuration of the level shifter according to the second embodiment.
- the level shifter according to the present embodiment includes a high voltage circuit 20A having a configuration different from that of the first embodiment.
- a high voltage circuit 20A having a configuration different from that of the first embodiment.
- the signal OUT_L is connected to the gates of the Nch transistors 21 and 22, and the resistive element 25 is connected between the drains.
- the resistive element 25 can be composed of a Pch transistor with a high voltage ground VSSH applied to the gate, an Nch transistor with a high voltage power supply VDDH applied to the gate, or a resistive element.
- a switch circuit 26 is connected to the drains of the Nch transistors 21 and 22. The switch circuit 26 precharges the drains of the Nch transistors 21 and 22 with the high voltage power supply VDDH.
- the switch circuit 26 can be composed of two Pch transistors connected between the drains of the Nch transistors 21 and 22 and the high voltage power supply VDDH.
- a switch circuit 27 is connected to the sources of the Nch transistors 21 and 22. Switch circuit 27 blocks the through current so that current does not flow to the ground when Nch transistors 21 and 22 are precharged.
- the switch circuit 27 can be composed of two Nch transistors connected between the sources of the Nch transistors 21 and 22 and the high voltage ground VSSH.
- the RS latch circuit 28 receives the drain voltages of the Nch transistors 21 and 22 and holds the output state when both drain voltages are at the H level, and the output changes when one of the drain voltages transitions to the L level.
- a signal OUT_H is obtained by logically inverting the output of the RS latch circuit 28.
- the non-inverted output and the inverted output of the RS latch circuit 28 become control signals for the switch circuits 26 and 27. That is, according to the output of the RS latch circuit 28, the switch circuits 26 and 27 connect either drain of the Nch transistors 21 and 22 to the high voltage power supply and disconnect the source from the high voltage ground. It operates to connect the source to the high voltage ground and disconnect the drain from the high voltage power supply.
- the operation of the high voltage circuit 20A is as follows.
- one of the Nch transistors 21 and 22 is turned on in response to the transition of the signal IN_L, and the drain voltage of the Nch transistor is temporarily set to the high voltage ground VSSH, that is, the L level. Become. Therefore, the output of the RS latch circuit 28 changes and the signal OUT_H transitions. Since the drains of the Nch transistors 21 and 22 are short-circuited via the resistive element 25, the drain voltage of the turned-on Nch transistor returns to the H level again, and the RS latch circuit 28 maintains the output state. Even if the signal OUT_L becomes high impedance in this state, the output state of the RS latch circuit 28 does not change. Therefore, the signal OUT_H can be held even when the low voltage circuit 10 stops operating.
- FIG. 5 shows an example of arrangement of level shifters on a semiconductor integrated circuit.
- the level shifter 2 is according to any one of the first and second embodiments, and its circuit pattern is assumed to be rectangular.
- the semiconductor integrated circuit 1 is manufactured by a fine process, and it is assumed that there are empty areas 3 in some places. Since the level shifter 2 is not subject to the arrangement restriction, it can be appropriately rotated according to the empty area 3. Therefore, the chip area can be used effectively.
- the level shifter according to the present invention is useful as a circuit element that propagates a signal between a plurality of circuits operating at different power supply voltages in a semiconductor integrated circuit that is manufactured by a fine process and requires a small area and low power consumption.
- Switch element 122 Resistance element 20 High voltage circuit 20A High voltage circuit 21 Nch transistor (1st Nch transistor) 22 Nch transistor (second Nch transistor) 23 Pch transistor (first Pch transistor) 24 Pch transistor (second Pch transistor) 25 resistive element 26 switch circuit (first switch circuit) 27 Switch circuit (second switch circuit) 28 RS latch circuit
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Abstract
Description
図1は、第1の実施形態に係るレベルシフタの回路構成を示す。本実施形態に係るレベルシフタは、低電圧振幅の入力パルス信号IN_Lから低電圧振幅の相補パルス信号OUT_Lを生成する低電圧回路10と、信号OUT_Lに基づいて高電圧振幅のパルス信号OUT_Hを生成する高電圧回路20とからなる。
第1の実施形態に係るレベルシフタでは、省電力などの目的で低電圧回路10の動作を停止させた場合、信号OUT_Lがハイインピーダンスとなり、信号OUT_Hが不定値となってしまう。そこで、低電圧回路10の動作が停止しても信号OUT_Hを保持できるような高電圧回路を実現する。
2 レベルシフタ
3 空き領域
10 低電圧回路
11 インバータ回路
12 抵抗性スイッチ回路
121 スイッチ素子
122 抵抗素子
20 高電圧回路
20A 高電圧回路
21 Nchトランジスタ(第1のNchトランジスタ)
22 Nchトランジスタ(第2のNchトランジスタ)
23 Pchトランジスタ(第1のPchトランジスタ)
24 Pchトランジスタ(第2のPchトランジスタ)
25 抵抗性素子
26 スイッチ回路(第1のスイッチ回路)
27 スイッチ回路(第2のスイッチ回路)
28 RSラッチ回路
Claims (7)
- 低電圧振幅の入力パルス信号を高電圧振幅に変換するレベルシフタであって、
前記入力パルス信号から低電圧振幅の相補パルス信号を生成する低電圧回路と、
前記相補パルス信号に基づいて高電圧振幅のパルス信号を生成する高電圧回路とを備え、
前記低電圧回路は、
高閾値電圧トランジスタで構成され、縦続接続された複数のインバータ回路と、
前記複数のインバータ回路の少なくとも一つの入出力間に接続され、導通時に抵抗として動作する少なくとも一つの抵抗性スイッチ回路とを有する
ことを特徴とするレベルシフタ。 - 請求項1のレベルシフタにおいて、
前記低電圧回路は、前記抵抗性スイッチ回路を複数個有しており、
前記複数の抵抗性スイッチ回路は、互いに独立に制御可能である
ことを特徴とするレベルシフタ。 - 請求項1のレベルシフタにおいて、
前記抵抗性スイッチ回路は、直列接続されたスイッチ素子および抵抗素子を有する
ことを特徴とするレベルシフタ。 - 請求項1のレベルシフタにおいて、
前記抵抗性スイッチ回路は、ゲートに入力される制御信号によってスイッチング動作するトランジスタである
ことを特徴とするレベルシフタ。 - 請求項1のレベルシフタにおいて、
前記高電圧回路は、
ソースに高電圧グランドが接続され、ゲートに前記相補パルス信号がそれぞれ接続された第1および第2のNchトランジスタと、
ソースに高電圧電源が接続され、ドレインに前記第1および第2のNchトランジスタのドレインがそれぞれ接続され、ゲートに前記第2および第1のNchトランジスタのドレインがそれぞれ接続された第1および第2のPchトランジスタとを有する
ことを特徴とするレベルシフタ。 - 請求項1のレベルシフタにおいて、
前記高電圧回路は、
ゲートに前記相補パルス信号がそれぞれ接続された第1および第2のNchトランジスタと、
前記第1および第2のNchトランジスタのドレイン間に接続された抵抗性素子と、
前記第1および第2のNchトランジスタの各ドレインと高電圧電源との接続の有無を切り替える第1のスイッチ回路と、
前記第1および第2のNchトランジスタの各ソースと高電圧グランドとの接続の有無を切り替える第2のスイッチ回路と、
前記第1および第2のNchトランジスタの各ドレイン電圧を入力とするRSラッチ回路とを有するものであり、
前記第1および第2のスイッチ回路は、前記RSラッチ回路の出力に応じて、前記第1および第2のNchトランジスタのいずれか一方のドレインを高電圧電源に接続するとともにソースを高電圧グランドから切断するとき、他方のソースを高電圧グランドに接続するとともにドレインを高電圧電源から切断する
ことを特徴とするレベルシフタ。 - 請求項1のレベルシフタを備えていることを特徴とする半導体集積回路。
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CN201080066523.6A CN102859877B (zh) | 2010-05-24 | 2010-12-07 | 电平位移器及包括该电平位移器的半导体集成电路 |
JP2012517002A JPWO2011148446A1 (ja) | 2010-05-24 | 2010-12-07 | レベルシフタおよびそれを備えた半導体集積回路 |
US13/685,052 US8653879B2 (en) | 2010-05-24 | 2012-11-26 | Level shifter and semiconductor integrated circuit including the shifter |
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US13/685,052 Continuation US8653879B2 (en) | 2010-05-24 | 2012-11-26 | Level shifter and semiconductor integrated circuit including the shifter |
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US8975943B2 (en) * | 2013-05-29 | 2015-03-10 | Silanna Semiconductor U.S.A., Inc. | Compact level shifter |
TWI581572B (zh) * | 2014-12-17 | 2017-05-01 | 新唐科技股份有限公司 | 具有電壓準位移位器的電路及晶片 |
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JPS63164526A (ja) * | 1986-12-25 | 1988-07-07 | Toshiba Corp | レベルコンバ−タ |
JP2006237760A (ja) * | 2005-02-23 | 2006-09-07 | Renesas Technology Corp | 半導体集積回路装置 |
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JP3596540B2 (ja) | 2001-06-26 | 2004-12-02 | セイコーエプソン株式会社 | レベルシフタ及びそれを用いた電気光学装置 |
JP3657243B2 (ja) | 2002-06-28 | 2005-06-08 | Necエレクトロニクス株式会社 | レベルシフタ、半導体集積回路及び情報処理システム |
CN100495923C (zh) * | 2005-02-17 | 2009-06-03 | 松下电器产业株式会社 | 电平转换电路及具有该电平转换电路的半导体集成电路 |
CN100594677C (zh) * | 2008-05-21 | 2010-03-17 | 友达光电股份有限公司 | 电平移位电路 |
KR100968152B1 (ko) * | 2008-06-04 | 2010-07-06 | 주식회사 하이닉스반도체 | 레벨 시프터 회로 |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS63164526A (ja) * | 1986-12-25 | 1988-07-07 | Toshiba Corp | レベルコンバ−タ |
JP2006237760A (ja) * | 2005-02-23 | 2006-09-07 | Renesas Technology Corp | 半導体集積回路装置 |
Cited By (1)
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WO2014148372A1 (ja) * | 2013-03-21 | 2014-09-25 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置 |
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US8653879B2 (en) | 2014-02-18 |
US20130082759A1 (en) | 2013-04-04 |
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