WO2011139061A3 - Method for aligning semiconductor materials - Google Patents

Method for aligning semiconductor materials Download PDF

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Publication number
WO2011139061A3
WO2011139061A3 PCT/KR2011/003268 KR2011003268W WO2011139061A3 WO 2011139061 A3 WO2011139061 A3 WO 2011139061A3 KR 2011003268 W KR2011003268 W KR 2011003268W WO 2011139061 A3 WO2011139061 A3 WO 2011139061A3
Authority
WO
WIPO (PCT)
Prior art keywords
materials
wafer
positions
semiconductor
accurately
Prior art date
Application number
PCT/KR2011/003268
Other languages
French (fr)
Korean (ko)
Other versions
WO2011139061A2 (en
Inventor
이경식
고영일
정현권
Original Assignee
한미반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020100041973A external-priority patent/KR101237056B1/en
Priority claimed from KR1020100048752A external-priority patent/KR101275697B1/en
Application filed by 한미반도체 주식회사 filed Critical 한미반도체 주식회사
Priority to CN201180028704.4A priority Critical patent/CN102934216B/en
Priority to SG2012078846A priority patent/SG185017A1/en
Publication of WO2011139061A2 publication Critical patent/WO2011139061A2/en
Publication of WO2011139061A3 publication Critical patent/WO2011139061A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

The present invention relates to a method which enables the positions of semiconductor materials to be accurately aligned so as to accurately transfer the semiconductor materials to processing positions in an apparatus for manufacturing a semiconductor package. According to the present invention, a wafer-processing apparatus, such as a singulation apparatus or the like that cuts a wafer-type material, in which a plurality of semiconductor packages is arranged into a lattice, into individual semiconductor package units, achieves a novel alignment system in that the alignment relationship between the center of a dowel hole and the center of a semiconductor package is photographed by means of a vision camera, and the positions of the materials in the X-Y-è directions are accurately aligned so as to accurately transfer the materials to the processing positions. Therefore, the wafer-processing apparatus can be actively used in a novel aligning method such as wafer-level packaging or the like. Particularly, the present invention relates to a method for aligning semiconductor materials, which can avoid the influence of errors caused by the vibration of equipment, etc., and ensure accurate measurement values in order to accurately align the materials.
PCT/KR2011/003268 2010-05-04 2011-05-02 Method for aligning semiconductor materials WO2011139061A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201180028704.4A CN102934216B (en) 2010-05-04 2011-05-02 For the method being directed at semi-conducting material
SG2012078846A SG185017A1 (en) 2010-05-04 2011-05-02 Method for aligning semiconductor materials

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020100041973A KR101237056B1 (en) 2010-05-04 2010-05-04 Method for Aligning Semiconductor Package Aggregate
KR10-2010-0041973 2010-05-04
KR1020100048752A KR101275697B1 (en) 2010-05-25 2010-05-25 Method for Aligning Semiconductor Wafer
KR10-2010-0048752 2010-05-25

Publications (2)

Publication Number Publication Date
WO2011139061A2 WO2011139061A2 (en) 2011-11-10
WO2011139061A3 true WO2011139061A3 (en) 2012-04-19

Family

ID=44904204

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/KR2011/003268 WO2011139061A2 (en) 2010-05-04 2011-05-02 Method for aligning semiconductor materials

Country Status (5)

Country Link
CN (1) CN102934216B (en)
PT (1) PT2011139061W (en)
SG (1) SG185017A1 (en)
TW (1) TWI543294B (en)
WO (1) WO2011139061A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6218511B2 (en) * 2013-09-02 2017-10-25 Ｔｏｗａ株式会社 Cutting apparatus and cutting method
JP6612670B2 (en) * 2016-03-31 2019-11-27 東京応化工業株式会社 Substrate processing apparatus and substrate processing method
JP2019027924A (en) * 2017-07-31 2019-02-21 セイコーエプソン株式会社 Electronic component conveyance device, electronic component inspection device, positioning device, component conveyance device, and positioning method
KR102019377B1 (en) * 2017-11-24 2019-09-06 한미반도체 주식회사 Sawing Apparatus of Semiconductor Materials
WO2020083612A1 (en) * 2018-10-23 2020-04-30 Asml Netherlands B.V. Method and apparatus for adaptive alignment

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000041236A (en) * 1998-12-22 2000-07-15 김영환 Pre-alignment device of wafer probe system
KR20010058703A (en) * 1999-12-30 2001-07-06 서성원 Prealign apparatus for semiconductor wafer
KR20010077238A (en) * 2000-02-01 2001-08-17 서정길 Alignment device of wafer and the compatible method
KR20090051929A (en) * 2007-11-20 2009-05-25 세크론 주식회사 Method of aligning a wafer and method of manufacturing a flip chip using the same
KR20090097170A (en) * 2006-12-06 2009-09-15 액셀리스 테크놀러지스, 인크. High throughput wafer notch aligner
KR20090130499A (en) * 2008-06-16 2009-12-24 정진황 Apparatus and method for aligning a substrate

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2808996B2 (en) * 1992-07-24 1998-10-08 富士通株式会社 Method for manufacturing semiconductor device
JPH06120322A (en) * 1992-10-05 1994-04-28 Hitachi Ltd Method of recognizing position of semiconductor wafer, and semiconductor wafer used therefor
JP2617870B2 (en) * 1993-10-04 1997-06-04 株式会社ディスコ Alignment method
JP4640715B2 (en) * 2000-07-14 2011-03-02 株式会社ディスコ Alignment method and alignment apparatus
TWI267913B (en) * 2005-09-23 2006-12-01 Advanced Semiconductor Eng Wafer dicing method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000041236A (en) * 1998-12-22 2000-07-15 김영환 Pre-alignment device of wafer probe system
KR20010058703A (en) * 1999-12-30 2001-07-06 서성원 Prealign apparatus for semiconductor wafer
KR20010077238A (en) * 2000-02-01 2001-08-17 서정길 Alignment device of wafer and the compatible method
KR20090097170A (en) * 2006-12-06 2009-09-15 액셀리스 테크놀러지스, 인크. High throughput wafer notch aligner
KR20090051929A (en) * 2007-11-20 2009-05-25 세크론 주식회사 Method of aligning a wafer and method of manufacturing a flip chip using the same
KR20090130499A (en) * 2008-06-16 2009-12-24 정진황 Apparatus and method for aligning a substrate

Also Published As

Publication number Publication date
TW201203439A (en) 2012-01-16
WO2011139061A2 (en) 2011-11-10
CN102934216B (en) 2016-08-03
PT2011139061W (en) 2014-03-04
SG185017A1 (en) 2012-11-29
TWI543294B (en) 2016-07-21
CN102934216A (en) 2013-02-13

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