WO2011138818A1 - Dispositif à transistors en couches minces, dispositif à réseau de transistors en couches minces, dispositif d'affichage électroluminescent organique, et procédé de fabrication d'un dispositif à transistors en couches minces - Google Patents

Dispositif à transistors en couches minces, dispositif à réseau de transistors en couches minces, dispositif d'affichage électroluminescent organique, et procédé de fabrication d'un dispositif à transistors en couches minces Download PDF

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WO2011138818A1
WO2011138818A1 PCT/JP2010/003132 JP2010003132W WO2011138818A1 WO 2011138818 A1 WO2011138818 A1 WO 2011138818A1 JP 2010003132 W JP2010003132 W JP 2010003132W WO 2011138818 A1 WO2011138818 A1 WO 2011138818A1
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gate
wiring
metal
gate wiring
thin film
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PCT/JP2010/003132
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English (en)
Japanese (ja)
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鐘ヶ江有宣
堀田定吉
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • the present invention relates to a thin film transistor device for an image display device in which thin film transistor devices having polycrystalline silicon, microcrystalline silicon, or the like as an active layer are integrally formed on a substrate, and an organic EL display device using the same.
  • Thin film transistors are used as drive substrates for display devices such as organic EL displays and liquid crystal displays, and are currently being actively developed for higher performance.
  • display devices such as organic EL displays and liquid crystal displays
  • crystallized semiconductor thin films polycrystalline silicon or microcrystalline silicon
  • Patent Documents 1 and 2 As a structure of a thin film transistor, a bottom gate structure in which a gate electrode is disposed below a semiconductor layer is mainly used (Patent Documents 1 and 2). The structure of the thin film transistor device 1000 on the bottom gate side will be described with reference to FIGS.
  • the thin film transistor device 1000 is a stacked structure of a substrate 1010, a first metal layer 1020, a gate insulating film 1030, a semiconductor film 1040, a second metal layer 1050, and an interlayer insulating film 1060, as shown in FIGS. is there.
  • a gate wiring 1021 and a gate electrode 1022 extending from the gate wiring 1021 are formed.
  • the gate insulating film 1030 is formed on the substrate 1010 and the first metal layer 1020 so as to cover the gate wiring 1021 and the gate electrode 1022. Further, the semiconductor film 1040 is stacked over the gate insulating film 1030 so as to overlap with the gate electrode 1022.
  • a source wiring 1051, a source electrode 1052 extended from the source wiring 1051, and a drain electrode 1053 are formed. Note that the source electrode 1052 and the drain electrode 1053 are disposed so as to face each other and overlap with part of the semiconductor film 1040.
  • the interlayer insulating film 1060 is stacked over the gate insulating film 1030, the semiconductor film 1040, and the second metal layer 1050 so as to cover the source wiring 1051, the source electrode 1052, and the drain electrode 1053.
  • the channel layer of the semiconductor film 1040 is crystallized in order to increase carrier mobility and improve electrical characteristics.
  • This crystallization is performed by heating the semiconductor film 1040 to a high temperature by heating with a high temperature furnace, a lamp light source, or laser irradiation. Therefore, the gate electrode 1022 formed under the semiconductor film 1040 is required to have heat resistance against heating. Therefore, in general, a heat-resistant metal such as a MoW alloy is used as a material for the gate electrode 1022.
  • heat accumulated in the semiconductor film 1040 is radiated through the gate electrode 1022 formed under the semiconductor film 1040.
  • the gate electrode 1022 needs to be thinned to suppress heat dissipation.
  • the gate electrode 1022 is thinned to promote crystallization of the semiconductor film 1040 as described above, the electric resistance of the gate wiring 1021 that is thinned together with the gate electrode 1022 is increased. As a result, problems such as a delay of an electric signal flowing through the gate wiring 1021 occur, and it becomes difficult to realize the thin film transistor device 1000 having excellent characteristics. That is, it is difficult to achieve both the promotion of crystallization of the channel layer and the reduction in resistance of the gate wiring 1021.
  • crossover region is a region where the gate wiring 1021 formed in the first metal layer 1020 and the source wiring 1051 formed in the second metal layer 1050 intersect (hereinafter referred to as “intersection region” or “cross”). It is expressed as “over region”.
  • the film thickness of the gate insulating film 1030 in this crossover region is thinner than that of other portions.
  • the gate insulating film 1030 in the crossover region may be broken, and a short circuit or a current leakage may occur between the gate wiring 1021 and the source wiring 1051.
  • This problem becomes more apparent when the gate wiring 1021 is made thicker in order to improve the wiring performance or when the gate insulating film 1030 is made thinner in order to improve the performance of the thin film transistor device 1000.
  • the present invention solves the above-described problems, and an object of the present invention is to provide a thin film transistor device having a good yield while simultaneously promoting the crystallization of the channel layer and reducing the wiring resistance.
  • a thin film transistor device includes a first gate wiring, a metal wiring intersecting with the first gate wiring, and the first gate wiring and the metal wiring on the first gate wiring. Outside the intersection region, a second gate wiring having a predetermined width thicker than the thickness of the first gate wiring formed to overlap the first gate wiring, and a region in which the second gate wiring is superimposed from the first gate wiring A gate electrode extending outward; a gate insulating film formed on the gate electrode; a semiconductor layer formed on the gate insulating film; and the metal wiring disposed on the semiconductor layer And a metal electrode which is a portion formed.
  • the second gate wiring is not formed in the intersection region, and the thickness of the intersection region of the first gate wiring with the metal wiring is smaller than the predetermined width.
  • FIG. 1 is a view showing a thin film semiconductor array substrate.
  • FIG. 2 is a perspective view of the organic EL display according to the first embodiment.
  • FIG. 3 is a partial perspective view showing the stacked structure of FIG. 2 more specifically, and is a diagram showing an example of a line bank.
  • FIG. 4 is a partial perspective view showing the stacked structure of FIG. 2 more specifically, and shows an example of a pixel bank.
  • FIG. 5 is a diagram illustrating a circuit configuration of the pixel circuit.
  • FIG. 6 is a front view illustrating a configuration of a pixel.
  • FIG. 7 is a cross-sectional view taken along the line VII-VII in FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG.
  • FIG. 9 is a cross-sectional view taken along the line IX-IX in FIG.
  • FIG. 10 is a perspective view of the main part viewed from the VII-VII cross section of FIG.
  • FIG. 11 is a view showing the structure of the VII-VII cross section of FIG. 6 corresponding to the manufacturing steps (a) to (h) of the thin film semiconductor for an image display device according to the first embodiment.
  • FIG. 12 is a view showing the structure of the VIII-VIII cross section of FIG. 6 corresponding to the manufacturing steps (a) to (h) of the thin film semiconductor for the image display device according to the first embodiment.
  • FIG. 13 shows a modification of the manufacturing steps (a) to (c) in FIG.
  • FIG. 14 shows a modification of the manufacturing steps (a) to (c) in FIG.
  • FIG. 13 shows a modification of the manufacturing steps (a) to (c) in FIG.
  • FIG. 15 is a front view showing a configuration of a conventional pixel.
  • 16 is a cross-sectional view taken along the line XVI-XVI of FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG.
  • FIG. 19 is a perspective view of the main part seen from the XVI-XVI cross section of FIG.
  • a thin film transistor device includes a first gate wiring, a metal wiring intersecting with the first gate wiring, and the first gate wiring and the metal wiring on the first gate wiring. Outside the intersection region, a second gate wiring having a predetermined width thicker than the thickness of the first gate wiring formed to overlap the first gate wiring, and a region in which the second gate wiring is superimposed from the first gate wiring A gate electrode extending outward; a gate insulating film formed on the gate electrode; a semiconductor layer formed on the gate insulating film; and the metal wiring disposed on the semiconductor layer And a metal electrode which is a portion formed.
  • the second gate wiring is not formed in the intersection region, and the thickness of the intersection region of the first gate wiring with the metal wiring is smaller than the predetermined width.
  • the gate electrode has a single-layer configuration, and the gate wiring has a two-layer configuration of a first gate wiring and a second gate wiring.
  • the gate electrode can be thinned, so that heat accumulated in the semiconductor layer by laser irradiation is not easily radiated through the gate electrode formed under the semiconductor layer. As a result, crystallization of the semiconductor layer can be promoted.
  • the gate wiring since the gate wiring has a two-layer structure, the thickness of the gate wiring can be made larger than that of the first gate wiring alone, so that the electrical resistance of the gate wiring can be reduced. For this reason, problems such as delay of the electric signal flowing through the gate wiring are less likely to occur.
  • the gate wiring in the crossover region can be thinned. As a result, it is possible to effectively prevent a short circuit and a current leakage between the gate wiring and the metal wiring due to the breaking of the gate insulating film in the crossover region.
  • the semiconductor layer may be crystallized by irradiating a laser beam that crystallizes the semiconductor layer on a channel region of the semiconductor layer excluding the second gate wiring.
  • a laser beam that crystallizes the semiconductor layer on a channel region of the semiconductor layer excluding the second gate wiring.
  • the first gate wiring and the gate electrode may be made of a refractory metal having a melting point equal to or higher than a temperature at which the channel region of the semiconductor layer is crystallized by laser irradiation.
  • the refractory metal may be a metal of Mo, W, Ta, Ti, Nb, or Vd, an alloy containing these metals, or a metal oxide containing at least one of In or Sn. .
  • the thickness of the first gate wiring and the thickness of the gate electrode may be the same. This eliminates the difference in thickness between the first gate line and the gate electrode, and in particular, impedance matching can be achieved at the connection portion between the first gate line and the gate electrode. As a result, the delay and attenuation of the gate signal transmitted from the first gate line to the gate electrode is extremely reduced.
  • the second gate wiring may be a wiring made of any one of Al, Cu, and Ag, or a wiring made of an alloy containing these metals.
  • Al, Ag, and Cu are suitable as materials constituting the second gate wiring because of their low electric resistance.
  • An alloy containing any one of Al, Ag, and Cu is also suitable as a material constituting the second gate wiring because of its low electric resistance.
  • the electrical resistance of the second gate wiring may be smaller than the electrical resistance of the first gate wiring.
  • the second gate wiring having a small electric resistance is formed on the first gate wiring, and thus the electric resistance of the entire gate wiring can be reduced.
  • the gate electrode may be extended from the first gate wiring in the vicinity of an intersection region between the first gate wiring and the metal wiring. Thereby, a gate wiring and a gate electrode can be connected with a short wiring. As a result, since a gate signal can be efficiently applied to the transistor, a thin film transistor device with a high response speed can be realized.
  • the metal wiring may be a source wiring. Accordingly, the source electrode can be extended from the source wiring, and the structure of the transistor can be simplified. Note that whether the metal electrode is a source electrode or a drain electrode is determined by the polarity of the transistor. Therefore, the source electrode can be a drain electrode depending on the polarity of the transistor.
  • the metal wiring may be a power supply wiring, and the metal electrode may be a source electrode or a drain electrode.
  • the drain electrode can be extended from the power supply wiring, and the structure of the transistor can be simplified.
  • a thin film transistor array device includes a plurality of the thin film transistor devices described above arranged in a matrix. Thereby, a thin film transistor array device having a small electric resistance of the gate wiring can be realized.
  • a display device is formed on the above-described thin film transistor array device.
  • the above-mentioned thin film transistor array device as a drive circuit board, even with a large organic EL display device, there is no signal delay, so that an organic EL display device with excellent video reproducibility and low power consumption is realized. it can. Note that the above-described effects can be obtained even when the thin film transistor array device according to one embodiment of the present invention is employed in a liquid crystal display device, not limited to an organic EL display device.
  • a method of manufacturing a thin film transistor device includes a first step of preparing a substrate, a second step of forming a metal layer on the substrate, a first gate wiring and the first gate from the metal layer.
  • the semiconductor layer may be crystallized by irradiating the channel region of the semiconductor layer excluding the second gate wiring with a laser beam.
  • a method of manufacturing a thin film transistor device includes a first step of preparing a substrate, a second step of forming a first metal layer on the substrate, and a second metal on the first metal layer.
  • the first gate having a predetermined width thicker than the thickness of the first gate wiring.
  • the semiconductor layer may be crystallized by irradiating the channel region of the semiconductor layer excluding the second gate wiring with a laser beam.
  • the second gate wiring may be configured with a material having high heat resistance, so that the resistance of the gate wiring can be reduced.
  • heat dissipation from the gate electrode can be suppressed. As a result, a thin film transistor device with high electrical characteristics can be realized.
  • FIG. 1 is a view showing a thin film semiconductor array substrate 1.
  • FIG. 2 is a perspective view of an organic EL display 10 which is an example of the display device according to the embodiment of the present invention.
  • FIG. 3 is a partial perspective view showing the stacked structure of FIG. 2 more specifically, and is a diagram showing an example of a line bank.
  • FIG. 4 is a partial perspective view showing the stacked structure of FIG. 2 more specifically, and shows an example of a pixel bank.
  • FIG. 5 is a diagram illustrating a circuit configuration of the pixel circuit 30 that drives the pixel 100.
  • the thin-film semiconductor array substrate 1 is composed of a plurality (two in FIG. 1) of organic EL displays 10.
  • the organic EL display 10 includes a thin film transistor device 20, an interlayer insulating film (planarization film) 11 (not shown in FIG. 2), an anode (lower electrode) 12, an organic EL layer from the lower layer. It is a laminated structure of (organic light emitting layer) 13 and transparent cathode (upper electrode) 14. Further, a hole transport layer (not shown) is laminated between the anode 12 and the organic EL layer 13, and an electron transport layer (not shown) is laminated between the organic EL layer 13 and the transparent cathode 14.
  • the thin film transistor device 20 includes a plurality of gate wirings 21 arranged in rows, a plurality of source wirings (metal wirings) 22 arranged in a row so as to intersect the gate wirings 21, and parallel to the source wirings 22.
  • a plurality of power supply wires 23 (not shown in FIG. 2) are provided.
  • the gate wiring 21 connects a gate electrode 41 (not shown in FIG. 2) of a thin film transistor operating as a switching element included in each pixel circuit 30 for each row.
  • the source line 22 connects a source electrode 42 (not shown in FIG. 2) of a thin film transistor operating as a switching element included in each pixel circuit 30 for each column.
  • the power supply wiring 23 connects a drain electrode 52 (not shown in FIG. 2) of a thin film transistor that operates as a driving element included in each pixel circuit 30 for each column.
  • each pixel 100 of the organic EL display 10 is composed of sub-pixels 100R, 100G, and 100B of three colors (red, green, and blue) as shown in FIGS.
  • a plurality of subpixels 100R, 100G, and 100B are arranged in the depth direction of FIG. 3 (this is referred to as a “subpixel column”).
  • FIG. 3 is a diagram showing an example of a line bank, and each sub-pixel column is separated from each other by the bank 15.
  • the bank 15 shown in FIG. 3 is a protrusion that extends in the direction parallel to the source line 22 between adjacent sub-pixel columns, and is formed on the thin film transistor device 20.
  • each sub-pixel column is formed between adjacent ridges (that is, the opening of the bank 15).
  • the anode 12 is formed for each of the sub-pixels 100R, 100G, and 100B on the thin film transistor device 20 (more specifically, on the interlayer insulating film 11) and in the opening of the bank 15.
  • the organic EL layer 13 is formed on the anode 12 and in the opening of the bank 15 for each sub-pixel column (that is, so as to cover the plurality of anodes 12 in each column).
  • the transparent cathode 14 is continuously formed on the plurality of organic EL layers 13 and the banks 15 (a plurality of protrusions) so as to cover all the sub-pixels 100R, 100G, and 100B.
  • FIG. 4 is a diagram showing an example of a pixel bank, and the sub-pixels 100R, 100G, and 100B are separated from each other by the bank 15.
  • the bank 15 shown in FIG. 4 is formed such that a ridge extending in parallel with the gate wiring 21 and a ridge extending in parallel with the source wiring 22 intersect each other.
  • subpixels 100R, 100G, and 100B are formed in a portion surrounded by the protrusions (that is, the opening of the bank 15).
  • the anode 12 is formed for each of the sub-pixels 100R, 100G, and 100B on the thin film transistor device 20 (more specifically, on the interlayer insulating film 11) and in the opening of the bank 15.
  • the organic EL layer 13 is formed for each of the sub-pixels 100R, 100G, and 100B on the anode 12 and in the opening of the bank 15.
  • the transparent cathode 14 is continuously formed on the plurality of organic EL layers 13 and the banks 15 (a plurality of protrusions) so as to cover all the sub-pixels 100R, 100G, and 100B.
  • a pixel circuit 30 is formed for each of the sub-pixels 100R, 100G, and 100B.
  • the sub-pixels 100R, 100G, and 100B and the corresponding pixel circuit 30 are electrically connected through the second contact hole 172 as shown in FIG.
  • the sub-pixels 100R, 100G, and 100B have the same configuration except that the characteristics (light emission color) of the organic EL layer 13 are different. Accordingly, in the following description, the sub-pixels 100R, 100G, and 100B are all referred to as “pixels 100” without being distinguished. Further, the present invention can be similarly applied to the line bank shown in FIG. 3 and the pixel bank shown in FIG.
  • the pixel circuit 30 includes a first transistor 40 that operates as a switch element, a second transistor 50 that operates as a drive element, and a capacitor 60 that stores data to be displayed in the corresponding pixel. Is done.
  • the first transistor 40 includes a gate electrode 41 connected to the gate line 21, a source electrode 42 connected to the source line 22, a drain electrode 43 connected to the capacitor 60 and the gate electrode 51 of the second transistor 50, It is composed of a semiconductor film 44 (not shown in FIG. 5).
  • the first transistor 40 stores the voltage value applied to the source line 22 in the capacitor 60 as display data.
  • the second transistor 50 includes a gate electrode 51 connected to the drain electrode 43 of the first transistor 40, a drain electrode 52 connected to the power supply wiring 23 and the capacitor 60, a source electrode 53 connected to the anode 12, and a semiconductor. It is comprised with the film
  • the second transistor 50 supplies a current corresponding to the voltage value held by the capacitor 60 from the power supply wiring 23 to the anode 12 through the source electrode 53.
  • the organic EL display 10 having the above configuration employs an active matrix system in which display control is performed for each pixel 100 located at the intersection of the gate wiring 21 and the source wiring 22.
  • FIG. 6 is a front view showing the configuration of the pixel 100.
  • FIG. 7 is a cross-sectional view taken along the line VII-VII in FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG.
  • FIG. 9 is a cross-sectional view taken along the line IX-IX in FIG.
  • FIG. 10 is a perspective view of the main part viewed from the VII-VII cross section of FIG. 7 also shows the interlayer insulating film 11, the anode 12, the organic EL layer 13, the transparent cathode 14, and the bank 15.
  • the pixel 100 includes a substrate 110, a first metal layer (conductive layer) 120, a second metal layer (conductive layer) 130, a gate insulating film 140, and a semiconductor film (semiconductor layer) 44. , 54, and a third metal layer (conductive layer) 150.
  • the first metal layer 120 stacked on the substrate 110 includes a first gate wiring 21a, a gate electrode 41 of the first transistor 40, and a gate electrode of the second transistor 50. 51 is formed.
  • the gate electrode 41 extends from the first gate line 21 a in the vicinity of the intersection region between the first gate line 21 a and the source line 22.
  • a second gate wiring 21b is formed in the second metal layer 130 laminated on the first metal layer 120, as shown in FIG. 6 and FIGS. 8 to 10, a second gate wiring 21b is formed.
  • the second gate line 21b is selectively superimposed on a part of the first gate line 21a. Note that “superimpose” in the present specification means that they are in a positional relationship where they overlap each other when viewed in the vertical direction.
  • the gate wiring 21 in each intersection region is configured only by the first gate wiring 21a.
  • the gate wiring 21 in the region other than the intersecting region is composed of electrically connected first and second gate wirings 21a and 21b.
  • the gate electrode 41 is formed in a region where the second gate wiring 21b is not formed.
  • the first gate wiring 21a and the gate electrode 41 have the same thickness dimension as shown in FIG.
  • the second gate wiring 21b has a thickness larger than that of the first gate wiring 21a.
  • the gate insulating film 140 is formed on the substrate 110, the first metal layer 120, and the second metal layer 130 so as to cover the gate wiring 21 (first and second gate wirings 21a and 21b) and the gate electrodes 41 and 51. Is formed.
  • the semiconductor film 44 is disposed on the gate insulating film 140 (between the gate insulating film 140 and the third metal layer 150) and in a region overlapping with the gate electrode 41.
  • the semiconductor film 54 is disposed on the gate insulating film 140 (between the gate insulating film 140 and the third metal layer 150) and in a region overlapping with the gate electrode 51.
  • the third metal layer 150 stacked on the gate insulating film 140 and the semiconductor films 44 and 54 includes a source wiring 22, a power supply wiring 23, a source electrode 42 and a drain electrode 43 of the first transistor 40, and a second transistor. 50 drain electrodes 52 and source electrodes 53 are formed. Note that the source electrode 42 extends from the source wiring 22 (or a part of the source wiring 22 functions as the source electrode 42). Similarly, the drain electrode 52 extends from the power supply wiring 23 (a part of the power supply wiring 23 functions as the drain electrode 52).
  • the source electrode 42 and the drain electrode 43 are formed at positions facing each other and overlapping each other on a part of the semiconductor film 44.
  • the drain electrode 52 and the source electrode 53 are formed at positions facing each other so that each overlaps with part of the semiconductor film 54.
  • a first contact hole (hole) 171 penetrating in the thickness direction is formed in the gate insulating film 140 at a position overlapping the drain electrode 43 and the gate electrode 51.
  • the drain electrode 43 is electrically connected to the gate electrode 51 formed in the first metal layer 120 through the first contact hole 171 as shown in FIG.
  • an interlayer insulating film is formed so as to cover the source wiring 22, the power supply wiring 23, the source electrodes 42 and 53, and the drain electrodes 43 and 52. 11 is formed.
  • a bank 15 is formed at a boundary portion between adjacent pixels 100. In the opening of the bank 15, an anode 12 formed in units of pixels 100 and an organic EL layer 13 formed in units of colors (subpixel columns) or pixels are formed. Further, a transparent cathode 14 is formed on the organic EL layer 13 and the bank 15.
  • a second contact hole (hole) 172 penetrating in the thickness direction is formed in the interlayer insulating film 11.
  • the anode 12 is electrically connected to the source electrode 53 formed in the third metal layer 150 through the second contact hole 172.
  • the second contact hole 172 is depicted as existing on the section VII-VII in FIG. .
  • the actual second contact hole 172 is formed so as to penetrate the interlayer insulating film 11 in the thickness direction at a position different from the VII-VII cross section, as shown in FIG.
  • the source electrode 53 and the lower end of the contact hole 172 are electrically connected via a connection portion 172 a extending in the horizontal direction (front side in FIG. 7) along the third metal layer 150.
  • the gate electrodes 41 and 51 have a one-layer configuration, and the gate wiring 21 has a two-layer configuration of a first gate wiring 21a and a second gate wiring 21b.
  • the gate electrodes 41 and 51 can be thinned, so that heat accumulated in the semiconductor films 44 and 54 by laser irradiation is dissipated through the gate electrodes 41 and 51 formed under the semiconductor films 44 and 54. It becomes difficult to be done. As a result, crystallization of the semiconductor films 44 and 54 can be promoted.
  • the gate wiring 21 has a two-layer structure, the thickness of the entire gate wiring 21 can be made thicker than the thickness of the first gate wiring 21a alone, so that the electrical resistance of the gate wiring 21 can be reduced. For this reason, problems such as delay of the electric signal flowing through the gate wiring 21 are less likely to occur.
  • the gate wiring 21 and the source wiring 22 intersect each other with the gate insulating film 140 interposed therebetween.
  • the gate wiring 21 and the power supply wiring 23 cross each other with the gate insulating film 140 interposed therebetween.
  • the gate wiring 21 includes the first gate wiring 21a only in the intersection region with the source wiring 22 and the power supply wiring 23, and the first and second gate wirings 21a and 21b are stacked in a region other than the intersection region. It is configured.
  • the thickness of the gate wiring 21 (first gate wiring 21a) can be reduced in the intersecting regions with the source wiring 22 and the power supply wiring 23, respectively.
  • the gate insulating film 140 is thinned, it is possible to effectively prevent the gate insulating film 140 from being broken in the intersecting region, and the yield of the thin film transistor device 20 is improved.
  • FIG. 11 is a view showing the structure of the section VII-VII in FIG. 6 corresponding to the manufacturing steps (a) to (h).
  • FIG. 12 is a view showing the structure of the VIII-VIII section of FIG. 6 corresponding to the manufacturing steps (a) to (h).
  • a substrate 110 is prepared.
  • the substrate 110 is generally made of an insulating material such as glass or quartz.
  • a silicon oxide film or a silicon nitride film (not shown) may be formed on the upper surface of the substrate 110.
  • the film thickness is about 100 nm.
  • the first metal layer 120 having heat resistance is formed on the substrate 110, patterning is performed by photolithography, etching, etc.
  • One gate wiring 21a and gate electrodes 41 and 51 are formed. That is, the first gate wiring 21a and the gate electrodes 41 and 51 have the same thickness.
  • the heat-resistant metal of Mo, W, Ta, Ti, Nb, Vd, or the alloy containing these metals is mentioned. Alternatively, it may be a metal oxide containing at least one of In or Sn. The thickness is preferably about 100 nm.
  • a second metal layer 130 is formed on the first metal layer 120, and the second gate wiring 21b is patterned.
  • the film thickness of the second metal layer 130 formed here is thicker than the first metal layer 120 formed previously.
  • the second gate line 21 b is formed on the first gate line 21 a and in a region that does not overlap with the source line 22 and the power line 23 to be formed later.
  • a material which comprises the 2nd metal layer 130 either low resistance metal Al, Cu, Ag, or those alloys are mentioned.
  • a barrier metal is formed of a heat-resistant metal such as Mo on the upper part, lower part, or both of Al having a thickness of about 300 nm. At this time, the thickness of Al is about 300 nm, and the thickness of Mo is about 50 nm.
  • the third metal layer 150 to be described later can also be made of the same material as that of the second metal layer 130.
  • a gate insulating film 140 is formed on the substrate 110, the first metal layer 120, and the second metal layer 130, and a semiconductor is formed on the gate insulating film 140.
  • a layer Note that the gate insulating film 140 and the semiconductor layer are continuously formed by a plasma CVD method or the like without breaking the vacuum.
  • As the gate insulating film 140 a silicon oxide film, a silicon nitride film, or a composite film thereof is formed. The thickness is about 200 nm.
  • the semiconductor layer is an amorphous silicon film of about 50 nm.
  • the semiconductor layer is modified from an amorphous semiconductor layer to a polycrystalline semiconductor layer by irradiating the semiconductor layer with an excimer laser or the like.
  • a crystallization method for example, dehydrogenation is performed in a furnace at 400 ° C. to 500 ° C., followed by crystallization with an excimer laser, and then hydrogen plasma treatment is performed in vacuum for several seconds to several tens of seconds. More specifically, crystallization is performed by irradiating an excimer laser or the like to raise the temperature of the amorphous semiconductor layer to a predetermined temperature range.
  • the predetermined temperature range is, for example, 1100 ° C. to 1414 ° C.
  • the average crystal grain size in the polycrystalline semiconductor layer is 20 nm to 60 nm.
  • the semiconductor layer is formed on the entire surface of the gate insulating film 140, but the excimer laser is selectively irradiated only to a portion to be a channel region of the semiconductor films 44 and 54 later (spot irradiation). That is, the gate electrodes 41 and 51 arranged immediately below the semiconductor films 44 and 54 are exposed to a high temperature in this step. Therefore, the first metal layer 120 constituting the gate electrodes 41 and 51 and the first gate wiring 21a needs to be formed of a metal (refractory metal) having a melting point higher than the upper limit (1414 ° C.) of the above temperature range. is there.
  • the second metal layer 130 constituting the second gate wiring 21b is a metal having a melting point lower than the lower limit (1100 ° C.) of the above temperature range. May be formed.
  • the third metal layer 150 to be described later may also be formed of a metal having a melting point lower than the lower limit (1100 ° C.) of the above temperature range.
  • the first metal layer 120 on which the gate electrodes 41 and 51 and the first gate wiring 21a are formed is more heat resistant than the second metal layer 130 (and a third metal layer 150 described later) on which the second gate wiring 21b is formed. It is made of highly metal.
  • the second metal layer 130 (and a third metal layer 150 described later) is formed of a metal having a lower resistance than the first metal layer 120.
  • the semiconductor layer is processed into island-like semiconductor films 44 and 54 by a photolithography method, an etching method, or the like.
  • a first through hole 171a is formed in the gate insulating film 140 by a photolithography method, an etching method, or the like.
  • the first through hole 171a later becomes the first contact hole 171.
  • a third metal layer 150 is formed on the gate insulating film 140 and the semiconductor films 44 and 54. At this time, the material constituting the third metal layer 150 is also filled in the first through hole 171a, and the first contact hole 171 is formed. Then, as shown in step (h) of FIGS. 11 and 12, the source wiring 22, the power supply wiring 23, the source electrodes 42 and 53, and the drain electrodes 43 and 52 are patterned on the third metal layer 150.
  • the source line 22 is formed at a position intersecting with the gate line 21 in a region constituted only by the first gate line 21a. That is, the source line 22 is formed at a position that does not overlap with the second gate line 21b. The same applies to the power supply wiring 23.
  • a low resistance semiconductor layer (not shown) is formed between the source electrode 42 and the semiconductor film 44 and between the drain electrode 43 and the semiconductor film 44.
  • this low-resistance semiconductor layer an amorphous silicon layer doped with an n-type dopant such as phosphorus or an amorphous silicon layer doped with a p-type dopant such as boron is generally used.
  • the thickness is about 20 nm.
  • a method for manufacturing the organic EL display 10 according to the embodiment will be described. Specifically, a method of sequentially laminating the interlayer insulating film 11, the bank 15, the anode 12, the organic EL layer 13, and the transparent cathode 14 on the thin film transistor device 20 will be described.
  • an interlayer insulating film 11 made of a silicon oxide film, a silicon nitride film, or a laminated film of these films is formed on the gate insulating film 140, the semiconductor films 44 and 54, and the third metal layer 150. Thereafter, a second through hole (not shown) penetrating the interlayer insulating film 11 is formed by a photolithography method and an etching method. This second through hole will later become the second contact hole 172.
  • the bank 15 is formed at a position corresponding to the boundary of each pixel 100 on the interlayer insulating film 11. Further, the anode 12 is formed for each pixel 100 in the opening of the bank 15 on the interlayer insulating film 11. At this time, the material constituting the anode 12 is filled in the second through hole, and the second contact hole 172 is formed. The anode 12 and the source electrode 53 are connected through the second contact hole 172.
  • the material of the anode 12 is, for example, a conductive metal such as molybdenum, aluminum, gold, silver, or copper, or an alloy thereof, an organic conductive material such as PEDOT: PSS, zinc oxide, or lead-doped indium oxide. Material. A film made of these materials is formed by a vacuum evaporation method, an electron beam evaporation method, an RF sputtering method, a printing method, or the like, and an electrode pattern is formed.
  • the organic EL layer 13 is formed on the anode 12 in the opening of the bank 15 for each color (subpixel column) or each pixel.
  • the organic EL layer 13 is formed by laminating layers such as a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer.
  • a hole injection layer a hole transport layer
  • a light emitting layer an electron transport layer
  • an electron injection layer e.g., copper phthalocyanine is used as the hole injection layer
  • ⁇ -NPD Bis [N- (1-Naphthyl) -N-phenyl] benzidine
  • Alq 3 tris (8-hydroxyquinoline
  • aluminum an oxazole derivative as the electron transport layer
  • Alq 3 a electron injection layer. Note that these materials are merely examples, and other materials may be used.
  • the transparent cathode 14 is a transparent electrode that is continuously formed on the organic EL layer 13.
  • the material of the transparent cathode 14 is, for example, ITO (Indium Tin Oxide), SnO 2 , In 2 O 3 , ZnO, or a combination thereof.
  • FIG. 13 is a view showing a modification of the manufacturing steps (a) to (c) in FIG.
  • FIG. 14 is a view showing a modification of the manufacturing steps (a) to (c) in FIG. Since the manufacturing steps (d) to (h) are common, the illustration is omitted.
  • the first metal layer 120 is formed on the substrate 110, and the second metal layer 130 is further formed on the first metal layer 120.
  • the first metal layer 120 is formed on the entire surface of the substrate 110, and the second metal layer 130 is formed on the entire surface of the first metal layer 120.
  • a photosensitive resist film 160 is formed on the second metal layer 130.
  • the photosensitive resist film 160 is composed of a first photosensitive resist film portion 160a having a relatively small thickness dimension and a second photosensitive resist film portion 160b having a relatively large thickness dimension.
  • the first photosensitive resist film portion 160a is formed immediately above a region (that is, an intersecting region) composed only of the gate electrodes 41 and 51 and the first gate wiring 21a among the gate wirings 21.
  • the second photosensitive resist film portion 160b is formed immediately above a region of the gate wiring 21 constituted by the first and second gate wirings 21a and 21b. Further, the photosensitive resist film 160 is not formed in a portion where the first metal layer 120 is finally removed.
  • the gate electrodes 41 and 51 and the gate wiring 21 are patterned by an etching method. Specifically, the second metal layer 130 is removed and the first metal layer 120 remains at the position of the first photosensitive resist film portion 160a. The first metal layer 120 left here becomes the gate electrodes 41 and 51 and the first gate wiring 21a in the intersection region. On the other hand, the first and second metal layers 120 and 130 remain at the position of the second photosensitive resist film portion 160b. The first and second metal layers 120 and 130 left here become the stacked first and second gate wirings 21a and 21b.
  • the mask can be reduced, and the manufacturing process can be simplified and the manufacturing cost can be reduced.
  • the pixel structure for driving an organic EL element was shown in the present Example, it is not restricted to this.
  • the present invention can be applied to all thin film transistor devices 20 configured using TFTs such as liquid crystal and inorganic EL.
  • the thin film transistor device of the present invention is useful as a driving backplane used in organic EL display devices, liquid crystal display devices, and the like.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electroluminescent Light Sources (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un dispositif à transistors en couches minces qui comporte : une première ligne de câblage de grille (21a) ; une ligne de câblage métallique qui couple la première ligne de câblage de grille (21a) ; une deuxième ligne de câblage de grille (21b) qui est formée, avec une épaisseur plus grande que la première ligne de câblage de grille (21a) et avec une largeur prédéterminée, sur la première ligne de câblage de grille (21a), en recouvrant la première ligne de câblage de grille (21a) dans une région à l'extérieur de la région où la première ligne de câblage de grille (21a) et la ligne de câblage métallique se coupent ; une électrode de grille (41) qui s'étend depuis la première ligne de câblage de grille (21a) jusqu'à l'extérieur de la région que la deuxième ligne de câblage de grille (21b) recouvre ; un film d'isolant de grille (140) formé sur l'électrode de grille (41) ; un film semi-conducteur (44) formé sur le film d'isolant de grille (140) ; et une électrode métallique, qui est une partie de la ligne de câblage métallique disposée sur le film semi-conducteur (44). La deuxième ligne de câblage de grille (21b) n'est pas formée dans la région d'intersection, et l'épaisseur de la région où la première ligne de câblage de grille (21a) coupe la ligne de câblage métallique est inférieure à la largeur prédéterminée.
PCT/JP2010/003132 2010-05-07 2010-05-07 Dispositif à transistors en couches minces, dispositif à réseau de transistors en couches minces, dispositif d'affichage électroluminescent organique, et procédé de fabrication d'un dispositif à transistors en couches minces WO2011138818A1 (fr)

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PCT/JP2010/003132 WO2011138818A1 (fr) 2010-05-07 2010-05-07 Dispositif à transistors en couches minces, dispositif à réseau de transistors en couches minces, dispositif d'affichage électroluminescent organique, et procédé de fabrication d'un dispositif à transistors en couches minces

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PCT/JP2010/003132 WO2011138818A1 (fr) 2010-05-07 2010-05-07 Dispositif à transistors en couches minces, dispositif à réseau de transistors en couches minces, dispositif d'affichage électroluminescent organique, et procédé de fabrication d'un dispositif à transistors en couches minces

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013111225A1 (fr) * 2012-01-26 2013-08-01 パナソニック株式会社 Appareil à réseau de transistors à couches minces et appareil d'affichage électroluminescent l'utilisant
CN110945674A (zh) * 2017-06-15 2020-03-31 高丽大学校世宗产学协力团 伸缩性基板结构体及其制作方法、伸缩性显示器及其制作方法以及伸缩性显示器使用方法

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JPH01167826A (ja) * 1987-12-24 1989-07-03 Fujitsu Ltd アクティブマトリクス型液晶表示装置の製造方法
JPH0430475A (ja) * 1990-05-25 1992-02-03 Mitsubishi Electric Corp 薄膜トランジスタアレイ基板
JPH0982980A (ja) * 1995-09-19 1997-03-28 Sony Corp 薄膜半導体装置の製造方法
JP2010041016A (ja) * 2008-08-06 2010-02-18 Akito Hara 半導体装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01167826A (ja) * 1987-12-24 1989-07-03 Fujitsu Ltd アクティブマトリクス型液晶表示装置の製造方法
JPH0430475A (ja) * 1990-05-25 1992-02-03 Mitsubishi Electric Corp 薄膜トランジスタアレイ基板
JPH0982980A (ja) * 1995-09-19 1997-03-28 Sony Corp 薄膜半導体装置の製造方法
JP2010041016A (ja) * 2008-08-06 2010-02-18 Akito Hara 半導体装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013111225A1 (fr) * 2012-01-26 2013-08-01 パナソニック株式会社 Appareil à réseau de transistors à couches minces et appareil d'affichage électroluminescent l'utilisant
JPWO2013111225A1 (ja) * 2012-01-26 2015-05-11 パナソニック株式会社 薄膜トランジスタアレイ装置及びそれを用いたｅｌ表示装置
KR101544663B1 (ko) 2012-01-26 2015-08-17 가부시키가이샤 제이올레드 박막 트랜지스터 어레이 장치 및 그것을 이용한 el 표시 장치
CN110945674A (zh) * 2017-06-15 2020-03-31 高丽大学校世宗产学协力团 伸缩性基板结构体及其制作方法、伸缩性显示器及其制作方法以及伸缩性显示器使用方法
CN110945674B (zh) * 2017-06-15 2023-11-28 高丽大学校世宗产学协力团 伸缩性基板结构体及其制作方法、伸缩性显示器及其制作方法以及伸缩性显示器使用方法

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