WO2011131028A1 - 一种体区接触的soi晶体管结构及其制备方法 - Google Patents

一种体区接触的soi晶体管结构及其制备方法 Download PDF

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WO2011131028A1
WO2011131028A1 PCT/CN2011/000679 CN2011000679W WO2011131028A1 WO 2011131028 A1 WO2011131028 A1 WO 2011131028A1 CN 2011000679 W CN2011000679 W CN 2011000679W WO 2011131028 A1 WO2011131028 A1 WO 2011131028A1
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soi
etching
layer
transistor structure
silicon
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French (fr)
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吴东平
张世理
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Fudan University
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Fudan University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H10D30/6711—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect by using electrodes contacting the supplementary regions or layers

Definitions

  • the invention belongs to the field of semiconductors and manufacturing technologies thereof, and in particular relates to a SOI crystal tube structure and a preparation method for body contact. Background technique
  • SOI silicon-on-insulator
  • the SOI integrated circuit chip has the advantages of strong anti-irradiation capability, simple isolation between devices, low parasitic capacitance, and strong latch-up resistance.
  • SOI fully depleted field effect transistors have excellent performance in short channel effect control and have better and higher micronity than bulk silicon transistors. Therefore, the ultra-thin silicon SOI substrate and the fully depleted field effect transistor fabricated thereon have great application prospects in future semiconductor integrated circuits.
  • SOI integrated circuit chips especially SOI fully depleted FET integrated circuit chips, have the attendant disadvantages: floating body effect and low heat dissipation capability.
  • the floating body effect causes the field effect transistor to have a certain memory effect, which reduces the reliability of the integrated circuit operation. Therefore, how to form a body contact of an efficient SOI field effect transistor is an important issue. Summary of the invention
  • the technical problem to be solved by the present invention is how to reduce the floating body effect and improve in the SOI structure. Cooling capacity.
  • the present invention proposes a SOI-day body-tube hook for body contact, comprising: a first structure filled with an insulating medium after etching off the SOI oxide layer and the upper silicon of the SOI, and SOI oxidation A polysilicon layer in the layer adjacent the first structure, the polysilicon layer connecting the SOI bottom silicon to the SOI upper silicon.
  • the SOI transistor structure further comprises: a rectangular gate stack structure on the surface of the SOI.
  • the SOI transistor structure further includes: a T-shaped gate stacked structure on the surface of the SOI, specifically, at the first structure, the *t stacked structure of the ⁇ -shaped structure is vertically rectangular A horizontal rectangle is added to the base.
  • the gate stack structure comprises at least one gate insulating layer and one gate conductive layer.
  • the present invention also provides a method for fabricating a body-area contact SOI transistor structure, including: generating a hard mask layer on the SOI, the method further includes:
  • Step 1 photolithography and etching to expose an opening of the silicon ( 1 ) at the bottom of the SOI;
  • Step 2 performing wet etching on the SOI oxide layer (2) through the opening;
  • Step 3 depositing a polysilicon layer at the opening, and performing anisotropic dry etching;
  • Step 4 depositing an insulating dielectric layer at the opening, and performing planarization processing;
  • Step 5 A gate stack structure is deposited and etched to form a source and a drain junction of the transistor by ion implantation.
  • the gate stack structure in the step 5 covers the opening.
  • the step 2 specifically refers to isotropic wet etching of the oxide layer (2) in the SOI with a solution containing hydrofluoric acid, wherein the oxide layer (2) in the SOI is laterally etched The distance of the lateral etching is controlled by the etching time.
  • the lateral etching distance 'j is the gate electrode length of the transistor.
  • the insulating dielectric layer deposited in the step 4 is a silicon dioxide layer; and the dielectric layer is planarized by chemical mechanical polishing or etching.
  • the gate stack structure is rectangular.
  • the gate stack structure is T-shaped, specifically, at the opening, the gate stack structure of the dome-shaped structure adds a horizontal rectangle on the basis of the vertical rectangle.
  • the present invention also provides an integrated circuit chip including at least one semiconductor device of the SOI transistor structure.
  • the configuration shown in the present invention can effectively form a contact region of the body SOI field effect transistor, the field effect transistor to eliminate body effect of SOI floating;:
  • the structure shown in the present invention makes the body region of the S.OI field effect transistor and the bottom silicon substrate in the SOI village bottom contact, which can improve the heat dissipation capability of the SOI transistor and its integrated circuit;
  • the structure and the preparation method of the present invention bring the body region of the SOI field effect transistor into contact with the bottom silicon substrate in the SOI substrate, thereby maximally utilizing the area of the substrate and improving the integration degree of the chip.
  • Figure 1 is a goat view of an SOI substrate
  • Figure 2 is a cross-sectional view taken along line AA' of Figure 1;
  • Figure 3 is a cross-sectional view in the AA' direction after depositing a hard mask layer on the junction shown in Figure 2;
  • FIG. 4 is a plan view showing an opening formed by photolithography, etching, etc. on the junction shown in FIG. 3;
  • FIG. 5 is a cross-sectional view in the AA' direction shown in FIG.
  • Figure 6 is a cross-sectional view of the oxide layer in the SOI after wet etching the structure shown in Figure 5;
  • Figure 7 is a polysilicon layer deposited on the structure shown in Figure 6 and anisotropic dry etching After the eclipse, the cross-sectional view of the direction;
  • Figure 8 is a plan view showing a dielectric layer deposited on the structure shown in Figure 7 and planarized;
  • Figure 9 is a cross-sectional view taken along line AA' of Figure 8;
  • Figure 10 is a plan view showing the active region etched on the structure shown in Figure 9;
  • Figure 11 is a cross-sectional view of the ⁇ , direction shown in Figure 10;
  • Figure 12 is a cross-sectional view taken along line BB' of Figure 10; - Figure 13 is a cross-section of the media layer deposited on the structure shown in Figure 11 and planarized.
  • Figure 14 is a cross-sectional view showing the direction AA of the hard mask layer on the surface of the SOI after etching on the structure shown in Figure 13;
  • Figure 15 is a cross-sectional view taken along the line AA of the gate insulating layer and the gate conductive layer on the structure shown in Figure 14;
  • Figure 16 is a plan view of the gate conductive layer and the insulating layer after etching the structure shown in Figure 15;
  • Figure 17 is a cross-sectional view taken along line AA of Figure 16;
  • Figure 18 is a plan view 2 after etching the gate conductive layer and the insulating layer on the structure shown in Figure 15;
  • Figure 19 is a cross-sectional view of the direction AA shown in Figure 18;
  • Figure 20 is a flow chart showing the method of fabricating the SOI transistor structure of the present invention. detailed description
  • the present invention proposes a body-area contact SOI transistor structure, as shown in FIG. 17, comprising: a first structure filled with an insulating medium 6 after etching off the SOI oxide layer 2 and the SOI upper silicon 3, and the SOI oxide layer 2 In the polysilicon layer 5 near the first structure, the polysilicon layer 5 connects the SOI bottom silicon 1 and the SOI upper silicon 3 together.
  • the SOI transistor structure further includes: a rectangular gate stacked structure on the surface of the SOI, as shown in Figs. 16 and 17, the rectangular gate stacked structure includes a rectangular gate insulating layer 8 and a rectangular gate conductive layer 9.
  • the SOI transistor structure further includes: a T-shaped gate stacked structure on the surface of the SOI, see FIGS. 18 and 19, specifically, at the first structure, the T-shaped gate stacked structure is at BB, direction An AA, a rectangular shape is added to the rectangular shape, and the T-shaped gate laminated structure includes a T-shaped gate insulating layer 8 and a T-shaped gate conductive layer 9.
  • the present invention also proposes an integrated circuit chip comprising at least one semiconductor device of the S ⁇ I transistor structure.
  • the present invention also provides a method for fabricating a body-area contact SOI transistor structure, as shown in FIG. 20, comprising: generating a hard mask layer on the SOI substrate, the preparation method further comprising:
  • Step 1 lithography, etching an opening that exposes silicon at the bottom of the SOI; Step 2, performing wet etching on the SOI oxide layer through the opening;
  • Step 3 depositing a polysilicon layer at the opening, and performing an anisotropic thousand etching; Step 4, depositing an insulating dielectric layer at the opening, and performing planarization processing; Step 5
  • a gate stack structure is deposited and etched to form a source and a drain junction of the transistor by ion implantation.
  • This embodiment includes the process steps shown in FIGS. 1 to 17:
  • Step 1 A silicon-on-insulator (SOI) substrate is provided. See FIG. 1 and FIG. 2, the SOI substrate includes: SOI bottom silicon 1, SOI oxide layer 2, and SOI upper silicon 3.
  • SOI silicon-on-insulator
  • Step 2 depositing a hard mask layer 4 on the SOI upper substrate, that is, the SOI upper silicon 3, as shown in FIG.
  • the hard mask layer 4 is an insulating dielectric layer and may be of the following materials: silicon nitride (Si 3 N 4 ), silicon dioxide (Si0 2 ), or silicon nitride, and a multilayer structure composed of silicon dioxide. .
  • Step 3 forming openings as shown in FIGS. 4 and 5 by a process such as photolithography, etching, or the like.
  • the hard mask layer 4 the SOI upper silicon 3 and the SOI oxide layer 2 are removed to expose the SOI bottom silicon 1.
  • Step 4 wet etching the SOI oxide layer 2 through the opening.
  • the SOI oxide layer 2 is isotropically etched with a solution containing hydrofluoric acid (HF), so that the SOI silicon oxide layer 2 at the opening is laterally etched, and the lateral etching distance can be controlled by the etching time.
  • a structure as shown in FIG. 6 is formed.
  • Step 5 depositing a polysilicon layer 5 and performing anisotropic dry etching.
  • the polysilicon layer 5 is anisotropically dried, and the remaining polysilicon layer 5 is connected to the SOI upper silicon 3 and the SOI bottom silicon 1. See Figure 7.
  • Step 6 Deposit an insulating dielectric layer 6 and perform a planarization process.
  • CMP chemical mechanical polishing
  • Step 7 Photolithography and etching are performed on the active area.
  • the active region is the region covered by 4 in FIG. 10, and the remaining portion is etched away. As in the portion around 4 in FIG. 10, the etching depth is required to expose the SOI bottom silicon 1 other than the active region 4. Therefore, it is necessary to etch away the hard mask layer 4, SOI on the structure around the active region.
  • the upper silicon 3, the SOI oxide layer 3, and the dielectric layer 6 in the opening are shown in Figs. 10, 11, and 12.
  • Step 8 depositing a dielectric layer around the etched active region, that is, the SOI bottom silicon 1
  • the deposited material is silicon dioxide, see Figure 13.
  • Step 9 Etching and removing the hard mask layer 4 and the dielectric layer 6 on the surface of the SOI expose the upper silicon 3 of the SOI, as shown in FIG.
  • Step 10 depositing a gate stack including a gate insulating layer 8 and a gate conductive layer 9.
  • the material of the gate insulating layer 8 is silicon dioxide, silicon nitride, a high-k dielectric containing zirconium or a mixture thereof.
  • the material of the gate conductive layer 9 is polysilicon, metal, or a multilayer structure composed of the same, and the metal may be TiN, TaN, as shown in Fig. 1.5.
  • Step 11 photolithography and pattern etching of the gate conductive layer 9 and the insulating layer 8.
  • the gate conductive layer 9 and the gate insulating layer 8 are etched to form a rectangular gate electrode of the field effect transistor as shown in Figs.
  • Step 12 finally entering the conventional CMOS process: ion implantation is performed in the upper SOI of the SOI on both sides of the gate electrode to form the source and drain of the transistor. Because of the self-aligned process, the SOI upper silicon 3 under the gate electrode forms the body region of the transistor.
  • the polysilicon layer 5 formed in the step 5 connects the SOI upper silicon 3 and the SOI bottom silicon 1 under the body region, that is, the gate electrode, thereby avoiding the floating effect of the usual SOI field effect transistor. .
  • Embodiment 2
  • step 11 adopts another shape of the gate electrode, as shown in Fig. 18 and Fig. 19, the gate electrode of this shape.
  • the advantage is that the process window that forms the contact of the body region can be increased, and the area of contact with the body region is increased.
  • the body contact means that the upper silicon 3 of the SOI and the lower silicon 1 of the SOI are brought into contact by the polysilicon 5.
  • the upper silicon 1 of the SOI below the gate electrode 9 is the body region. 18 and FIG. 16, the area of the gate electrode is increased, so that the area of the upper portion of the SOI covered by the gate electrode is increased, so that the upper silicon 3 of the SOI can form a better contact with the lower silicon 1.
  • the structure and the preparation method provided by the invention can effectively form the SOI field effect transistor
  • the body contact eliminates the floating body effect of the SOI field effect transistor and improves the heat dissipation capability of the SOI transistor and its integrated circuit, while maximizing the area of the substrate and improving the integration of the chip.

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Description

说 明 书
一种体区接触的 SOI晶体管结构及其制备方法 技术领域
本发明属于半导体及其制造技术领域， 尤其涉及一种体区接触的 SOI 晶 体管结构及制备方法。 背景技术
近年来， 以硅集成电路为核心的微电子技术得到了迅速的发展， 集成电路 芯片的发展基本上遵循摩尔定律， 即半导体芯片的集成度以每 18个月翻一番 的速度增长。 可是随着半导体芯片集成度的不断增加， MOS 晶体管的沟道长 度也在不断的缩短， 当 MOS晶体管的沟道长度变得非常短时， 短沟道效应会 使半导体芯片性能劣化， 甚至无法正常工作。传统的硅集成电路芯片一般制作 在体硅上。
以绝缘体上的硅（SOI, Silicon on insulator ) 为衬底的大规模集成电路芯 片从 90纳米技术节点开始被部分半导体公司制造。 SOI集成电路芯片具有抗 辐照能力强、 器件之间隔离简单、 寄生电容小、 抗闩锁效应强等优点。 同时， SOI全耗尽型场效应晶体管在短沟道效应的控制上有优异的表现，和体硅晶体 管相比有更好的更高的可缩微性。 因此， 超薄硅体 SOI 衬底以及制作在其上 的全耗尽型场效应晶体管在未来的半导体集成电路中有着很大的应用前景。
与此同时， SOI集成电路芯片， 特别是 SOI全耗尽型场效应晶体管集成电 路芯片也有随之而来的缺点： 浮体效应和较低的散热能力。浮体效应导致场效 应晶体管产生一定的记忆效应， 降低了集成电路运行的可靠性。 因此， 如何形 成高效的 SOI场效应晶体管的体区接触是一个重要的课题。 发明内容
本发明所要解决的技术问题是， 如何降低 SOI 结构中的浮体效应和提高 散热能力。
为解决上述技术问题， 本发明提出了一种体区接触的 SOI 日¾体管 勾,， 包括： 在刻蚀掉 SOI氧化层和 SOI上部硅后填充有绝缘介质的第一结构， 和 SOI氧化层中在所述第一结构附近的多晶硅层，所述多晶硅层将 SOI底部硅与 SOI上部硅连接在一起。
优选地， 所述 SOI晶体管结构还包括： 在 SOI表面上的长方形栅叠层结 构。
优选地， 所述 SOI晶体管结构还包括： 在 SOI表面上的 T形栅叠层结构， 具体是指在所述第一结构处， 所述 τ 形结构的 *t叠层结构在竖向长方形的基 础上增加了一块横向的长方形。
优选地， 所述栅叠层结构至少包括一层栅绝缘层和一层栅导电层。
另， 本发明还提出了一种体区接触的 SOI晶体管结构的制备方法， 包括： 在 SOI上生成一硬掩模层， 所述制备方法还包括：
步骤 1 , 光刻、 刻蚀一可露出 SOI底部硅（ 1 ) 的开口；
步骤 2, 通过所述开口， 对 SOI氧化层（2 )进行湿法刻蚀；
步骤 3， 在所述开口处， 淀积一多晶硅层， 并进行各向异性干法刻蚀； 步骤 4, 在所述开口处， 淀积一绝缘介质层， 并进行平整化处理； 步骤 5， 淀积并刻蚀形成栅叠层结构， 通过离子注入形成晶体管的源、 漏 结。
优选地， 所述步骤 5中的栅叠层结构覆盖所述开口。
优选地， 所述步骤 2具体是指， 用含氢氟酸的溶液对 SOI中的氧化层（2 ) 进行各向同性湿法刻蚀， 所述 SOI中的氧化层（2 )被横向刻蚀， 横向刻蚀的 距离由刻蚀时间进 4亍控制。
优选地， 所述橫向刻蚀的距离 'j、于所述晶体管的栅电极长度。
优选地， 所述步骤 4中淀积的绝缘介质层， 为二氧化硅层； 所述对该介质 层进行平整化处理， 采用的是化学机械抛光或刻蚀的方法。
优选地， 所述步骤 5中栅叠层结构为长方形。 优选地， 所述步骤 5 中栅叠层结构为 T形， 具体是指在所述开口处， 所 述 Τ形结构的栅叠层结构在竖向长方形的基础上增加了一块横向的长方形。
另， 本发明还提出了一种集成电路芯片， 所述芯片上包括至少一个所述 SOI晶体管结构的半导体器件。
与传统的 SOI晶体管结构相比， 本发明的优势如下：
本发明所示的结构能够有效形成 SOI场效应晶体管的体区接触，消除 SOI 场效应晶体管的浮体效应； :
本发明所示结构使 S.OI场效应晶体管的体区和 SOI村底中的底部硅衬底 接触， 能够改善 SOI晶体管及其集成电路的散热能力；
本发明所示结构及甚制备方法使 SOI场效应晶体管的体区和 SOI衬底中 的底部硅衬底接触， 能够最大限度地利用衬底的面积， 提高芯片的集成度。 附图说明
图 1是 SOI衬底的羊面图；
图 2是图 1所示 AA'方向的截面图；
图 3是在图 2所示结^]上淀积一硬掩模层后 AA'方向的截面图；
图 4是在图 3所示结^]上通过光刻、 刻蚀等工艺形成一开口的平面图； 图 5是图 4所示 AA'方向的截面图；
图 6是在图 5所示结构上湿法刻蚀 SOI中的氧化层后 ΑΑ，方向的截面图； 图 7是在图 6所示结构上淀积一多晶硅层并进行各向异性干法刻蚀后 ΑΑ， 方向的截面图； ·
图 8是在图 7所示结构上淀积一介质层并进行平整化处理后的平面图； 图 9是图 8所示 AA'方向的截面图；
图 10是在图 9所示结构上刻蚀出有源区后的平面图；
图 11是图 10所示 ΑΑ，方向的截面图；
图 12是图 10所示 BB'方向的截面图； - 图 13是在图 11所示结构上淀积介质层并进行平整化处理后 ΑΑ，方向的截 面图；
图 14是在图 13所示结构上刻蚀除去 SOI表面的硬掩模层后 AA，方向的截 面图；
图 15是在图 14所示结构上淀积栅绝缘层、栅导电层后 AA，方向的截面图； 图 16是在图 15所示结构上刻蚀栅导电层和绝缘层后的平面图一； 图 17是图 16所示 AA，方向的截面图；
图 18是在图 15所示结构上刻蚀栅导电层和绝缘层后的平面图二； 图 19是图 18所示 AA，方向的截面图；
图 20是本发明 SOI晶体管结构制备方法的流程图。 具体实施方式
本发明提出了一种体区接触的 SOI晶体管结构， 见图 17， 包括： 在刻蚀 掉 SOI氧化层 2和 SOI上部硅 3后填充有绝缘介质 6的第一结构， 和 SOI氧 化层 2中在所述第一结构附近的多晶硅层 5， 所述多晶硅层 5将 SOI底部硅 1 与 SOI上部硅 3连接在一起。
所述 S0I晶体管结构还包括： 在 S0I表面上的长方形栅叠层结构， 见图 16和图 17， 所述长方形栅叠层结构包括长方形栅绝缘层 8和长方形栅导电层 9。
所述 SOI晶体管结构还包括： 在 SOI表面上的 T形栅叠层结构， 见图 18 和图 19， 具体是指在所述第一结构处， 所述 T形栅叠层结构在 BB，方向长方 形的基础上增加了一块 AA，方向的长方形， 所述 T形栅叠层结构包括 T形栅 绝缘层 8和 T形栅导电层 9。
另， 本发明还提出了一种集成电路芯片， 所述芯片包括至少一个所述 S〇I 晶体管结构的半导体器件。
另， 本发明还提出了一种体区接触的 SOI 晶体管结构的制备方法， 见图 20, 包括： 在 SOI衬底上生成一硬掩模层， 所述制备方法还包括：
步骤 1 , 光刻、 刻蚀一可露出 SOI底部硅的开口； 步骤 2， 通过所述开口， 对 SOI氧化层进行湿法刻蚀；
步骤 3， 在所述开口处， 淀积一多晶硅层， 并进行各向异性千法刻蚀； 步骤 4， 在所述开口处， 淀积一绝缘介质层， 并进行平整化处理； 步骤 5 , 淀积并刻蚀形成栅叠层结构， 通过离子注入形成晶体管的源、 漏 结。
下面就上述制备方法进行具体说明：
实施例一
本实施例包括图 1至图 17所示的工艺步骤：
步骤 1， 提供一块绝缘体上的硅（SOI, Silicon On Insulator)衬底， 见图 1 和图 2, 所述 SOI衬底包括： SOI底部硅 1、 SOI氧化层 2和 SOI上部硅 3。
步骤 2, 在所述 SOI村底即 SOI上部硅 3上淀积一硬掩模层 4， 见图 3。 所述硬掩模层 4 为绝缘介质层， 可为以下材料： 氮化硅（Si3N4)、 二氧化硅 ( Si02 )、 或者是氮化硅.、 二氧化硅组成的多层结构。
步骤 3， 通过光刻、 .刻蚀等工艺形成如图 4和图 5所示的开口。 刻蚀时， 除掉硬掩模层 4、 SOI上部硅 3和 SOI氧化层 2, 露出 SOI底部硅 1。
步骤 4, 通过所述开口湿法刻蚀 SOI氧化层 2。 比如用含氢氟酸（HF )的 溶液， 各向同性刻蚀 SOI氧化层 2, 因此所述开口处的 SOI氧化硅层 2被横向 刻蚀， 横向刻蚀的距离可以由刻蚀时间进行控制， 形成如图 6所示的结构。
步骤 5 , 淀积一多晶硅层 5并进行各向异性干法刻蚀。 进行各向异性干法 刻蚀该多晶硅层 5， 剩余的多晶硅层 5连接了 SOI上部硅 3和 SOI底部硅 1。 见图 7。
步骤 6， 淀积一绝缘介质层 6并进行平整化处理。 淀积的绝缘介质层 6， 一般为二氧化硅， 对该介质层进行平整化处理， 一般用化学机械抛光 (CMP) 或刻蚀等方法， 形成如图 8、 图 9所示的结构。
步骤 7， 光刻、 刻蚀贸出有源区。 所述有源区为图 10中 4所覆盖的区域， 其余部分被刻蚀掉， 如图 10中 4周围的部分， 刻蚀的深度是要求露出有源区 4以外的 SOI底部硅 1。 所以需要刻蚀掉有源区周围结构上的硬掩模层 4、 SOI 上部硅 3、 SOI氧化层 3 、 开口中的介质层 6， 见图 10、 图 11、 图 12。
步骤 8, 在所述被刻蚀掉的有源区周围， 即 SOI底部硅 1上淀积一介质层
7并进行平整化处理。 与步骤 6—样， 淀积的材料为二氧化硅， 见图 13。
步骤 9, 刻蚀除去 SOI表面的硬掩模层 4和介质层 6, 露出 SOI上部硅 3 , 见图 14。
步骤 10， 淀积形成栅叠层， 包括栅绝缘层 8和栅导电层 9。 所述栅绝缘层 8的材料， 为二氧化硅、 氮化硅、 含锆的高 K介质或者为它们组成的混合物。 所述栅导电层 9的材料 为,多晶硅、 金属、 或者它们组成的多层结构， 金属可 以是 TiN， TaN, 见图 1.5 . ,.
步骤 11 , 光刻、 图形化刻蚀栅导电层 9和绝缘层 8。 刻蚀栅导电层 9和栅 绝缘层 8, 形成如图 16、 图 17所示的场效应晶体管的长方形栅电极。
步骤 12, 最后进入常规的 CMOS工艺： 在栅电极两边的 SOI上部硅 3中 进行离子注入， 形成晶体管的源极和漏极。 因为采用的是自对准工艺， 栅电极 之下的 SOI上部硅 3中.形成晶体管的体区。
由此可见， 步骤 5 中^成的多晶硅层 5将所述体区即栅电极之下的 SOI 上部硅 3和 SOI底部硅 , 1连接在一起， 从而避免了通常的 SOI场效应晶体管 的浮体效应。 实施例二
除了步骤 11 以外， .,其他步骤与实施例一中的步骤完全相同， 此方法中步 骤 11采用了另外一种栅电 '极的形状， 见图 18、 图 19， 这种形状的栅电极的优 点是可以增大形成体区接触的工艺窗口， 而且增大了体区接触的面积。 所述体 区接触是指， SOI上部硅 3和 SOI下部硅 1通过多晶硅 5形成接触。 而栅电极 9以下的 SOI上部硅 1就是体区。 图 18与图 16相比， 栅电极的面积增大， 所 以栅电极所覆盖的 SOI上部硅 1 即体区面积增大， 所以 SOI上部硅 3与下部 硅 1能形成更好的接触。 、
采用本发明所提供的结构和制备方法， 能够有效形成 SOI 场效应晶体管 的体区接触， 消除 SOI场效应晶体管的浮体效应， 并改善 SOI晶体管及其集 成电路的散热能力，同时能够最大限度地利用衬底的面积，提高芯片的集成度。
当然， 本发明还可有其他多种实施例，在不背离本发明精神及其实质的情 这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。

Claims

权 利 要 求 书
1、 一种体区接触的 SOI晶体管结构， 其特征在于， 包括： 在刻蚀掉 SOI 氧化层和 SOI上部硅后填充有绝缘介质的第一结构， 和 SOI氧化层中在所述 第一结构附近的多晶硅层， 所述多晶硅层将 SOI底部硅与 SOI上部硅连接在 一起。
2、 如权利要求 1所述 S0I晶体管结构， 其特征在于， 所述 SOI晶体管结 构还包括： 在 SOI表面上的长方形栅叠层结构。
3、 如权利要求 1所述 SOI晶体管结构， 其特征在于， 所述 SOI晶体管结 构还包括： 在 SOI表面上的 T形栅叠层结构， 具体是指在所述第一结构处， 所述 T形结构的栅叠层结构在竖向长方形的基础上增加了一块横向的长方形。
4、 如权利要求 2和 3所述 SOI晶体管结构， 其特征在于， 所述栅叠层结 构至少包括一层栅绝缘层和一层栅导电层。
5、 一种体区接触的 SOI晶体管结构的制备方法， 包括： 在 SOI村底上生 成一硬掩模层， 其特征在于，所述制备方法还包括：
步骤 1 , 光刻、 刻蚀一个可露出 SOI底部硅的开口；
步骤 2, 通过所述开口， 对 SOI氧化层进行湿法刻蚀；
步骤 3 , 在所述开口处， 淀积一多晶硅层， 并进行各向异性千法刻蚀； 步骤 4, 在所述开口处， 淀积一绝缘介质层， 并进行平整化处理； 步骤 5 , 淀积并刻蚀形成栅叠层结构， 通过离子注入形成晶体管的源、 漏 结。
6、 如权利要求 5所述 SOI晶体管结构的制备方法， 其特征在于， 所述步 骤 5中的栅叠层结构覆盖所述开口。
7、 如权利要求 5所述 SOI晶体管结构的制备方法， 其特征在于， 所述步 骤 2具体是指， 用含氢氟酸的溶液对 SOI中的氧化层进行各向同性湿法刻蚀， 所述 SOI中的氧化层被横向刻蚀， 横向刻蚀的距离由刻蚀时间进行控制。
8、 如权利要求 7所述 SOI晶体管结构的制备方法， 其特征在于， 所述横 向刻蚀的距离小于所述晶体管的栅电极长度。
9、 如权利要求 5所述 SOI晶体管结构的制备方法， 其特征在于， 所述步 骤 4中淀积的绝缘介质层为二氧化硅层； 所述对该介质层进行平整化处理； 采 用的是化学机械抛光或刻蚀的方法。
10、 如权利要求 5所述 SOI晶体管结构的制备方法， 其特征在于， 所述 步骤 5中栅叠层结构为长方形。
11、 如权利要求 5所述 SOI晶体管结构的制备方法， 其特征在于， 所述步 骤 5中栅叠层结构为 T形， 具体是指在所述开口处， 所述 T形结构的栅叠层 结构在竖向长方形的基础上增加了一块横向的长方形。
12、 一种集成电路芯片， 其特征在于， 所述芯片上包括至少一个如权利要 求 1所述的 SOI晶体管结构的半导体器件。
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