WO2011129044A1

WO2011129044A1 - Apparatus for supplying voltage

Info

Publication number: WO2011129044A1
Application number: PCT/JP2011/000778
Authority: WO
Inventors: 彰樋口; 章政譲原; 大輔坂牧
Original assignee: 株式会社アドバンテスト
Priority date: 2010-04-16
Filing date: 2011-02-10
Publication date: 2011-10-20
Also published as: TW201205101A; KR20120034618A; JP2011226854A; KR101374339B1

Abstract

Disclosed is an apparatus for supplying voltages, wherein current supplying performance is improved without increasing the power supply capacity inside of an integrated circuit device. The apparatus is provided with the integrated circuit device, and a voltage supply section, which generates a drive voltage and supplies the drive voltage to the integrated circuit device. The integrated circuit device has: a plurality of circuits; a plurality of voltage input terminals, which receive, from the outside, a drive voltage for driving a corresponding circuit among the circuits; and a reference terminal, which outputs a reference voltage to be the reference of the drive voltage to be received from the outside. The voltage supply section generates the drive voltage, which is obtained by power-amplifying the reference voltage.

Description

Device to supply voltage

The present invention relates to an apparatus for supplying a voltage.

There is known a test apparatus that tests a plurality of devices under test (sometimes referred to as DUTs) in parallel (see, for example, Patent Document 1). In addition, a test apparatus including a test integrated circuit device in which a function necessary for testing a DUT is mounted on a single chip is also known (see, for example, Non-Patent Document 1).
Patent Document 1 International Publication No. 2008/020555 Pamphlet Non-Patent Document 1 "B8501ES Press Release", [online], November 19, 2009, Nippon Engineering Co., Ltd., [April 8, 2010 search], Internet <URL : http://www.jec.co.jp/news_b8501es.html>

By the way, in such a test integrated circuit device, for example, when the number of test signals to be supplied to the DUT is increased, it is necessary to increase the current supply capability necessary for outputting the test signals.

In order to solve the above problems, in the first aspect of the present invention, an integrated circuit device having a reference terminal for outputting a reference value serving as a reference of a drive voltage received from the outside, and the drive voltage corresponding to the reference value And a voltage supply unit for supplying the integrated circuit device to the integrated circuit device.

Note that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

The structure of the test apparatus 10 which concerns on embodiment of this invention is shown with several DUT200. 1 shows a configuration of a test board 20 according to an embodiment of the present invention. The structure of the test part 30 which concerns on embodiment of this invention is shown. 2 shows an exemplary configuration of an input / output circuit 50 according to an embodiment of the present invention. The structure of the test board 20 further provided with the power supply part 90 which concerns on embodiment of this invention is shown.

Hereinafter, the (1) aspect of the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and the features described in the embodiments are as follows. Not all combinations are essential for the solution of the invention.

FIG. 1 shows the configuration of a test apparatus 10 according to this embodiment together with a plurality of DUTs 200. The test apparatus 10 tests a plurality of DUTs 200 in parallel. The DUT 200 is, for example, a non-volatile memory such as a flash memory.

The test apparatus 10 includes a plurality of test boards 20, a control board 22, a device connection unit 24, a test controller 26, and a network unit 28. Each of the plurality of test boards 20 is connected to one or more DUTs 200. Each of the plurality of test boards 20 exchanges signals with one or more connected DUTs 200 to test the one or more DUTs 200.

The control board 22 supplies a power supply voltage to each of the plurality of test boards 20. The control board 22 controls each of the plurality of test boards 20. As an example, the control board 22 controls a connection state between the plurality of test boards 20 and the corresponding DUT 200. The test apparatus 10 may include a plurality of control boards 22. As an example, the plurality of test boards 20 and the control board 22 are accommodated in a test head which is a main body of the test apparatus 10.

The device connection unit 24 holds the plurality of DUTs 200 in a state where they can be attached and removed from the outside. In addition, the device connection unit 24 electrically connects each of the plurality of held DUTs 200 to the corresponding test board 20. The device connection unit 24 electrically connects the plurality of DUTs 200 and the control board 22.

The test controller 26 exchanges communication packets such as UDP / IP (User Datagram Protocol / Internet Protocol) with the plurality of test boards 20 and the control board 22 to control the plurality of test boards 20 and the control board 22. Further, the test controller 26 inputs information from the user and outputs information to the user. The test controller 26 is, for example, a computer that executes a program. The test controller 26 executes a program in accordance with an instruction from the user and controls the test apparatus 10.

The network unit 28 connects the plurality of test boards 20 and the control board 22 to the test controller 26 so that they can communicate with each other. The network unit 28 is a hub that relays a high-speed serial bus such as Ethernet (registered trademark).

FIG. 2 shows a configuration of the test board 20 according to the present embodiment. The test board 20 includes a plurality of test units 30, a plurality of sub-controllers 32, a plurality of memories 34, and a board controller 36. For example, a plurality of test units 30, a plurality of sub-controllers 32, a plurality of memories 34, and a board controller 36 constituting the test board 20 are mounted on a single board. In this case, the board controller 36, the test unit 30 and the like may be connected to one board by a connector after being mounted on the sub board.

Each of the plurality of test units 30 tests a single DUT 200 by executing a test program that represents a sequence for sequentially generating a logic pattern, an expected value pattern, and the like. Each of the plurality of test units 30 tests the corresponding DUT 200 by transmitting and receiving a signal of the logical pattern indicated in the test program to and from the corresponding DUT 200. For example, if the DUT 200 is a non-volatile memory, each of the plurality of test units 30 detects pass / fail of a cell for each address position in the corresponding DUT 200.

In addition, each of the plurality of test units 30 performs a test independently. For example, even when the plurality of test units 30 start the test at the same timing, signals to be transmitted and received and timings differ according to the state of the corresponding DUT 200.

Each of the plurality of sub-controllers 32 is connected to one or a plurality of different test units 30 among the plurality of test units 30. In this example, each of the plurality of sub-controllers 32 is connected to two test units 30. Each of the plurality of memories 34 corresponds to each of the plurality of sub-controllers 32 on a one-to-one basis. Each of the plurality of memories 34 is written and read by the corresponding sub-controller 32.

Each of the plurality of sub-controllers 32 controls data transfer between the corresponding test unit 30 and the board controller 36. In addition, each of the plurality of sub-controllers 32 reads out the test result stored in the internal memory of the test unit 30 and stores it in the memory 34. For example, if the DUT 200 is a non-volatile memory, fail data indicating the position of the defective address is read from the internal memory of the corresponding test unit 30 and stored in the corresponding memory 34. Further, each of the plurality of sub-controllers 32 reads out the test program stored in the corresponding memory 34 and transfers it to the corresponding test unit 30 in accordance with an instruction from the corresponding test unit 30.

The board controller 36 exchanges communication packets with the test controller 26 via the network unit 28. Further, the board controller 36 writes data to the designated test unit 30 among the plurality of test units 30 based on a command included in the communication packet supplied from the test controller 26. Thereby, the board controller 36 can control each of the plurality of test units 30 in accordance with the command supplied from the test controller 26.

Further, the board controller 36 reads data from the designated test unit 30 or the memory 34 among the plurality of test units 30 based on the command included in the communication packet. Thereby, the board controller 36 can transfer the test result of the designated test unit 30 to the test controller 26 in accordance with the instruction supplied from the test controller 26.

FIG. 3 shows a configuration of the test unit 30 according to the present embodiment. The test unit 30 includes an integrated circuit device 40 and a power supply unit 42. The integrated circuit device 40 is, for example, a device in which one or a plurality of chips are packaged. The power supply unit 42 generates a drive voltage and supplies it to the integrated circuit device 40.

The integrated circuit device 40 includes a test circuit 48, a plurality of input / output circuits 50, a plurality of voltage input terminals 54, a voltage setting unit 56, and a reference terminal 58.

The test circuit 48 generates a logic pattern representing the logic of the test signal to be supplied to the DUT 200 corresponding to each of the plurality of pins of the DUT 200. Further, the test circuit 48 compares the received value of the response signal output from each of the plurality of pins of the DUT 200 and the expected value of the response signal to determine pass / fail for each address position of the corresponding DUT 200. To do.

Each of the plurality of input / output circuits 50 is connected to each of a plurality of pins of the DUT 200. Each of the plurality of input / output circuits 50 receives a corresponding logic pattern from the test circuit 48 and outputs a test signal having a voltage level corresponding to the received logic pattern. For example, each of the plurality of input / output circuits 50 outputs a test signal having an H logic voltage or an L logic voltage according to the received logic pattern. Further, as an example, each of the plurality of input / output circuits 50 connects a corresponding pin to a termination voltage via a termination resistor according to the received logic pattern.

Also, each of the plurality of input / output circuits 50 inputs a response signal from a corresponding pin of the corresponding DUT 200. Each of the plurality of input / output circuits 50 compares the level of the input response signal with a threshold level and supplies a logic signal representing the value of the response signal to the test circuit 48.

Here, each of the plurality of input / output circuits 50 receives the drive voltage supplied from the external power supply unit 42 and operates according to the received drive voltage. As an example, each of the plurality of input / output circuits 50 receives an H logic voltage and an L logic voltage as drive voltages. Thereby, each of the plurality of input / output circuits 50 can output a test signal by the power of the external power supply unit 42. Each of the plurality of input / output circuits 50 receives a termination voltage as a drive voltage. Thereby, each of the plurality of input / output circuits 50 can terminate the corresponding pin by the power of the external power supply unit 42.

Each of the plurality of voltage input terminals 54 is provided corresponding to each of the plurality of input / output circuits 50, and receives a drive voltage for driving the corresponding input / output circuit 50 from the external power supply unit 42. In this example, the integrated circuit device 40 includes a first voltage input terminal 54-1, a second voltage input terminal 54-2, and a third voltage input terminal corresponding to each of the plurality of input / output circuits 50. 54-3.

The first voltage input terminal 54-1 receives the H logic voltage from the power supply unit. The second voltage input terminal 54-2 receives the L logic voltage from the power supply unit. The third voltage input terminal 54-3 receives the termination voltage from the power supply unit. Thereby, each of the plurality of input / output circuits 50 can receive a drive voltage from the external power supply unit 42.

The voltage setting unit 56 generates a reference value serving as a reference for a driving voltage received from the outside. More specifically, the voltage setting unit 56 generates a reference voltage equal to the drive voltage to be supplied to the plurality of input / output circuits 50 as a reference value.

In this example, the voltage setting unit 56 includes a first setting unit 62, a second setting unit 64, and a third setting unit 66. The first setting unit 62 generates a first reference voltage equal to the H logic voltage. The second setting unit 64 generates a second reference voltage equal to the L logic voltage. The third setting unit 66 generates a third reference voltage equal to the termination voltage. The 1st setting part 62, the 2nd setting part 64, and the 2nd setting part 64 are DA converters as an example.

The reference terminal 58 outputs the reference value generated by the voltage setting unit 56 to the outside. More specifically, the reference terminal 58 outputs the reference voltage generated by the voltage setting unit 56 to the outside as a reference value. In this example, the integrated circuit device 40 includes a first reference terminal 58-1, a second reference terminal 58-2, and a third reference terminal 58-3. The first reference terminal 58-1 outputs the first reference voltage generated by the first setting unit 62 to the outside. The second reference terminal 58-2 outputs the second reference voltage generated by the second setting unit 64 to the outside. The third reference terminal 58-3 outputs the third reference voltage generated by the third setting unit 66 to the outside.

The power supply unit 42 generates a drive voltage corresponding to the reference value output from the integrated circuit device 40 and supplies it to the integrated circuit device 40. More specifically, the power supply unit 42 generates a drive voltage obtained by amplifying the reference voltage output from the reference terminal 58 by a current buffer circuit. That is, the power supply unit 42 keeps the driving voltage constant and amplifies the current according to the load.

In this example, the power supply unit 42 includes a first supply unit 72, a second supply unit 74, and a third supply unit 76. The first supply unit 72 generates an H logic voltage obtained by power amplification of the first reference voltage. The second supply unit 74 generates an L logic voltage obtained by power amplification of the second reference voltage. The third supply unit 76 generates a terminal voltage obtained by power amplification of the third reference voltage.

Further, the power supply unit 42 distributes and supplies the generated drive voltage to each of the plurality of voltage input terminals 54 of the integrated circuit device 40. As an example, the power supply unit 42 supplies the drive voltage via a plurality of wires that connect the output terminal of the drive voltage and each of the plurality of voltage input terminals 54.

According to the test unit 30 having the above-described configuration, even if the number of test signals to be supplied from the integrated circuit device 40 to the DUT 200 is large, the current without increasing the power supply inside the integrated circuit device 40. Supply capacity can be increased.

Note that the integrated circuit device 40 may further include a connection line that internally connects the plurality of voltage input terminals 54 when the drive voltages to be supplied to each of the plurality of input / output circuits 50 have the same value. As a result, the integrated circuit device 40 can accurately set the voltages of the test signals output from the plurality of input / output circuits 50 to the same level.

FIG. 4 shows a configuration of the input / output circuit 50 according to the present embodiment. As an example, the input / output circuit 50 includes an input / output terminal 78, a driver 80, a first comparator 82, a second comparator 84, a termination resistor 86, and a switch 88. The input / output terminal 78 is connected to a corresponding pin in the DUT 200.

In the driver 80, the logic pattern generated from the test circuit 48 is given to the input terminal, and the output terminal is connected to the input / output terminal 78. Then, the driver 80 outputs the H logic voltage V _IH received via the first voltage input terminal 54-1 in response to receiving the logic pattern indicating the H logic. Further, the driver 80 outputs the L logic voltage V _IL received via the second voltage input terminal 54-2 in response to receiving the logic pattern indicating the L logic.

The first comparator 82 receives the H-side threshold voltage V _OH for determining whether or not the response signal is H logic at the minus-side input terminal. The first comparator 82 has a positive input terminal connected to the input / output terminal 78. The first comparator 82 outputs a logic signal indicating whether or not the response signal received via the input / output terminal 78 is equal to or higher than the H-side threshold voltage _VOH .

The second comparator 84 receives the L-side threshold voltage V _OL for determining whether or not the response signal is L logic at the plus-side input terminal. The second comparator 84 has a negative input terminal connected to the input / output terminal 78. Then, the second comparator 84 outputs a logic signal indicating whether or not the response signal received via the input / output terminal 78 is equal to or lower than the L-side threshold voltage _VOL .

Termination resistor 86 has a resistance value that terminates the pin of DUT 200. For example, the termination resistor 86 has a resistance value of 50Ω or 75Ω. Terminating resistor 86 has one end connected to the output terminal 78 via the switch 88, the terminal voltage V _T received via the third voltage input terminal 54-3 is supplied to the other end. In response to receiving a logic pattern indicating termination of the corresponding pin, the switch 88 connects the input / output terminal 78 and the termination resistor 86 and receives a logic pattern other than termination of the corresponding pin. Accordingly, the input / output terminal 78 and the termination resistor 86 are opened.

The input / output circuit 50 configured as described above can output a test signal based on the drive voltage supplied from the external power supply unit 42. Further, such an input / output circuit 50 can connect a corresponding pin of the DUT 200 to a termination voltage supplied by an external power supply unit 42 via a termination resistor.

FIG. 5 shows a configuration of the test board 20 further including a plurality of power supply units 90. Each of the plurality of test boards 20 may further include a plurality of power supply units 90.

Each of the plurality of power supply units 90 is provided corresponding to each of the plurality of integrated circuit devices 40 on a one-to-one basis. In this example, each of the plurality of power supply units 90 is provided in the corresponding test unit 30.

Each of the plurality of power supply units 90 generates a power supply voltage in which a voltage supplied from an external power supply is stabilized within a predetermined fluctuation range. As an example, each of the plurality of power supply units 90 steps down a voltage supplied from an external power supply, and generates a power supply voltage stabilized within a predetermined fluctuation range (for example, a ± 5% range of 5 volts). To do. Each of the plurality of power supply units 90 supplies the generated power supply voltage to the corresponding integrated circuit device 40.

According to such a test board 20, even if the fluctuation range of the power supply voltage allowed by the integrated circuit device 40 is narrower than the amount of change in the voltage output from the external power supply, the integrated circuit device 40 is stabilized. Can be operated.

As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

The execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior”. It should be noted that they can be implemented in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for the sake of convenience, it means that it is essential to carry out in this order. is not.

10 test equipment, 20 test board, 22 control board, 24 device connection unit, 26 test controller, 28 network unit, 30 test unit, 32 sub-controller, 34 memory, 36 board controller, 40 integrated circuit device, 42 power supply unit, 48 test circuit, 50 input / output circuit, 54 voltage input terminal, 56 voltage setting unit, 58 reference terminal, 62 first setting unit, 64 second setting unit, 66 third setting unit, 72 first supply unit, 74 second Supply unit, 76 third supply unit, 78 input / output terminal, 80 driver, 82 first comparator, 84 second comparator, 86 termination resistor, 88 switch, 90 power supply unit, 200 DUT

Claims

An integrated circuit device having a reference terminal for outputting a reference value serving as a reference of a driving voltage received from the outside;
A voltage supply unit that generates the drive voltage according to the reference value and supplies the drive voltage to the integrated circuit device;
A device comprising:
The integrated circuit device outputs a reference voltage equal to the drive voltage as the reference value;
The apparatus according to claim 1, wherein the voltage supply unit generates the drive voltage obtained by power amplification of the reference voltage.
The integrated circuit device includes a plurality of circuits and a plurality of voltage input terminals that receive the driving voltage for driving the corresponding circuit among the plurality of circuits from the outside.
The apparatus according to claim 1, wherein the voltage supply unit distributes and supplies the drive voltage to each of the plurality of voltage input terminals.
The apparatus according to claim 3, wherein the integrated circuit device has a connection line that connects the plurality of voltage input terminals internally.
The apparatus according to claim 1, wherein the integrated circuit device tests a device under test.
The integrated circuit device has a plurality of drivers for supplying signals to the device under test;
The apparatus according to claim 5, wherein the voltage supply unit generates an H logic voltage and an L logic voltage of a test signal output from the plurality of drivers as the drive voltage.
The integrated circuit device has a termination resistor that terminates a pin of the device under test.
The apparatus according to claim 5, wherein the voltage supply unit generates a termination voltage connected to the pin via the termination resistor as the drive voltage.
The apparatus is a test apparatus including a plurality of test boards for testing a device under test,
Each of the plurality of test boards is
A plurality of said integrated circuit devices each testing a device under test;
A plurality of the voltage supply units;
A plurality of power supplies provided corresponding to each of the plurality of integrated circuit devices, generating a power supply voltage in which a voltage supplied from an external power supply is stabilized within a predetermined fluctuation range, and supplying the power supply voltage to the corresponding integrated circuit device And
The apparatus according to claim 1, comprising:
The apparatus according to claim 8, wherein the plurality of power supply units generate the power supply voltage by stepping down a voltage supplied from the external power supply.