JPH04131777A - Three-value output circuit of ic tester - Google Patents

Abstract

PURPOSE:To provide a circuit having a good switching characteristic by changing over between three values at a high speed using a transistor circuit formed from differentially operating transistors. CONSTITUTION:When H and L levels are fed to terminals 11 and 12, respectively, transistors TR1B, TR1C are turned on, and No.1 level is given out of an output terminal 16. If then the L and H levels are fed to the terminals 11 and 12, respectively, transistors TR1B, TR1D are turned on, and No.2 level is given to the output terminal 16. When on the other hand the L and H levels are fed to terminals 13 and 14, respectively, and also the inputting is made so that the terminals 11, 12 are fixed to the No.2 level outputting state, then transistors TR2A, TR2D are turned on, and No.3 level is given to the output terminal 16. Thus three-value output can be taken out quickly by configuring the circuit with transistors.

Description

[Detailed Description of the Invention] [Industrial Application Fields] This invention is used for a driver circuit of an IC tester;
This is a 31-sen output circuit that can handle high-speed measurement of 10 bins.

[Prior Art] Next, the configuration of a ternary output circuit according to the prior art will be explained with reference to FIG.

4 is a 2 (11 output circuit), 4 is a resistor, 5 is a switch circuit, 6 is a determination circuit, 7 and 8 are logic input terminals, and 9 is an output terminal.

When the "H" level is input to the terminal 7, the binary output circuit 3 outputs the level ■1) l to the output 9, and outputs r to the terminal 7.
When the LJ level is input, the level ■1L is output to the output 9. At this time, the r l (J level) is input to the terminal 8, and the switch circuit 5 is not operating.

In this case, the binary output circuit 3 responds to the input of the device by
It becomes possible to supply the level.

Next, when the rLJ level is input to terminal 8, terminal 7
The output of the binary output circuit 3 is in a high impedance state regardless of the input of , the switch circuit 5 operates, and the level v1 is outputted to the output 9 through the resistor 4.

In this case, it becomes possible to drive the output of the device with the level 1 as the terminal voltage of the device and the resistor 4 as the terminal resistance, and the output of the driven device is measured by the high impedance input determination circuit 6.

When the I10 pin of the device is connected to the output 9, the binary output circuit 3 and the switch circuit 5 must be switched at high speed.

[Problems to be Solved by the Invention] In FIG. 4, since the switch circuit 5 is used, it cannot be operated at high speed, and the rising and falling edges are not sharp. Furthermore, since the switch circuit 5 independent of the binary output circuit 3 is used, the switching time is on the order of Ions, making it impossible to support high-speed devices.

This invention uses a TR circuit composed of differential transistors (hereinafter referred to as TR) to output levels of 3 (+1!) at high speed, I, VtL, and ■, and has good switching characteristics. The purpose is to provide a value output circuit.

[Means for Solving the Problems] In order to achieve this object, in the present invention, a TR1A having a logic input signal 21 as an input, and a TR1B having a logic input (22) as an input and being differential with the TRIA. , TR1
A constant current source 1E that drives A.
TR1D differential with RIC, level terminal 15 and TR1
A resistor 1G connected between D, a constant current [1F that drives TRIC・1D, and T which inputs the logic input signal 23]
TR2B, which has the logic input signal 24 as its input and is differential with TR2A; and TR2C, which has the output of TR2B as its base input and connects the output of TR] and C to its collector.
, the output of TR2A is used as the base input, the output of TR1D is connected to the collector, and the 'I' R is differentially connected to TR2C.
2D, constant current M2E that drives TR2A/2B, and T
Equipped with a constant current source 2F that drives R2C and 2D, TR1
A logic output signal 25 is taken out from D.

[Function] Next, the 3(I! output circuit according to the present invention will be explained with reference to FIG. 1. In FIG. 1, 1A to 1D and 2A to 2D are TR
11E and 1F are constant current sources, 1G is a resistor, 2E and 2F are constant current sources, 11 to 14 are input terminals for logic signals 21 to 24, 15 is a first level terminal, and 16 is an output terminal. TR1A to TR1D constitute a binary output circuit, and T
R2A to TR2D constitute a 1-value output circuit.

When the [HJ level is input to the terminal 13 and the "L" level is input to the terminal 14, TR2B operates and TR2A does not operate. A current I2A flows from the constant current source 2E to the power supply terminal 2G through the TR2B and the bias resistor. The potential of the base of TR2C is higher than that of the base of TR2D, and TR2
C works and TR2D does not work. In this state, the output terminal 16 is determined by the output of the binary output circuit 1.

Input rHJ level to terminal 11, rLJ level to terminal 12.
When a level is input, TR1B operates and constant current source 1
From E to TRI B and bias resistor to power supply terminal I
Current A flows to H. TRI from the base of TR1D
Since the base of C has a higher potential, TRI C operates and TR1D does not operate, terminal 15 and output terminal 1
6 have the same potential, and the first level is output from the output terminal 16.

Next, when the rLJ level is input to terminal 11 and the "H" level is input to terminal 12, TR1B operates and TR1
D works.

Here, the currents, 1, 1, I2A, and I2B are controlled to the following current values.

I, A: a X (Vllll VIL)...
Old・・・・・・・・・・・・・・・(1) I 2A= b
X (VIL Vt)・・・・・・・・・・・・
・・・・・・・・・(2) The first level value is Vl,...
Let the second level value be V I L and the third level value be ■. a and b are positive coefficients that change the current value according to the level difference, but do not change the level switching time.

I1B=(Vl□-VIL)/R・・・・・・・・・・
・・・・・・・・・・・・(3) I 211= (VIL
-VT)/R・・・・・・・・・・・・・・・
...(4) R is the resistance value of the resistor 1G.

When TR1D operates, currents 1 and 6 flow into the constant current source 1F from the first level terminal 15 through the resistor 1G and TR1D. Since the current I1B of equation (3) flows through the output terminal 16, ■1L, that is, the second level is output.

“L” level is input to terminal 13, and [(j
The level is inputted, and at the same time, the terminals 11 and 12 are inputted so as to be fixed at the second level output state. As a result, TR2A operates, and TR2D, whose base has a high potential, operates. At this time, a current of 12% flows from the first level terminal 15 to the constant current [2F through the resistor 1G and TR2D. Since currents I, B and current I2B flow from the first level terminal 15 to the resistor 1G, Vr, that is, the third level, is outputted to the output terminal 16 from equations (3) and (4).

Next, the relationship between the logic input signals 21 to 24 and the logic output signal 25 will be explained with reference to the time chart of FIG.

3A shows the waveform of the logic input signal 21, FIG. 3A shows the waveform of the logic input signal 22, FIG. 3 shows the waveform of the logic input signal 23, and FIG. 3 shows the waveform of the logic input signal 24. FIG. 3 shows the waveform of the 734+n logic output signal 25 taken out from the output terminal 16.

The logic input signals 21 and 22 are inverted signals of "H" and "L", and the logic input signals 23 and 24 are also "H".
"L" is an inverted signal.

Further, the first level, second level, and third level are controlled to have the following relationship.

■、□＞VI L＞Vt・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・(5
) for driving the output of the device, the third level vr
is the termination voltage, and the resistor 1G operates as the termination resistance.

This follows Thevenin's theorem as seen from the output terminal 16.

The determination circuit 10 in FIG. 2 is placed in a divided resistor 1G. This is because the determination circuit 10 operates at high speed.
This is to limit the input voltage since no buffer circuit is provided at the input.

Since no external switch circuit is used, the switching time for the three-value output can be reduced to less than ins.

[Effects of the Invention] According to the present invention, since the ternary output circuit is constituted by the TR, the ternary output can be taken out at high speed.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of the 3(t!! output circuit) of the IC tester according to the present invention, FIG. 2 is a connection diagram of the determination circuit for FIG. 1, and FIG. A time chart of the logic output signal 24, FIG.
FIG. 2 is a configuration diagram of a ternary output circuit of a C tester. 1A to 1D...TR (h transistor), 1E・
1F...constant current source, 1G...resistance, 2
A to 2D...TR12E/2F...Constant current source, 11 to 14...Logic signal input terminal, 2
1 to 24...Logic input signal, 25...
Logical output signal. In Figure 1, the circuit is configured by TR, and the agent
Patent Attorney Kin Tsukasa Komata Diagram A

Claims (1)

[Claims] 1. A first transistor (1A) that receives a first logic input signal (21) as an input, and a first transistor (1A) that receives a second logic input signal (22) as an input. The second transistor (1B) differentially connected to
, the first transistor (1A) and the second transistor (1A)
B), a third transistor (1C) which receives the output of the first transistor (1A) as input, and a third transistor (1C) which receives the output of the second transistor (1B) as input. , a fourth transistor (1C) differentially connected to the third transistor (1C);
1D), a resistor (1G) connected between the level terminal (15) and the output of the fourth transistor (1D), and a resistor (1G) connected between the third transistor (1C) and the fourth transistor (1D).
D) and a fifth transistor (2F) that receives the third logic input signal (23) as an input.
A) and a sixth transistor (2B) which receives the fourth logic input signal (24) and is differentially connected to the fifth transistor (2A).
and the output of the sixth transistor (2B) is the base input,
The output of the third transistor (1C) is connected to the collector of the seventh transistor (2C), the output of the fifth transistor (2A) is the base input, and the output of the fourth transistor (1D) is connected to the collector. and an eighth transistor (2D) that is differentially connected to the seventh transistor (2C), a fifth transistor (2A), and a sixth transistor (2C).
B); a fourth constant current source (2F) that drives a seventh transistor (2C) and an eighth transistor (2D); Logic output signal (25) from transistor (1D)
A three-value output circuit for an IC tester, which is characterized in that it extracts .