201205101 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電壓供應裝置。 【先前技術】 並行地對多個㈣m元件（树亦_ (devieeunde】 test’DUT))進行測試的測試裝置已為人所知（例如夂昭 專利文獻1)。而且，包括將用崎DUT進行測試所需的 功能安裝在-塊晶片上的職㈣積體電路元件的測試裝 置亦已為人所知（例如參照非專利文獻丨）。 〜 專利文獻1國際公開第2008/020555號手冊 非專利文獻 1 B8501ES press release”，[〇nijne]， 2009年11月19日，日本Engineering股份有限公司，細 年4月8曰檢索]’網路〈Url: kttp://www.iec.co.jp/news hRSQles.html> 然而，此種測試用的積體電路元件在例如應供應至 DUT的測試信號的數量增加時，必需增大用以輪 號所需的電流供應能力。 ' 【發明内容】 為了解決上述課題，本發明的第丨態樣提供_種電壓 供應裝置，包括：積體電路元件，包括使成為自外部接收 的驅動電壓的基準的基準值輸出的基準端子；以及電壓供 應部，產生與上述基準值相應的上述驅動電壓並將該驅動 電壓供應至上述積體電路元件。 另外，上述的發明的概要並未列舉本發明的所有必要 4 201205101 特徵而且，該些特徵群的次（sub)組合亦可成為發明。 —為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 【實施方式】 以下’透過發明的實施形態來說明本發明的（一）方 面，但以下的實施形態並不限定申請專利範圍所述的發 而且貫知》形悲中所說明的特徵的所有組合並不限於 發明的解決手段所必需者。 圖1將本實施形態的測試裝置10的構成連同多個 UT200併表示。測试裝置10並行地對多個DUT200進 ，測試。作為一例，DUT200為快閃記憶體（flash mem〇ry ) 等的非揮發性記憶體。 測試裝置10包括多個測試板20、控制板22、元件連 接部24、測試控制器26、及網路部28。多個測試板2〇的 各個與一個或多個DUT200連接。多個測試板2〇的各個 在與所連接的一個或多個DUT200之間進行信號的收發， 並對該些一個或多個DUT200進行測試。201205101 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a voltage supply device. [Prior Art] A test apparatus for testing a plurality of (four) m elements (decedeunde test 'DUT) in parallel is known (for example, 夂昭 Patent Document 1). Further, a test apparatus including a functional (four) integrated circuit component on which a function required for testing with a Saku DUT is mounted on a -chip wafer is also known (for example, refer to Non-Patent Document 丨). ~ Patent Document 1 International Publication No. 2008/020555 Handbook Non-Patent Document 1 B8501ES press release", [〇nijne], November 19, 2009, Japan Engineering Co., Ltd., April 8th Search] 'Network <Url: kttp://www.iec.co.jp/news hRSQles.html> However, the integrated circuit component for such testing must be increased when, for example, the number of test signals to be supplied to the DUT is increased. The present invention provides a voltage supply device including: an integrated circuit component including a driving voltage that is received from the outside. a reference terminal for outputting a reference value of the reference; and a voltage supply unit that generates the drive voltage corresponding to the reference value and supplies the drive voltage to the integrated circuit element. Further, the summary of the invention does not exemplify the invention. All necessary 4 201205101 features and sub-combinations of the feature groups may also be invented. - To make the above features and advantages of the present invention more apparent, The embodiment will be described in detail below with reference to the accompanying drawings. [Embodiment] Hereinafter, the aspect (1) of the present invention will be described by way of embodiments of the invention, but the following embodiments are not limited to the scope of the claims. All combinations of features described in the stipulations are not limited to those required by the inventive solution. Figure 1 shows the configuration of the test apparatus 10 of the present embodiment along with a plurality of UTs 200. The test apparatus 10 is in parallel The DUT 200 is a non-volatile memory such as a flash memory or the like. The test device 10 includes a plurality of test boards 20, a control board 22, and component connection portions 24 as an example. The test controller 26 and the network portion 28. Each of the plurality of test boards 2 is connected to one or more DUTs 200. Each of the plurality of test boards 2 is signaled between the connected one or more DUTs 200 Transceiver, and test one or more of the DUTs 200.
控制板22對多個測試板20的各個供應電源電壓。而 且’控制板22對多個測試板20的各個進行控制。作為一 例，控制板22對多個測試板20與對應的DUT2〇〇之間的 連接狀態進行控制。測試裝置10亦可包括多個控制板 作為一例，多個測試板20及控制板22收納於作 農置1〇的本體部的測試頭（testhead)的内部。M 疋件連接部24以可自外部安裝及卸下的狀態來保持 201205101. J / JZJpif 多個DUT200。而且，元件連接部24將所保持的多個 DUT200的各個與對應的測試板20之間予以電性連接。而 且，元件連接部24將多個DUT200與控制板22之間予以 電性連接。 測試控制器26將用戶資料報協定/網際網路協定 (User Datagram Protocol/Internet Protocol，UDP/IP )等的 通信封包(packet)在多個測試板20及控制板22之間交換， 並對多個測試板20及控制板22進行控制。而且，測試控 制器26輸入來自用戶的資訊，且對用戶輸出資訊。作為一 例’測試控制器26為執行程式的電腦。測試控制器26根 據來自用戶的指示而執行程式，並對該測試裝置1〇進行控 制。 網路部28將多個測試板20及控制板22、與測試控制 器26之間可通信地加以連接。網路部28為用來轉接 Ethernet (註冊商標）等的高速串列匯流排（serial bus )的 集線器(hub)。 圖2表示本實施形態的測試板2〇的構成。測試板2〇 包括多個測试部30、多個子控制器（8油c〇ntr〇uer ) μ、 多個記憶體34、及板控制器36。例如，構成測試板2〇的 多個測試部30、多個子控制器32、多個記憶體％及板控 制器36安裝於一塊基板上。於此情況下，板控制 測試部30等可在安餘子魏上之制由連接^而^ 於一塊基板。 多侧試部3〇的各個執行表示用以依次產生邏輯圖 6 201205101 -5 案及期望值（expectation value )圖案等的序列的測試程 式，並對一個DUT200進行測試。多個測試部3〇的各個 於與對應的一個DUT200之間發送或接收由測試程式所示 的邏輯圖案的信號，藉此來測試對應的一個DUT200。若 例如DUT200為非揮發性記憶體，則多個測試部3〇的各 個檢測對應的DUT200内的每個位址位置的單元（cdl) 否優良。 ，lu叫兩0丨分別獨立地執行測試。例如， 多個測試部3G即使於明—時序開始測試的情況下，根 對應的DUT200的狀態而發送或接收的信號及時序亦會 所不同。 多個子控制器32的各個連接於多個測試部3〇中的 L L同Ϊ —個或多個測試部3G。本例中，多個子控制器32 個兩部3〇。多個記憶體34的各個與多 各個Ϊ由二μ各個—對—地相對應。多個記憶體34的 二工心的子控制器32來進行資料的寫人及讀出。 Φΐ, ί6 30 個靖扪得送。而且，多個子控制器32的各 該測試隱體中的測試結果，並將 不不良位址的位置的失 丨仏㈣。買出表 料記憶於對應的々卜触貧枓（fai1 data)，並將該失效資 各個㈣水Γ的憶體34中。而且’多個子控制器32的 x *對應的測試部3〇的指示，讀出記憶於對應的 201205101 中的戦程式並將該崎程式傳送至對應的測 …板控制器36經由網路部28而與測試 通k封包的交換。而且，板控制器％ 工 仃 26供應的通信封包中所包含的指令 測試控制器 中的指定的測試部30寫入資料。藉此、夕個測試部30 控制U供應的指令-多 藉此’板控制器36能夠根據由職控制器％ 而將指定的測試部3G的測試結果等傳送至測試i 圖3表示本實施形態的測試部3〇的構成。輯部邛 包括積體電路元件40及電源供應部42。作為一例 電路元件40為將-個或多個晶片封裝（paekage)化所^ 的疋件。電源供應部42產生驅動電壓並將該驅動電壓Z 至積體電路元件40。 〜△ 積體電路元件40包括測試電路48、多個輸入輪出電 路50、多個電壓輸入端子54、電壓設定部56、及基 子 58。 ％ 測試電路48將表示應供應至DUT200的測試信號的 邏輯的邏輯圖案對應於DUT200的多個接腳的各個而產 生。進而’測試電路48中，將自DUT200的多個接聊的 8 201205101 37523pif 出的應答信號（reply Signal)的接收值與該應答信 的期望值加以比較，來判斷對應的DUT2GG的各個的每 個位址位置是否優良。 抹阶^個輸人如電路5G的各瓣接於DUT2G()的多個 ==個。多個輸入輸出電路50的各個自測試電路48 電壓位準的測Si ft接收到的邏輯圖案相應的 的各個根據接㈣的個輸人輸出電路50 電壓的測試信號。來輸出H邏輯電壓或L邏輯 的各個根據接收到的邏輯2一^多個輸入輸出電路50 腳連接至終端電壓。輯圖案，經由終端電阻將對應的接 的對^5G _ _的 DUT· 個將所輸人的應答信號。H ^個輸人輸出電路5〇的各 以比較，並將表示應答^準與臨限沖讀οΜ)值位準加 路48。 .唬的值的邏輯信號供應至測試電 此處’多個輸入輪出_ 源供應部42供應的軸 G的各個接收由外部的電 行動作。作為一例，多{聖’並根據接收到的驅動電壓進 邏_及4輯電輪出電路5〇的各個接收Η 輸出電路5〇的各個能夠:為驅動電壓。藉此，多個輸入 來輸出測試信號。而且=由外部的電源供應部42的電力 終端電壓來作為驅動電個輪入輸出電路50的各個接收 的各個能夠藉由外#a#。藉此，多個輸入輸出電路50 ㈣電源供應部^的電力而使對應的 201205101 接腳成為終端。 多個電壓輸入端早y 路50的各個來設置%子自^的各個對應於多個輸入輪出電 動對應的輪人輸出魏=的電源供應部42接收用以驅 端子54-3。 询八触千54 2及第3電壓輸入 ㈣第2電壓輸人端子54_1自電源供應部42接收Η、羅錄 輯電壓mt _供應部42接收L邏 山♦广.+電壓輸入端子54_3自電源供應部42接收線 2堅。藉此’多個輸入輸出電路5〇的各個 ： 電源供應部42接_動電壓。 目外稍 電堅°又疋0卩56產生成為自外部接收的驅動電壓的美 ，的基準值。更具體而言，電塵設定部56產生與應供應^ 夕個輸入輸出電路50的驅動電壓相等的基準電壓來作為 基準值。 # 本例中’電壓設定部56具有第1設定部62、第2設 定部64、及第3設定部66。第1設定部62產生與H邏輯 電壓相等的第1基準電壓。第2設定部64產生與L邏輯 電壓相等的第2基準電壓。第3設定部66產生與終端電壓 相等的第3基準電壓。作為一例，第1設定部62、第2設 定部64及第2設定部64為DA轉換器。 基準端子58將藉由電壓設定部56而產生的基準值輸 出至外部。更具體而言，基準端子58將藉由電壓設定部 201205101 56而產生的基準電壓作為基準值而輸出至外部。本例中， 積體電路元件40具有第1基準端子58-1、第2基準端子 58-2、及第3基準端子58_3。第！基準端子58_丨二藉由第 1設定部62而產生的第丨基準電壓輸出至外部。第2曰基準 端子58-2將藉由第2設定部64而產生的第 ^ 出至外部。第3基準端子似將藉由第3設定；^ = 生的第3基準電壓輸出至外部。 電源供應部42產生與自積體電路元件4〇輸出的基準 值相應的驅動電壓並將該驅動電壓供應至積體電路元件 40。更具體而言，電源供應部42產生藉由電流緩衝電路來 對自基準端子58輸出的基準電壓進行電力放大而得的驅 動電壓。亦即，電源供應部42將驅動電壓設為固定，並根 據負載將電流予以放大。 、 本例中，電源供應部42包括第1供應部72、第2供 應部74、及第3供應部76。第1供應部72產生對第 準電壓進行電力放大而得的H邏輯電壓。第2供應部二 產生對第2基準電壓進行電力放大而得的[邏輯電壓。第 3供應部76產生對第3基準電壓進行電力放大而得的終端 電壓。 … 而且，電源供應部42將所產生的驅動電壓分配供應 至積體電路元件40的多個電壓輸入端子54的各個。作為 一例’電源供應部42經由用於連接驅動電壓的輪出端與多 個電壓輸入端子54的各個的多條配線來供應驅動電壓。 根據如以上構成的測試部30,即使於自積體電路元件 11 201205101 40應供應至DUT200的測試信號的數量多的情況下， ^積體魏潘4〇_部的電雜可提高電流供應能 另外’積體電路元件40於應供應至多個輸入輸出電 路50的各個的驅動電壓為相同值的情況下，亦可更:J於 m接多個電壓輸入端子54的連接線。藉此:積體 _的 圖4表示本實施形態的輸入輸出電路5〇的構成。作 為一例，輸入輸出電路50包括輸人輪+ % 關沾。輸入輸出端子78連接於DUT2〇〇的對應的接腳; 2器80中，輸入端被提供了由測試電路48產生的 it Λ’且輸出端連接於輸人輸出端子78。而且，驅動The control board 22 supplies a power supply voltage to each of the plurality of test boards 20. Moreover, the control panel 22 controls each of the plurality of test boards 20. As an example, the control board 22 controls the connection state between the plurality of test boards 20 and the corresponding DUTs 2'. The test apparatus 10 may include a plurality of control boards as an example. The plurality of test boards 20 and the control board 22 are housed inside a test head that is a body portion of the farm. The M-piece connection portion 24 is held in a state in which it can be externally mounted and removed. 201205101. J / JZJpif Multiple DUTs 200. Further, the component connecting portion 24 electrically connects each of the plurality of held DUTs 200 and the corresponding test board 20. Further, the component connecting portion 24 electrically connects the plurality of DUTs 200 and the control board 22. The test controller 26 exchanges a communication packet such as a User Datagram Protocol/Internet Protocol (UDP/IP) between the plurality of test boards 20 and the control board 22, and The test board 20 and the control board 22 are controlled. Moreover, the test controller 26 inputs information from the user and outputs information to the user. As an example, the test controller 26 is a computer that executes programs. The test controller 26 executes the program based on instructions from the user and controls the test device. The network unit 28 communicably connects the plurality of test boards 20 and control boards 22 to the test controller 26. The network unit 28 is a hub for transferring a high speed serial bus of Ethernet (registered trademark) or the like. Fig. 2 shows the configuration of the test board 2A of the present embodiment. The test board 2A includes a plurality of test sections 30, a plurality of sub-controllers (8 oils), a plurality of memories 34, and a board controller 36. For example, a plurality of test sections 30 constituting the test board 2, a plurality of sub-controllers 32, a plurality of memory %, and a board controller 36 are mounted on a single substrate. In this case, the board control test unit 30 and the like can be connected to each other by a connection. Each of the executions of the multi-side test unit 3 indicates a test procedure for sequentially generating a sequence of logic diagrams 6, 201205101 -5 and an expectation value pattern, and tests one DUT 200. A plurality of test sections 3A each transmit or receive a signal of a logical pattern indicated by the test program with a corresponding one of the DUTs 200, thereby testing a corresponding one of the DUTs 200. If, for example, the DUT 200 is a non-volatile memory, each of the plurality of test sections 3A detects whether the cell (cdl) of each address location in the corresponding DUT 200 is excellent. , lu called two zeros to perform the test independently. For example, even when the test unit 3G starts the test, the signals and timings transmitted or received by the corresponding DUT 200 may be different. Each of the plurality of sub-controllers 32 is connected to one or more of the plurality of test sections 3A. In this example, there are 32 sub-controllers in two parts. Each of the plurality of memories 34 and the plurality of memories 34 correspond to each other by two μ pairs. The sub-controller 32 of the plurality of memories 34 performs the writing and reading of the data. Φΐ, ί6 30 Jing Jing have to send. Moreover, the test results in the test hidden bodies of the plurality of sub-controllers 32 will not be lost in the position of the bad address (4). The purchased material is memorized in the corresponding fai1 data, and the invalidation is made in each of the four (4) scorpions. Further, the instruction of the test unit 3〇 corresponding to x* of the plurality of sub-controllers 32 reads the program stored in the corresponding 201205101 and transmits the sagittal program to the corresponding measurement board controller 36 via the network unit 28. And the exchange with the test pass k packets. Further, the specified test unit 30 in the command test controller included in the communication packet supplied from the board controller % 写入 26 writes the data. Thereby, the test unit 30 controls the command of the U supply - the board controller 36 can transmit the test result of the designated test unit 3G and the like to the test according to the incumbent controller %. FIG. 3 shows the embodiment. The structure of the test unit 3〇. The assembly unit includes an integrated circuit component 40 and a power supply unit 42. As an example, the circuit component 40 is a component that encapsulates one or more wafers. The power supply unit 42 generates a driving voltage and Z the driving voltage Z to the integrated circuit element 40. The Δ integrated circuit component 40 includes a test circuit 48, a plurality of input wheel-out circuits 50, a plurality of voltage input terminals 54, a voltage setting unit 56, and a base 58. The % test circuit 48 generates a logical pattern representing the logic of the test signal to be supplied to the DUT 200 corresponding to each of the plurality of pins of the DUT 200. Further, in the 'test circuit 48, the received value of the reply signal from the plurality of 201205101 37523pif of the DUT 200 is compared with the expected value of the response signal to determine each bit of the corresponding DUT 2GG. Is the location good? The wiper is input such that each of the lobes of the circuit 5G is connected to the plurality of DUT2G() == one. Each of the plurality of input and output circuits 50 of the self-test circuit 48 has a voltage level of the measured logic signal corresponding to each of the input signals of the output voltage of the input circuit 50 according to (4). Each of the output H logic voltages or L logics is connected to the terminal voltage according to the received logic 2 and the plurality of input and output circuits 50. The pattern is set, and the response signal of the input is input to the corresponding DUT of the pair of ^5G _ _ via the terminating resistor. Each of the H^ input output circuits 5〇 is compared, and the response level and the threshold read value are added. The logic signal of the value of 唬 is supplied to the test power. Here, the respective receptions of the axis G supplied from the plurality of input wheel-out source supply units 42 are operated by an external electric circuit. As an example, each of the plurality of receiving circuits 〇 and the respective receiving/output circuits 5 of the four-stage electric wheel-out circuit 5A can be driven voltages. Thereby, multiple inputs are used to output the test signal. Further, each of the respective receptions of the drive electric wheel input/output circuit 50 by the power terminal voltage of the external power supply unit 42 can be externally #a#. Thereby, the plurality of input/output circuits 50 (4) power of the power supply unit ^ causes the corresponding 201205101 pin to become the terminal. Each of the plurality of voltage input terminals y is configured to receive the terminal 54-3 for each of the plurality of input wheel outputs corresponding to the plurality of input wheel outputs. The first voltage input terminal 54_1 is received from the power supply unit 42. The supply voltage is received from the power supply unit 42. The supply unit 42 receives the L logic mountain ♦ wide. + voltage input terminal 54_3 from the power supply. The supply unit 42 receives the line 2 firmly. Thereby, each of the plurality of input/output circuits 5A: the power supply unit 42 is connected to the dynamic voltage. The target value of the driving voltage that is received from the outside is generated by a slight voltage. More specifically, the dust setting unit 56 generates a reference voltage equal to the driving voltage to be supplied to the input/output circuit 50 as a reference value. In the present example, the voltage setting unit 56 includes a first setting unit 62, a second setting unit 64, and a third setting unit 66. The first setting unit 62 generates a first reference voltage equal to the H logic voltage. The second setting unit 64 generates a second reference voltage equal to the L logic voltage. The third setting unit 66 generates a third reference voltage equal to the terminal voltage. As an example, the first setting unit 62, the second setting unit 64, and the second setting unit 64 are DA converters. The reference terminal 58 outputs the reference value generated by the voltage setting unit 56 to the outside. More specifically, the reference terminal 58 outputs the reference voltage generated by the voltage setting unit 201205101 56 as a reference value to the outside. In this example, the integrated circuit element 40 has a first reference terminal 58-1, a second reference terminal 58-2, and a third reference terminal 58_3. The first! The reference terminal 58_丨2 outputs the second reference voltage generated by the first setting unit 62 to the outside. The second reference terminal 58-2 is outputted to the outside by the second setting unit 64. The third reference terminal seems to be output to the outside by the third setting; The power supply unit 42 generates a driving voltage corresponding to the reference value output from the integrated circuit element 4A and supplies the driving voltage to the integrated circuit element 40. More specifically, the power supply unit 42 generates a drive voltage obtained by electrically amplifying the reference voltage output from the reference terminal 58 by the current buffer circuit. That is, the power supply unit 42 sets the drive voltage to be fixed and amplifies the current according to the load. In the present example, the power supply unit 42 includes a first supply unit 72, a second supply unit 74, and a third supply unit 76. The first supply unit 72 generates an H logic voltage obtained by electrically amplifying the reference voltage. The second supply unit 2 generates a [logic voltage] obtained by power-amplifying the second reference voltage. The third supply unit 76 generates a terminal voltage obtained by electrically amplifying the third reference voltage. Further, the power supply unit 42 supplies the generated drive voltage distribution to each of the plurality of voltage input terminals 54 of the integrated circuit element 40. As an example, the power supply unit 42 supplies the drive voltage via a plurality of wires for connecting the wheel-out terminal of the drive voltage and the plurality of voltage input terminals 54. According to the test unit 30 configured as above, even in the case where the number of test signals to be supplied to the DUT 200 from the integrated circuit element 11 201205101 40 is large, the electric power of the integrated body can increase the current supply energy. Further, when the integrated circuit elements 40 are supplied to the respective driving voltages of the plurality of input/output circuits 50 to have the same value, the connecting lines of the plurality of voltage input terminals 54 may be connected to each other. Thereby, Fig. 4 of the integrated body _ shows the configuration of the input/output circuit 5A of the present embodiment. As an example, the input and output circuit 50 includes an input wheel + % close. The input and output terminals 78 are connected to corresponding pins of the DUT 2A; in the device 80, the input terminal is provided with it Λ' generated by the test circuit 48 and the output terminal is connected to the input terminal 78. And drive
Hit於接收到表示H邏輯的邏輯圖案，而輸出經由 電壓輸入端子54-1接收到的η邏輯電壓ν 80，應於接收到表示L邏輯的邏輯圖 經由第2電壓輸入端子54_2接收到的L邏輯電壓 第1比較器82於負側（minus side)輪入端收用 乂判定應答信號是否為H邏輯的H侧臨限值電壓v〇H。而 ^中=1比較器82將正侧（plusside)輸入端連接二人 且，第1比較器82輸出表示經由輸入輸 子78接收到的應答信號是否為H側臨限值電壓v〇h 乂上的邏輯信號。 12 201205101 J / &比較器84於正側輸入端，接收用以判定應答信 Α疋否為L邏輯I側臨限值電壓VGL。而且，第2比較 器匕將負側輪入端連接於輸入輸出端子78。而且，第2 ^車^器84輸出表示經由輸人輸出端子78接收到的應答信 说疋H ^侧臨限值電壓Vql以下的邏輯信號。 。，端電P且86具有使DUT200的接腳作為終端的電阻 彳為例，終端電阻86具有50 Ω或75 Ω的電阻值。 終端電阻86的—端經由關88而連接於輸人輸出端子 78,另^端被供應有經由第3電壓輸人端子μ而接收到 ϋ 2電[vt。開關88相應於接收到表示使對應的接腳 :端的邏輯圖案而將輸入輸出端子78與終端電阻86 加以，接’ J_相應於接收到使對應的接腳作為終端的以外 的邏輯圖案而使輪人輸出端子78與終端電阻86開放。 此種構成的輸入輸出電路5〇能夠根據由外部的電源 供應部42而供應的驅動電壓來輸出測試信號。而且，此種 輸入輸出電路5G能触DUT2⑻㈣應的接腳經由終端 電阻而連接於藉由料的電·觸42而供 壓。 圖5表示更包括多個電源部9〇的測試板2〇的構成。 多個測試板20的各個亦可為更包括多個電源部9〇的構成。 多個電源部9G的各個财個積體電路元件4〇的各個 -對-地相對鼓設置。本财，多個電源部9()的各個設 置於對應的測試部30内。 多個電源部9〇的各個生成將自外部電源供應的電壓 13 201205101 在預先規定的變動範圍内穩定化而得的電源電壓。作為一 例，多個電源部90的各個降低自外部電源供應的電壓，而 生成在預先規定的變動範圍（例如5伏的±5%的範圍）内 穩定化而得的電源電壓。而且，多個電源部90的各個將所 生成的電源電壓供應至對應的積體電路元件4〇。 根據此種測試板20，即使於積體電路元件4〇所允許 的電源電壓的變動範圍較自外部電源輸出的電麗的變化量 窄的情況下，亦可使積體電路元件4G穩定地動作。 以上’使用實施形態對本發明進行了綱，但本發明 的技術範圍並不限定於上述實施形態所記載的範圍。可於 上述實施形態中添加多種變更或改良， 人員所知曉。根據申請專利範圍的記 ::二 變更f良的形態亦可包含於本發明的技術二:此種 申請專利範圍、說明書及圖式中表示的裝置 理的執行順序，縣_示「更前」^各處Hit receives the logic pattern indicating the H logic, and outputs the n logic voltage ν 80 received via the voltage input terminal 54-1, and receives the L received via the second voltage input terminal 54_2 on the logic diagram indicating the L logic. The logic voltage first comparator 82 receives on the minus side of the wheel side and determines whether the response signal is the H-side threshold voltage v〇H of the H logic. The ^1=1 comparator 82 connects the plus side input terminal to the two persons, and the first comparator 82 outputs whether the response signal received via the input source 78 is the H-side threshold voltage v〇h. The logic signal on it. 12 201205101 J / & Comparator 84 is received at the positive side input terminal for determining whether the response signal is the L logic I side threshold voltage VGL. Further, the second comparator 连接 connects the negative side wheel end to the input/output terminal 78. Further, the second driver 84 outputs a logic signal indicating that the response signal 疋 H ^ side threshold voltage Vq1 received via the input terminal 78 is equal to or lower. . For example, the terminal resistor 86 has a resistance value of 50 Ω or 75 Ω as an example of a resistor 彳 having a pin of the DUT 200 as a terminal. The terminal end of the terminating resistor 86 is connected to the input terminal 78 via the switch 88, and the other terminal is supplied with the 电压 2 electric power [vt] via the third voltage input terminal μ. The switch 88 receives the input/output terminal 78 and the terminating resistor 86 in response to receiving a logic pattern indicating that the corresponding pin: the terminal is connected, and the 'J_ corresponds to receiving a logic pattern other than the corresponding pin as the terminal. The wheel output terminal 78 is open to the terminating resistor 86. The input/output circuit 5A having such a configuration can output a test signal based on the driving voltage supplied from the external power supply unit 42. Further, the input/output circuit 5G can be connected to the pin of the DUT 2 (8) (4) via the terminating resistor to be connected to the electric contact 42 of the material. Fig. 5 shows a configuration of a test board 2A including a plurality of power supply units 9A. Each of the plurality of test boards 20 may also be configured to include a plurality of power supply units 9A. Each of the plurality of integrated circuit elements 4A of the plurality of power supply units 9G is disposed opposite to the drum. In the present invention, each of the plurality of power supply units 9 () is placed in the corresponding test unit 30. Each of the plurality of power supply units 9A generates a power supply voltage obtained by stabilizing the voltage 13 201205101 supplied from the external power supply within a predetermined fluctuation range. As an example, each of the plurality of power supply units 90 reduces the voltage supplied from the external power supply, and generates a power supply voltage that is stabilized within a predetermined fluctuation range (for example, a range of ±5% of 5 volts). Further, each of the plurality of power supply units 90 supplies the generated power supply voltage to the corresponding integrated circuit element 4A. According to the test board 20, even if the variation range of the power supply voltage allowed in the integrated circuit element 4 is smaller than the amount of change in the power output from the external power supply, the integrated circuit element 4G can be stably operated. . The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. Many changes or improvements can be added to the above embodiments, which are known to the person. According to the scope of the patent application: The second modification may be included in the second aspect of the present invention: the execution order of the device shown in the scope of the patent application, the specification and the drawing, and the county_ Everywhere
St:要，處理的輸出用於後處二： 令的i作二程來f現。關於申請專利範圍、說明書及圖式 次，蓉二-’雖然為方便起見而使用了「首先，」、「其 二太::說明’但並未指必需以該順序來實施。、 择热本發明已以實施例揭露如上， 201205101 【圖式簡單說明】 圖1將本發明的實施形態的測試裝置10的構成連同 多個DUT200 —併表示。 圖2表示本發明的實施形態的測試板20的構成。 圖3表示本發明的實施形態的測試部30的構成。 圖4表示本發明的實施形態的輸入輸出電路50的構 成的一例。 圖5表示更包括本發明的實施形態的電源部90的測 試板20的構成。 【主要元件符號說明】 10:測試裝置 一 20 :測試板 22 :控制板 24 :元件連接部 26:測試控制器 28 :網路部 30 :測試部 32 :子控制器 34 :記憶體 36 :板控制器 40 :積體電路元件 42 :電源供應部 48 :測試電路 50 :輸入輸出電路 54 :電壓輸入端子 54-1 :第1電壓輸入端子 15 201205101 54-2 :第2電壓輸入端子 54-3 :第3電壓輸入端子 56 :電壓設定部 58 :基準端子 58-1 :第1基準端子 58-2 :第2基準端子 58-3 :第3基準端子 62 第1設定部 64 第2設定部 66 第3設定部 72 第1供應部 74 第2供應部 76 第3供應部 78 輸入輸出端子 80 驅動器 82 第1比較器 84 第2比較器 86 終端電阻 88 開關 90 電源部 200 : DUT (被測試元件） Vih · Η邏輯電壓 Vm : L邏輯電壓 V0H : Η侧臨限值電壓 V0L : L側臨限值電壓 VT :終端電壓 16St: Yes, the output of the processing is used for the second two: Let i do two passes to f. Regarding the scope of application for patents, specifications and drawings, Rong Er-'s use "first," and "second two:: explanation" for convenience. However, it does not mean that it must be implemented in this order. The present invention has been described above by way of example, 201205101. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a configuration of a test apparatus 10 according to an embodiment of the present invention together with a plurality of DUTs 200. Fig. 2 shows a test board 20 according to an embodiment of the present invention. Fig. 3 shows a configuration of a test unit 30 according to an embodiment of the present invention. Fig. 4 shows an example of a configuration of an input/output circuit 50 according to an embodiment of the present invention. Fig. 5 shows a power supply unit 90 further including an embodiment of the present invention. The configuration of the test board 20. [Main component symbol description] 10: Test device 20: Test board 22: Control board 24: Component connection portion 26: Test controller 28: Network portion 30: Test portion 32: Sub-controller 34: Memory 36: Board controller 40: Integrated circuit component 42: Power supply unit 48: Test circuit 50: Input/output circuit 54: Voltage input terminal 54-1: First voltage input terminal 15 201205101 54-2: 2 electricity Input terminal 54-3: third voltage input terminal 56: voltage setting unit 58: reference terminal 58-1: first reference terminal 58-2: second reference terminal 58-3: third reference terminal 62 first setting unit 64 Second setting unit 66 Third setting unit 72 First supply unit 74 Second supply unit 76 Third supply unit 78 Input/output terminal 80 Driver 82 First comparator 84 Second comparator 86 Terminating resistor 88 Switch 90 Power supply unit 200: DUT (tested component) Vih · Η logic voltage Vm : L logic voltage V0H : 临 side threshold voltage V0L : L side threshold voltage VT : terminal voltage 16