KR100921222B1 - semiconductor test header apparatus - Google Patents

Abstract

The RUT of the DUT in place of such a PE part in addition to the PE part comprising a driver for writing a test pattern to a device under test (DUT) and a comparator for comparing a level of a read signal input from the DUT by the driver to a predetermined reference value. By providing a separate R / B inspection unit that checks the operation state of the DUT from the signal level output from the / B (Ready / Busy) pin, the unit price of the automatic test equipment (ATE), which is determined by the number of PE units, can be reduced. It relates to a semiconductor test head device.

Semiconductor, Test, ATE, DUT, Driver, Comparator, R / B, NAND Flash

Description

Semiconductor test head apparatus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test head device, and more particularly, a PE unit comprising a driver for writing a test pattern to a device under test (DUT) and a comparator for comparing a level of a read signal input from the DUT by the driver to a predetermined reference value. In addition to this PE, by providing a separate R / B inspection unit for checking the operation state of the DUT from the signal level output from the D / R (B) (Ready / Busy) pin, ATE price is determined by the number of PE The present invention relates to a semiconductor test head device capable of lowering the cost of automatic test equipment.

As is well known, a semiconductor manufactured by a semiconductor manufacturing process is subjected to a test process for correct operation according to its characteristics after manufacturing. The semiconductor test is performed by a semiconductor test system (hereinafter, also referred to as ATE), which is a kind of automatic test equipment (ATE). A conventional semiconductor test system will be described in more detail with reference to FIGS. 1 to 3 below. do.

1 is a perspective view showing the overall configuration of a conventional semiconductor test system. As shown in FIG. 1, the overall configuration of a conventional semiconductor test system includes a test head 2 for largely testing semiconductors and a predetermined number of semiconductors to be transported to perform a test, and the semiconductors are classified according to the test results. And a high-fix (HIFIX) board (1) interposed between the loading handler (3) and the test head (2) and the handler (3) to establish an electrical connection between the semiconductor and the test head (2). have. That is, the semiconductor and the high-fixed board (1) seated in the insert on the test tray in a state where the high-fixed board 1 in which the sockets of the (m * n) arrays are arranged and the test site of the handler 3 are matched. (Mxn) semiconductor devices are tested simultaneously by the sockets on ().

2 is an electrical block diagram schematically showing a conventional semiconductor test head device, and FIG. 3 is an electrical circuit diagram showing a conventional semiconductor test head device in detail.

As shown in FIG. 2, the test head 2 includes a single test head substrate and various circuit elements mounted on one side or both sides thereof. Referring to the configuration of the test head substrate, the test head 2 is defined for a semiconductor test. A pattern driver for recording an ALPG (Algorithm Pattern Generater) 10 for generating a test pattern signal and a test pattern signal output from the ALPG 10 to a device under test (hereinafter referred to as a 'DUT') 50. A PE (Pin Electronic) section including a comparator 33 for comparing the read signal of the test pattern read by the DUT 50 with the reference signal corresponding to the characteristic of the semiconductor and the comparison signal 31 and 31. 30, the control computer 5 for controlling the semiconductor test system and the interface unit 70 for the interface of the test head (2).

Here, the PE unit 30 is a circuit that applies a current and a voltage according to the test pattern directly to the semiconductor provided in the DUT 50. In addition, when the test pattern signal is output by the test pattern signal generator of the ALPG 10, the pattern driver 31 of the PE unit 30 transmits the corresponding test pattern signal to the DUT 50 having a ball grid array (BGA) type. The data is recorded in the semiconductor under test. The pattern signal recorded as described above is read by the DUT 50 and output to the comparator 33. The comparator 33 compares the read signal of the test pattern with the reference signal according to a result of the interface unit ( The control computer 5 transmits the data to the control computer 5 through 70, and the control computer 5 can analyze the corresponding comparison signal to check whether the semiconductor works correctly according to its characteristics.

In addition, as shown in FIG. 3, the configuration of the test head device will be described in more detail. A time delay element 31a connected to an input terminal of the pattern driver 31 to compensate for a time delay between drivers, Programmable load 35 for adjusting the current applied to the DUT 50 to a predetermined current level, an output voltage controller for adjusting the voltage applied to the DUT 50 to a predetermined voltage level (dynamic Clamp; outputs the signal output from the DCLP) 37 and the pattern driver 31 to the DUT 50 at a termination of the pattern driver 31, that is, the impedance between the pattern driver 31 and the DUT 50. And matching impedance matching element 31b. Here, the comparator 33 is a so-called window comparator that compares the level of the signal read out from the DUT 50 with a predetermined high level reference value (VOH) and the signal read out from the DUT 50. It consists of a low level comparator for comparing the level with a predetermined low level reference value (VOL).

In the above-described configuration, the PE unit 30 and the components for improving the signal processing speed of the PE unit 30, that is, the time delay element 31b, the output current control unit 35, and the output voltage control unit 37 And the impedance matching element 31b forms one input / output (I / O) channel, and hundreds of thousands, tens of thousands or tens of thousands, depending on the number of DUTs 50 seated in an insert on the test tray. It is formed. Thus, ATE is priced based on the number of these I / O channels.

Meanwhile, the nand flesh memory has a separate R / B pin for outputting an operation state of the memory, in addition to a plurality of I / O pins for inputting / outputting data. Therefore, when the ATE checks the NAND flash memory, one of the PE units must be connected to the R / B pin, and thus, the NAND flash memory can be inspected only when the ATE is connected to the R / B pin.

However, according to the conventional semiconductor test head device, assigning the PE part to the R / B pin to check the level of the signal input from the R / B pin is inefficient in operating the ATE, and the PE according to the number of R / B pins. There is a problem that the unit price of ATE becomes higher because more wealth must be constructed.

For example, if ATE has 1,024 I / O channels and memory has 8 I / O pins, ATE can simultaneously check 128 memories. However, when ATE checks NAND flash memory, the number of possible memory tests is 113 (= 1,024 / 9) since the R / B pins must be allocated to I / O channels separately. Above all, ATE is generally divided into boards (I / O channels), so I / O channels can not be shared by each board. Therefore, if 1,024 I / O channels are divided into 32 board units, it can be seen that the number of NAND flash memories that can be actually inspected is 96 because three memories are allocated to one board. Furthermore, allocating three memories per board leaves five I / O channels per board, leaving 160 I / O channels total.

In addition, ATE allocates eight I / O channels per memory, but not all of these I / O channels perform the functions of the pattern driver / compressor described above, one of which is a pattern representing a logic value. In some cases, the signal is used only for a level driver for applying a voltage level, for example, Vpp, to a memory, not a signal. Therefore, it is inefficient to implement all of the I / O channels in the configurations shown in FIG. Here, Vpp is a high potential higher than the driving potential Vcc of the memory, which is mainly used to eliminate the threshold voltage Vt loss.

The present invention has been made to solve the above-described problems, by providing a separate means for checking the operation state of the DUT at the signal level input from the R / B pin of the DUT in place of the PE unit and outputting a level signal to the DUT, ATE It is an object of the present invention to provide a semiconductor test head device that can improve the efficiency of the.

In order to achieve the above object, the semiconductor test head apparatus of the present invention corresponds to a pattern driver for recording a pattern signal into a semiconductor under test and a characteristic of the semiconductor signal under test and the read signal of the test pattern read by the semiconductor under test. A semiconductor test head device comprising a comparator for comparing a reference signal and outputting the comparison value, wherein a single I / O channel is formed separately from the comparator and the pattern driver, and the R of the semiconductor under test And an R / B inspection unit which checks the level of the R / B signal input from the / B pin and outputs a value indicating an operating state of the semiconductor under test.

The semiconductor test head apparatus may further include a level voltage supply unit supplying a level signal required by the semiconductor under test; To transmit a level signal input from the level voltage supply unit to the semiconductor under test, and apply a level signal to the translator and the semiconductor under test that transmit the R / B signal input from the semiconductor under test to the R / B inspection unit. It is preferable to further comprise a level driver for driving the translator.

In addition, the R / B inspection unit, the translator and the level driver preferably form one I / O channel.

In addition, the semiconductor test head device is preferably applied to the inspection of the NAND flash memory, the NOR flash memory and the PRAM.

In addition, the level voltage supply unit is preferably implemented as an operational amplifier.

According to the semiconductor test head apparatus of the present invention, by providing a separate R / B inspection unit for confirming the operation state of the DUT from the signal level output from the R / B pin of the DUT in place of the PE unit, the price by the number of configurations of the PE unit There is an effect that can lower the unit cost of the determined automatic test equipment (ATE).

In addition, the level driver and the R / B checker form one I / O channel, which reduces the number of I / O channels allocated to the NAND flash memory, thereby increasing the number of memories that can be simultaneously checked. It is effective. In other words, in the example described at the end of the above-mentioned [Background Art], since the conventional number of I / O channels allocated to the memory is nine, the number of memorys that can be checked at the same time is 96 and the remaining I / O channels which cannot be used by ATE This is 160. On the other hand, according to the present invention, since the number of I / O channels allocated to each memory is reduced by one, the ATE can simultaneously check 128 memories without the remaining I / O channels.

Hereinafter, a semiconductor test head device according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 and 5 are electrical circuit diagrams of a semiconductor test head device according to an embodiment of the present invention.

First, the semiconductor test head device of the present invention records the test pattern signal output from the ALPG 10 and the ALPG 10 generating the predetermined test pattern signal for the semiconductor test as shown in FIG. 2 to the DUT 50. A PE unit including a comparator 33 for comparing the readout signal of the test pattern read by the pattern driver 31 and the DUT 50 with a reference signal corresponding to the characteristics of the semiconductor and outputting a comparison value thereof; 30, an interface unit 70 for interfacing the control computer 5 and the test head 2 to control the semiconductor test system.

In addition, the semiconductor test head device of the present invention, as shown in Figures 4 and 5, by checking the level of the R / B signal input from the R / B pin of the DUT 50 to determine the operating state of the DUT 50 R / B inspection unit 120 for outputting a DUT state value LIO_IN, a level voltage supply unit 160 (see FIG. 5) for supplying a level signal VIH required by the DUT 50, and a level voltage supply unit 160. Transmitter 130 and DUT 50 which transmit the level signal VIH input from the DUT 50, and transmit the R / B signal input from the DUT 50 to the R / B inspection unit 120. Level driver 110 for driving the translator 130 to apply the level signal VIH, the first switching unit 140 for turning on / off the connection between the DUT 50 and the translator 130, and the DUT 50. DC measurement unit (hereinafter referred to as 'PMU') 150 for inspecting the DC power of the second power supply unit 150 and the second switching unit 170 for turning on / off the connection between the DUT 50 and the PMU 150 It can be made, including).

In the above-described configuration, the translator 130 determines the signal direction by the control signal LIO_DIR output from the control computer 5. For example, when the control signal LIO_DIR is high, the R / B signal input from the DUT 50 is bypassed to the R / B checker 120, while the control signal LIO_DIR is low. When the value is low, the level signal VIH output from the level voltage supply unit 160 is bypassed to the DUT 50 by the driving signal LIO_OUT input from the level driver 110.

Here, the operation in which the translator 130 bypasses the level signal VIH will be described in detail. When the driving signal LIO_OUT input from the level driver 110 has a high value, the level voltage supply unit 160 and the DUT ( The connection between 50 is established. At this time, the level voltage supply unit 160 adjusts the voltage level of the level signal VIH by the value of the input level control signal DAC_OUT to output to the DUT 50. At this time, the voltage of the level signal VIH may be between 1.65 and 5.5V.

In addition, the translator 130 may be implemented as "SN74LVC1T45" which is one of the commercialization models of the driver device. In addition, the level voltage supply unit 160 may be implemented as a general operational amplifier (OPAMP).

When the first switching unit 140 and the second switching unit 170 is turned on by the control computer 5, the other is turned off, that is, the level driving to the DUT 50 or the DUT 50 In the case of R / B checking), the connection between the translator 130 and the DUT 50 is established by the first switching unit 140, whereas the second switching is performed when the power test is performed for the DUT 50. The unit 170 establishes a connection between the PMU 150 and the DUT 50.

The PMU 150 is a device generally used for ATE, which applies a voltage to the DUT 50 and thereby measures the current output from the DUT 50 or applies the current to the DUT 50 and thereby the DUT 50. ) Is to measure the output voltage.

The R / B inspection unit 120 checks only a single predetermined level, which does not require a high level reference value (VOH) or a low level reference value (VOL), instead of the high-end window comparator configured in the existing I / O channel. It is desirable to implement a low level level detector.

Meanwhile, the semiconductor test head device of the present invention is preferably applied to the inspection of the NAND flash memory, the nor flash memory and the phase-change RAM (PRAM) in which the R / B pins are formed. The present invention can be applied to various memories for outputting an operation state without being limited thereto.

In addition, as the PE unit 30 forms one I / O channel, the R / B inspection unit 120, the translator 130, and the level driver 110 according to the present invention also have separate I / O channels. To form.

The semiconductor test head device of the present invention is not limited to the above-described embodiments, and may be variously modified and implemented within the range permitted by the technical idea of the present invention.

1 is a perspective view showing a conventional semiconductor test system,

2 is a schematic diagram schematically showing a conventional semiconductor test header device;

3 is an electrical circuit diagram showing a conventional semiconductor test head device in detail,

4 and 5 are electrical circuit diagrams of a semiconductor test head device according to an embodiment of the present invention.

*** Explanation of symbols for the main parts of the drawing ***

1: high fix board 2: test head

3: handler 5: control computer

10: ALPG 30: PE part

31: pattern driver 33: comparator

31a: impedance matching element 31b: time delay element

35: output current control unit 37: output voltage control unit

50: DUT 70: interface unit

120: R / B inspection unit 130: translator

140: first switching unit 150: DC inspection unit

160: level voltage supply unit 170: second switching unit

Claims (5)

A pattern driver for writing a pattern signal to the semiconductor under test and a comparator for comparing the read signal of the test pattern read by the semiconductor under test with a reference signal corresponding to the characteristic of the semiconductor under test and outputting a comparison value thereof. In a semiconductor test head device, A single I / O channel is formed separately from the comparator and the pattern driver, and the level of the R / B signal input from the R / B pin of the semiconductor under test is examined to indicate an operation state of the semiconductor under test. The semiconductor test head device further comprises an R / B inspection unit for outputting a value. The method of claim 1, A level voltage supply unit supplying a level signal required by the semiconductor under test; A translator which transfers a level signal input from the level voltage supply unit to the semiconductor under test and delivers an R / B signal input from the semiconductor under test to the R / B inspection unit; And a level driver for driving the translator to apply a level signal to the semiconductor under test. The method of claim 2, And the R / B inspection unit, the translator, and the level driver form one I / O channel. The method of claim 3, wherein A semiconductor test head device, which is applied to inspection of NAND flash memory, NOR flash memory, or PRAM. The method according to claim 3 or 4, And the level voltage supply unit is implemented as an operational amplifier.

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