KR20030046801A - Parallel logic devices/circuits tester for plural logic devices/circuits and parallel memory chip repairing apparatus - Google Patents

Abstract

PURPOSE: A parallel logic circuit test unit for testing plural logic circuits and an apparatus for mending a parallel memory IC are provided to test a DUT(Device Under Test) within a short time by using a comparison device. CONSTITUTION: A test unit includes a central control portion(10) and one or more test blocks(20) in order to test operating states of DUTs(201b-203b,201c-203c) by comparing reference devices(201a-203a) with the DUTs. The central control portion generates signals applied to the reference device and the DUT and determines the operating state of the DUT by using a compared result of a data signal of the reference device and a data signal of the DUT. The test block is used for comparing a data signal of the reference device with a data signal of the DUT according to a signal of the central control portion and outputting the compared result to the central control portion.

Description

Parallel logic circuit test apparatus and parallel memory IC repair apparatus for testing a plurality of logic circuits in real time {parallel logic devices / circuits tester for plural logic devices / circuits and parallel memory chip repairing apparatus}

The present invention relates to a logic circuit test apparatus and a memory IC repair apparatus for real-time testing whether a device and a logic circuit including the device are defective. DUT test boards having the same circuit configuration as the device under test (DUT) or the reference PCB (Printed Circuit Board) and the reference PCB are arranged in parallel to provide the same input signal to the reference device and the device under test or the reference PCB and the DUT test board. It is operated by applying and comparing the signal output from the reference device and the device under test or the signal output from the reference PCB and the DUT test board by using the hardware-configured comparison means. The present invention relates to a parallel logic circuit tester that can determine whether a device operates normally on a PCB. In addition, when the device to be inspected is a memory IC, the present invention relates to a memory IC repair apparatus capable of accurately identifying and repairing a defective position of the memory IC using the comparison result of the above-described comparison means.

In general, a test for failure of logic circuits such as a semiconductor chip or a semiconductor chip module is a final process of determining whether a device is defective after completion of a product, and a logic circuit test apparatus capable of inspecting a large amount of devices efficiently and quickly is provided. It is requested.

1 is a block diagram of a conventional logic circuit test apparatus for testing a logic circuit such as a semiconductor chip.

The central inspection unit 100 inspects each inspection through an address line (A), a control line (C), and a data input / output (I / O) line (D) connected to the sockets 201a, 201b, and 201c of the handler 200. Address signals, control signals, and data signals applied to the target elements 202a, 202b, and 202c are generated. That is, the central inspection unit 100 controls the operation of the inspection target elements 202a, 202b, and 202c with the control signal in the write mode, and designates specific positions of the inspection target elements 202a, 202b, and 202c with the address signal. Record the data at that location. In addition, the central inspection unit 10 also controls the operation of the inspection target elements 202a, 202b, and 202c with the control signal in the read mode, and designates specific positions of the inspection target elements 202a, 202b, and 202c with the address signal. Read data to the location. The central inspection unit 100 predicts the data signal generated by the central inspection unit 100 and thus applied to the respective inspection target elements 202a, 202b, and 202c. It is determined whether or not the inspection target elements 202a, 202b, and 202c are defective by comparison with the result value.

The conventional logic circuit test apparatus receives data signals from all the inspection target elements 202a, 202b, and 202c in the central inspection unit 100 and generates them and applies them to the inspection target elements 202a, 202b, and 202c. The expected result of the data signal is compared with each other in software. In addition, although the address signal and the control signal between the central inspection unit 100 and the test block 200 can be shared, the data I / O lines cannot be shared, so that data I / O lines corresponding to each inspection target element have a one-to-one correspondence. This is necessary.

At this time, the test process for the elements to be inspected (202a, 202b, 202c) in the central inspection unit 100 is made independently for each inspection element. That is, since data signals are transmitted through different I / O lines, each data signal is independent of other data signals. Therefore, the test for the entire inspection target element does not end at the same time, and as the number of inspection target elements increases, the overall test time becomes longer. In addition, since the data signal comparison process is performed for each inspection target element by software in the central inspection unit 100, as the number of elements to be inspected increases, the operation of the central inspection unit 100 takes more load. Thus, for stable operation of the test apparatus, it is necessary to use an expensive processor capable of high speed processing. In addition, the data I / O line is an expensive device capable of transmitting signals at high speed, and thus, a test device for testing a large number of inspection target devices has a burden of manufacturing cost increase due to an increase in expensive data lines. do. As described above, in the conventional test apparatus, as the number of devices to be inspected increases, there are many economic and physical restrictions in proportion thereto.

In addition, in the conventional test apparatus, since the output signal from the test block is a data signal of each inspection target device, the output signal can only be used for a simple test of the inspection target device.

Some test devices test the blocks in sequential order in order to save the time to load the device under test into the handler's socket. However, since the test time is longer than the loading time, this test is not effective except to increase the efficiency of the test block.

Accordingly, an object of the present invention for solving the above problems is to arrange in parallel a test board having the same circuit configuration as a reference device and a plurality of inspection target elements or a reference PCB and a reference PCB in parallel under the same conditions. It operates by applying the same input signal to the device or reference PCB and test board, and compares the signal output from the reference device and the inspection target device or the signal output from the reference PCB and the test board using a hardware constructed comparison means. The present invention provides a parallel logic circuit test apparatus capable of determining whether a plurality of inspection target devices are defective or whether the inspection target devices operate normally on a PCB. In addition, when the device to be inspected is a memory IC, the waveform of the defective cell of the device to be inspected can be easily observed and repaired using the comparison result from the aforementioned comparison means corresponding to the device to be inspected as defective. To provide a repair device.

1 is a block diagram of a conventional logic circuit test apparatus for testing a logic circuit such as a semiconductor chip;

2 is an overall block diagram of a logic circuit test apparatus according to a first embodiment of the present invention;

3 is a block diagram of a comparison test unit of FIG. 2, FIG.

4A and 4B are timing diagrams of a data signal from a reference element and a data signal from an element to be inspected in the comparison inspection unit;

5 is an overall block diagram of a logic circuit test apparatus according to a second embodiment of the present invention;

6 is a block diagram of the repair apparatus of the present invention;

7 is a view briefly illustrating a test of a memory IC on a wafer using a wafer probe header equipped with a wafer tester probe block;

* Explanation of symbols for main parts of the drawings

10: central inspection unit 20: the first test block

21a, 22a, 23a: Standard socket

21b, 21c, 22b, 22c, 23b, 23c: DUT socket

24, 25: bus driver 26: first delay means

201a, 202a, 203a: reference element

201b, 201c, 202b, 202c, 203b, and 203c: device under test (DUT)

231a to 231d: comparators 232a to 232d: switch section

233: logic elements 234a to 234d: second delay means

30: 2nd test block 31a, 32a, 33a: PCB socket

301a, 302a, 303a: reference PCB

31b, 31c, 32b, 32c, 33b, 33c: DUT test board

40: wafer tester probe block

41b, 41c, 42b, 42c, 43b, 43c: probe set

401b, 401c, 402b, 402c, 403b, 403c: probe

50: repair part 60: wafer probe header

70: wafer

C00, C10, C01, C11, C02, C12: comparative inspection

The parallel logic circuit test apparatus of the present invention for achieving the above object is loaded with a reference element and a plurality of inspection target elements (hereinafter referred to as "DUT") in parallel, under the same conditions and a plurality of inspection targets The same signal is input to the device, and the data signal from the reference device and the data signal from the device to be inspected are compared with each other by using a hardware constructed comparison means. Test whether in real time.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 shows an overall block diagram of a logic circuit test apparatus according to a first embodiment of the present invention.

The central inspection unit 10 generates an address signal, a control signal, and a data signal for testing whether the DUT, such as a digital IC or a digital circuit module, is defective and generates the address line (A), the control line (C), and the data line ( Output via D0, D2,…). The central inspection unit 10 receives the comparison signals R00, R02, ..., R10, R12, ..., ... from the first test block 20, which will be described later, to determine whether each DUT is defective and is determined to be defective. Find out the defective location of the DUT. These comparison signals are data signals from one or more reference elements 201a, 202a, 203a, ... and DUTs 201b, 201c, ..., 202b, 202c, ... connected in parallel with each reference element in one or multiple rows. , 203b, 203c, ..., ... are the signals obtained by comparing the data signals, respectively, which will be described later in detail.

The first test block 20 has reference elements 201a, 202a, 203a, ... and DUTs 201b, 201c, ..., 202b, 202c, ..., 203b, 203c, ..., ... respectively loaded and electrically connected thereto. A plurality of sockets 21a, 21b, 21c ..., 22a, 22b, 22c ..., 23a, 23b, 23c ..., ... are installed. Each of the sockets 21a, 22a, 23a, hereinafter referred to as " reference sockets " loaded with the reference elements 201a, 202a, and 203a ... are referred to as DUTs 201b, 201c, ..., 202b, 202c, ..., 203b, 203c. ..., ..., ... are respectively installed in parallel with the loaded sockets 21b, 21c, ..., 22b, 22c, ..., 23b, 23c, ...: hereinafter referred to as "DUT socket". That is, the reference socket 21a and the DUT sockets 21b, 21c, ... form one parallel set, and the reference socket 22a and the DUT sockets 22b, 22c, ... form another parallel set, The reference socket 23a and the DUT sockets 23b, 23c, ... form another parallel set. Each parallel set may be independently configured such that a plurality of parallel sets may be formed as one test block or may be separated and combined, respectively, as shown in FIG. 2. In each of the DUT sockets 21b, 21c, ..., 22b, 22c, ..., 23b, 23c, ..., ..., the comparison inspection unit C00, C10, ..., C01, C11, ..., C02, C12, ..., ...) Are respectively installed correspondingly.

The circuit pattern of the first test block 20 is configured such that the same signals are applied to one reference socket 21a and a plurality of DUT sockets 21b, 21c, ... installed in parallel thereto. In this case, the same signal means not only having the same data value but also one signal output from the same data terminal of the central inspection unit 10. That is, as shown in FIG. 2, data is stored in the parallel sets 21a, 21b, 21c, ... by using the data line D'0 branched from the data line D0 connected between the central inspection unit 10 and the reference socket 21a. Apply the signal at the same time. The same signal is applied to each of the parallel sets to the other parallel sets 22a, 22b, 22c... 23a, 23b, 23c...

Each of the comparison inspection units C00, C10, ..., C01, C11, ..., C02, C12, ..., ... is provided with data signals output from the respective reference elements 201a, 202a, 203a, ..., and each DUT 201b, 201c, ..., 202b, 202c, ..., 203b, 203c, ..., ... are compared, and the result is output as a 1-bit signal for each DUT. 3 is a block diagram of the comparison inspection unit C00. Other comparative inspection units C01, C02, ..., C10, C11, ... of the present invention all have the same structure and function. Therefore, the present invention will be described below with one comparison inspection unit C00, a corresponding reference element 201a, and a DUT 201b.

The comparison inspection unit C00 performs a logical sum or logical product operation with the switch units 232a to 232d and the comparators 231a to 231d of the data lines as many as the number of bits of the data line (in the embodiment of the present invention). Consisting of a logic element 233. The switch sections 232a to 232d are turned on in the write mode so that the data signal from the central inspection unit 10 is applied to the DUT 201b, and turned off in the read mode to turn off the data signal from the reference element 201a and the DUT 201b. Are applied to the comparators 231a to 231d, respectively. Comparators 231a to 231d compare the two input data signals. The logic element 233 logically sums or logically multiplies the data output from the comparators 231a to 231d and outputs a one-bit signal R00 to the central inspection unit 10. By the way, the switch sections 232a to 232d cause a delay in the progress of data. Therefore, a means is needed to compensate for this. The second delay means described below plays this role.

The bus driver 24 is a means for preventing a decrease in processing speed due to an increase in load (mainly capacitance) of each signal line of the central inspection unit 10 generated during parallel inspection. The connected DUTs 201b, 201c, ..., 202b , 202c, ..., 203b, 203c, ..., ... decrease the capacitance for each signal line. A buffer or flip-flop F / F may be used as the capacitance reducing means 24. Without such capacitive reduction means 24, as the number of DUTs increases, the total capacitance value of the DUTs increases, resulting in a problem that the drive capability of the system is degraded. However, the capacitance reduction means 24 causes the control signal and the address signal to be delayed for a predetermined time. In order to compensate for the delay of the signal, the bus driver 25 causes the data lines D '0, D' 2,... Install on At this time, the bus drivers 24 and 25 are made of the same element.

The first delay means 26 is provided on the address line A and the control line C in order to compensate for the delay of the data signal by the switch sections 232a to 232d in the write mode, so as to address the delay time of the data signal. Delay the signal and the control signal. However, the use of the second delay means 26 delays the data signal from the DUT 201b in the read mode and is not synchronized with the data signal from the reference device 201a. Thus, the two data signals can be compared as shown in FIG. 4A. The problem of shortening of time occurs. In order to solve this problem, it is necessary to delay the data signal from the reference element 201a applied to each of the comparators 231a to 231d by the delay time by the second delay element 26, and the second delay means 234a. 234d) performs this function. The first delay means 26 and the second delay means 234a to 234d may be omitted in the low speed tester, and may be implemented by other means such as clock adjustment by a PLL or the like.

The operation of the logic circuit test apparatus of the present invention will be described as a whole.

Since the functions of the reference elements, the DUTs, and the comparison inspection unit are the same, one parallel set 201a, 201b, 201c, ... is used for convenience of description, in particular, the DUT 201b, the corresponding reference element 201a, and the comparison inspection unit C00. ) And the operation of the corresponding data lines D0, D'0, and D''0.

When the control signal is in the write mode, the data signal generated by the central inspection unit 10 is applied to the reference element 201a loaded in the reference socket 21a through the data line D0, and simultaneously with the reference element 201a. It is applied to the DUTs 201b, 201c, ... that are connected in parallel, and is written to the position designated by the address signal. Next, when the control signal is in the read mode, the switch sections 232a to 232d are turned off so that the data signals from the reference element 201a and the DUT 201b are respectively the data line D'0 and the data line D '. '0) is applied to the comparison inspection unit C00. The two data signals applied to the comparison test unit C00 are compared for each bit in the comparators 231a to 231d and the comparison result is output to the logic element 233. The logic element 233 logically sums or logically multiplies the output signals from the comparators 231a to 231d and outputs a one-bit signal R00 to the central inspection unit 10. The central inspection unit 10 determines whether or not the DUT 201b is defective by using the received signal R00, and in particular, it is possible to know exactly where the defect is located at which address. However, a problem occurs that the data signal applied to the DUT 201b in the write mode is delayed for a predetermined time by the switch units 232a to 232d. In order to solve this problem, an address signal and a control signal applied to the DUT 201b must be delayed by a delay time by the switch units 232a to 232d. Accordingly, as shown in FIG. 2, the first delay means 26 is provided on the address line A and the control line C connected to the DUT 201b. As such delay means, a buffered driver is used. However, the first delay means 26 delays the control signal and the address signal applied to the DUT 201b even in the read mode so that the data signal from the DUT 201b is delayed and applied to the comparison check unit C00. This causes a problem that the comparable time between the data signal from the reference element 201a and the data signal from the DUT 201b is shortened as shown in FIG. 4A. In order to solve this problem, the data signal applied from the reference element 201a to the comparison inspection unit C00 in the read mode should be delayed by the delay time by the first delay means 26. To this end, as shown in FIG. 3, the second delay means equal to the first delay means 26 on the terminal into which the data signal from the reference element 201a is input in the read mode among the two input terminals of the comparators 231a to 231d. 234a-234d are provided. That is, these second delay means 234a to 234d are not used in the write mode but delay the data signal only in the read mode. Fig. 4 shows that the use of the second delay means 234a to 234d makes the two data signals synchronized so that the comparable time becomes longer.

5 is a block diagram of a logic circuit test apparatus according to a second embodiment of the present invention.

Some DUTs do not operate normally when they are mounted on a specific printed circuit board (PCB) such as normal or memory modules. The test apparatus of FIG. 5 is for judging whether the DUT is normally mounted on a specific PCB.

The second test block 30 includes the first test block 20, the reference sockets 21a, 22a, 23a, ..., and the DUT sockets 21b, 21c, ..., 22b, 22c, ..., 23b, 23c, ..., ... ) Function is different. That is, the PCB sockets 31a, 32a, 33a, ... that can load the reference PCBs 301a, 302a, 303a, ..., which are good PCBs, instead of the reference sockets 21a, 22a, 23a, ... of FIG. Is installed. And, instead of the DUT sockets 21b, 21c, 22b, 22c, 23b, and 23c of FIG. 2, the DUT test boards 31b, 31c, ..., 32b, 32c, ..., 33b, 33c, ... are PCB sockets 31a, 32a, 33a, ...) in parallel. The DUT test boards 31b, 31c, ..., 32b, 32c, ..., 33b, 33c, ... are referred to when the DUTs 201b, 201c, ..., 202b, 202c, ..., 203b, 203c, ..., ... are loaded, respectively. It has the same circuit configuration as the PCB. Therefore, the DUT test boards 31b, 31c, loaded with data from the reference PCBs 301a, 302a, 303a, ..., and the DUTs 201b, 201c, ..., 202b, 202c, ..., 203b, 203c, ..., ... Comparing the data from…, 32b, 32c,…, 33b, 33c,…, the DUTs 201b, 201c,…, 202b, 202c,…, 203b, 203c,…,… are normally available on any particular circuit PCB. It can be judged whether or not it works without actually assembling it.

FIG. 6 illustrates output signals R00, R01, R02, ..., R10 from the comparison test units C00, C01, C02, ... C10, C11, C12, ..., ... of FIG. 2 when the DUT is a memory IC in FIG. Is a block diagram of a repair apparatus for finding and repairing defective cells of each IC on a wafer using R11, R12, ..., ..., and FIG. 7 is a test of memory ICs on a wafer using a wafer probe header. It is a drawing briefly showing how.

The wafer tester probe block 40 includes one or more probe sets 41b, 41c, ..., 42b, 42c, ..., 43b, 43c, ..., ... that can test a plurality of memory ICs on the wafer 70, respectively. And comparison inspection units C00, C10, ..., C01, C11, ..., C02, C12, ..., ... corresponding to one to one, and are mounted on the wafer probe head 60 and used. At this time, the plurality of probe sets 41b, 41c, ..., 42b, 42c, ..., 43b, 43c, ..., ... is loaded with reference elements 201a, 202a, 203a, ... as shown in FIGS. The reference sockets 201a, 201b, 201c, ... are connected in parallel. That is, during the wafer test, when the probes 401b, 401c, ..., 402b, 402c, ..., 403b, 403c, ..., ... are electrically connected to the terminals of each memory IC on the wafer, each probe set 41b, 41c , ..., 42b, 42c, ..., 43b, 43c, ..., ...) perform the same function as the plurality of sockets loaded with the DUTs in the first test block 20 of FIG. 2. Also, in Fig. 6, the sockets 201a, 201b, 201c, ... into which the reference elements are loaded are replaced with PCB sockets into which a good quality PCB can be loaded, and the probe sets 41b, 41c, ..., 42b, 42c, ..., 43b. , 43c, ..., ... have the same circuit configuration as that of the reference PCB, as in the second embodiment described above, it is possible to determine whether or not the memory IC operates normally on which specific PCB as well as whether the memory IC is defective.

The repair unit 50 repairs a defective cell by replacing a defective cell of the memory IC with an extra cell in the corresponding memory IC, and repairing the defective cell is the same as that of a conventional repair apparatus. In the case of the invention, the output signal R00, R01, ..., R10, R11, ..., ... is easily received from the comparison inspection unit C00, C10, ..., C01, C11, ..., C02, C12, ..., ... It is characterized by the ability to locate and repair cells.

FIG. 6 illustrates an embodiment in which a plurality of probe sets are provided to test and repair a plurality of memory ICs at the same time. However, it is obvious that one probe set may be used.

In addition, the user inputs a test result signal (R00, R01, ..., R10, R11, ..., ...) and inputs the defect type for the defective cell by inputting it to a measuring instrument (waveform analyzer) such as an oscilloscope or a logic analyzer as a source. You can judge. In addition to determining whether there are any defects by simply comparing data values, such as memory ICs, when testing ASICs, it is necessary to determine the type of defects as well as the determination of defects. Therefore, in this case, it is very useful to analyze the output data of the comparison inspection unit C00, C10, ..., C01, C11, ..., C02, C12, ..., ... with a measuring instrument to determine the type of defective cells.

As described above, the present invention is configured in such a way that the same signal can be applied to a plurality of DUTs connected in parallel with the reference element, and furthermore, by comparing the data values of the reference element and the DUT using a hardware comparison comparison unit It is possible to determine whether or not a plurality of DUT failure. In addition, the output signal of the comparison inspection unit can be applied to a repair apparatus that can identify the type of defective cells as well as whether the DUT is defective or to easily repair the defective cells.

Claims (12)

A test apparatus for determining whether a plurality of inspected elements are defective by comparing a non-defective element with a plurality of inspected elements as a reference element. Generating signals applied to the reference element and the plurality of inspected elements for testing the inspected elements, and comparing the data signals from the reference element with data signals from the plurality of inspected elements A central controller which determines whether or not the respective inspection target elements are defective; And The reference element and the plurality of inspection target elements are electrically loaded in parallel, and the data signals output from the reference element and the data signals output from the respective inspection target elements in one-to-one correspond to the signals applied from the central controller. And at least one test block for comparing the corresponding results and outputting the comparison result to the central controller. The parallel logic circuit test apparatus according to claim 1, wherein the central controller detects a defective position of the inspection target element determined to be defective and outputs an address of the defective position. The parallel logic circuit of claim 1, wherein the test block branches the data signal applied from the central controller and applies the same to the reference element and the plurality of inspection target elements loaded in the test block. Testing device. The method of claim 1, wherein the test block is A plurality of sockets to which the reference element and the plurality of inspection target elements are loaded and electrically connected; A comparison inspecting unit installed in the sockets to which the inspection target elements are loaded in a one-to-one correspondence, and comparing a data signal output from a corresponding inspection object element with a data signal output from the reference element to output a comparison result; And And a circuit pattern for simultaneously applying the data signal from the central control unit to the reference element and the plurality of inspection target elements and applying the output signal of the comparison inspection unit to the central control unit. Testing device. 5. The parallel logic circuit test apparatus according to claim 4, further comprising a measuring unit for outputting a waveform for a defective position of a defective inspection target element by using the output signal from the comparison inspection unit as a trigger signal. The method of claim 4 or 5, wherein the comparison inspection unit A switch unit which turns on the data lines connected to the respective inspection target elements in a write mode and off in a read mode; A comparator for comparing a data signal from the reference element with a data signal from the inspection target element in a read mode and outputting a comparison result; And And a logic element for ORing the output signal of the comparator and outputting the result. 7. The method of claim 6, further comprising delaying a control signal and an address signal applied to the inspected element by a delay time by the switch unit to compensate for a time delay of the data signal applied to the inspected element by the switch unit. First delay means for; And In order to compensate for the delay of the data signal output from the inspection target device by the first delay means and applied to the comparator in a read mode, the data signal output from the reference device and applied to the comparator is the first delay time. Parallel logic circuit test apparatus further comprises a second delay means for delaying by. 8. The parallel logic circuit test apparatus according to claim 7, wherein the first and second delay means are buffered drivers. In a test apparatus for determining whether a proven good PCB (Printed Circuit Board) as a reference PCB and whether or not the normal operation when the device under test (DUT) is used in a PCB having the same circuit configuration as the reference PCB, A PCB socket into which the reference PCB is loaded; A plurality of DUT test boards having the same circuit configuration as that of the reference PCB when the inspection target device is loaded and connected to the PCB socket in parallel and the inspection device is loaded; A comparison inspection unit which is installed in a one-to-one correspondence to the DUT test board, and compares the data signal from the PCB socket with the data signal from the DUT test board loaded with the inspection target element and outputs a comparison result; Generates a signal applied to the reference PCB and the test target device test board for testing the test target device, and receives a comparison result from the comparison tester, and when the test target device is assembled to the PCB, whether or not it normally operates. Central control unit for determining; And And a circuit pattern for simultaneously applying a data signal from the central controller to the reference PCB and the plurality of test boards and for applying an output signal of the comparison tester to the central controller. A memory IC test and repair apparatus for determining whether a memory IC is defective and repairing a defective cell by comparing a data signal of a memory IC on a wafer with the reference memory IC as a good device, Whether the memory IC is defective by generating signals applied to the reference device and the plurality of memory ICs for testing the memory IC and receiving a data signal comparison result between the reference device and the plurality of memory ICs. Central control unit for determining; A reference element block into which the at least one reference element is loaded; And It is mounted on a wafer probe head and transmits signals from the central controller to each memory IC and receives data signals from each memory IC to compare data signals from the reference device with data signals from each memory IC. Memory IC parallel test and repair device comprising a wafer test probe block for outputting a comparison result. The memory of claim 10, further comprising a repair unit configured to repair the bad memory IC by receiving a comparison result from the wafer test probe block and replacing the bad cell of the bad memory IC with an extra cell of the bad memory IC. IC parallel testing and repair. The method of claim 10 or 11, wherein the wafer test probe block is At least one probe set electrically connected in parallel with the reference element and electrically connected to each of the memory ICs to transmit signals from the central controller to each of the memory ICs and to output data signals from the memory ICs ; At least one comparison inspection unit installed in the probe set in a one-to-one correspondence and comparing a data signal from a corresponding memory IC with a data signal from the reference device connected in parallel with the memory IC and outputting a comparison result; And And a circuit pattern for simultaneously applying the data signal from the central controller to the reference device and the probe set connected in parallel with the reference device, and outputting the output signal of the comparison tester to the outside. Parallel test and repair.