KR100697776B1 - Semiconductor test apparatus - Google Patents

Abstract

The present invention provides a control unit for generating a control signal, a reference semiconductor device that receives the control signal and outputs a reference result signal that is a comparison criterion, and a result signal for receiving and receiving the control signal, respectively, to determine whether there is a defect. A plurality of test target semiconductor elements each outputting and the control signal are applied to each of the plurality of test target semiconductor elements in parallel and outputted from each of the plurality of test target semiconductor elements and the reference result signal to be compared The present invention relates to a semiconductor test apparatus including test logic for testing whether each of the test target semiconductor devices is defective.

According to the present invention, when a test is performed with a conventional semiconductor test apparatus for testing a semiconductor chip or a semiconductor module used in an existing high speed operation system, a test error may not occur because a high speed synchronization signal may not be generated. It can be used in a mounting system in response to a high speed synchronization signal, and it can reduce manufacturing cost, management and maintenance cost, is highly scalable, and can test multiple semiconductor chips or semiconductor modules at the same time. In addition, instead of testing a semiconductor chip or a semiconductor module by converting it into a separate low-speed signal, a test may be performed by applying a high-speed synchronization signal to a plurality of semiconductor chips in real time.

Semiconductor chips, modules, test devices, tester logic, mounting systems, test extension logic, control signals, instructions

Description

Semiconductor Test Equipment {SEMICONDUCTOR TEST APPARATUS}

1A to 1B are schematic diagrams of a semiconductor test apparatus according to the prior art.

2 is a configuration diagram of a semiconductor test apparatus according to a first embodiment of the present invention.

3 is a configuration diagram of test logic of the semiconductor test apparatus according to the first embodiment of the present invention.

4 is a timing diagram of a semiconductor test apparatus according to a first embodiment of the present invention.

5 is a configuration diagram of a semiconductor test apparatus according to a second embodiment of the present invention.

6 is a configuration diagram of test extension logic in the semiconductor test apparatus according to the second embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

20b: relay 60: semiconductor test device

60b: data comparison processing stage 70: semiconductor chip

80: signal generator 110: signal generator

120: good semiconductor chip 130: semiconductor chip

140: buffer 150: relay

160: comparator 210: control unit

220: reference semiconductor device 230: test target semiconductor device

240: test logic 250: test expansion logic

310: PLL 320: Clock Synchronous Transmitter

330: command reading unit 340: address register

350: CA synchronous transmission unit 360: data register array

365: data register 370: data synchronization transceiver

380: data comparator 390: communication interface

395: external server 610: PLL

620: clock synchronization transmitter 630: CA register

640: CA synchronous transmission unit 650: data register

660: data synchronization transmitter

The present invention relates to a semiconductor test apparatus, and more particularly, to test a semiconductor chip or a semiconductor module used in an existing high speed operation system, which can be used in a mounting system corresponding to a high speed synchronization signal, The present invention relates to a semiconductor test apparatus that can reduce management and maintenance costs, is highly scalable, and can test multiple semiconductor chips or semiconductor modules at the same time.

In general, a test of a semiconductor chip is a final process of determining good quality after completion of a product, and a semiconductor test apparatus capable of efficiently testing a large amount of products has been developed and used.

FIG. 1A is a diagram illustrating an example of a semiconductor test apparatus according to the prior art, and is a semiconductor using a master-slave method, filed on November 18, 2000 and registered on October 16, 2002, by Memory & Testing Co., Ltd. It is a figure disclosed by the patent registration number 10-0358919 of the chip inspection apparatus.

As shown, the Patent Registration No. 10-0358919 discloses a configuration for driving a signal using a buffer 90a or 90b.

That is, by using the buffers 90a and 90b, the capacitance value of the entire semiconductor test apparatus 60 observed by the signal generator 80 is reduced to enable high-speed data comparison of a plurality of semiconductor chips or modules regardless of time delay. Disclosed is a configuration.

However, the structure of Patent Registration No. 10-0358919 is a separate data comparison processing stage 60b-1 to 60b-n and a relay 20b for each of the semiconductor chips 70b-1 to 70b-n to be tested. -1 to 20b-n), which is a waste of space in the configuration of the test apparatus, and among these separate data comparison processing stages 60b-1 to 60b-n and the relays 20b-1 to 20b-n. If any one fails, the data comparison processing stage or relay must be replaced, which increases the cost of managing and maintaining the semiconductor test apparatus. Also, for each of the semiconductor chips 70b-1 to 70b-n under test, asynchronous elements such as data comparison processing stages 60b-1 to 60b-n and relays 20b-1 to 20b-n are added, for example, hundreds. Semiconductor chip tests using high-speed synchronization signals used in modern mounting systems ranging from MHz to several GHz are not practical.

1B is a view showing another example of a semiconductor test apparatus according to the prior art. As shown, the conventional semiconductor test apparatus is a good quality for comparison with the signal generator 110 for generating a signal such as a command or address signal (C / A), a data signal (D), a clock (CLK), etc. The semiconductor chip 120, the plurality of semiconductor chips 130a to 130x to be tested, the plurality of semiconductor chips 130a to 130x, the command or address signal C / A, the data signal D, and the clock ( A buffer 140 for transmitting the CLK and the like, and a chip output data signal transmitted from each of the semiconductor chips 130a to 130x or a data signal D transmitted to each of the semiconductor chips 130a to 130x. A plurality of relays (150a to 150x) for relaying the plurality of comparators (160a to 150x) and the chip output data relayed from the relays (150a to 150x) compared with the chip output data output from the good semiconductor chip 120 160x). The results R / x tested by the comparators 160a through 160x are then connected to the signal generator 110 or a component that processes the semiconductor test results so that each of the plurality of semiconductor chips 130a through 130x can be checked for defects. It is composed. Reference numeral R / x denotes x result signals R transmitted from the plurality of semiconductor chips 130a to 130x.

In the configuration of FIG. 1B, a conventional semiconductor test apparatus that does not use a buffer is generated by the signal generator 110 using the buffer 140 in order to solve a problem that an operation speed decreases when a plurality of semiconductor chips are connected. When the applied signal is applied to the semiconductor chip to be tested, the overall capacitance value of the load is lowered to improve the overall operation speed of the semiconductor test apparatus. However, as shown in this configuration, the buffer 140 and the semiconductor chips 130a to 130x to be tested are connected in a daisy chain form, and thus the configuration of the conventional semiconductor test apparatus disclosed in FIG. When a high speed signal is applied, an error is generated due to a severe reflection of the signal when the high speed signal is applied, thereby increasing the possibility of an error during semiconductor testing. In particular, semiconductor testing using the mounting system increases the likelihood of these errors.

Also, for each semiconductor chip 130a to 130x to be tested, the addition of asynchronous elements, such as relays 150a to 150x and comparators 160a to 160x, allows for high speed synchronization, such as those used in modern mounting systems ranging from hundreds of MHz to several GHz. Testing of semiconductor chips using signals becomes practically impossible. In addition, one relay 150a to 150x and one comparator 160a to 160x should be provided for each semiconductor chip 130a to 130x to be tested, thus making the manufacturing process complicated and costly, and also causing one relay or comparator to fail. I also need to replace the relay or comparator in each case, which increases the cost of managing and maintaining the semiconductor test device.

In addition, in the case of trying to test a plurality of semiconductor chips in one semiconductor test apparatus, the configuration disclosed in FIG. 1B has a disadvantage in that scalability is deteriorated since the use of the high speed synchronization signal is practically impossible.

Therefore, there is a growing need for highly scalable semiconductor test devices that can be used in mounting systems in response to high-speed synchronization signals, reduce manufacturing costs, management and maintenance costs.

An object of the present invention is that when a test is performed with a conventional semiconductor test apparatus for testing a semiconductor chip or a semiconductor module used in an existing high speed operation system, a test error is not likely to occur due to a failure to respond to a high speed synchronization signal. Can be used in mounting systems to respond to high-speed synchronization signals, reduce manufacturing and management and maintenance costs, provide high scalability, test multiple semiconductor chips or semiconductor modules simultaneously, and The present invention provides a semiconductor test apparatus capable of testing a semiconductor chip or a semiconductor module by converting the signal into a signal and applying a high-speed synchronization signal to a plurality of semiconductor chips in real time.

In order to achieve the above technical problem, the present invention provides a control unit for generating a control signal, a reference semiconductor device for receiving the control signal from the control unit and outputting a reference result signal as a comparison criterion, and for determining whether or not A plurality of test target semiconductor devices each receiving a control signal and outputting a result signal to be compared with each other, and applying the control signal received from the controller to each of the plurality of test target semiconductor devices in parallel and And a test logic to test whether each of the test target semiconductor devices is defective by comparing the result signal to be compared with the reference result signal output from each of the semiconductor devices, wherein the test logic interprets the control signal to perform the command. Is the reference peninsula if Storing the reference result signal output from the multi-element device, transmitting a command or address (C / A) signal to the test target semiconductor device, and receiving a plurality of the result signal to be compared output from the plurality of test target semiconductor devices The semiconductor test apparatus is characterized in that the comparison with the reference result signal.

In the semiconductor test apparatus according to the present invention, the control signal preferably includes a command or address (C / A) signal, a data (D) signal, and a clock (CLK).

delete

In the semiconductor test apparatus according to the present invention, the test logic is configured to synchronously duplicate a PLL providing a reference clock based on the clock (CLK) signal transmitted from the controller, and the reference clock of the PLL. A clock synchronous transmission unit which transmits in parallel to the plurality of test target semiconductor devices, and the command signal transmitted from the control unit, analyzes the clock latencies (CL) and BL (Burst) in the address signal in the case of MRS (Mode Register Set). Length), and if the command is a read command, transmits the corresponding command or address (C / A) signal after one clock to the plurality of test target semiconductor devices and transmits the data (D) signal transmitted from the controller. Is blocked after the CL by the BL, and in the case of other commands, the command is transmitted to the plurality of semiconductor devices after one clock. The synchronous copying of the command reading unit, an address register storing the address signal transmitted from the control unit, and the command or address signal (C / A) transmitted from the command reading unit or the address register A CA synchronous transmission unit for transmitting in parallel to the semiconductor device under test, a data register array for storing the reference result signal transmitted from the reference semiconductor element and the data (D) signal transmitted from the control unit, and the command reading unit A plurality of comparisons transmitted from the plurality of test target semiconductor devices in parallel by synchronously replicating the data (D) signal transmitted from the data register array based on an instruction and transmitting the data D signals in parallel to the plurality of test target semiconductor devices A data synchronization transceiver for receiving a result signal to be generated; Stirrer preferably comprises an array comparing the reference signal and the result of the plurality of comparison result signals to be transmitted from the comparison data to determine whether the failure of the semiconductor device under test parts.

In the semiconductor test apparatus according to the present invention, the test logic may provide a communication interface between the data comparator and a server connected to the outside to transmit a result of determining whether the data comparator is defective to the external server. It is preferable to further include.

In the semiconductor test apparatus according to the present invention, the data register array preferably includes a plurality of data registers to store data corresponding to a time of CL + 2 CLK or more.

The present invention includes a control unit for generating a control signal, a reference semiconductor element receiving the control signal from the control unit and outputting a reference result signal as a comparison reference, and receiving and comparing the control signal to determine whether or not it is defective. A plurality of test target semiconductor devices each outputting a result signal and the control signal received from the control unit in parallel to each of the plurality of test target semiconductor devices and the comparison output from each of the plurality of test target semiconductor devices One or more test logics which test whether each of the test target semiconductor devices is defective by comparing a result signal to be compared with the reference result signal, and one which synchronously replicates the control signal and transmits the same to the one or more test logics in parallel. With more test extension logic It provides a conductive testing device.

In the semiconductor test apparatus according to the present invention, the control signal includes a command or address (C / A) signal, a data (D) signal, and a clock (CLK), and each of the one or more test extension logics is the above-mentioned. A PLL providing a reference clock based on the clock (CLK) signal transmitted from a control unit, a clock synchronous transmission unit synchronously replicating the reference clock of the PLL and transmitting the same to the one or more test logics in parallel; CA register for storing the command or address (C / A) signal transmitted from the control unit and the command or address (C / A) signal stored in the CA register synchronously replicated to the one or more test logic A CA synchronous transmission unit for transmitting in parallel, a data register for storing the data (D) signal transmitted from the control unit, and the data register Preferably it comprises the data (D) signals to be stored synchronously transmitting unit that transmits the motive CA in parallel to the at least one test logic to replicate.

EMBODIMENT OF THE INVENTION Hereinafter, the semiconductor test apparatus of this invention is demonstrated in detail with reference to drawings.

2 is a configuration diagram of a semiconductor test apparatus according to a first embodiment of the present invention.

As illustrated, the semiconductor test apparatus according to the first embodiment of the present invention includes a control unit 210, a reference semiconductor device 220, a test logic 240, and a plurality of test target semiconductor devices 230a to 230x. do.

The controller 210 transmits a control signal. The control signal may be a test signal generated from a device dedicated to semiconductor testing such as, for example, an automatic test equipment (ATE), but a mounting test device configured to perform testing of semiconductor devices at high speed in a mounting environment using a high speed mounting system. It is preferable that the control unit is a control signal actually used in the form of a command or address signal (C / A), a data signal (D), and a clock (CLK). Such a mounting test apparatus has an advantage that a test using a high speed synchronization signal is possible.

The reference semiconductor device 220 receives a control signal generated by the controller 210, for example, a command or address signal C / A, a data signal D, and a clock CLK, and internally receives a command or address signal ( C / A) and processing according to the data signal D to output the result. Since the result output from the reference semiconductor device 220 is compared with the result output from the test target semiconductor devices 230a to 230x, and thus becomes a criterion for determining whether the test target semiconductor devices 230a to 230x are defective. The result output from the reference semiconductor element 220 is referred to as a "reference result signal."

The plurality of test target semiconductor devices 230a to 230x are tested to determine whether they are defective, and likewise, a control signal such as a command or address signal C / A through the control unit 210 and the test logic 240, and The data signal D and the clock CLK are received, and the result is output by performing processing according to the command or address signal C / A and the data signal D. Since the result output from each of the plurality of test target semiconductor devices 230a through 230x is compared with the reference result signal, the result output from each of the plurality of test target semiconductor devices 230a through 230x is then referred to as a “comparative result signal”. It is called.

The semiconductor device 220 or the semiconductor device 230a to 230x to be tested may be, for example, a semiconductor chip or a semiconductor component, but may be, for example, a semiconductor module such as a memory module including a plurality of memory components. Therefore, the term "semiconductor device" in the present invention should be interpreted as a generic term for such a semiconductor chip, component or module.

The test logic 240 applies a control signal such as a command or address signal C / A, a data signal D, and a clock CLK to each of the plurality of test target semiconductor devices 230a to 230x in parallel. In addition, each of the plurality of test target semiconductor devices 230a to 230x is tested for defects by comparing the result signal to be compared with the reference result signal output from each of the plurality of test target semiconductor devices 230a to 230x.

The test logic 240 is designed to have a small input capacitance. Therefore, in the case of a mounting test apparatus configured to perform testing of a semiconductor device at a high speed in a mounting environment using a high speed mounting system, the input capacitance is insignificant when viewed from the side of the controller 210 or the reference semiconductor device 220. Alternatively, the influence on the operation of the semiconductor device 220 may be minimized. Therefore, in the case of the test apparatus using the mounting system, the controller 210 or the semiconductor device 220 may operate normally even if the test logic 240 is added to the original mounting configuration.

In addition, the test logic 240 applies a control signal to each of the plurality of test target semiconductor devices 230a to 230x in parallel. That is, in the case of the configuration disclosed in the conventional FIG. 1 or the Patent Registration No. 10-0358919, each of the test target semiconductor chips 130a to 130x or 70b-1 to 70b-n in a daisy chain form in the buffer 140 or 90b. In order to apply a command or address signal, a high-speed operation is impossible and an increase in the number of semiconductor chips under test in one buffer is practically impossible. Thus, a signal is applied to a plurality of semiconductor devices under test in parallel.

In more detail, the test logic 240 interprets a control signal including an instruction or address signal C / A, a data signal D, and a clock CLK, and is transmitted from the controller 210. If the command is not a read operation, all signals are transferred to the test target semiconductor devices 230a to 230x one clock later, and in the case of the read operation, the reference result signal output from the reference semiconductor device 220 is stored. In this case, a command or an address (C / A) is transmitted to the test target semiconductor devices 230a to 230x. Thereafter, when a result signal to be compared is output from the test target semiconductor devices 230a to 230x, it is compared with the stored reference result signal to determine whether each of the test target semiconductor devices 230a to 230x is defective.

3 is a block diagram of test logic of the semiconductor test apparatus according to the first embodiment of the present invention.

As shown, the test logic of the semiconductor test apparatus according to the first embodiment of the present invention includes a PLL 310, a clock synchronizing transmitter 320, an instruction reading unit 330, an address register 340, The CA synchronous transmission unit 350, the data register array 360, the data synchronous transmission and reception unit 370, and the data comparison unit 380 are included.

It may also be configured to further include a communication interface 390 to transmit test results to the external server 395.

A phase locked loop (PLL) 310 receives a clock (CLK) signal transmitted from the controller 310 and provides a reference clock that operates in synchronization with the reference signal. Since the PLL 310 is a conventionally known device, detailed description thereof will be omitted.

The clock synchronous transmitter 320 synchronously duplicates the reference clock provided from the PLL 310 and transmits the same in parallel to the plurality of test target semiconductor devices 230a to 230x. For example, a synchronous configuration such as a synchronous buffer may be used to transmit signals to the plurality of test target semiconductor devices 230a to 230x in parallel. That is, the clock is replicated using a plurality of synchronous buffers and transmitted in parallel to the plurality of test target semiconductor devices 230a to 230x.

The command reading unit 330 analyzes the input command and extracts parameter information including CL (Clock Latency) and BL (Burst Length) from the incoming address signal in the case of an MRS (Mode Register Set) command. In addition, the parameter information may be configured to include other information related to the operation of the semiconductor device.

In addition, if a normal command is transmitted instead of the initial system setting command, the command may be classified into, for example, a read command and other commands including a write command. In the case of other instructions, it is interpreted and transmitted to the test target semiconductor devices 230a through 230b one clock later. In the case of a read command, the test target semiconductor device is transmitted one clock after the corresponding address and the command (C / A) signal. The data D signal transmitted from 230a to 230b but transmitted from the control unit 310 is blocked by the command reading unit 330 for a period of time after the CL.

The address register 340 stores an address signal transmitted from the controller 210, and then transmits the address signal to the test target semiconductor devices 230a to 230x through the synchronous transmitter 350.

The CA synchronous transmission unit 350 synchronously replicates the command or address (C / A) signal transmitted from the command reading unit 330 or the address register 340 to the plurality of test target semiconductor devices 230a to 230x. Send in parallel. The CA synchronous transmitter 350 may be configured using a plurality of synchronous buffers in the same manner as the clock synchronous transmitter 320.

The data register array 360 stores the data D signal including the reference result signal transmitted from the reference semiconductor element 220 in the internal data registers 365a to 365n, and the data registers 365a to 365n of the data registers 365a to 365n. The number is provided to store data corresponding to a time of CL + 2CLK or more. That is, in the configuration as shown in FIG. 2, after the read command is transmitted from the test logic 240 to the test target semiconductor devices 230a to 230x, the result signal to be compared in the test target semiconductor devices 230a to 230x is transmitted after CL. Therefore, the results of the semiconductor devices 230a to 230x under test can be compared later by CL + 2CLK.

The data synchronization transmitter / receiver 370 synchronously duplicates the data D signal of the data register array 360 based on the instructions of the command readout unit 330 in parallel to the semiconductor devices 230a to 230x under test. And a signal transmitted from the semiconductor devices 230a to 230x under test, that is, a plurality of result signals to be compared. That is, the data synchronization transceiver 370 is an interface capable of transmitting and receiving data in both directions.

The data comparator 380 compares a reference result signal stored in the data register array 360 with a plurality of result signals to be transmitted from the test target semiconductor devices 230a to 230x through the data synchronization transceiver 370. Thus, whether the test target semiconductor devices 230a to 230x are normal or defective is tested.

In addition, the communication interface 390 provides a communication interface between the data comparator 380 and the external server 395, and transmits a test result such as normal or bad to the external server 395.

4 is a timing diagram of a semiconductor test apparatus according to a first embodiment of the present invention. In FIG. 4, it is assumed that CL = 1 CLK and BL = 2 CLK, and each symbol, for example, CA @ 220, represents a signal waveform of 220, that is, a reference semiconductor element 220, and D in 240 represents 240. FIG. That is, the signal waveform in the test logic 240 is shown.

As illustrated, in the case of a command except read, for example, a write command, when the command or address (C / A) signal is transmitted from the controller 210 to the reference semiconductor device 220, the reference semiconductor device ( Data write (DW1 to DW2) is executed in 220, a signal (Write) is transmitted to the test logic 240, and write is performed to each test target semiconductor device (230a to 230c) one clock later (DW1 to DW2). ). That is, after a write command is applied from the control unit 210 to the reference semiconductor device 220, writing or writing is performed one clock later, and writing to the test target semiconductor devices 230a to 230c is performed two clocks later.

In addition, in the case of a read command, when a read command (Read) is transmitted from the control unit 210 to the reference semiconductor device 220, data read is executed in the reference semiconductor device 220 one clock later (DR1 to DR2), and test logic A signal Read is transmitted at 240, and after one clock thereafter, data read from the reference semiconductor device 220, that is, the reference result signals DR1 to DR2, are transmitted and stored in the test logic 240. The data D1 to D2 are read from the target semiconductor devices 230a to 230c. After another clock, the reference result signals DR1 to DR2 are first read for comparison, and the result signals D1 to D2 to be compared are transmitted from the test target semiconductor devices 230a to 230c for comparison. That is, after the read command, after 2 CLK + CL, comparison of the result signal D1 to D2 to be compared with the reference result signals DR1 to DR2 is performed. Since FIG. 4 is BL = 2CLK, each data is transmitted by 2 CLK, but the timing diagram of FIG. 4 may be different depending on the value of BL or CL.

The semiconductor test apparatus according to the first embodiment of the present invention is a test apparatus configured to modify the system to test a large amount of the semiconductor element in order to test a semiconductor element such as a memory component, which is used in a conventional high speed system. It is preferable. To this end, the test logic 240 is additionally connected as a load in addition to the reference semiconductor device 220 serving as a load to the control unit 210 that controls a specific semiconductor device, that is, the reference semiconductor device 220 in a high-speed system. From the standpoint of 210, there is no influence other than a slight increase in load, so the operation on the original system is normally performed.

The tester logic 240 analyzes the control signals transmitted and received between the control unit 210 and the reference semiconductor device 220 and transmits the control signals to the plurality of test target semiconductor devices 230a to 230x and the test target semiconductor devices 230a to 230x. By comparing the signal output from the) is configured to determine whether or not.

Note that the test signal is using the high speed synchronous control signal generated in the actual system as it is, and the test logic 240 replicates the high speed synchronous control signal in parallel to the semiconductor devices 230a to 230x under test. It is a configuration to transmit.

 Therefore, the semiconductor test apparatus according to the first exemplary embodiment of the present invention removes buffers, relays, and comparators, which are conventional asynchronous configurations, and adjusts them to the system synchronization to test the semiconductor devices 230a to 230x to be tested in the test logic 240. The point-to-point architecture enables many high-speed semiconductor device tests, such as high-speed memory tests, to be performed.

In addition, the test logic 240 of the semiconductor test apparatus according to the first embodiment of the present invention is preferably connected to the test target semiconductor devices 230a to 230x in a one-to-one structure, but does not affect the operation of the test apparatus system. The command or address signal (C / A) output may be configured to be shared by a plurality of semiconductor devices under test. Such a configuration may increase the number of semiconductor devices testable by the test logic 240.

In addition, one of the important differences between the test logic 240 and the test target semiconductor elements 230a to 230x of the semiconductor test apparatus and the one-to-one structure using the buffer of the conventional semiconductor test apparatus according to the present invention is data ( D) The signal line is bidirectional. That is, from the standpoint of the semiconductor devices 230a to 230x to be tested, it appears that the controller 210 is connected to the controller 210.

In addition, in order to increase the number of semiconductor devices to be tested, test extension logic may be added in the first embodiment of the present invention shown in FIG. 2.

5 is a configuration diagram of a semiconductor test apparatus according to a second embodiment of the present invention.

As illustrated, the semiconductor test apparatus according to the second embodiment of the present invention includes a control unit 210, a reference semiconductor element 220, test logic 240 to 240 ′, and a plurality of test target semiconductor elements 230a to 230x. Or 230'a through 230'x, and test extension logic 250. The control unit 210, the reference semiconductor element 220, the test logic 240 to 240 ′, and the plurality of test target semiconductor elements 230a to 230x or 230'a to 230'x are the first embodiment of the present invention. Since it is the same as in the semiconductor test apparatus according to the example, detailed description thereof will be omitted.

The test extension logic 250 may be a control signal transmitted from the control unit 210, for example, a command signal or an address signal C / A, a data signal D, and a clock CLK. Are transmitted in parallel to the plurality of test logic 240 or 240 '.

That is, the test extension logic 250 is configured to apply a control signal to one or more test logics 240 or 240 'so that the number of semiconductor devices 230a to 230x or 230'a to 230'x to be tested is extended. It can be expanded in proportion to the number of test logic 240 or 240 ′ driven by the logic 250.

6 is a configuration diagram of test extension logic in a semiconductor test apparatus according to a second embodiment of the present invention.

As shown, the test extension logic 250 includes a PLL 610, a clock synchronous transmitter 620, a CA register 630, a CA synchronous transmitter 640, a data register 650, and data synchronization. And a transmission unit 660.

The PLL 610 receives a clock (CLK) signal transmitted from the controller 310 and provides a reference clock that operates in synchronization with the reference signal.

The clock synchronous transmitter 620 synchronously duplicates the reference clock provided from the PLL 610 and transmits the same to the plurality of test logic 240 or 240 ′ in parallel.

The CA register 630 stores an instruction or address (C / A) signal transmitted from the controller 210 based on the reference clock provided from the PLL 610.

The CA synchronous transmission unit 640 synchronously replicates an instruction or address (C / A) signal stored in the CA register 630 and transmits the same to a plurality of test logic 240 or 240 'in parallel.

The data register 650 stores the data D signal transmitted from the controller 210 based on the reference clock provided from the PLL 610.

The data synchronization transmitter 660 synchronously replicates the data D signal stored in the data register 650 and transmits the data D signal in parallel to the plurality of test logics 240 or 240 '.

In other words, unlike the test logic 240 or 240 ', the test extension logic 250 does not need a function such as comparing data or a function for interpreting an instruction, and merely tests the signal of the controller 210 with the test logic 240 or 240'. It acts as an interface to send).

In the timing diagram of the semiconductor test apparatus according to the second exemplary embodiment of the present invention, since the test extension logic 250 is inserted between the control unit 210 and the test logic 240, the test logic 240 is generally seen in the overall test system. Can be considered to be one clock later. That is, in the timing diagram of FIG. 4, the comparison between the result signals D1 to D2 to be compared with the reference result signals DR1 to DR2 is performed after 2 CLK + CL after the read command, but the semiconductor test apparatus according to the second embodiment of the present invention is performed. The timing diagram of FIG. 3 is omitted since only the point where the comparison of the reference signal (DR1 to DR2) with the result signal (D1 to D2) to be compared after 3 CLK + CL after the read command is performed.

In addition, in the second embodiment of the present invention, the test extension logic (not shown) may be disposed in the control unit 210 and the test extension logic 250. In this case, the number of semiconductor devices that can be simultaneously tested by the controller 210 may be increased exponentially.

Although the present invention has been described in detail, this is for illustrative purposes only, and the protection scope of the present invention is not limited thereto, and the protection scope of the present invention is defined through the description of the claims.

As described above, according to the present invention, when a test is performed with a conventional semiconductor test apparatus for testing a semiconductor chip or a semiconductor module used in an existing high speed operation system, a test error may not occur due to a failure to correspond to a high speed synchronization signal. By addressing high-probability shortcomings, it can be used in mounting systems in response to high-speed synchronization signals, reducing manufacturing and management and maintenance costs, providing high scalability, and simultaneously testing semiconductor chips or semiconductor modules. In addition, instead of testing a semiconductor chip or a semiconductor module by converting it into a separate low-speed signal, a test may be performed by applying a high-speed synchronization signal to a plurality of semiconductor chips in real time.

Claims (8)

A control unit for generating a control signal, A reference semiconductor device receiving the control signal from the controller and outputting a reference result signal as a comparison reference; A plurality of test target semiconductor devices each receiving the control signal and outputting a result signal to be compared to determine whether there is a defect; The test object is applied by applying the control signal received from the control unit to each of the plurality of test target semiconductor elements in parallel and comparing the result signal to be compared with the reference result signal output from each of the plurality of test target semiconductor devices. Test logic to test whether each semiconductor device is defective Including, but the test logic, When the command is a read command by interpreting the control signal, the reference result signal output from the reference semiconductor device is stored, and a command or address (C / A) signal is transmitted to the test target semiconductor device. And a plurality of the result signals to be compared which are output from the semiconductor device under test to be compared with the reference result signal. The method of claim 1, The control signal includes a command or address (C / A) signal, a data (D) signal and a clock (CLK). delete The method of claim 2, The test logic, A PLL providing a reference clock based on the clock (CLK) signal transmitted from the controller; A clock synchronous transmission unit for synchronously replicating the reference clock of the PLL and transmitting the same to the plurality of test target semiconductor devices in parallel; The command signal transmitted from the control unit is analyzed to extract parameters including CL (Clock Latency) and BL (Burst Length) from the address signal in the case of MRS (Mode Register Set), and if the command is a read command, the corresponding command or Transmits an address (C / A) signal after one clock to the plurality of test target semiconductor devices, and blocks the data (D) signal transmitted from the controller after the CL as much as the BL. A command reading unit for transmitting a command to the plurality of semiconductor devices; An address register for storing an address signal transmitted from the controller; A CA synchronous transmission unit for synchronously replicating the command or address signal (C / A) transmitted from the command reading unit or the address register to the plurality of test target semiconductor devices in parallel; A data register array configured to store the reference result signal transmitted from the reference semiconductor element and the data D signal transmitted from the controller; Based on the command of the command reading unit, the data (D) signal transmitted from the data register array is synchronously copied and transmitted in parallel to the plurality of test target semiconductor devices, and transmitted from the plurality of test target semiconductor devices. A data synchronization transceiver for receiving the plurality of result signals to be compared; A data comparator for determining whether the test target semiconductor device is defective by comparing the reference result signal transmitted from the data register array with the plurality of result signals to be compared. Semiconductor test apparatus comprising a. The method of claim 4, wherein The test logic, And a communication interface configured to provide a communication interface between the data comparator and an externally connected server to transmit a result of determining whether the data comparator is defective to the external server. The method of claim 4, wherein And the data register array includes a plurality of data registers to store data corresponding to a time of CL + 2 CLK or more. A control unit for generating a control signal, A reference semiconductor device receiving the control signal from the controller and outputting a reference result signal as a comparison reference; A plurality of test target semiconductor devices each receiving the control signal and outputting a result signal to be compared to determine whether there is a defect; The test target is applied by applying the control signal received from the controller to each of the plurality of test target semiconductor devices in parallel and comparing the result signal to be compared with the reference result signal output from each of the plurality of test target semiconductor devices. One or more test logics for testing each semiconductor device for failure; One or more test extension logic for synchronously replicating the control signal and transmitting in parallel to the one or more test logics Semiconductor test apparatus comprising a. The method of claim 7, wherein The control signal includes a command or address (C / A) signal, a data (D) signal, and a clock (CLK), Each of the one or more test extension logics, A PLL providing a reference clock based on the clock (CLK) signal transmitted from the controller; A clock synchronous transmission unit for synchronously replicating the reference clock of the PLL and transmitting the same to the one or more test logics in parallel; A CA register for storing the command or address (C / A) signal transmitted from the controller; A CA synchronous transmission unit for synchronously replicating the command or address (C / A) signal stored in the CA register and transmitting the same to the one or more test logics in parallel; A data register for storing the data (D) signal transmitted from the controller; CA synchronization transmitter for synchronously replicating the data (D) signal stored in the data register and transmitting in parallel to the one or more test logic Semiconductor test apparatus comprising a.

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