KR101020643B1 - wafer motherboard - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer motherboard for connecting a test head and a probe card in a wafer test system, and more particularly to a wafer motherboard having a redundant cell analysis function.

The wafer motherboard of the present invention is a wafer motherboard for connecting a test head and a probe card for a wafer test, wherein a signal for acquiring a read signal output by the wafer is obtained by a pattern signal output from the test head to the wafer. module; A comparator unit for comparing the read signal input from the signal acquisition module with a predetermined reference signal, and outputting cell information according to the comparison result, a storage unit for storing cell information output from the comparator unit; Including a spare cell analysis module configured to analyze the cell information stored in the storage unit to determine whether or not the memory is good, and if the memory is determined to be defective, including an analysis unit for determining whether or not repair is possible. Characterized in that made.

Wafer, test, repair, spare cell, memory, probe, probe

Description

Wafer motherboard with extra cell analysis

The present invention relates to a wafer motherboard for connecting a test head and a probe card in a wafer test system.

As is well known, a wafer state memory completed through a variety of processes goes through several stages of assembly and testing, resulting in a complete memory. The memory test can be divided into a wafer test performed in a wafer state before assembly and a package test performed in a package state after the assembly process.

In particular, the basic purpose of wafer testing is to detect bad dies and prevent them from connecting to subsequent processes prior to bringing the die into a package. And another important purpose is to repair faulty cells to improve yield. There are many cells in memory. For example, in the case of 1G DRAM, more than 100 million memory cells exist in one memory. If only one fault cell is found, the memory cannot be used. Therefore, a memory usually prepares a means for replacing a failed cell with a spare cell if a fault exists in some cells after making an extra cell at the time of design. The cell for replacing such a failed cell is called a redundant cell, and analyzing whether it is possible to replace all the failed cells with given spare cells is called redundant cell analysis. This is called repair.

1 and 2 are schematic and electrical block diagrams of a conventional wafer test system, respectively.

As shown in FIG. 1, a test head 20 is connected to a memory tester aka, a main frame 10 via a cable, on one side a wafer motherboard aka, a performance board. (performance board, 40) is installed.

The wafer motherboard 40 is interposed between the test head 20 and the probe card 50 to establish an electrical connection between the two. In addition, the wafer motherboard 40 is typically connected to the probe card 50 by a zero input force (ZIF) connection method.

A plurality of probes 51 are formed below the probe card 50 to directly contact pads on the wafer 60.

The probe station 30 is intended to move the wafer 60 in the desired direction and position to bring the probe 51 into contact with the pad of the wafer 60. That is, the probe station 30 is a device for automatically supplying the wafer 60 to the probe card 50, and handling the wafer to test the die by sequentially probing several dies.

As shown in FIG. 2, the configuration of the memory tester 10 includes information about an algorithm pattern generator 11, a system bus 12, and cells that generate a predetermined test pattern signal for wafer testing. Error catch ram (ECR) 14, a special purpose memory for storing, Redundant CPU 15, which performs redundant cell analysis by analyzing data stored in the ECR 14, and wafer test. It comprises a computer 13.

In addition, the configuration of the test head 20 is a TGFC (Timing &Formatting; 21) for combining and outputting a pattern signal and a timing signal input from the ALPG (11), wafer pattern signal output from the TGFC (21) A comparator for comparing the read signal of the test pattern read by the driver and the wafer 60 written in the 60 with the reference signal corresponding to the characteristic of the memory and outputting the comparison value to the ECR 14. and a pin electronic (PE) including a comparator, a programmable power supply (PPS) for powering the wafer, and a parametric measurement unit (PMU) for DC testing of the wafer.

According to the above configuration, the RCPU 15 analyzes the cell information stored in the ECR 14 to analyze whether the corresponding memory is good or bad. In addition, it is determined whether or not the memory with the defective cell can be repaired.

In general, since the memory is a large quantity of production and a lot of inspection time, several such as 512 memory is tested at the same time. This requires an ECR 14 with the same capacity as the memory being tested simultaneously. For example, in order to simultaneously test 512 DUTs having a device under test (DUT) of 64 Gbit and having this capacity, a massive ECR 14 of 32,748 Gbits (32 Tera bits) is required.

Meanwhile, as memory capacity continues to increase, the capacity of ECR required for wafer testing also increases. However, in the case of the conventional memory tester, since the capacity of the ECR is configured to be small, there is a problem in that the number of tests must be reduced at the same time in order to test a large memory. Of course, existing memory testers can be retrofitted, but doing so requires a significant cost.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a wafer motherboard having an extra cell analysis function in order to increase the number of memory that can be tested simultaneously without modifying the memory tester in a wafer test.

In order to achieve the above object, the wafer motherboard of the present invention is a wafer motherboard for connecting a test head and a probe card for a wafer test, wherein the reading is output by the wafer by a pattern signal output from the test head to the wafer. A signal acquisition module for obtaining a signal; A comparator unit for comparing the read signal input from the signal acquisition module with a predetermined reference signal, and outputting cell information according to the comparison result, a storage unit for storing cell information output from the comparator unit; Including a spare cell analysis module configured to analyze the cell information stored in the storage unit to determine whether or not the memory is good, and if the memory is determined to be defective, including an analysis unit for determining whether or not repair is possible. Is done.

In the above-described configuration, the storage unit performs a storing process of storing the cell information output by the comparator unit in the storage unit and an analysis process of causing the analysis unit to read and analyze the cell information stored in the storage unit at the same time. Preferably, the spare cell analysis module is divided into an area for the storage process and an area for the analysis process, wherein the redundant cell analysis module converts the area where the analysis process is completed into an area for the storage process and the area where the storage process is completed. It is preferable to further comprise a memory controller for switching to the area for the process.

According to the present invention, by providing an extra cell analysis function to the wafer motherboard, it is possible to analyze a large amount of memory without modification of the memory tester. In other words, the cost of retrofitting a memory tester to expand ECR can be saved. In addition, the user can easily add as many ECRs as desired.

Hereinafter, a wafer motherboard having a redundant cell analysis function according to a preferred embodiment of the present invention with reference to the accompanying drawings will be described in detail.

3 is an electrical block diagram of a wafer motherboard according to an embodiment of the present invention, FIG. 4 is a detailed block diagram of the redundant cell analysis module shown in FIG. 3, and FIG. 5 is an embodiment of the present invention. It is a conceptual diagram for explaining the redundant cell analysis method according to.

As shown in FIG. 3, the wafer motherboard 100 connects the test head 200 and the probe card 500 to test the wafer. The test head 200 according to a characteristic aspect of the present invention may be used. The memory is analyzed by analyzing a signal acquisition module 110 for acquiring a read signal output by the wafer, that is, a response signal to the pattern signal, and a read signal input from the signal acquisition module 110 by the pattern signal output to the wafer. It includes a spare cell analysis module 120 to determine whether or not good quality, and whether the repair is possible if the memory is defective.

In the above-described configuration, the signal acquisition module 110 is specifically implemented as a switch element, when the switch ON signal is input from the relay controller 240 provided in the test head 200 I / O (input / output) signal To catch the read signal on the line.

In addition, the redundant cell analysis module 120 compares the read signal input from the signal acquisition module 110 with a predetermined reference signal, as shown in FIG. 4, according to a characteristic aspect of the present invention. A comparator unit 121 for outputting cell information, a storage unit 123 for storing cell information output by the comparator unit 121, and cell information stored in the storage unit 123 It determines whether the memory is good or not, and in the case of the memory determined to be defective comprises an analysis unit 124 for determining whether or not repair is possible.

In addition, the wafer motherboard 100 is connected to the memory tester through the LAN cable 300, so that the analysis unit 124 may deliver the analysis results to the memory tester.

In addition, the analyzer 124 may receive information for redundant cell analysis, such as wafer size, the number of cells existing in one memory, and a cell address, from the memory tester through the cable 300.

In addition, the storage unit 123 stores the cell information output from the comparator unit 121 in the storage unit 123 and the cell information stored in the storage unit 123 by the analysis unit 124. In order to simultaneously perform an analysis process for reading and analyzing, it is preferable to be divided into an area for a storage process and an area for an analysis process, that is, an ECR (A) and an ECR (B) as shown in FIG. 4.

In addition, the redundant cell analysis module 120 may further include a memory controller 122 for converting an area where the analysis process is completed into an area for the storage process and converting the area where the storage process is completed to the area for the analysis process. desirable. That is, the reason why the storage unit 123 is divided into two areas and the memory controller 122 is additionally configured in the redundant cell analysis module 120 is to shorten the test time.

In FIG. 3, reference numeral 130 denotes a connection terminal for connecting to the test head 200, and reference numeral 140 is a connection terminal for connecting to the probe card 500.

In addition, reference numeral 210 denotes a programmable power supply (PPS) for supplying power to the wafer, reference numeral 220 denotes a parametric measurement unit (PMU) for DC test of the wafer, reference numeral 230 denotes a driver pin, and reference numeral 250 Is the I / O pin.

On the other hand, the redundant cell analysis method according to an embodiment of the present invention can be performed as follows.

In general, tests performed prior to laser repair are referred to as pre-laser tests. Although several test items are applied to the pre-laser test, they typically consist of three stages: a DC test, a functional test that simply checks the function of the memory, and a cell test that checks each cell for failure.

As shown in FIG. 5, when performing a cell test, the memory tester 400 outputs a signal for commanding the start of a cell test to the test head 200.

Then, the test head 200 drives the relay controller 240 to output the switch ON signal to the signal acquisition module 110 installed on the wafer motherboard 100.

Accordingly, the signal acquisition module 110 acquires a read signal from the I / O signal line and transfers it to the redundant cell analysis module 120.

Then, the redundant cell analysis module 120 analyzes whether the memory cell has failed or whether the defective memory can be repaired and outputs the analysis result to the memory tester 400.

Meanwhile, when the cell test is completed and another test is to be performed, the memory tester 400 outputs a signal to the test head 200 to command the end of the cell test.

Accordingly, the test head 200 transmits a switch OFF signal to the signal acquisition module 100 so that the switch element is turned off.

The wafer motherboard having the redundant cell analysis function of the present invention is not limited to the above-described embodiments and can be modified in various ways within the scope of the technical idea of the present invention.

1 and 2 are schematic and electrical block diagrams of a conventional wafer test system, respectively.

3 is an electrical block diagram of a wafer motherboard according to an embodiment of the present invention.

4 is a detailed block diagram of the redundant cell analysis module shown in FIG. 3.

5 is a conceptual diagram illustrating a method of analyzing a redundant cell according to an embodiment of the present invention.

*** Explanation of symbols for the main parts of the drawing ***

10: memory tester

11: ALPG (algorithmic pattern generater) 12: system bus

13: Computer 14: error catch ram (ECR)

15: Redundant CPU

20: test head

21: TGFC (Timing & Formatting) 22: PE (pin electronic)

23: programmable power supply (PPS)

24: parametric measurement unit (PMU)

30: probe station 40: wafer motherboard

50: probe card 51: probe

60: wafer

100: wafer motherboard

110: signal acquisition module 120: redundant cell analysis module

121: comparator unit 122: memory controller

123: storage unit 124: analysis unit

130, 140: connector

200: test head

210: PPS 220: PMU

230: driver pin 240: relay controller

250: I / O pin

300: LAN cable 400: memory tester

500: probe card

Claims (2)

In the wafer motherboard connecting the test head and the probe card for the wafer test, A signal acquisition module for acquiring a read signal output from the wafer by the pattern signal output from the test head to the wafer; And A comparator unit for comparing a read signal input from the signal acquisition module with a predetermined reference signal, outputting cell information according to the comparison result, and an ECR (Error Catch) for storing cell information output from the comparator unit; RAM) and an analysis unit for analyzing the cell information stored in the ECR to determine whether the memory is good, and if it is determined that the memory is defective, whether or not the repair unit can be repaired. Wafer motherboard, characterized in that comprises a. The method of claim 1, The ECR stores the cell information output by the comparator in the ECR and the analysis process by which the analyzer reads and analyzes the cell information stored in the ECR. Area and the area for the analysis process, The redundant cell analysis module may further include a memory controller configured to convert an area where the analysis process is completed into an area for the storage process and convert the area where the storage process is completed into an area for the analysis process. Motherboard.

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