KR19990060855A - Probe test method of memory device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a probe test method of a memory device.

2. Technical problem to be solved by the invention

This is to solve the problem that most of the time of wafer probe test is required to perform the repair when the test and repair of the memory device is performed in the order of test, repair operation, and repair.

3. Summary of the Solution of the Invention

The probe card in the test system can be equipped with a chip that performs a repair regardless of the central processing unit, thereby reducing wafer test time by performing tests and repairs in parallel.

Description

Probe test method of memory device

The present invention relates to a probe test method of a memory device, and more particularly, to a probe test method of a memory device that can reduce the overall test time of the memory device during the wafer test by performing the device test and repair in parallel.

After fabrication, the semiconductor memory device performs a probe test on each memory cell, analyzes the address of the memory cell in which the initial failure occurs as a result of the test, and then repairs the repairable cell.

There are two types of repairs, a fuse cutting method using a laser and an electrical repair method that performs repair by applying an electrical signal. In the case of a fuse cutting method, a center used for testing a wafer probe is used. In addition to the CPU, a separate central processing unit or utility is used to analyze the initial bad address, make it into a file, and then use a laser repair device to repair the probe. On the other hand, the electrical repair method takes a lot of time to perform the repair because the repair is performed during the probe test of the wafer.

1 is a block diagram of a conventional wafer test system.

When the test controller 11 sends a command to the test system 12 by the written test program, the test unit 13 of the test system 12 passes through the prober, that is, the test head 14 and the probe card 15. A pass / fail is determined for the MUT (Memory Under Test) 16 hereinafter. If a memory cell having an initial failure is detected as a result of the determination, the address of the detected memory cell is stored in the multiplier cell address storage memory 17. Thereafter, the test central processing unit 18 analyzes a bad address stored in the bad cell address storage memory 17 to analyze whether a corresponding memory cell can be repaired. As a result of analyzing the repair possibility of the memory cell, if repair is possible, the test unit 13 sends a signal through the test head 14 to perform electrical repair.

In other words, after determining the normal / defective memory cell through DC / Function test, if the memory cell is determined to be defective, the address of the cell is detected to determine whether the cell can be repaired, and in the case of repairable cell, electrical repair is performed. It is. In this case, in order to perform a repair operation, a calculation operation must be performed to determine whether an initial bad address can be repaired after a normal / defective determination of a memory cell, and the repair operation is performed after the test of the memory cell. Should be performed. There are two cases of repair operations performed after testing of memory cells. First, a laser repair method such as DRAM or SRAM is performed by only performing a test of a memory cell, storing data for a repairable MUT as a file, and performing repair through a separate repair process. The second method is to perform electrical repair immediately after the test during the probing of the memory cell, and both methods have the order of test, repair operation, and repair.

2 is a functional diagram illustrating a conventional wafer test process. As shown, since the test and the repair are performed in series, it can be seen that most of the time for performing the wafer probe test is devoted to performing the repair, which causes a lot of time.

Therefore, the present invention is equipped with a chip that performs a repair separately from the central processing unit that performs the test when the test is performed on the device under test (DUT), which has already been tested, in parallel with the test. Accordingly, an object of the present invention is to provide a test method of a memory device capable of shortening the time required for performing repair by performing repair.

In accordance with another aspect of the present invention, there is provided a method of testing a memory device, the method comprising: a test controller transferring a test command to a test unit of a test system by a test program; and a probe card of a test head according to the command of the test unit. Determining whether the MUT is normal or defective by using the method, and storing the address of the defective memory cell in the defective cell address storage memory according to the determination result of the test head, and storing the defective cell address storage memory in the defective cell address storage memory. Analyzing whether the memory cell can be repaired by a test central processing unit by analyzing a bad address, and when repairing is possible as a result of analyzing whether the cell can be repaired, repairing the data through the data bus from the central processing unit. Repair of cell with ASIC chip MUT test in parallel with receiving required data, performing a repair by inputting a signal required for repair from the ASIC chip for repair to the MUT repair unit, and performing repair for a defective memory cell in the MUT repair unit And a step of performing a test of another memory cell in the unit.

1 is a block diagram of a probe test system of a conventional memory device.

2 is a functional diagram illustrating a process of performing a probe test of a conventional memory device.

3 is a block diagram of a probe test system of a memory device according to the present invention.

Explanation of symbols for the main parts of the drawings

21: test controller 22: test system

23: test unit 24: test head

25: probe card 26: MUT

27: multiplier cell address storage memory

28: test CPU 251: repair ASIC chip

253: MUT repair unit 254: MUT test unit

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3 is a block diagram of a memory cell test system in accordance with the present invention.

The configuration of the overall test system is similar to that of the conventional test system, but the probe card 35 of the test system according to the present invention is composed of a MUT test unit used to test the MUT and a MUT repair unit used to repair the MUT.

The overall operation is as follows.

When the test controller 31 sends a command to the test system 32 by the written test program, the test unit 33 of the test system 32 passes through the prober, that is, the test head 34 and the probe card 35. A pass / fail is determined for the MUT 36 (hereinafter referred to as MUT) 36. If the determination results in the initial failure of the memory cell, the address of the detected memory cell is stored in the defective cell address storage memory 37. Thereafter, in block-1 of the test central processing unit 38, the defective address stored in the defective cell address storage memory 37 is analyzed to analyze whether the corresponding memory cell is repairable. As a result of analyzing the repair possibility of the memory cell, if repair is possible, the repair specific ASIC (Aplication Specific) for the cell mounted in the probe card 35 via the data bus is provided with the data necessary for the cell repair in block-1 of the CPU 38. IC; hereinafter referred to as ASIC) to the chip 351. The repair ASIC chip 351, which has received the data necessary for repair, performs the repair by transferring a signal for repair to the MUT repair unit 353 through the signal bus 352.

While repair for a repairable defective memory cell is performed in the MUT repair unit 353 in the probe card 35, a test for another cell is performed in the MUT test unit 354. That is, the failure test for the next memory cell is performed independently of the memory cell currently being repaired.

As such, since the repair and the test are performed independently through the ASIC chip, the test and the repair can be performed in parallel, thereby reducing the time required for the repair, such as repair operation and repair of the repaired cell.

As described above, according to the present invention, since the test and the electrical repair of the memory cell are performed in parallel at the same time, the time required for the repair during the probe test of the memory device can be shortened and the cost of the memory device can be reduced. have.

Claims (1)

Transmitting, by the test controller, the test command to the test unit of the test system by the test program; Determining whether the MUT is normal or bad by using the probe card of the test head according to the command of the test unit, Storing the address of the defective memory cell in the defective cell address storage memory according to the determination result of the test head; Analyzing whether or not a corresponding memory cell is repaired in a test central processing unit by analyzing a bad address stored in the bad cell address storage memory; Analyzing the possibility of the repair of the cell and receiving the data necessary for the repair of the cell from the CPU to the repair ASIC chip through the data bus if repair is possible; Performing repair by inputting a signal necessary for repair from the repair ASIC chip to the MUT repair unit; And performing a test of another memory cell in a MUT test unit in parallel with performing a repair on a bad memory cell in the MUT repair unit.