KR20100027276A - Test board - Google Patents

Abstract

PURPOSE: A test board is provided to tested a plurality of DUT(Devices Under Test) at the same time by group by grouping the DUTs into a control block such as PLD(Programmable Logic Device). CONSTITUTION: A test board(100) comprises a test group(200) equipped with a plurality of DUT(250). The test board comprises signal terminals(110, 120, 130) of predetermined for offering the predetermined signals in order to be actually driven like real operating situation in DUT. A control block(210) is provided signals inputted from signal terminals. A plurality of DUTs mounted within the test group is tested at the same time.

Description

Test board

The present invention relates to a test board, and more particularly, to a test board capable of simultaneously performing a plurality of device under test (DUT).

In general, the probability of failure of a semiconductor device (or semiconductor chip) is known to be the highest occurring within an initial 1000 hours, and thereafter, it is known to be almost constant until the life of the semiconductor device is over.

In the production of semiconductor devices, the burn-in test is a test designed for the characteristics of each semiconductor device in a chamber in which a constant temperature (eg, 125 ° C. or higher) is maintained in a harsher condition than a general use environment (eg, room temperature). Under the condition that the semiconductor device is mounted on a board and the temperature of the chamber is maintained at a constant temperature of 125 ° C. or more for a specific time), an initial failure of the semiconductor device is detected more quickly in a general environment through a life acceleration experiment. Such burn-in tests are performed to detect potential failures of semiconductor devices that may occur after shipping of semiconductor devices.

This burn-in test is performed by mounting a semiconductor device to be tested (device under test, hereinafter referred to as DUT) on a burn-in board.

Referring to FIG. 1, a plurality of DUTs 20 are mounted in a matrix form on a burn-in board 10 having first to third connectors 11, 12, and 13. Input / output signals A, clock signals B, and address signals C may be input to the first to third connectors 11, 12, and 13 in any order. A plurality of signal wires 30 for transferring the signals A, B, and C to each DUT 20 between the first to third connectors 11, 12, 13 and each DUT 20. This is arranged.

In the test of the general burn-in board, respective signals A, B, and C are provided through the signal wires 30, and signal writing is performed for each DUT 20.

On the other hand, the signal reading of the DUT 20 is mounted on the test board 10 by using a signal selected from the clock signal B, for example, a CE (chip enable) signal or an OE (output enable) signal as a scan signal. The DUT 20 of any one or more (for example, eight when eight input / output wires are provided) is designated, and then the output signal (data) of the designated DUT 20 is read out.

However, as a DUT mounted on a general burn-in board is configured to receive predetermined signals from a plurality of signal wires extending from each signal terminal, signal delay deviation may occur for each position of the DUT. Due to this signal delay, the size of the signal input for each DUT may also be different. Moreover, when signal wiring is provided for each of the plurality of DUTs, a fast response cannot be expected in terms of the overall operation due to the load capacity connected to each DUT 20. Also, signal delays of different positions of the first end and the end are different. You can not expect a quick response even if it occurs. Here, the first end and the other end of the location may refer to the first DUT and the last DUT in the same row, or may refer to a DUT located in different rows.

In particular, this signal delay prevents all DUTs mounted on the burn-in board from writing signals at the same time.

In addition, in the case of a scan signal for selecting a specific DUT, a test is performed in a serial manner in which a scan signal is specified for a DUT that can be specified among all the DUTs. Thus, in the case of the signal read operation as described above, at least one DUT 20 Readouts were performed separately. Because of this, it took a long time during the test progress.

It is therefore an object of the present invention to provide a test board which can reduce the test time.

Another object of the present invention is to provide a test board capable of simultaneously testing a plurality of DUTs mounted on a test board in groups.

In order to achieve the above object of the present invention, a test board according to an embodiment of the present invention, the board having a plurality of signal terminals and a plurality of test groups located on the board, each test group Has a plurality of device under test (DUT), and a control block configured to receive signals input from the signal terminals and collectively test the plurality of DUTs mounted in the test group.

The test board according to another embodiment of the present invention may include a plurality of test groups including a control block and a plurality of device under tests (DUTs) which are collectively controlled by the control block. Groups are configured to receive input signals from signal terminals individually so that tests may be performed collectively for each test group, and signal writing of the DUT is simultaneously performed for all the DUTs of the entire test groups. The signal read of is configured to be performed one per test group.

In this case, the total number of read out DUTs is n number in which the number of input / output signals input to the one test group and n times the number of input / output signals per DUT shared in one test group coincide.

According to the present invention, the test board of the present invention forms a test group by grouping a plurality of DUTs mounted on the test board around a control block such as a programmable logic device (PLD).

Accordingly, since signals need to be provided only to the test group without providing signals for each DUT, signal simplification can be achieved, thereby greatly reducing signal delay. Thus, a high frequency test is also possible.

Moreover, the test group includes a buffer unit therein, which buffers the input signals that are primarily input, and then simultaneously provides the input signals to each DUT. Accordingly, all the DUTs can be simultaneously written, that is, signals can be applied without signal delay.

In other words, the present invention does not directly supply the signals to all the DUTs as conventionally, but instead supplies the signals to the control block and then transmits the signals 1: 1 to the DUTs in the test group regulated by one control block. Designed and configured. Accordingly, the number of loads of the DUT and the capacitive load of the wiring can be reduced, and the signal delay can be greatly reduced. This enables high frequency testing.

In addition, since the test board of the present embodiment can be individually controlled for each test group, a read operation can also be performed for each test group. Accordingly, at the same time, output signals of the DUT as many as the number of test groups can be simultaneously read, thereby greatly reducing the read time, that is, the test time.

In addition, each control block includes a circuit for determining a pass / fail of a DUT, and thus, a test speed may be improved than that of each DUT using a conventional scan signal.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2 and 3, the test board 100 of the present embodiment may include at least two test groups 200 having a plurality of DUTs 250. In addition, the test board 100 includes predetermined signal terminals 110, 120, and 130 for providing predetermined signals to each of the DUTs 250 constituting the test group 200 to be driven as in an actual operating situation. . The signals include various types of input / output signals IO, clock signals CLK, and address signals ADD.

The signals are transmitted to each test group 200 through signal wires 150a, 150b, and 150c. That is, each signal is transmitted to the corresponding test group 200 through signal wires connected between the signal terminals 110, 120, and 130 and each test group 200. In this case, in FIG. 2, the wiring 150a through which the input / output signal is transmitted, the wiring 150b through which the clock signal is transmitted, and the wiring 150c through which the address signal is transmitted are represented by one wire, respectively, as described above. Since the IO, the clock signal CLK, and the address signal ADD are input in plural kinds, they can be substantially composed of a plurality of wirings.

The test group 200 may be composed of a control block 210 and a plurality of DUTs 250. Here, the DUT 250 included in the test group 200 is a part of the DUTs 250 to be processed on the entire board 100. In the test group 200, the control block 210 may have the form of an auxiliary board in a form in which a plurality of DUTs 250 are inserted into and fixed to the entire board 100, and the control block 210 may be a whole board ( It can be inserted and fixed by the connector on 100).

The control block 210 is a programmable logic device (PLD), for example, a field programmable gate array (FPGA). The control block 210 receives input signals IO, CLK, and ADD from signal terminals 110, 120, and 130, and then, within the same test group 200. Configured to batch control and test the DUTs 250. The control block 210 writes data (signal) to the DUT 250 in the same manner as the actual driving situation, and reads the data (signal) to the DUT 250. ) Determine whether or not a failure has occurred.

This control block 210 includes a register unit 220 and a buffer unit 240, which selects the write and read operations of the DUT 250 and at the same time fail the DUT 250. and determine whether or not to fail. The register unit 220 may be configured with as many unit registers 230 as the number of DUTs 250 integrated in the test group 200. In this case, the number of registers 230 integrated in the register unit 220 may have a close relationship with the number of IO lines, and for example, may correspond to the number of IO lines input to each control block. In other words, when the pass / fail of the DUT 250 is determined, since the pass / fail is determined for each input / output signal, the total number of the register units 220 may be equal to the number of input / output signals of the total DUTs 250.

As shown in FIG. 4, the unit register 230 may include a first selector 231, a comparator 233, a storage 235, and a second selector 237.

The first selector 231 is configured to determine an input path of the input / output signal IO <n>. The first selector 231 may include first and second buffers B1 and B2. The first buffer B1 is configured to buffer the input / output signal IO <n>, and the second buffer B2 is connected to the storage unit 235 according to the first selection signal SEL1, for example, a read selection signal. It is provided as a path to read the stored device read result.

The comparator 233 is configured to compare the input / output signal IO <n> with the DUT signal DUT <n> and output the result. The comparison unit 233 may be configured to output “0” when the two input signals are the same and “1” when the two input signals are different. The comparator 233 configured as an exclusive logic circuit may include an output signal (ie, an input / output signal IO <n>) of the first selector 231 and an output signal DUT <of the second selector 237. n>) and configured to compare these two signals.

The storage 235 is configured to latch the output signal of the comparator 233 for a predetermined period of time. The storage unit 235 may include a DQ flip-flop and an OR gate. The DQ flip-flop latches the output signal of the OR gate until the reset signal is enabled, and the OR gate performs an operation operation on the output signal of the comparator 233 and the output signal of the DQ flip-flop FF. do.

The second selector 237 may be composed of third and fourth buffers B3 and B4. The third buffer B3 is configured to transfer the output signal of the first selector 231 to the corresponding DUT 250 according to whether the second select signal SEL2, for example, the write select signal, is enabled. B4 buffers the signal of the corresponding DUT 250 and provides it to the input terminal of the comparison unit 233. This register 230 is driven as follows.

First, during the write operation, the first selection signal SEL1 is disabled and the second selection signal SEL2 is enabled. Accordingly, the input / output signal IO <n> is provided to the corresponding DUT 250 through the first buffer B1 and the third buffer B3.

Meanwhile, in a read operation, the first input signal of the comparator 233 is input as an expected value through the first buffer B1, and the signal of the corresponding DUT 250 is compared with the comparator 233 through the fourth buffer B4. Is provided as a second input signal. The comparison unit 233 compares the expected value with the output signal of the DUT 250, and the result is stored in the storage unit 235 for a predetermined time, for example, until the reset signal is enabled. The stored result value is an output signal of the storage unit 235 to the outside through the second buffer B2 under the condition that the first selection signal SEL_1 is enabled and the second selection signal SEL_2 is disabled. The value is output.

The buffer unit 240 is configured to buffer the input / output signal IO, the clock signal CLK, and the address signal ADD to each DUT 250. The signal wires 150a, 150b, and 150c of the present embodiment have a relatively short distance compared with the related art, thereby greatly reducing signal delay.

In addition, by buffering the input / output signal IO, the clock signal CLK, and the address signal ADD transmitted through the signal wires 150a, 150b, and 150c of the present embodiment, the buffers are simultaneously provided to the corresponding DUT 250. This extra signal delay can be eliminated. In this case, the number of signals or signal wires provided to the test group 200 may be determined by signals provided to each DUT 250. That is, when 16 signals are required to drive the DUT 250, the signal wires provided to the test group 200 may also be 16 + M (where M is a natural number).

Meanwhile, the plurality of DUTs 250 in the test group 200 may be arranged in the same number at regular intervals in the upper row and the lower row about the control block 210. In this embodiment, the test board 100 is configured such that 20 DUTs 250 are arranged in one test group 200, that is, one control block 210 collectively controls 20 DUTs 250. . When 160 DUTs are mounted on a general burn-in board, in this embodiment, eight test groups 200 including 20 DUTs are installed to control the DUT 250. Here, the number and arrangement of the DUT 250 may be variously changed. That is, the number of DUTs 250 arranged in the test group 200 may vary according to the number of input / output signals and the size of the DUT 250.

The test method of the test board having such a configuration is as follows.

The data (signal) writing operation will first be described. In this case, the operation of writing the data to the DUT 250 may be a step of applying a signal while driving the DUT 250 in the same manner as in the actual operation situation as described above. The write operation is first performed by the input / output signals IO, the clock signal CLK, and the address signals ADD input from the signal terminals 110, 120, and 130 through the respective test wires 150a, 150b, and 150c. 200 to control block 210. Since the input / output signal IO, the clock signal CLK, and the address signal ADD are provided to the test group 200 without being individually provided for each DUT 250, the test group 200 transmits a complex signal. The input signals IO, CLK, and ADD may be provided without a signal delay due to a path. In addition, the buffer unit 240 included in the control block 210 performs buffering before providing the input signals IO, CLK, and ADD to the DUT 250, and simultaneously buffers the corresponding DUTs 200. The input / output signal IO, the clock signal CLK and the address signal ADD are input. At this time, the input / output signal IO is input to the corresponding DUT 250 by the selective driving of the first and second selection signals SEL1 and SEL2 of each unit register 230 in the control block 210.

Accordingly, the input signals IO, CLK, and ADD are input to the eight test groups 200 with almost no signal delay, and additionally buffering and timing from each buffer unit 240 are unified. Provided to the DUT 250. Accordingly, all the DUTs 250 mounted in the test board 100 are simultaneously written in the grouped state.

Meanwhile, the data reading operation will be described below. In the present embodiment, it will be interpreted that the reading operation of data includes not only reading data stored in the DUT 250 but also checking whether a specific signal is properly input (supplied).

First, a read operation of 20 DUTs 250 mounted in the test group 200 is performed by using one of the clock signals CLK input to the test group 200, for example, a chip enable signal, as a scan signal. The DUT 250 is selected. Next, the first and second selection signals SEL1 and SEL2 of the register 230 connected to the designated DUT 250 are selectively driven as described above, so that the comparator 232 of the register 230 may select a corresponding register ( Substantial comparison operation between the input and output signal IO input to the 230 and the output signal of the DUT 250 is performed. If the input / output signal IO and the output signal of the DUT 250 are different, the register 230 maintains the fail 1 state until the reset signal is input, otherwise, the normal state (0) ) Thus, through the process of reading data (signal) in the DUT 250, it is possible to determine whether a failure occurred in the test DUT 250.

In addition, since the read operation is performed for each test group 200, as many DUTs 250 as the number of test groups 200 can perform the read operation at the same time. That is, when the test board 100 is divided into eight test groups 200 and 20 DUTs are mounted in each test group 200 as in the present embodiment, eight DUTs 250 simultaneously read operations. The output signals of all the DUTs can be read out by only 20 read operations.

Therefore, it is possible to test the entire DUT only by the time of testing one test group, which greatly reduces the test time.

In addition, since the test group can provide a signal independently to the DUT, the signal characteristics are improved, and since the DUT is directly connected to the FPGA-type test group, there is no fan out, thereby achieving a stable signal supply.

The present invention is not limited to the above embodiment.

In the present embodiment, the case in which eight test groups, that is, eight PLDs are installed in one test board has been described, but various modifications can be made in consideration of the number of DUTs mounted in the test board.

As mentioned above, this invention can be variously implemented in the range which does not deviate from the summary of this invention.

1 is a schematic plan view of a typical burn-in board,

2 is a plan view of a test board according to an embodiment of the present invention;

3 is a block diagram showing a test group of a test board of the present invention, and

4 is a detailed circuit diagram illustrating a unit register of the test group of FIG. 3.

<Explanation of symbols for the main parts of the drawings>

100: test board 200: test group

210: control block 220: register unit

230: register 240: buffer unit

250: DUT

Claims (14)

A main board having a plurality of signal terminals and a plurality of test groups located on the main board, Each of the test groups A plurality of device under tests (DUTs), and And a control block configured to receive signals input from the signal terminals and collectively test the plurality of DUTs mounted in the test group. The method of claim 1, The control block, And simultaneously write the signals to each of the DUTs and optionally read the output signals of the DUTs. The method of claim 1, And a register unit to determine the signal writing and reading of the DUT by a clock signal (CLK) group input to the control block, and to output a test result by comparing an output signal of the DUT with a reference signal. The method of claim 3, wherein And the register unit includes a unit register corresponding to the number of DUTs mounted in the test group. The method of claim 4, wherein The register is, A first selector for determining signal writing and reading of the DUT; A comparator for comparing an output signal of the DUT with an input / output signal input as a reference signal when the output signal of the DUT is read; And And a storage configured to latch the output signal of the comparator for a predetermined time. The method of claim 5, wherein The selection unit, A first selector configured to transmit an input / output signal input through the signal terminal and an output signal of the DUT to the comparator, when the signal of the DUT is read; And And a second selector configured to set a path so that an input / output signal input through the signal terminal is provided to the DUT when writing a signal of the DUT. The method of claim 6, The first selector comprises a first buffer for buffering the input / output signal, and And a second buffer configured to transfer an output signal of the storage unit to the first buffer according to a read selection signal. The method of claim 7, wherein The second selector may include a third buffer configured to transfer a signal of the first selector to a corresponding DUT according to whether a write select signal is enabled or not; And And a fourth buffer buffering the signal of the corresponding DUT and providing the buffer to the comparison unit. The method of claim 3, wherein The control block further includes a buffer unit configured to buffer the signals input from the signal terminals and to provide the same timing for each DUT. The method of claim 1, And the control block is a programmable logic device (PLD). The method according to claim 2 or 10, The test group has a form of an auxiliary board in which the control block is inserted and fixed in the form that the plurality of DUT is inserted and fixed to the entire board, the control block is inserted into the connector on the connector. And a plurality of test groups including a control block and a plurality of device under tests (DUTs) which are collectively controlled by the control block. The plurality of test groups are configured to receive input and output signals separately from signal terminals so that tests may be performed collectively for each test group. Test writing of the DUT is performed simultaneously for all DUTs of the entire test groups, and signal reading of the DUT is configured to be performed for each test group. The method of claim 12, The total number of the read out DUT is the same as the number of input and output signals input to the one test group. The method of claim 13, The test group may have a form of an auxiliary board in which the control block is inserted and fixed in a form in which the plurality of DUTs are inserted and fixed in the entire board, and the control block is inserted and fixed in a connector.

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