JPH11183569A - Ic testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an IC testing apparatus in which a matching signal is corrected and in which whether a pattern is matched or not can be judged by installing a rate adjusting circuit which corrects the deviation of the timing of matching signals which are reported respectively from digital functional circuits whose test rate is different. SOLUTION: When the synchrinizing signal (d) of a second functional unit is skipped, a rate adjusting circuit 26 outputs the output signal (f) of the rate adjusting circuit 26 as '1'. A matching judgment circuit 18 can output apparently a normal judgment signal (g) used to judge a pattern matching operation by using only the matching signal (b) of a first unit. The adjusting circuit 26 outputs the matching signal (e) of the second unit as it is when a matching-cycle enable signal C is at '0'. Thereby, when a DUT sets the enable signal C at '1' during a matching cycle, it detects the judgment signal (g), and it sets the enable signal C at '0'. Thereby, the judgment signal (g) can be used as a pass/ fail signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC test apparatus characterized in that two digital function units operate at different test rates. More specifically, the present invention relates to an IC test apparatus in which the state of an object to be tested is a state expected by a tester. The present invention relates to an improvement in a circuit configuration for realizing a pattern match determination function for determining whether or not a pattern match is determined.

[0002]

2. Description of the Related Art A first digital function unit is characterized by a high-speed, large-capacity memory and a small number of pins, and a second digital function unit is characterized by a low-speed, small-capacity memory and a large number of pins. IC where digital function unit operates at different test rates
The test equipment was a liquid crystal display (LCD).
This is effective in a test of a driving device (hereinafter, referred to as an LCD driver) of a play).

[0003] Such an IC test apparatus is described, for example, in Japanese Patent Application No. 9-49966 proposed by the present applicant.

The LCD driver outputs two types of signals in response to a high-speed, few-pin input signal. They are a high-speed, low-pin interface signal and a low-speed, high-pin LCD drive signal.

FIG. 3 shows a configuration example of a conventional IC test apparatus for testing this type of driver. In this example, the LCD
One of the outputs, such as a driver, has a high speed and few pins, and the other output has a low speed and many pins (DUT: Device
Focusing on the characteristics of Under Test 2, a high-speed output side of the DUT is connected to a first digital function unit 10 that processes input signals at high speed, and a low-speed output side receives a low-speed output signal from the DUT. A second digital function unit 20 operating at a test rate different from that of the first digital function unit is connected.

The first digital function unit 10 on the high-speed side generates a test input signal C to the DUT 2 and simultaneously outputs an interface signal D which is an output signal on the high-speed side.
(Pass / fail), and outputs a low-speed synchronization signal A generated by thinning out a high-speed synchronization signal (not shown) to the second digital function unit 20 on the low-speed side. The second digital function unit 20 on the low-speed side includes the first digital function unit 10
The pass / fail of the LCD output signal E which is the output signal on the low-speed side of the DUT 2 is determined according to the synchronization signal A given by the DUT 2. I do.

As described above, a high-speed but expensive digital function unit and a low-speed but inexpensive digital function unit are utilized,
By using them in combination, cost performance is improved.

[0008]

However, in the conventional structure, only the type of DUT whose output signal is uniquely determined with respect to the input signal can be tested. That is, a type of DUT in which an output signal corresponding to an input signal is not uniquely determined (for example, a DUT having a built-in microprocessor unit) needs to perform a branch operation while observing an output state during a test. For example, when the output state matches a certain condition (mismatch), the test is started.

The branching operation according to the output state can be determined based on whether or not the output pattern of both the high-speed output signal and the low-speed output signal of the DUT matches the output pattern expected by the tester. In other words, the two match signals obtained by comparing the expected value of the output pattern expected by the tester with the high-speed and low-speed output signals are compared with each other taking into account the timing shift due to the difference in the rate. If it is determined that they match (unmatch), the process branches (for example, starts a test).

The determination as to whether or not the DUT has entered a certain state (for example, a test can be started) is a pattern match determination, and the period during which the DUT waits until it reaches a certain state is a match cycle. The conventional IC test apparatus does not include a circuit for performing the pattern match determination.

For this reason, in the conventional IC test apparatus, the M
DUT with built-in PU (typically CPU, CG
There is an LCD driver which incorporates the above. There was a problem that it was not possible to cope with the test of ()).

The present invention solves the above-mentioned problem, and
An object of the present invention is to provide an IC test apparatus in which two digital function units can operate at different test rates and perform pattern match determination.

[0013]

In order to achieve the above object, according to the first aspect of the present invention, there is provided a method for correcting a timing difference between match signals notified from digital function units having different test rates. A rate adjustment circuit is provided.

According to the first aspect of the present invention, by providing the rate adjusting circuit, the shift of the match signal of the high-speed and low-speed digital function units is corrected,
This makes it possible to make a pattern match determination that was not possible conventionally. Further, a function of a pattern match determination can be added with a slight modification to the circuit configuration of the pass / failure determination which has been conventionally performed, so that the cost performance is greatly improved.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of an IC test apparatus according to the present invention. The first digital function unit 10a includes an expected value memory 12 for storing an expected value of an output pattern on the high-speed side of the DUT 30, and a digital comparator for comparing the high-speed output signal z of the DUT with the expected value of the output pattern on the high-speed side. And a timing generator 13 for generating an execution timing signal for the comparison operation.
If the digital comparator 14 does not match the expected value with the output signal, a fail memory 15 for storing the fail information is provided.

Further, a pattern memory 16 for storing an expected value of an output pattern on the low-speed side of the DUT 30, a timing generator 17 for generating a timing signal for executing a comparison operation of the digital comparator 24 on the low-speed output side, and a first digital function unit 10a And a digital function controller 11 that comprehensively manages both the second digital function unit 20a and a match determination circuit 18 that compares a match signal b on the high-speed side with an output signal f of the rate adjustment circuit and outputs a pattern match determination signal g. It is equipped with.

Second digital function unit 2
0a is the DUT3 stored in the pattern memory 16.
A digital comparator 24 for comparing the expected value of the output pattern on the low-speed side of 0 with the low-speed output signal y of the DUT 30;
A fail memory 25 for storing the fail information is mounted. Further, the rate adjustment between the match signal e output from the slave controller 21 for controlling each unit in the second digital function unit 20a and the digital comparator 24 operating at a low rate and the match determination circuit 8 operating at a high rate. Is carried.

A test input signal x output from the first digital function controller 11 is connected to an input terminal of the DUT 30. The high-speed output signal z of the DUT 30 is connected to a digital comparator 14 operating at a high rate, and the low-speed output signal y is connected to a digital comparator 24 operating at a low rate.

The operation of the IC test apparatus having the above configuration will now be described with reference to the time chart of FIG. The synchronization signal d (low speed rate) of the second digital function unit 20a is created by thinning out the synchronization signal a (high speed rate) of the first digital function unit.

The match signal b of the first digital function unit is updated at the rising edge of the synchronizing signal a of the first digital function unit at the high rate, and the match signal e of the second digital function unit is updated at the time of the low rate. It is updated when the synchronization signal d of the second digital function unit rises. The pattern match is determined as a match when the match signals of the first and second digital function units are both “1”, and is determined as an unmatch when either one is “0” or both are “0”. This is performed at the rising edge of the synchronization signal a of the first digital function unit.

Next, when the match signal “b” of the first digital function unit and the match signal “e” of the second digital function unit are closely watched, the rate No. in FIG. Since the synchronization signal d of the second digital function unit is not input to 2, 4, 5, 8, and 10, there is a point where the match signal e of the second digital function unit retains the previous value as it is. is there. This indicates that the match determination of the second digital function unit 20a on the low-rate side has been skipped due to rate adjustment. The pattern match determination at this point should be performed only with the match signal b of the first digital function unit, and the match signal e of the second digital function unit must be excluded. A circuit provided for the purpose of implementing this is the rate adjusting circuit 26.

The rate adjusting circuit 26 receives the match signal e of the second digital function unit as an input, and the rate at which the synchronization signal d of the second digital function unit is not input (rate Nos. 2, 4 and 4).
5, 8, 10) all output signals in a matched state. That is, when the synchronization signal d of the second digital function unit is skipped, the rate adjustment circuit 26 outputs the output signal f of the rate adjustment circuit as “1”. Since the pattern match determination is performed only with the match signal b of one digital function unit, a normal pattern match determination signal g can be output.

The rate adjusting circuit 26 operates as described above when the match cycle enable signal c is "1", and outputs the match signal e of the second digital function unit as it is when it is "0". With this, the DUT
During the match cycle, the pattern match determination signal g is detected by setting the match cycle enable signal to "1", and the pattern match determination signal g is set to the pass / fail signal by setting the match cycle enable signal to "0". Can be used.

With such a configuration, in an IC test apparatus in which two digital function units operate at different test rates, pattern match judgment and pass / fail judgment of the two digital function units can be performed.

It should be noted that the foregoing description has been directed to specific preferred embodiments for the purpose of illustration and illustration of the invention. Therefore, the present invention is not limited to the above-described embodiments, and includes many more modifications without departing from the spirit thereof.
This includes deformation.

[0026]

As described above, according to the present invention, the following effects can be obtained. In the invention described in claim 1, 2
In an IC test apparatus in which two digital function units operate at different test rates, the rate of a match signal output from a digital comparator operating at a low rate and a match signal output from a digital comparator operating at a high rate are adjusted. The inclusion of the rate adjustment circuit enables pattern match determination.

According to the invention described in claim 2, the conventional IC
The pattern match determination can be easily realized by a slight modification such as providing a match determination circuit in the test apparatus. According to the third aspect of the present invention, since the pattern match determination and the pass / fail determination can be realized by the same circuit, an inexpensive and simple circuit configuration can be realized. According to the fourth aspect of the present invention, an expected value can be individually set in advance, so that an efficient test can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of an IC test apparatus according to the present invention.

FIG. 2 is a time chart of the IC test apparatus according to the present invention.

FIG. 3 is a configuration diagram illustrating an example of a conventional IC test apparatus.

[Explanation of symbols]

10a first digital function unit 11 digital function controller 12 expected value memory of first digital function unit 13 timing generator of first digital function unit 14 digital comparator of first digital function unit 15 of first digital function unit Fail memory 16 Pattern memory of the second digital function unit 17 Timing generator of the second digital function unit 18 Match determination circuit 20a Second digital function unit 21 Slave controller 22 Expected value memory of the second digital function unit 24 Second Digital function unit of the digital comparator 25 Fail memory 26 rate adjusting circuit tal functional units

Claims (4)

[Claims] 1. A test input device for testing a device under test equipped with a microprocessor having two types of output signals, a high-speed output signal and a low-speed output signal, for one high-speed input signal. A first digital function unit for providing a signal and simultaneously testing a high-speed output signal, and a second digital function unit for receiving the low-speed output signal of the device under test and operating at a test rate different from that of the first digital function unit Wherein the two digital function units are configured to compare respective output signals with expected values to obtain a match signal indicating match / mismatch. Equipped with a rate adjustment circuit to correct the timing deviation of the match signal IC test equipment according to claim and. 2. A match / unmatch determination of a pattern match determination signal based on a match signal obtained on the first digital function unit side and a match signal on the second digital function unit side obtained via the rate adjusting circuit. 2. The IC test apparatus according to claim 1, further comprising a match determination circuit that performs a match determination. 3. The IC test apparatus according to claim 1, wherein said rate adjusting circuit can detect both a pattern match judgment signal and a pass / fail signal by switching its operation. 4. The IC test apparatus according to claim 1, wherein said expected value can be individually set in advance in said first and second digital function units.