WO2011117939A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2011117939A1
WO2011117939A1 PCT/JP2010/005609 JP2010005609W WO2011117939A1 WO 2011117939 A1 WO2011117939 A1 WO 2011117939A1 JP 2010005609 W JP2010005609 W JP 2010005609W WO 2011117939 A1 WO2011117939 A1 WO 2011117939A1
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Prior art keywords
semiconductor device
solder
electrode
semiconductor
manufacturing
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PCT/JP2010/005609
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English (en)
French (fr)
Inventor
永井秀一
森田竜夫
小島俊之
上田大助
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パナソニック株式会社
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Publication of WO2011117939A1 publication Critical patent/WO2011117939A1/ja

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/005—Soldering by means of radiant energy
    • B23K1/0056—Soldering by means of radiant energy soldering by means of beams, e.g. lasers, E.B.
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • the present disclosure relates to a power semiconductor device used for an inverter module or the like and a method of manufacturing the same.
  • GaN gallium nitride
  • FET field-effect transistors
  • a current flows in the vertical direction of the device (current flows from the front surface to the back surface of the semiconductor element), and the vertical device is advantageous because a large current passing area can be obtained.
  • the nitride semiconductor has a large dielectric breakdown electric field, the drift layer can be made thin, and even in a lateral device structure, a device having a small on-resistance for a large current can be realized (for example, non-patent) See literature 1).
  • the semiconductor element is subjected to chip die bonding to the chip mount frame of the package by solder material, wire bonding the gate electrode, drain electrode and source electrode to the lead frame for each terminal of the package by Au or Al, etc.
  • solder material wire bonding the gate electrode, drain electrode and source electrode to the lead frame for each terminal of the package by Au or Al, etc.
  • wire inductance and resistance greatly affect device characteristics, multiple wires with large radius have been used.
  • Copper clip bonding can realize a low resistance connection because the current passing area can be made larger than that of a wire.
  • the current passing area of the copper clip 1003 becomes large, so the resistance can be small.
  • the size of the semiconductor chip is large when the electrode pad 1002 becomes large. This leads to an increase in chip cost. Therefore, it is desirable that the area of the copper clip 1003 in contact with the area of the electrode pad 1002 be as similar as possible so as to avoid waste.
  • nitride semiconductors are characterized by being capable of high speed operation, but there is a problem that the gate electrode is very small in order to realize high speed operation, and the protrusion of solder to the outside of the electrode pad region becomes remarkable.
  • the reflow process requires a certain amount of solder between the electrode pad and the copper clip.
  • resistance is large. For example, after applying solder on the electrode pad, if the copper clip is strongly pressed against the electrode pad when installing the copper clip, the electrode clip region of the solder may be protruded outside. For this reason, the solder between the electrode pad and the copper clip can not be thinned.
  • the inventors of the present invention use a laser solder device (see, for example, Patent Document 2) capable of heating locally and locally, and a GaN semiconductor element. Copper clip bonding was done. However, when the upper portion of the copper clip is irradiated with laser light, the heat is dissipated through the copper clip having good heat dissipation, and therefore the solder between the copper clip and the electrode pad is not melted. Therefore, the semiconductor chip is broken when bonding is performed by increasing the laser light intensity.
  • this laser soldering apparatus can emit light only at one place, the laser bonding technology has a problem when mounting on many elements.
  • An object of the present disclosure is to realize a semiconductor device in which terminal bonding is performed with low resistance using a copper clip (metal frame) on a small nitride semiconductor or the like and a method for manufacturing the semiconductor device.
  • the illustrated semiconductor device includes an electrode formed on the top of the semiconductor element and a metal frame in which a connection portion is connected to the electrode by solder or an adhesive, and the metal frame is formed in the connection portion and penetrates the metal frame
  • the planar shape of the first surface of the through hole in contact with the electrode of the metal frame is different from the planar shape of the second surface opposite to the first surface.
  • the through hole may have an area in the first surface smaller than that in the second surface. In this way, it is possible to realize terminal connection in which the area of the metal frame is large and the terminal connection resistance is small.
  • the semiconductor device may be a lateral device. In this way, a power semiconductor device capable of high speed operation can be realized.
  • the semiconductor element may be a nitride semiconductor. In this way, a power semiconductor device capable of high-speed operation at high temperature can be realized.
  • the electrode to which the metal frame is joined may be a terminal or a gate terminal which controls the operation of the semiconductor element. In this way, all the terminals can be bonded only by metal frame mounting. Therefore, a low cost semiconductor device can be realized.
  • the metal frame may be joined and the area of the electrode may be 0.25 mm 2 or less. By doing this, it is possible to realize a low-cost semiconductor device that can operate at high speed.
  • step (b) may be performed after step (a). In this way, since excess solder does not enter between the upper electrode on the semiconductor element and the metal frame, it is possible to obtain a terminal connection with very low contact resistance.
  • a plurality of laser beams may be focused simultaneously from one laser light source.
  • multiple metal frame bonding can be performed simultaneously.
  • the semiconductor device of the present disclosure it is possible to realize copper clip bonding in a state in which the solder is controlled so as not to protrude outside the electrode pad region to a semiconductor element having a very small electrode pad, and a semiconductor having a small bonding loss.
  • the device can be realized.
  • FIG. 2 is a cross-sectional view taken along line II-II of FIG.
  • FIG. 7 is a view showing one manufacturing process of the semiconductor device according to the embodiment;
  • (A) And (b) is sectional drawing which shows the modification of a through-hole. It is a perspective view which shows the modification of a metal frame. It is a perspective view which shows the modification of a metal frame. It is sectional drawing which shows the conventional semiconductor device.
  • FIG. 1 is a perspective view of a semiconductor device according to an embodiment
  • FIG. 2 is a cross-sectional view taken along the line II-II of FIG.
  • a semiconductor chip 101 is mounted on a chip mount frame 107 of a package by a die bonding material 208 of solder.
  • the semiconductor chip 101 is a nitride semiconductor field effect transistor (FET: Field-Effect Transistor), and an electrode pad 102 such as a gate electrode pad, a drain electrode pad, a source electrode pad, etc. is formed on the semiconductor chip 101.
  • FET Field-Effect Transistor
  • Each electrode pad 102 and each terminal lead frame 106 of the package are connected by a copper clip 103.
  • the copper clip 103 is a metal frame made of copper material.
  • the respective electrode pads 102 of the semiconductor chip 101 and the copper clip 103, and the lead frames 106 for the respective terminals and the copper clip 103 are bonded by a solder material 104.
  • a plurality of through holes 105 are formed in a portion of the copper clip 103 above the electrode pad 102 of the semiconductor chip 101, and the solder material 104 is injected into the plurality of through holes 105.
  • the through holes 105 are formed in the copper clip 103, the excess solder 104 protrudes from the through holes 105 to the upper portion of the copper clip 103, so the solder between the copper clip 103 and the electrode pad 102 is an electrode pad. It is possible to prevent the outside of the 102 area.
  • the surface area of the copper clip 103 is reduced and the volume of the solder 104 is increased, so that the contact resistance is increased by the increase of the solder 104.
  • the structure of the through hole 105 of the present embodiment is tapered, and the hole diameter of the surface of the copper clip 103 on the electrode side of the semiconductor chip 101 is smaller than the hole diameter of the upper portion of the copper clip 103. For this reason, compared with the case where the through hole has a straight shape, the contact area of the copper clip 103 with the electrode pad 102 can be increased, and the resistance can be reduced.
  • the arrangement of the through holes 105 makes it possible to control the spread of the solder 104 between the copper clip 103 and the electrode pad 102.
  • the spread of the direction can be controlled very precisely.
  • the thickness of the solder 104 between the copper clip 103 and the electrode pad 102 is very thin ( ⁇ 50 ⁇ m), copper clip bonding with very small contact resistance can be realized.
  • the semiconductor device manufacturing method shown in FIG. 1 will be described below with reference to FIG.
  • the position adjustment is performed so that the copper clip 103 is in contact with the semiconductor chip 101 mounted on the chip mount frame 107 and the contact surface of the electrode pad 102 on the semiconductor chip 101 and the copper clip 103 contacts.
  • Install Since the through hole 105 is formed in the copper clip 103, the through hole 105 can also be used as an alignment marker for position adjustment.
  • solder is injected into the plurality of through holes 105 formed in the copper clip 103. Since the solder is applied to the through holes 105 after the copper clip 103 is placed on the upper portion of the electrode, the solder is deposited on the upper portion of the copper clip 103 even when the amount of applied solder is large. It does not affect the spread of solder on the area.
  • the focal point of the laser beam 310 of the laser soldering apparatus 309 (for example, lead-free compliant laser soldering unit ULD-730 manufactured by Japan Unix Co., Ltd.) is the through hole 105 in the copper clip 103 and its inside Perform light alignment so as to be located around the solder of
  • the laser beam 310 emitted from the laser solder device 309 as shown in FIG. 3 is branched using the optical diffractive element 311 (DOE: Diffractive Optical Elements), and the laser is placed at a position where soldering is performed through the F- ⁇ lens 312
  • DOE Diffractive Optical Elements
  • the laser solder 310 is used to irradiate the laser beam 310 to the through hole 105 of the copper clip 103 and the solder in the inside of the through hole 105 to heat and melt the solder. Since the through hole 105 is formed in the copper clip 103 of the present embodiment, the laser beam 310 can be directly irradiated to the solder, and the heat due to the laser beam 310 does not escape from the copper clip 103. And the solder between the electrode pads 102 on the semiconductor chip 101 can be melted. In this structure, the copper clip 103 is mounted using the laser solder device 309, and the laser beam 310 is locally irradiated.
  • the copper clip 103 is irradiated with the intensity of the laser beam 310 or the irradiation region of the laser beam 310. It is possible to precisely control the spread of the solder between the electrode pad 102 and the electrode pad 102. Furthermore, since only the upper portion of the semiconductor chip 101 is partially heated, the die bonding material on the back surface of the semiconductor chip 101 is not remelted, and a low temperature chip die bonding material or a high temperature electrode bonding material is used. be able to. In addition, it is possible to perform copper clip bonding using a bonding material that melts at a high temperature, such as solder, to a semiconductor chip that is weak to heat.
  • the melted solder in the through hole 105 flows between the copper clip 103 and the electrode pad 102 on the semiconductor chip 101 by capillary action or the like, and solidifies in a region not sufficiently heated by the laser beam 310. It does not spread more than. Therefore, the spread of the solder can be controlled by the shape of the through hole 105, and the solder between the copper clip 103 and the electrode pad 102 on the semiconductor chip 101 can be made very thin, so the contact resistance is very small. It is possible to
  • the irradiation of the laser beam 310 from the laser soldering device 309 is stopped, the solder material is solidified by cooling, and copper clip bonding is completed.
  • the solder 104 is used as a bonding material for the chip die bonding material 208 and the copper clip 103.
  • a conductive material such as silver paste may be used.
  • the copper clip 103 is a metal frame of a copper material, but may be another metal.
  • the through hole in the copper clip 103 may be a through hole 405A having a narrow upper portion of the copper clip 103, and as shown in FIG. 4B, the through hole is a straight through hole 405B. It may be.
  • the through holes are described as a plurality of circular holes.
  • the through holes may be flat rectangular through holes 505 or may be through holes of other shapes.
  • a plurality of through holes 605 may be formed in a planar rectangular shape or another shape.
  • FET field effect transistor
  • the semiconductor device of the present disclosure is very effective as an electronic component or the like using a nitride semiconductor for high power.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Mechanical Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Plasma & Fusion (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

　半導体装置は、半導体素子１０１の上部に形成された電極１０２と、接続部が電極１０２と半田又は接着材によって接続された金属フレーム１０３とを備えている。金属フレーム１０３は、接続部に形成され且つ金属フレーム１０３を貫通する貫通孔１０５を有している。貫通孔１０５は、金属フレーム１０３の電極１０２と接触した第１の面における平面形状が、第１の面と反対側の第２の面における平面形状と異なっている

Description

半導体装置及びその製造方法
　本開示は、インバータモジュール等に用いられるパワー半導体装置及びその製造方法に関する。
　近年、窒化ガリウム（ＧａＮ）に代表される直接遷移型で広いバンドギャップを有する窒化物半導体（一般式：（ＩｎxＡｌ1-x）yＧａ1-yＮで表される混晶物等）は、シリコンに比べ絶縁破壊電界及び飽和電子速度が大きいということから、高耐圧、高周波、高温動作の電子デバイスとして注目されている。特に、窒化ガリウム系材料を用いた電界効果トランジスタ（ＦＥＴ：Field-effect Transistor）の研究が活発に行われている。
窒化ガリウムのＦＥＴは、ソース、ドレイン、ゲート電極が同一の半導体表面に形成されており、電流が横方向に流れるため横型デバイスと呼ばれる。大電流電子デバイスとしては、一般的にデバイスの縦方向に電流を流す（半導体素子表面から裏面に電流が流れる。）縦型デバイスの方が、電流通過面積を大きく取れるので有利とされている。しかし、窒化物半導体は、絶縁破壊電界が大きいためドリフト層を薄くできき、横型デバイス構造であっても大電流用のオン抵抗が小さいデバイスを実現することが出来できている（例えば、非特許文献１を参照。）。
　半導体素子はパッケージのチップマウントフレームに半田材によってチップダイボンディングを行い、ゲート電極、ドレイン電極、ソース電極をパッケージの各端子用リードフレームにＡｕ又はＡｌ等でワイヤボンディングした後、全体を樹脂モールドすることでパッケージ化される。パワーデバイスの実装においては、ワイヤのインダクタンスや抵抗がデバイス特性に大きく影響するため、半径の大きいワイヤを複数本使用するなどしてきた。
　近年、図７に示すようなワイヤの代わりに銅の金属フレームを用いて電極接続を行い、低コストで作業時間も少ない銅クリップ（リードフレーム）ボンディング方法が採用されてきている（例えば、特許文献１を参照。）。この際、半導体素子１００１上の電極パッド１００２の上に、チップダイボンド材１００８より低融点の半田１００４を塗布し、銅クリップ１００３を設置した後、加熱・冷却するリフロー工程が採用されている。
　銅クリップボンディングは、ワイヤに比べ電流通過面積を大きくできることから、低抵抗接続が実現できる。この銅クリップボンディングにおいて、半導体チップ１００１の電極バッド１００２が大きいと銅クリップ１００３の電流通過面積が大きくなるので抵抗が小さくでききるが、横型デバイスの場合は電極パッド１００２が大きくなると半導体チップのサイズが大きくなり、チップコストの増大につながる。このため、電極パッド１００２の面積と接触する銅クリップ１００３の面積は、無駄のないように極力同じような構成が望まれる。
特表２００９－５１４２４２号公報 特表２００８－２６００３５号公報
IEEE Trans.Electron Devices、2005年、52巻、9号、ｐ.1963-1968
　上記銅クリップボンディングを横型デバイスである窒化物半導体素子に適用する場合、チップコストを下げるために各電極パッド面積が小さく形成されており、半田が電極パッド領域外にはみ出してしまう問題がある。さらに、窒化物半導体は高速動作が可能なことが特徴であるが、高速動作を実現するためにゲート電極は非常に小さく、半田の電極パッド領域外へのはみ出しが顕著となるという問題がある。
　また、銅クリップボンディングのリフロー工程の際にチップダイボンド材が再溶融してしまうことで位置のずれが生じる。リフロー工程時に半導体チップや銅クリップが、リフロー工程中の半田の融解・凝固により移動してしまい、電極パッドが小さい場合には半田や銅クリップ自体が、電極パッド領域外に設置されるという問題がある。
　さらに、電極パッドと銅クリップの間の半田は、接触抵抗を小さくするために極力少なくする必要があるが、リフロー工程では、電極パッドと銅クリップの間の半田量がある程度必要であるため、接触抵抗が大きいという問題がある。例えば、電極パッドの上に半田を塗布した後に、銅クリップを設置する際に、銅クリップを強く電極パッドに押し付けると、半田の電極パッド領域外にはみ出してしまう。このため、電極パッドと銅クリップ間の半田を薄くできない。
　そこで、本願発明者等は、小さい電極パッドへの銅クリップボンディングの課題を解決するため、局所領域且つ局所的に加熱できるレーザ半田装置（例えば、特許文献２を参照。）を用い、ＧａＮ半導体素子の銅クリップボンディングを行った。しかしながら、銅クリップ上部にレーザ光を照射すると放熱性が良い銅クリップを通じて熱が放熱されるため、銅クリップと電極パッド間の半田が融解することはなかった。そこでレーザ光強度を強くしてボンディングを行うと半導体チップが破壊してしまった。
　さらに、このレーザ半田装置は一箇所でしか光を照射することができないため、レーザボンディング技術は多くの素子に実装を行う場合には問題がある。
　本開示は、電極パッドが小さい窒化物半導体等に銅クリップ（金属フレーム）を用いて低抵抗で端子ボンディングされている半導体装置及びその製造方法を実現できるようにすることを目的とする。
　例示の半導体装置は、半導体素子の上部に形成された電極と、接続部が電極と半田又は接着材によって接続された金属フレームとを備え、金属フレームは、接続部に形成され且つ金属フレームを貫通する貫通孔を有し、貫通孔は金属フレームの電極と接触した第１の面における平面形状が、第１の面と反対側の第２の面における平面形状と異なっている。これにより、小さい電極パッドを有する半導体素子に金属フレームボンディングが適用可能となり、特性の優れた半導体素子が実現できる。
　例示の半導体装置において貫通孔は、第１の面における面積が、第２の面における面積よりも小さくてもよい。このようにすれば、金属フレームの面積が大きく、端子接続抵抗が小さい端子接続を実現できる。
　例示の半導体装置において半導体素子は、横型デバイスであってもよい。このようにすれば、高速動作が可能なパワー半導体装置が実現できる。
　例示の半導体装置において半導体素子は、窒化物半導体であってもよい。このようにすれば、高温で高速動作が可能なパワー半導体装置が実現できる。
　例示の半導体装置において、金属フレームが接合されている電極は半導体素子の動作を制御する端子又はゲート端子としてもよい。このようにすれば、金属フレーム実装のみですべての端子をボンディングすることができる。従って、低コストの半導体素子が実現できる。
　例示の半導体装置において、金属フレームが接合されてい記電極の面積は、０．２５ｍｍ2以下であってもよい。このようにすれば、高速動作が可能で、低コストの半導体装置が実現できる。
　例示に係る半導体装置の製造方法は、半導体素子上に形成された上部電極に金属フレームを設置する工程（ａ）と、金属フレームに形成された貫通孔に半田又は接着材を塗布する工程（ｂ）と、工程（ａ）及び工程（ｂ）よりも後において半田又は接着材にレーザ光を照射する工程（ｃ）とを備えている。
　例示の半導体装置の製造方法において、工程（ａ）よりも後において工程（ｂ）を行ってもよい。このようにすれば、半導体素子上の上部電極と金属フレームとの間に余剰な半田が入らないため、非常に接触抵抗が小さい端子接続が得られる。
　例示の半導体装置の製造方法において、工程（ｃ）において、１つのレーザ光源からレーザ光が同時に複数の焦点を結ぶようにしてもよい。このようにすれば、同時に複数の金属フレームボンディングが可能となる。これにより、各ボンディング工程回数によって増加する位置ずれを防ぐことができ、複数の金属フレームボンディングされた半導体装置を得ることができる。
　本開示の半導体装置によれば、電極パッドが非常に小さい半導体素子に、電極パッド領域外に半田がはみ出さないよう制御された状態で銅クリップボンディングを実現することができ、接合損失が少ない半導体装置を実現できる。
一実施形態に係る半導体装置を示す斜視図である。 図１のII－II線における断面図である。 一実施形態に係る半導体装置の一製造工程を示す図である。 （ａ）及び（ｂ）は、貫通孔の変形例を示す断面図である。 金属フレームの変形例を示す斜視図である。 金属フレームの変形例を示す斜視図である。 従来の半導体装置を示す断面図である。
　以下、一実施形態に係る半導体装置の構造について、図１及び図２を用いて説明する。図１は一実施形態の半導体装置の斜視図であり、図２は図１のII－II線における断面図である。半導体チップ１０１がパッケージのチップマウントフレーム１０７に半田のダイボンド材２０８で実装されている。半導体チップ１０１は、窒化物半導体の電界効果トランジスタ（ＦＥＴ：Field-Effect Transistor）であり、半導体チップ１０１上には、ゲート電極パッド、ドレイン電極パッド、ソース電極パッド等の電極パッド１０２が形成されている。各電極パッド１０２とパッケージの各端子用リードフレーム１０６とは、銅クリップ１０３によって接続されている。銅クリップ１０３は銅材料でできた金属フレームである。
　半導体チップ１０１の各電極パッド１０２と銅クリップ１０３、及び各端子用リードフレーム１０６と銅クリップ１０３は半田材１０４で接着されている。半導体チップ１０１の電極パッド１０２の上の銅クリップ１０３の部分に貫通孔１０５が複数の形成されており、その複数の貫通孔１０５の中に半田材１０４が注入されている。
　本構造では、銅クリップ１０３に貫通孔１０５が形成されているために、余剰の半田１０４は貫通孔１０５から銅クリップ１０３上部にはみ出すため、銅クリップ１０３と電極パッド１０２間の半田が、電極パッド１０２領域外にはみ出すことを防ぐことができる。
　銅クリップ１０３に貫通孔１０５がある場合、銅クリップ１０３の表面積が減り半田１０４の体積が増えるため、半田１０４の増加により接触抵抗が増加する。本実施形態の貫通孔１０５の構造はテーパー形状になっており、銅クリップ１０３の半導体チップ１０１電極側の面の孔径が、銅クリップ１０３上部の孔径に比べて小さい構造となっている。このため、貫通孔がストレート形状である場合に比べ、銅クリップ１０３の電極パッド１０２との接触面積が大きくでき、抵抗を小さくすることが可能となる。
　さらに、本実施形態では、貫通孔１０５が複数あるため、この貫通孔１０５の配列によって、銅クリップ１０３と電極パッド１０２との間の半田１０４の広がりを制御することが可能となり、半田１０４の横方向の広がりを非常に精密に制御することができる。また、本実施形態では、銅クリップ１０３と電極パッド１０２の間の半田１０４の厚さが非常に薄い（～５０μｍ）ため、非常に小さい接触抵抗の銅クリップボンディングが実現できる。
　以下に、図１に示した半導体装置製造方法について、図３を用いて説明する。第１の製造工程として、チップマウントフレーム１０７に実装されている半導体チップ１０１に銅クリップ１０３を、半導体チップ１０１上の電極パッド１０２と銅クリップ１０３の接触面が接触するように、位置調整しながら設置する。銅クリップ１０３に貫通孔１０５が形成されているため、貫通孔１０５を位置調整用のアライメントマーカーとしても使用することができる。
　その後、第２の製造工程として、銅クリップ１０３内に形成された複数の貫通孔１０５内に半田を注入する。銅クリップ１０３を電極上部に設置してから半田を貫通孔１０５に塗布するため、塗布した半田の量が多い場合にも、銅クリップ１０３上部に半田が析出し、半導体チップ１０１上の電極パッド１０２領域上の半田の広がりに影響しない。
　次に、第３の製造工程として、レーザ半田装置３０９（例えば、ジャパンユニックス社製鉛フリー対応レーザ半田付ユニットULD-730）のレーザ光３１０の焦点が銅クリップ１０３内の貫通孔１０５及びその内部の半田周辺に位置するように光アライメントを行う。このとき、図３のようにレーザ半田装置３０９から出射したレーザ光３１０は、光学回折素子３１１（ＤＯＥ：Diffractive Optical Elements）を用いて分岐され、Ｆ－θレンズ３１２を通して半田付けを行う位置にレーザ光３１０の焦点が結ぶようになっている。この方法を用いれば、レーザ半田装置３０９を用いて一括で銅クリップ１０３を実装することが可能となり、製造工程の大幅な短縮と共に、レーザ半田付け工程の課題を解決することができる。例えば、銅クリップボンディングを一個ずつ行うと、半田材の融解・硬化工程で位置ずれが起こってしまい他の銅クリップ１０３が実装できなくなってしまう。特に、複数の銅クリップ１０３が一体化したフレームを使用した場合は、位置ずれで実装できなくなってしまう問題が生じていたが、この一括レーザ半田付け工程により解決することができる。
　第４の製造工程として、レーザ半田装置３０９を用いて、銅クリップ１０３の貫通孔１０５及びその内部の半田周辺にレーザ光３１０を照射し、半田が加熱・融解する。本実施形態の銅クリップ１０３には貫通孔１０５が形成されているため、直接半田にレーザ光３１０を照射することができ、レーザ光３１０による熱は銅クリップ１０３から逃げることがなく、銅クリップ１０３と半導体チップ１０１上の電極パッド１０２の間にある半田を融解することができる。本構造は、レーザ半田装置３０９を用いて銅クリップ１０３を実装しており、レーザ光３１０を局所的に照射しているので、レーザ光３１０の強度やレーザ光３１０の照射領域で、銅クリップ１０３と電極パッド１０２との間の半田の広がりを精密に制御することが可能となる。さらに、半導体チップ１０１の上部のみを部分的に加熱しているため、半導体チップ１０１裏面のダイボンディング材が再溶融することがなく、低温のチップダイボンディング材又は、高温の電極ボンディング材を使用することができる。また、熱に弱い半導体チップに半田等の高温で融解するボンディング材を用いた銅クリップボンディングを行うとことが可能となる。本工程において、融解した貫通孔１０５内の半田は、毛細管現象等で銅クリップ１０３と半導体チップ１０１上の電極パッド１０２の間に流れ込み、レーザ光３１０で十分に加熱されない領域で凝固するため、それ以上広がらない。そのため、半田の広がりを貫通孔１０５形状で制御することができると共に、銅クリップ１０３と半導体チップ１０１上の電極パッド１０２との間の半田を非常に薄くすることができるため接触抵抗を非常に小さくすることが可能となる。
　次に、第５の製造工程として、レーザ半田装置３０９からのレーザ光３１０の照射を停止し、半田材が冷却により固化され、銅クリップボンディングが完成する。
　本実施形態において、チップダイボンド材２０８や銅クリップ１０３のボンディング材として半田１０４を用いて説明したが、銀ペーストなどの伝導性を有する材料であってもよい。
　本実施形態において、銅クリップ１０３は銅材料の金属フレームとしてしたが、その他の金属であってもよい。
　図４（ａ）に示すように、銅クリップ１０３内の貫通孔は、銅クリップ１０３上部が狭い貫通孔４０５Ａであってもよく、図４（ｂ）に示すようにストレート形状の貫通孔４０５Ｂであってもよい。
　本実施形態では、貫通孔を複数の円形孔として説明したが、図５に示すように平面長方形状の貫通孔５０５であってもよく、その他の形状の貫通孔であってもよい。図６に示すように平面長方形状又はその他の形状の貫通孔６０５が複数形成されていてもよい。
　本実施形態では、ゲート、及びドレイン及びソースが各個形成された半導体素子を用いて説明したが、ゲート端子及びその他の端子が複数であってもよい。
　本実施形態では、電界効果トランジスタ（ＦＥＴ：Field-Effect Transistor）を用いて説明したが、その他のデバイス構造であってもよい。
　本開示の半導体装置は、高パワー用の窒化物半導体を用いた電子部品等として非常に有効である。
１０１　　　半導体チップ
１０２　　　電極パッド
１０３　　　銅クリップ
１０４　　　半田
１０５　　　貫通孔
１０６　　　端子用リードフレーム
１０７　　　チップマウントフレーム
２０８　　　ダイボンド材
３０９　　　レーザ半田装置
３１０　　　レーザ光
３１１　　　光学回折素子
３１２　　　レンズ
４０５Ａ　　貫通孔
４０５Ｂ　　貫通孔
５０５　　　貫通孔
６０５　　　貫通孔

Claims (14)

  1. 　半導体装置は、
    　半導体素子の上部に形成された電極と、
    　接続部が前記電極と半田又は接着材によって接続された金属フレームとを備え、
    　前記金属フレームは、前記接続部に形成され且つ前記金属フレームを貫通する貫通孔を有し、
    　前記貫通孔は、前記金属フレームの前記電極と接触した第１の面における平面形状が、前記第１の面と反対側の第２の面における平面形状と異なっている。
  2. 　請求項１に記載の半導体装置において、
    　前記貫通孔は、前記第１の面における面積が、前記第２の面における面積よりも小さい。
  3. 　請求項１に記載の半導体装置は、
    　前記半導体素子が横型デバイスである。
  4. 　請求項１に記載の半導体装置は、
    　前記半導体素子が窒化物半導体である。
  5. 　請求項１に記載の半導体装置において、
    　前記電極は前記半導体素子の動作を制御する端子又はゲート端子である。
  6. 　請求項１に記載の半導体装置において、
    　前記電極の面積は、０．２５ｍｍ2以下である。
  7. 　半導体装置の製造方法は、
    　半導体素子上に形成された上部電極に金属フレームを設置する工程（ａ）と、
    　前記金属フレームに形成された貫通孔に半田又は接着材を塗布する工程（ｂ）と、
    　前記工程（ａ）及び工程（ｂ）よりも後において前記半田又は前記接着材にレーザ光を照射する工程（ｃ）とを備えている。
  8. 　請求項７に記載の半導体装置の製造方法は、
    　前記工程（ａ）よりも後において前記工程（ｂ）を行う。
  9. 　請求項７に記載の半導体装置の製造方法は、
    　前記工程（ｃ）において、１つのレーザ光源から前記レーザ光が同時に複数の焦点を結ぶ。
  10. 　請求項７に記載の半導体装置の製造方法において、
    　前記貫通孔は、前記金属フレームの前記上部電極と接する第１の面における面積が、前記第１の面と反対側の第２の面における面積よりも小さい。
  11. 　請求項７に記載の半導体装置の製造方法において、
    　前記半導体素子は、横型デバイスである。
  12. 　請求項７に記載の半導体装置の製造方法において、
    　前記半導体素子は、窒化物半導体である。
  13. 　請求項７に記載の半導体装置の製造方法において、
    　前記電極は、前記半導体素子の動作を制御する端子又はゲート端子である。
  14. 　請求項７に記載の半導体装置の製造方法において、
    　前記電極の面積は、０．２５ｍｍ2以下である。
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