WO2011081474A2 - Dispositif électroluminescent à semi-conducteur et son procédé de préparation - Google Patents

Dispositif électroluminescent à semi-conducteur et son procédé de préparation Download PDF

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WO2011081474A2
WO2011081474A2 PCT/KR2010/009560 KR2010009560W WO2011081474A2 WO 2011081474 A2 WO2011081474 A2 WO 2011081474A2 KR 2010009560 W KR2010009560 W KR 2010009560W WO 2011081474 A2 WO2011081474 A2 WO 2011081474A2
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layer
light emitting
emitting device
semiconductor
semiconductor light
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Korean (ko)
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WO2011081474A3 (fr
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김문덕
노영균
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우리엘에스티 주식회사
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Priority claimed from KR1020090136002A external-priority patent/KR101171250B1/ko
Priority claimed from KR1020090135703A external-priority patent/KR101117484B1/ko
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Publication of WO2011081474A3 publication Critical patent/WO2011081474A3/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/0242—Crystalline insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02513—Microstructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen

Definitions

  • the present disclosure relates generally to a semiconductor light emitting device and a method of manufacturing the same, and more particularly, to a semiconductor light emitting device using a quantum dot structure and a method of manufacturing the same.
  • the semiconductor light emitting device refers to a semiconductor optical device that generates light through recombination of electrons and holes, for example, a group III nitride semiconductor light emitting device.
  • the group III nitride semiconductor consists of a compound of Al (x) Ga (y) In (1-x-y) N (0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1, 0 ⁇ x + y ⁇ 1).
  • GaAs type semiconductor light emitting elements used for red light emission, etc. are mentioned.
  • FIG. 1 is a view illustrating an example of a conventional Group III nitride semiconductor light emitting device, wherein the Group III nitride semiconductor light emitting device is grown on the substrate 100, the buffer layer 200 grown on the substrate 100, and the buffer layer 200.
  • the p-side electrode 600 formed on the group nitride semiconductor layer 500, the p-side bonding pad 700 formed on the p-side electrode 600, the p-type group III nitride semiconductor layer 500 and the active layer 400 are formed.
  • the n-side electrode 800 and the passivation layer 900 are formed on the n-type group III nitride semiconductor layer 300 exposed by mesa etching.
  • the active layer ( 400) There is an active research to improve the degradation of the internal quantum efficiency due to the strain energy generated by the difference in lattice constant between the quantum well layer and the barrier layer.
  • the internal quantum efficiency is reduced by forming a piezoelectric field in the active layer by the strain energy, thereby separating the wave function of electrons and holes. This is called the piezoelectric effect.
  • the thickness of the existing buffer layer 200 is thickened to reduce the magnitude of strain energy due to the lattice constant difference between the substrate 100 and the n-type group III nitride semiconductor layer 300.
  • the buffer layer 200 needs to be grown from several um to several tens of um, there is a problem that the increase in growth time and material consumption increase the unit cost.
  • the buffer layer 200 is formed of a ternary compound semiconductor (eg, Al (x) Ga (1-x) N (0 ⁇ x ⁇ 1)), and the n-type group III nitride semiconductor layer is formed from the substrate 100.
  • the composition ratio of Ga is gradually increased in the (300) direction to bring the lattice constant closer to the n-type group III nitride semiconductor layer 300. This method has a problem that requires a high growth technology.
  • FIG. 9 is a diagram illustrating an example of an InGaN quantum well layer described in US Pat. No. 5,959,307.
  • the p-type group III nitride semiconductor layer 300 is grown after the Group III nitride semiconductor layer 300 and the InGaN quantum well layer 300 are grown.
  • the InGaN quantum well layer 400 Prior to growing 500, the InGaN quantum well layer 400 is left for about 2 to 20 seconds, and has a thickness of 70 ⁇ s or less including the indium rich region 400a and the indium deficient region 400b in the transverse direction.
  • Techniques for improving the efficiency of the light emitting device by forming the InGaN quantum well layer 400 is described, the average value of x in the In x Ga 1-x N quantum well layer formed by this technique is only about 0.2.
  • FIG. 10 is a view for explaining an example of a method of growing an InGaN quantum well layer described in US Patent Publication No. 2007/0075307. Due to a large difference in lattice constant and thermal expansion coefficient between InN and another group III nitride semiconductor, FIG. Pointing out the difficulty of growing a high-quality InGaN quantum well layer having a high InN composition, supplying an In source and an N source, receiving Ga from the underlying GaN layer to form an In-rich InGaN layer (S1), By growing the cover layer (S3) through the growth stop state in which the supply of the In source is interrupted (S2), in the stacking direction of the semiconductor layer, the amount of indium increases, the indium-rich region, and the amount of indium decreases.
  • S3 cover layer
  • S2 cover layer
  • a technique for forming an In-rich In x Ga 1-x N (x> 0.5) quantum well layer as a region is described.
  • quantum dot (QD) structures have been attracting attention because they are three-dimensionally confined in charge, stable to heat, have a small wavelength spread, and have a high emission intensity.
  • the InGaN quantum dot is less In
  • the group III nitride semiconductor Al x Ga y In 1-xy N (0 ⁇ x ⁇ 1,0 ⁇ y ⁇ 1,0 ⁇ x + y ⁇ 1)
  • Al x Ga y In 1-xy N (0 ⁇ x ⁇ 1,0 ⁇ y ⁇ 1,0 ⁇ x + y ⁇ 1)
  • a semiconductor light emitting device having at least one layer of a quantum dot structure.
  • a semiconductor light emitting device having an active layer having a quantum dot structure is provided.
  • a semiconductor light emitting device having a layer of quantum dot structure between a substrate and an active layer is provided.
  • FIG. 1 is a view showing an example of a conventional group III nitride semiconductor light emitting device
  • FIG. 2 illustrates an example of a semiconductor light emitting device according to the present disclosure
  • 3 is a graph showing lattice constants and band gap energies of materials constituting the substrate and the strain relaxation layer;
  • FIG. 4 is a view illustrating a process of forming an In (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer having a quantum dot structure;
  • FIG. 6 is a view comparing the wave function in the active layer of the semiconductor light emitting device according to the present example with the conventional one
  • FIG. 8 is a view showing another example of a semiconductor light emitting device according to the present disclosure.
  • FIG. 11 illustrates an example of a method of forming an InGaN quantum dot according to the present disclosure
  • FIG. 12 is an AFM photograph of a quantum dot structure formed according to the method shown in FIG.
  • FIG. 13 is a diagram illustrating a photoluminescence (PL) measurement result of a quantum dot structure formed according to the method shown in FIG. 11, wherein the x-axis is wavelength (nm) and the y-axis is intensity.
  • PL photoluminescence
  • 16 is an AFM photograph of a quantum dot structure formed according to the method shown in FIG. 14;
  • FIG. 17 is a diagram illustrating a photoluminescence (PL) measurement result of a quantum dot structure formed according to the method illustrated in FIG. 14, wherein the x axis is energy (eV) and the y axis is intensity.
  • PL photoluminescence
  • the semiconductor light emitting device 10 may include a sapphire (Al 2 O 3 ) substrate 11, a strain relief layer 12, and an n-type group III nitride semiconductor.
  • a layer 13, an active layer 14, a p-type group III nitride semiconductor layer 15, a p-side electrode 16, a p-side bonding pad 17 and an n-side electrode 18, and a protective film 19 This may be further provided.
  • the strain relief layer 12 is provided between the sapphire substrate 11 and the n-type group III nitride semiconductor layer 13, and moves In (x) Ga (1-x) from the sapphire substrate 11 toward the active layer 14.
  • the N (0 ⁇ x ⁇ 1) layer 12a and the Al (y) Ga (1-y) N (0 ⁇ x ⁇ 1) layer 12b are alternately stacked and formed.
  • the In (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer 12a is stacked in a quantum dot structure.
  • a buffer layer 12c may be provided between the strain relaxed buffer layer 12 and the sapphire substrate 11 to minimize crystal defects of the strain relaxed buffer layer 12.
  • the buffer layer 12c is made of Al (z) Ga (1) having a lattice constant smaller than the lattice constant of the In (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer 12a and larger than the sapphire substrate 11. -z) N (0 ⁇ z ⁇ 1) may be provided.
  • an undoped GaN layer 12d may be grown between the strain relief layer 12 and the n-type Group III nitride semiconductor layer 13.
  • FIG. 3 is a graph showing lattice constants and band gap energies of materials constituting the substrate and the strain relaxed buffer layer.
  • In (x) Ga (1-x) N (0 ⁇ x ⁇ 1) provided on the sapphire substrate 11 is shown. Since the layer 12a has a lattice constant larger than that of the sapphire substrate 11, the layer 12a is subjected to compressive stress, and is provided on the In (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer 12a.
  • the Al (y) Ga (1-y) N (0 ⁇ x ⁇ 1) layer 12b is larger than the lattice constant of the In (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer 12a. Since it has a small lattice constant, it is subjected to tensile stress.
  • the In (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer 12a is formed in a quantum dot structure. Since the quantum dot structure is a three-dimensional structure, 2 Compared with the dimensional structure, it is possible to have the most stable lattice constant with less strain.
  • the piezoelectric effect can be more effectively alleviated, and the In (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer 12a and Al (y) Ga (1-1-) are required to alleviate the piezoelectric effect.
  • y) The number of repeated stacks of the N (0 ⁇ x ⁇ 1) layer 12b can be minimized.
  • the In (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer 12a and Al (y) Ga (1-y) N (0 ⁇ x ⁇ 1) layer 12b are repeated.
  • the number of laminations is preferably set within 20 times so that the thickness of the In (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer 12a does not exceed the critical thickness.
  • the In (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer 12a having a quantum dot structure may have crystal defects (eg, pinholes) of the strain relaxed buffer layer 12. -holes, threading dislocations, etc., to alleviate internal quantum efficiency of semiconductor light emitting devices.
  • FIG. 4 is a view illustrating a process of forming an In (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer having a quantum dot structure
  • FIG. 5 is an In (x) Ga (1-x) having a quantum dot structure.
  • the N (0 ⁇ x ⁇ 1) layer is shown.
  • In (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer 12a of the quantum dot structure is Al (y) Ga (1-y). It can be seen that there is a property to settle in crystal defects such as pinholes formed in the N (0 ⁇ x ⁇ 1) layer 12b, whereby In (x) Ga (1-x) N (0 ⁇ It can be seen that the x ⁇ 1) layer 12a can effectively suppress the potential of crystal defects in the active layer 14. As a result, an effect of increasing the internal quantum efficiency of the semiconductor light emitting device can be expected.
  • FIG. 5 shows an Al 0.2 Ga 0.8 N buffer layer having a thickness of 500 nm at a growth temperature of 780 ° C. on an sapphire substrate by MBE growth method, and thereafter an In 0.2 Ga 0.8 N layer having a thickness of about 1 nm at a growth temperature of 450 ° C. And the growth of the Al 0.2 Ga 0.8 N layer of 20 nm thickness 4 times at the growth temperature of 650 °C, and the growth of In 0.2 Ga 0.8 N layer of about 1 nm thickness at the growth temperature of 450 °C, It can be seen that the In 0.2 Ga 0.8 N layer has a quantum dot structure.
  • the thickness of the Al 0.2 Ga 0.8 N layer is a value selected for the experiment, it is preferable to form a thickness within the range of 10 nm to 50 nm to form an effective In 0.2 Ga 0.8 N quantum dot structure.
  • FIG. 6 is a view comparing the wave function in the active layer of the semiconductor light emitting device according to the present example with the conventional one, (a) is a conventional semiconductor light emitting device, (b) is a case of the semiconductor light emitting device according to the present example It is seen.
  • the piezoelectric effect in the active layer is alleviated, the deformation of the energy band gap is prevented, and the wave function of electrons and holes is distributed in the center of the active layer, thereby improving the internal quantum efficiency.
  • FIG. 7 is a graph showing the results of the optical characteristics change experiment of the semiconductor light emitting device according to the present example, (a) is a case where only the buffer layer made of AlGaN is provided, (b) is a case according to this example.
  • the emission wavelength is 467 nm, but in (b), the emission wavelength is shortened to 463 nm while increasing the emission intensity by about two times or more than in the case of (a). This means that the internal quantum efficiency of the semiconductor light emitting device is improved by the strain relaxed buffer layer 12 according to the present example.
  • the semiconductor light emitting device 20 according to the present example is a silicon (Si) substrate 21 is used
  • the strain relaxed buffer layer 22 is formed of an Al (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer 22a and In (y) from the silicon (Si) substrate 21 toward the active layer 24.
  • Ga (1-y) N (0 ⁇ y ⁇ 1) layers 22b are alternately stacked and provided.
  • the In (y) Ga (1-y) N (0 ⁇ y ⁇ 1) layer 22b is stacked in a quantum dot structure, and the strain relaxed buffer layer 22 and the silicon (Si) substrate 21 are formed. Between the buffer layer 22c provided with Al (z) Ga (1-z) N (0 ⁇ z ⁇ 1) to minimize crystal defects of the strain relaxed buffer layer 22, or the strain relaxed buffer layer 22 Of course, an undoped GaN layer 22d may be grown between the n-type Group III nitride semiconductor layer 23.
  • a tensile stress is applied to the x) N (0 ⁇ x ⁇ 1) layer 22a, and is provided on the Al (x) Ga (1-x) N (0 ⁇ x ⁇ 1) layer 22a and is formed of Al (x Compressed to In (y) Ga (1-y) N (0 ⁇ y ⁇ 1) layer 22b having a lattice constant larger than that of Ga (1-x) N (0 ⁇ x ⁇ 1) layer 22a.
  • the stress acts.
  • the y ⁇ 1) layer 22b is subjected to tensile and compressive stresses, respectively, which are canceled out by the mutual compensation effect.
  • the stress acting on the active layer 24 provided on the strain relief layer 22 is minimized, and the piezoelectric effect can be alleviated.
  • FIG. 11 is a view showing an example of a method of forming an InGaN quantum dot according to the present disclosure, the basic concept is a heat treatment process after the InN thin film (1) and the GaN thin film (2) alternately grown while varying the thickness according to the wavelength By mixing them through, it is possible to consider various cases (when the amount of In and the amount of In) is large, depending on the In composition, but the case of the small In amount is shown in FIG.
  • the GaN buffer layer was grown to a thickness of 500 nm on a Si (111) substrate at a temperature of 750 ° C., and then the temperature was lowered to a thickness of 0.3 nm and 1.5 nm, respectively, at a temperature of 450 ° C.
  • FIG. 13 is a diagram illustrating a photoluminescence (PL) measurement result for a quantum dot structure formed according to the method shown in FIG. 11, and shows an InGaN quantum dot related signal in a 454 nm region.
  • PL photoluminescence
  • the composition of In is preferably controlled by inserting a relatively thin GaN thin film 2 at a thickness of 1 to 2 monolayers (ML) as a blocking layer. As shown in FIG.
  • the InN thin film 1 is grown to a ratio of 90% of the thickness of the GaN thin film 2, and after the heat treatment, the InN thin film 1 and the GaN thin film 2 are dissolved.
  • the phase change occurs due to the difference of points, In is combined by diffusion, and a uniform InN quantum dot 3 and GaN layer 4 are formed. Therefore, a GaN barrier is formed on the InN quantum dot 3, thereby exhibiting a quantum effect.
  • InN quantum dots 3 are embedded in the GaN layer 4.
  • FIG. 16 is an AFM image of a quantum dot structure formed according to the method shown in FIG. 14, and shows measurement results corresponding to In 0.95 Ga 0.05 N quantum dot structures, and it can be seen that the amount of In is uniformly distributed.
  • FIG. 17 is a view showing photoluminescence (PL) measurement results of a quantum dot structure formed according to the method shown in FIG. 14.
  • the light emission characteristics of the quantum dot structure thus formed are confirmed by low temperature PL measurement, and have a long wavelength of about 1450 nm. Observations were made at. Therefore, it can be seen that by utilizing the growth method according to the present disclosure, the disadvantages of In can be compensated for, and a uniform quantum dot structure can be grown even at a large In amount.
  • FIG. 18 is a diagram illustrating an example of a Group 3 semiconductor light emitting device manufactured according to the present disclosure, wherein the Group 3 nitride semiconductor light emitting device includes a sapphire substrate 10, a buffer layer 20, and a buffer layer grown on the sapphire substrate 10.
  • a single InGaN quantum dot structure is provided in the active layer 40, a multi-layered InGaN quantum dot structure may be provided.
  • the InN thin film and the GaN thin film can be used to form an InGaN quantum dot structure including more In, but the present disclosure excludes that some In is included in the InN thin film and some In is included in the GaN thin film. It is not.
  • the method according to the present disclosure is suitable for forming an active layer, and the quantum dot structure is mainly used for the active layer, the method according to the present disclosure is not limited to being applied to the formation of the active layer, and may be applied wherever such a structure is required.
  • indium gallium nitride quantum dot According to the method of forming one indium gallium nitride quantum dot according to the present disclosure, it is possible to form an indium gallium nitride nitride quantum dot that can control the indium composition in a wide range.
  • any one of the first and second semiconductor layer is a strain relief layer stacked in a quantum dot (quantum dot) structure; semiconductor light emitting device comprising a.
  • the first and second semiconductor layers have a lattice constant larger than the lattice constant of the substrate, and the lattice constant of the first semiconductor layer is larger than the lattice constant of the second semiconductor layer. This configuration causes alternating compressive and tensile stresses.
  • a semiconductor light emitting element further comprising a first buffer layer having a lattice constant smaller than the lattice constant of the first semiconductor layer and larger than the substrate between the strain relaxation layer and the substrate.
  • a second buffer layer is provided between the strain relaxation layer and the active layer, the semiconductor having a lattice constant greater than the lattice constant of the second semiconductor layer and smaller than the lattice constant of the first semiconductor layer and for supplying electrons to the active layer.
  • the substrate is provided with a sapphire (Al 2 O 3 ) substrate
  • the first semiconductor layer is provided with In (x) Ga (1-x) N (0 ⁇ x ⁇ 1)
  • the second semiconductor layer is Al (y) Ga (1-y) N (0 ⁇ x ⁇ 1) is provided.
  • a semiconductor light emitting element characterized in that the Al composition ratio y of the second semiconductor layer sequentially provided from the substrate toward the active layer gradually decreases.
  • the first and second semiconductor layers have a lattice constant smaller than the lattice constant of the substrate, and the lattice constant of the first semiconductor layer is larger than the lattice constant of the second semiconductor layer.
  • the substrate is provided with a silicon (Si) substrate, the first semiconductor layer is provided with Al (x) Ga (1-x) N (0 ⁇ x ⁇ 1), and the second semiconductor layer is In (y). Ga (1-y) N (0 ⁇ y ⁇ 1), characterized in that the semiconductor light emitting device.
  • the stress generated due to the lattice constant difference between the substrate and the active layer is canceled by the first and second semiconductor layers alternately stacked under tensile stress and compressive stress, deformation of the active layer Can be minimized.

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Abstract

La présente invention porte sur un procédé de préparation d'un dispositif électroluminescent à semi-conducteur, et sur un dispositif électroluminescent à semi-conducteur préparé par ce procédé, où le dispositif électroluminescent à semi-conducteur possède une couche active, et sur un procédé de préparation de la couche active, comprenant les étapes suivantes : lamination tour à tour de manière répétée, d'une couche mince InN-dominante et d'une couche mince GaN-dominante ; et élévation de la température et traitement thermique des couches minces InN-dominantes et des couches minces GaN-dominantes laminées tour à tour et d'une manière répétée, pour former un point quantique InxGa1-xN (0 < x < 1).
PCT/KR2010/009560 2009-12-31 2010-12-30 Dispositif électroluminescent à semi-conducteur et son procédé de préparation WO2011081474A2 (fr)

Applications Claiming Priority (4)

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KR10-2009-0135703 2009-12-31
KR1020090136002A KR101171250B1 (ko) 2009-12-31 2009-12-31 인듐갈륨나이트라이드 양자점을 형성하는 방법
KR1020090135703A KR101117484B1 (ko) 2009-12-31 2009-12-31 반도체 발광소자
KR10-2009-0136002 2009-12-31

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WO2011081474A2 true WO2011081474A2 (fr) 2011-07-07
WO2011081474A3 WO2011081474A3 (fr) 2011-11-03

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US20070108456A1 (en) * 2005-11-14 2007-05-17 Palo Alto Research Center Incorporated Superlattice strain relief layer for semiconductor devices
JP2007227671A (ja) * 2006-02-23 2007-09-06 Rohm Co Ltd 発光素子
US20080054248A1 (en) * 2006-09-06 2008-03-06 Chua Christopher L Variable period variable composition supperlattice and devices including same
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3107051A1 (fr) * 2020-02-12 2021-08-13 Centre National De La Recherche Scientifique Procédé de fabrication de nanostructures de nitrure d’aluminium et de gallium (AlGaN)
WO2021160664A1 (fr) * 2020-02-12 2021-08-19 Centre National De La Recherche Scientifique PROCEDE DE FABRICATION DE NANOSTRUCTURES DE NITRURE D'ALUMINIUM ET DE GALLIUM (AlGaN)

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