WO2011074164A1 - 自動利得制御装置、受信機、電子機器、及び自動利得制御方法 - Google Patents
自動利得制御装置、受信機、電子機器、及び自動利得制御方法 Download PDFInfo
- Publication number
- WO2011074164A1 WO2011074164A1 PCT/JP2010/006197 JP2010006197W WO2011074164A1 WO 2011074164 A1 WO2011074164 A1 WO 2011074164A1 JP 2010006197 W JP2010006197 W JP 2010006197W WO 2011074164 A1 WO2011074164 A1 WO 2011074164A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- gain control
- automatic gain
- value
- control device
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims description 4
- 238000001514 detection method Methods 0.000 claims abstract description 103
- 238000006243 chemical reaction Methods 0.000 claims abstract description 35
- 238000009499 grossing Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 16
- 238000012935 Averaging Methods 0.000 description 9
- 238000005070 sampling Methods 0.000 description 7
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005562 fading Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
Definitions
- the present disclosure relates to an automatic gain control device and an automatic gain control method used in a radio receiver or the like.
- ADC Analog to Digital Converter
- the automatic gain control device automatically adjusts the gain of the variable gain amplifier according to the level of the input signal, and keeps the level of the output signal constant.
- the automatic gain control device controls the gain of the variable gain amplifier so as to be inversely proportional to the maximum value of the input signal, and keeps the level of the output signal constant.
- Patent Document 1 describes a receiver that blocks a signal when the level of an output signal exceeds a reference level.
- Patent Document 2 describes a level control system that attenuates an input signal in accordance with the amplitude of the output signal.
- the device of Patent Document 1 or 2 erroneously detects the peak value of the pulsed noise as the maximum value instead of the original maximum value of the input signal.
- the gain of the amplifier is adjusted so that the error signal, which is the difference between this maximum value and the reference signal, is zero, that is, the maximum value is the size of the reference signal. Even if is constant, the gain is not stable or becomes too small.
- An object of the present invention is to perform automatic gain control with excellent followability even when the input signal includes pulse noise.
- An automatic gain control apparatus amplifies an input signal according to a gain control signal and outputs an amplified input signal, and the amplified input signal corresponds to an absolute value thereof.
- a conversion unit that converts the signal into a signal having a value, and a peak of a signal other than pulse noise by excluding a predetermined number of values including a maximum value from the value of the signal after conversion by the conversion unit in the peak detection period
- a peak detection unit for detecting a level, an error calculation unit for calculating an error between the peak level and a reference signal, and outputting the error signal, and updating and outputting the gain control signal based on the error signal
- a gain control unit for detecting a level, an error calculation unit for calculating an error between the peak level and a reference signal, and outputting the error signal, and updating and outputting the gain control signal based on the error signal.
- the receiver includes an automatic gain control device and a demodulation unit.
- the automatic gain control device amplifies an input signal in accordance with the gain control signal, outputs the amplified input signal, and converts the amplified input signal into a signal having a value corresponding to the absolute value thereof.
- the conversion unit for conversion the peak value of the signal other than pulse noise is detected by excluding a predetermined number of values including the maximum value from the value of the signal after the conversion by the conversion unit, And a peak detector that outputs noise position information indicating the timing of pulse noise, an error calculator that calculates an error between the peak level and the reference signal, and outputs the error signal, and an error signal And a gain control unit that updates and outputs the gain control signal based on the gain control signal.
- the demodulator includes a noise canceller, which demodulates the output signal of the amplifier and outputs a demodulated signal. The noise canceller removes noise from the signal in the demodulator using the noise position information.
- An electronic apparatus includes a receiver, a signal processing unit that performs predetermined signal processing on a demodulated signal output from the receiver, and a signal that is signal-processed by the signal processing unit.
- An output unit configured to display at least one of a displayed video and an audio output represented by the signal processed by the signal processing unit.
- an input signal is amplified by an amplifier according to a gain control signal to obtain an amplified input signal, and the amplified input signal is a value corresponding to an absolute value thereof.
- the peak detection period a predetermined number of values including the maximum value are excluded from the converted signal values to detect the peak level of signals other than pulse noise, and the peak An error between the level and the reference signal is calculated as an error signal, and the gain control signal is updated based on the error signal.
- the embodiment of the present invention it is possible to accurately detect the peak value of signals other than pulse noise even when pulse noise exists. For this reason, it is possible to prevent the gain value set in the amplifier from converging or becoming too small.
- FIG. 1 is a block diagram showing a configuration example of an automatic gain control apparatus according to an embodiment of the present invention.
- FIG. 2 is a graph showing an example of sample values of signals input to the memory of FIG.
- FIG. 3 is a block diagram showing another configuration example of the automatic gain control device of FIG.
- FIG. 4 is a graph showing an example of sample values of signals input to the maximum value detection unit of FIG.
- Fig.5 (a) is a graph which shows the example of the waveform of FM signal at the time of pulsed noise mixing.
- FIG. 5B is a graph showing a change in the gain of the amplifier when one of the signals of FIG. 5A is input to the automatic gain control device of FIG.
- FIG. 6 is a graph showing another example of sample values of signals input to the memory of FIG. FIG.
- FIG. 7 is a block diagram showing still another configuration example of the automatic gain control device of FIG.
- FIG. 8A is a graph showing an example of sample values of signals input to the memory of FIG.
- FIG. 8B is a graph showing an example of sample values input to the maximum value detection unit of FIG.
- FIG. 9 is a block diagram showing still another configuration example of the automatic gain control device of FIG.
- FIG. 10 is a block diagram showing still another configuration example of the automatic gain control device of FIG.
- FIG. 11 is a block diagram illustrating a configuration example of a wireless receiver according to the embodiment of the present invention.
- FIG. 12 is a block diagram illustrating a configuration example of the electronic device according to the embodiment of the invention.
- FIG. 13 is a block diagram illustrating a configuration example of an automatic gain control apparatus to which a complex signal is input.
- FIG. 1 is a block diagram showing a configuration example of an automatic gain control apparatus according to an embodiment of the present invention.
- 1 includes a variable gain amplifier (GCA) 12, an AD converter (ADC) 14, a decimation unit 16, a conversion unit 18, a peak detection unit 20, an error calculation unit 32, a gain And a control unit 34.
- the peak detection unit 20 includes a memory 22, a sample selection unit 24, and an averaging circuit (averager) 26.
- the amplifier 12 amplifies the input signal SI and outputs the amplified signal SA to the ADC 14.
- the amplifier 12 receives the gain control signal GA from the gain control unit 34, amplifies the input signal SI in accordance with the gain control signal GA, and outputs the amplified input signal as the signal SA. That is, the amplifier 12 provides the input signal SI with a gain corresponding to the gain control signal GA.
- the amplification includes attenuation (when the gain expressed in decibels is negative).
- the ADC 14 performs A / D (Analog-to-Digital) conversion processing on the amplified signal SA, and outputs the obtained digital signal (sample value) SC to the outside of the decimation unit 16 and the automatic gain control device 100. To do.
- the decimation unit 16 performs processing by a low-pass filter (not shown) on the signal SC output from the ADC 14, and then converts the signal into a signal having a low sampling rate by thinning out the sample value, and outputs the signal.
- the low-pass filter is used to prevent aliasing during decimation.
- the converter 18 converts the decimated signal into a signal having a value corresponding to the magnitude, and outputs the signal to the memory 22.
- the conversion unit 18 includes, for example, a square circuit and an absolute value circuit, and converts each sample value of the decimated signal into a value corresponding to each absolute value.
- the peak detection unit 20 excludes a predetermined number of values including the maximum value from the sample value of the signal after conversion by the conversion unit 18 during the peak detection period, and pulse noise (pulse noise) from the remaining value.
- the peak level PK of the signal other than is detected.
- the peak level is an average value in a certain period in which the peak value of the signal or a value close thereto is present.
- FIG. 2 is a graph showing an example of sample values of signals input to the memory 22 of FIG.
- the length of each vertical line indicates the corresponding sample value output from the conversion unit 18. The same applies to the graphs showing the following sample values.
- Black circles S1 to S16 indicate N values (upper N samples) in order from the largest of the values input during the peak detection period.
- Sample values indicated by black circles S1 to S7 are values due to pulse noise.
- the memory 22 holds the value of the top N samples among the values within the peak detection period input as a signal after conversion by the conversion unit 18. For example, each time a new sample value is received, the memory 22 determines whether or not to hold the value. That is, it is determined whether or not the new sample value is larger than the minimum value among the N sample values held in the memory 22 at that time. If it is determined that the new sample value is greater than the minimum value, the new sample value is replaced with the minimum value and held. Thereby, the memory 22 can hold the upper sample value. Samples held in the memory 22 at the end of the peak detection period are indicated by black circles S1 to S16 in FIG.
- the sample selection unit 24 selects the value of the upper X sample (that is, the M + 1 to M + Xth samples counted from the larger one) excluding the upper M sample value among the N sample values held in the memory 22. At the end of the peak detection period, or after that, it is output to the averaging circuit 26. In the case of FIG. 2, the values of eight samples of black circles S1 to S8 are not selected, and the values of four samples of black circles S9 to S12 are selected.
- the averaging circuit 26 calculates an average value of the values of the X samples selected by the sample selection unit 24, and outputs the obtained average value as a peak level PK in the peak detection period.
- the data held in the memory 22 is reset every time the peak detection period ends.
- the error calculation unit 32 calculates an error between the peak level PK obtained by the averaging circuit 26 and the reference signal RS and outputs it as an error signal ER.
- the reference signal RS is a signal having a substantially constant level.
- the gain control unit 34 updates the gain control signal GA based on the error signal ER and outputs it to the amplifier 12. By repeating the above operation for each peak detection period, the signal level of the output signal SA of the amplifier 12 is maintained at a substantially constant level according to the reference signal RS. Assume that the length of the peak detection period and the cycle for updating the gain control signal GA are constant as an example.
- the values of the eight samples of the black circles S1 to S8 are not selected. Therefore, according to the automatic gain control device 100 of FIG.
- the peak level PK corresponding to the signal SA can be accurately measured for each peak detection period.
- the values of M, N, and X may be set by a register from the outside of the apparatus 100 of FIG.
- FIG. 3 is a block diagram showing another configuration example of the automatic gain control device of FIG.
- the automatic gain control device 200 of FIG. 3 is configured in the same manner as the automatic gain control device 100 of FIG. 1 except that a peak detection unit 220 is provided instead of the peak detection unit 20.
- the peak detection unit 220 further includes a maximum value detection unit 28.
- the automatic gain control device 200 of FIG. 3 is configured not to require a huge amount of memory.
- the maximum value detection unit 28 receives the signal after the conversion by the conversion unit 18, and for each period of a predetermined length shorter than the peak detection period (for each K samples (K is an integer of 2 or more)) in the short period. The maximum sample value is output.
- the memory 22 holds the value of the top N samples among a plurality of maximum values within the peak detection period input from the maximum value detection unit 28.
- the black circles in FIG. 4 indicate the maximum value for each K sample, and black circles S 1 to S 8 among them indicate the sample values held in the memory 22.
- the sample selection unit 24 selects the value of the upper X samples (that is, the M + 1 to M + Xth samples) excluding the upper M samples from the N sample values held in the memory 22, and at the end of the peak detection period or Thereafter, the data is output to the averaging circuit 26.
- the values of the two samples of the black circles S1 and S2 are not selected, and the values of the four samples of the black circles S3 to S6 are selected.
- the maximum value detection unit 28 represents a sample value resulting from pulse noise having a temporal width as one sample. Since the maximum value detector 28 outputs the sample value to the memory 22 at a sampling rate of 1 / K with respect to the sampling rate of the signal input thereto, the number of values stored in the memory 22 is reduced. Also, unlike simple decimation, there is no possibility of missing the peak value of the signal. According to the automatic gain control device 200 of FIG. 3, the circuit scale can be reduced even when the sampling interval is short or the peak detection period is long compared to the time during which the pulse noise continues.
- FIG. 5A is a graph showing an example of a waveform of an FM (Frequency Modulation) signal when pulsed noise is mixed.
- FIG. 5B is a graph showing a change in the gain of the amplifier 12 when one of the signals in FIG. 5A is input to the automatic gain control apparatus 200 in FIG.
- FIG. 5A shows the pulse noise mixed in the FM signals FM1 and FM2.
- FIG. 5B when the gain is controlled using only the maximum value in the peak detection period, the gain G0 after convergence is small and the signal is not sufficiently amplified. This is because the pulse noise and the signal cannot be distinguished and are affected by the pulse noise.
- the automatic gain control apparatus 200 of FIG. 3 it can be seen that the gain G1 after convergence is large, the value thereof is stable, and the followability is excellent.
- FIG. 6 is a graph showing another example of sample values of signals input to the memory 22 of FIG.
- the memory 22 makes a determination each time a new value is received, and always holds the top N samples of the input values, but the maximum value of the sample values held by the memory 22 is updated with a new value. Does not hold the value of L samples (L is an integer equal to or greater than 1) that is input immediately after the operation is skipped.
- the value L may be set by a register from the outside of the apparatus 100.
- FIG. 7 is a block diagram showing still another configuration example of the automatic gain control device of FIG.
- the automatic gain control device 300 in FIG. 7 is configured in the same manner as the automatic gain control device 100 in FIG. 1 except that the peak detection unit 320 is provided instead of the peak detection unit 20.
- the peak detection unit 320 includes a memory 322, a sample selection unit 324, an averaging circuit 326, and a maximum value detection unit 328.
- FIG. 8A is a graph showing an example of sample values of signals input to the memory 322 in FIG.
- FIG. 8B is a graph illustrating an example of sample values input to the maximum value detection unit 328 of FIG.
- the memory 322 operates in units of a period (corresponding to K samples) shorter than the peak detection period. That is, the memory 322 holds a sample value within a period corresponding to K samples, which is input as a signal after conversion by the conversion unit 18, and stores the held value in the sample selection unit 324 at the end of the period or thereafter. Output.
- the sample selection unit 324 selects a value other than the L sample value including the maximum value and the sample values before and after the time value from among the output K sample values held in the memory 322 and outputs the maximum value detection unit 328. Output to.
- the maximum value detection unit 328 detects the maximum value from the values of the KL samples selected and output by the sample selection unit 324, and outputs the maximum value to the averaging circuit 326.
- the averaging circuit 326 calculates an average value of a plurality of maximum values detected by the maximum value detection unit 328 during the peak detection period, and outputs the obtained average value to the error calculation unit 32 as the peak level PK.
- FIG. 9 is a block diagram showing still another configuration example of the automatic gain control device of FIG.
- the automatic gain control device 400 of FIG. 9 is configured in the same manner as the automatic gain control device 100 of FIG. 1 except that it further includes a low-pass filter (LPF) 36.
- LPF low-pass filter
- the LPF 36 receives the error signal ER output from the error calculator 32, passes the low frequency component of this signal (in other words, smoothes this signal), and outputs the obtained signal to the gain controller 34. To do.
- the gain control unit 34 updates the gain control signal GA based on the signal output from the LPF 36.
- the LPF 36 is, for example, a first-order IIR (infinite impulse response) filter, and may operate once every gain update period. According to the automatic gain control device 400 of FIG. 9, it is possible to suppress fluctuations in the gain control signal GA due to erroneous detection by the peak detection unit 20 and minute fluctuations in the error signal ER due to other noises or the like. Similarly, other automatic gain control devices herein such as automatic gain control devices 200 and 300 may further include an LPF 36 that smoothes the error signal ER.
- FIG. 10 is a block diagram showing still another configuration example of the automatic gain control apparatus of FIG.
- the automatic gain control device 500 of FIG. 10 includes a peak detection unit 520 and a gain control unit 534 instead of the peak detection unit 20 and the gain control unit 34, and further includes a cycle determination unit 38, as shown in FIG.
- the automatic gain control device 100 is configured in the same manner.
- the length of the peak detection period and the cycle for updating the gain control signal GA have been described as being constant, but may not be constant.
- the length of the peak detection period and the gain update period may be changed based on the magnitude of the error signal ER.
- ⁇ length of peak detection period
- the cycle determination unit 38 determines an appropriate peak detection period length DP and gain update cycle RI based on the magnitude of the error signal ER output from the error calculation unit 32.
- the peak detection unit 520 detects the peak level PK for each length DP of the peak detection period determined by the period determination unit 38.
- the gain control unit 534 updates the gain control signal GA once every gain update cycle RI determined by the cycle determination unit 38.
- the other points of the peak detector 520 and the gain controller 534 are the same as those of the peak detector 20 and the gain controller 34.
- the period determination unit 38 shortens the length DP of the peak detection period and the gain update period RI.
- the period determination unit 38 increases the length DP of the peak detection period and the gain update period RI.
- the period determination unit 38 may make the length DP of the peak detection period and the gain update period RI inversely proportional to the magnitude of the error signal ER.
- the peak detection unit 520 is configured in the same manner as the peak detection unit 20 of FIG. 1 except that the sample selection unit 524 is provided instead of the sample selection unit 24.
- the length DP of the peak detection period is input from the period determination unit 38 to the sample selection unit 524, and the sample selection unit 524 operates according to the length DP of the peak detection period.
- the sample selection unit 24 in FIG. 1 selects the value of the upper X sample from the value of the N sample held in the memory 22 excluding the value of the upper M sample.
- the sample selection unit 524 in FIG. 10 changes the number M of excluded values according to the length DP of the peak detection period. Other points are the same as those of the sample selection unit 24.
- the longer the peak detection period the more affected by noise, so the sample selection unit 524 changes the number M of excluded values to a larger number as the length DP of the peak detection period is longer.
- the sample selection unit 524 sets the number M of excluded values to a number proportional to the length DP of the peak detection period. According to this, even if the peak detection period is long, it can be made less susceptible to noise.
- the automatic gain control apparatus 200 of FIG. 3 may include a sample selection unit 524 and a gain control unit 534 instead of the sample selection unit 24 and the gain control unit 34, and may further include a period determination unit 38. .
- FIG. 11 is a block diagram showing a configuration example of a radio receiver according to the embodiment of the present invention.
- a radio receiver 670 in FIG. 11 includes an automatic gain control device 600 and a demodulation unit 40.
- the automatic gain control device 600 is configured in the same manner as the automatic gain control device 100 of FIG. 1 except that a peak detection unit 620 is provided instead of the peak detection unit 20.
- the peak detection unit 620 is configured in substantially the same manner as the peak detection unit 20 of FIG.
- the memory included in the peak detection unit 620 detects the position (timing) of the pulse noise and outputs noise position information NP indicating the position of the pulse noise.
- the memory detects the position of the sample value having a large value (for example, M sample values S1 to S7 from the larger one in FIG. 2) as the position of the pulse noise.
- the peak detection unit 620 may be configured in substantially the same manner as the peak detection units 220 and 320 in FIGS. 3 and 7, and the maximum value detection unit 28 or 328 has a large sample value (for example, the sample value in FIG. 4).
- the positions of S1 and S2) may be detected as the positions of pulse noise, and noise position information NP indicating these positions may be output.
- the demodulator 40 demodulates the signal SC output from the ADC 14 and outputs the obtained demodulated signal DM.
- the demodulator 40 has a noise canceller 42.
- the noise canceller 42 removes the pulse noise from the signal SC of the demodulator 40 using the noise position information NP so that the influence of the pulse noise does not appear in the demodulated signal DM. Since the noise canceller 42 can reliably know the position of the pulse noise by using the noise position information NP, it can operate more efficiently than when the noise position information NP is not used.
- the demodulator 40 does not necessarily have the noise canceller 42.
- the automatic gain controller 600 instead of the automatic gain controller 600, any one of the automatic gain controllers 100, 200, 300, 400, and 500 is used. May be.
- FIG. 12 is a block diagram showing a configuration example of the electronic device according to the embodiment of the present invention.
- 12 includes the automatic gain control device 100, the demodulator 40, the signal processor 52, and the video / audio output unit 54.
- Automatic gain control apparatus 100 outputs signal SC to demodulator 40, which demodulates signal SC and outputs demodulated signal DM.
- the signal processing unit 52 performs predetermined signal processing such as decoding on the demodulated signal DM and outputs the result.
- the video / audio output unit 54 includes at least one of a display panel and a speaker.
- the video / audio output unit 54 displays a video represented by the signal processed by the signal processing unit 52 on the display panel, and the signal processing unit 52. At least one of the outputs from the loudspeaker of the sound represented by the signal processed in step (1).
- Examples of the electronic device 180 include a radio receiver and a television receiver.
- the automatic gain control device 100 any one of the automatic gain control devices 200, 300, 400, 500, and 600 may be used.
- the automatic gain control apparatus further includes another variable gain amplifier coupled in series with the variable gain amplifier. You may have.
- the automatic gain control device may have a plurality of variable gain amplifiers coupled in series, in which case at least one of the plurality of variable gain amplifiers is controlled as described above. Is done.
- the input signal and the output signal of the automatic gain control device are real signals
- these signals may be complex signals.
- a complex signal (in-phase signal SII and quadrature signal SIQ) output from the quadrature demodulator is used as an input signal of the automatic gain control device.
- FIG. 13 is a block diagram illustrating a configuration example of an automatic gain control apparatus to which a complex signal is input.
- the automatic gain control device 700 in FIG. 13 includes variable gain amplifiers 12A and 12B, ADCs 14A and 14B, decimation units 16A and 16B, a conversion unit 718, a peak detection unit 20, an error calculation unit 32, and a gain control unit. 34.
- the amplifiers 12A and 12B are the same as the amplifier 12 of FIG. 1 except that the signals SII and SIQ are input.
- the ADCs 14A and 14B are the same as the ADC 14 of FIG. 1, and the decimation units 16A and 16B are the same as the decimation unit 16 of FIG.
- the ADC 14A outputs the converted signal SCI to the decimation unit 16A and the demodulation circuit outside the automatic gain control device 700.
- the ADC 14B outputs the converted signal SCQ to the decimation unit 16B and the demodulation circuit.
- the decimation units 16A and 16B perform decimation similarly to the decimation unit 16 and output the obtained signals DCI and DCQ to the conversion unit 718, respectively.
- the conversion unit 718 includes a square circuit, for example, obtains I 2 + Q 2 or ⁇ (I 2 + Q 2 ) and outputs it to the peak detection unit 20.
- the peak detection unit 20, the error calculation unit 32, and the gain control unit 34 are the same as those described with reference to FIG.
- Each of the automatic gain control devices 200, 300, 400, 500, and 600 has variable gain amplifiers 12 A and 12 B, ADCs 14 A and 14 B, decimation units 16 A and 16 B, and a conversion unit 718, similar to the automatic gain control device 700. May be.
- each functional block in this specification can be typically realized by hardware.
- each functional block can be formed on a semiconductor substrate as part of an IC (integrated circuit).
- the IC includes an LSI (large-scale integrated circuit), an ASIC (application-specific integrated circuit), a gate array, an FPGA (field programmable gate array), and the like.
- some or all of each functional block can be implemented in software.
- such a functional block can be realized by a processor and a program executed on the processor.
- each functional block described in the present specification may be realized by hardware, may be realized by software, or may be realized by any combination of hardware and software.
- the influence of pulse noise can be reduced with a relatively simple circuit configuration. Therefore, the present invention uses an automatic gain control device and the same. This is useful for in-car radio tuners.
Landscapes
- Circuits Of Receivers In General (AREA)
- Control Of Amplification And Gain Control (AREA)
- Noise Elimination (AREA)
Abstract
Description
18,718 変換部
20,220,320,520,620 ピーク検出部
32 誤差算出部
34,534 利得制御部
22,322 メモリ
24,324,524 サンプル選択部
26,326 平均化回路
28,328 最大値検出部
36 ローパスフィルタ
38 周期決定部
40 復調部
42 ノイズキャンセラ
52 信号処理部
54 映像/音声出力部
100,200,300,400,500,600,700 自動利得制御装置
180 電子機器
670 無線受信機
Claims (12)
- 入力信号を利得制御信号に応じて増幅して、増幅された入力信号を出力する増幅器と、
前記増幅された入力信号を、その絶対値に対応する値を有する信号に変換する変換部と、
ピーク検出期間において、前記変換部による変換後の信号の値から、最大値を含む所定の数の値を除外して、パルス性雑音以外の信号のピークレベルを検出するピーク検出部と、
前記ピークレベルと基準信号との間の誤差を算出して、誤差信号として出力する誤差算出部と、
前記誤差信号に基づいて前記利得制御信号を更新して出力する利得制御部とを備える
自動利得制御装置。 - 請求項1に記載の自動利得制御装置において、
前記ピーク検出部は、
前記変換部による変換後の信号が入力され、前記ピーク検出期間内に入力された値のうち、大きい方からN個(Nは2以上の整数)の値を保持するメモリと、
前記メモリに保持された値のうち、大きい方から数えてM+1番目からM+X番目までのX個(MはM<Nを満たす自然数、XはX≦N-Mを満たす自然数)の値を選択するサンプル選択部と、
前記サンプル選択部で選択された値の平均値を計算して前記ピークレベルとして出力する平均化器とを有する
自動利得制御装置。 - 請求項2に記載の自動利得制御装置において、
前記ピーク検出部は、前記ピーク検出期間より短い所定の長さの期間ごとに、前記変換部による変換後の値から最大値を検出して出力する最大値検出部を更に有し、
前記メモリには、前記最大値検出部から出力された値が入力される
自動利得制御装置。 - 請求項2に記載の自動利得制御装置において、
前記メモリは、新たな値を受け取るごとに、前記新たな値を保持すべきか否かを判定し、保持する値のうちの最大値が前記新たな値によって更新された場合には、その直後に入力される所定の数の値は保持しない
自動利得制御装置。 - 請求項1に記載の自動利得制御装置において、
前記ピーク検出部は、
前記変換部による変換後の信号が入力され、前記ピーク検出期間より短い所定の長さの期間に入力された値を保持するメモリと、
前記メモリに保持された値のうち、最大値とその前後の値とを含む所定の数の値以外を選択するサンプル選択部と、
前記サンプル選択部で選択された値から最大値を検出する最大値検出部と、
前記最大値検出部で検出された最大値の、前記ピーク検出期間における平均値を計算して、前記ピークレベルとして出力する平均化器とを有する
自動利得制御装置。 - 請求項1に記載の自動利得制御装置において、
前記誤差信号に平滑化を行って出力するローパスフィルタを更に備え、
前記利得制御部は、前記ローパスフィルタで平滑化された信号に基づいて前記利得制御信号を更新して出力する
自動利得制御装置。 - 請求項1に記載の自動利得制御装置において、
前記誤差信号の大きさに基づいて、前記ピーク検出期間の長さを決定する周期決定部を更に備え、
前記ピーク検出部は、前記ピーク検出期間ごとにピークレベルを検出し、
前記利得制御部は、前記ピーク検出期間を含む期間ごとに前記利得制御信号を更新する
自動利得制御装置。 - 請求項7に記載の自動利得制御装置において、
前記ピーク検出部は、前記所定の数を、前記ピーク検出期間の長さに応じて変更する
自動利得制御装置。 - 請求項1に記載の自動利得制御装置において、
前記可変利得増幅器と直列に結合された他の可変利得増幅器を更に有する
自動利得制御装置。 - 自動利得制御装置と、
復調部とを備え、
前記自動利得制御装置は、
入力信号を利得制御信号に応じて増幅して、増幅された入力信号を出力する増幅器と、
前記増幅された入力信号を、その絶対値に対応する値を有する信号に変換する変換部と、
ピーク検出期間において、前記変換部による変換後の信号の値から、最大値を含む所定の数の値を除外して、パルス性雑音以外の信号のピークレベルを検出し、かつ、パルス性雑音のタイミングを示す雑音位置情報を出力するピーク検出部と、
前記ピークレベルと基準信号との間の誤差を算出して、誤差信号として出力する誤差算出部と、
前記誤差信号に基づいて前記利得制御信号を更新して出力する利得制御部とを有し、
前記復調部は、ノイズキャンセラを有し、前記増幅器の出力信号を復調して復調信号を出力し、
前記ノイズキャンセラは、前記雑音位置情報を用いて前記復調部内の信号から雑音を取り除く
受信機。 - 請求項10に記載の受信機と、
前記受信機から出力される復調信号に所定の信号処理を行って出力する信号処理部と、
前記信号処理部で信号処理された信号によって表される映像の表示、及び、信号処理部で信号処理された信号によって表される音声の出力のうちの少なくとも一方を行う出力部とを備える
電子機器。 - 増幅器によって入力信号を利得制御信号に応じて増幅して、増幅された入力信号を求め、
前記増幅された入力信号を、その絶対値に対応する値を有する信号に変換し、
ピーク検出期間において、前記変換後の信号の値から、最大値を含む所定の数の値を除外して、パルス性雑音以外の信号のピークレベルを検出し、
前記ピークレベルと基準信号との間の誤差を誤差信号として算出し、
前記誤差信号に基づいて前記利得制御信号を更新する
自動利得制御方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011520268A JPWO2011074164A1 (ja) | 2009-12-15 | 2010-10-19 | 自動利得制御装置、受信機、電子機器、及び自動利得制御方法 |
US13/305,111 US20120071127A1 (en) | 2009-12-15 | 2011-11-28 | Automatic gain control device, receiver, electronic device, and automatic gain control method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009-283792 | 2009-12-15 | ||
JP2009283792 | 2009-12-15 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/305,111 Continuation US20120071127A1 (en) | 2009-12-15 | 2011-11-28 | Automatic gain control device, receiver, electronic device, and automatic gain control method |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2011074164A1 true WO2011074164A1 (ja) | 2011-06-23 |
Family
ID=44166939
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2010/006197 WO2011074164A1 (ja) | 2009-12-15 | 2010-10-19 | 自動利得制御装置、受信機、電子機器、及び自動利得制御方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20120071127A1 (ja) |
JP (1) | JPWO2011074164A1 (ja) |
WO (1) | WO2011074164A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014052553A (ja) * | 2012-09-07 | 2014-03-20 | Panasonic Corp | 音量補正装置 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9070371B2 (en) * | 2012-10-22 | 2015-06-30 | Ittiam Systems (P) Ltd. | Method and system for peak limiting of speech signals for delay sensitive voice communication |
CN107659279B (zh) * | 2017-09-30 | 2023-10-27 | 浙江芯劢微电子股份有限公司 | 一种音频自动增益控制方法及装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1043874A2 (en) * | 1999-04-07 | 2000-10-11 | British Broadcasting Corporation | Detection and removal of clipping in multicarrier receivers |
JP2002185432A (ja) * | 2000-10-06 | 2002-06-28 | Alcatel | 広帯域無線信号をクリッピングするための方法および対応する送信器 |
JP2004364124A (ja) * | 2003-06-06 | 2004-12-24 | Fujitsu Ten Ltd | デジタル放送受信機 |
JP2006135989A (ja) * | 2004-11-05 | 2006-05-25 | Samsung Electronics Co Ltd | Mcm信号受信システムでのインパルスノイズ除去回路 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100790967B1 (ko) * | 2005-07-27 | 2008-01-02 | 삼성전자주식회사 | 자동이득 조절기의 제어전압을 디지털적으로 제어할 수있는 자동이득 조절기 및 제어방법 |
-
2010
- 2010-10-19 JP JP2011520268A patent/JPWO2011074164A1/ja not_active Withdrawn
- 2010-10-19 WO PCT/JP2010/006197 patent/WO2011074164A1/ja active Application Filing
-
2011
- 2011-11-28 US US13/305,111 patent/US20120071127A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1043874A2 (en) * | 1999-04-07 | 2000-10-11 | British Broadcasting Corporation | Detection and removal of clipping in multicarrier receivers |
JP2002185432A (ja) * | 2000-10-06 | 2002-06-28 | Alcatel | 広帯域無線信号をクリッピングするための方法および対応する送信器 |
JP2004364124A (ja) * | 2003-06-06 | 2004-12-24 | Fujitsu Ten Ltd | デジタル放送受信機 |
JP2006135989A (ja) * | 2004-11-05 | 2006-05-25 | Samsung Electronics Co Ltd | Mcm信号受信システムでのインパルスノイズ除去回路 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014052553A (ja) * | 2012-09-07 | 2014-03-20 | Panasonic Corp | 音量補正装置 |
Also Published As
Publication number | Publication date |
---|---|
US20120071127A1 (en) | 2012-03-22 |
JPWO2011074164A1 (ja) | 2013-04-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2006121146A (ja) | 無線受信機のフィルタ制御方法および装置およびそれを用いた無線受信機用集積回路 | |
US8660221B2 (en) | Fast and robust AGC apparatus and method using the same | |
US7203476B2 (en) | Method and apparatus for minimizing baseband offset error in a receiver | |
JP2008535396A (ja) | 動的ゲイン及び位相補償のための方法及び装置 | |
KR20190039552A (ko) | 입력 신호 충실도 및 출력 요건들에 기초한 다중 경로 지상 분열 | |
WO2011074193A1 (ja) | 自動利得制御装置及び電子機器 | |
CN107968667B (zh) | 一种直流失调消除电路及方法 | |
JP4843094B2 (ja) | 受信装置、および、プログラム | |
WO2011074164A1 (ja) | 自動利得制御装置、受信機、電子機器、及び自動利得制御方法 | |
US8676140B2 (en) | Efficient scheme for automatic gain control in communication systems | |
JP2005536162A (ja) | 異なる帯域幅を有する複数のデジタルフィルタを含む通信信号受信方法および関連する受信機 | |
US20100284541A1 (en) | Receiving apparatus | |
US7145490B2 (en) | Automatic gain control system and method | |
JPH08293748A (ja) | 自動利得制御装置及び移動端末機及び自動利得制御方法 | |
JP2006237793A (ja) | 高周波信号受信部とこれを用いた高周波信号受信装置 | |
WO2011114397A1 (ja) | 受信機 | |
JP5119965B2 (ja) | 受信装置とこれを用いた電子機器 | |
JP2004134917A (ja) | 自動利得制御装置、無線受信装置及び自動利得制御方法 | |
JP2009177568A (ja) | 受信装置とこれを用いた電子機器 | |
JP5360227B2 (ja) | 受信装置及び利得制御方法 | |
EP1843466B1 (en) | Method and apparatus for leveling an increasing or decreasing slope of an AM modulated receiving signal | |
JPH06350468A (ja) | Rssi出力回路 | |
JP5061958B2 (ja) | 追尾受信装置 | |
US20110181354A1 (en) | Reception device and electronic device using the same | |
JP5297487B2 (ja) | 受信装置及び利得制御方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 2011520268 Country of ref document: JP |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10837202 Country of ref document: EP Kind code of ref document: A1 |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 10837202 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 10837202 Country of ref document: EP Kind code of ref document: A1 |