WO2011074156A1 - Dispositif capteur d'image à semi-conducteur et caméra le comprenant - Google Patents

Dispositif capteur d'image à semi-conducteur et caméra le comprenant Download PDF

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Publication number
WO2011074156A1
WO2011074156A1 PCT/JP2010/004880 JP2010004880W WO2011074156A1 WO 2011074156 A1 WO2011074156 A1 WO 2011074156A1 JP 2010004880 W JP2010004880 W JP 2010004880W WO 2011074156 A1 WO2011074156 A1 WO 2011074156A1
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layer
semiconductor substrate
photoelectric conversion
charge
discharge
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PCT/JP2010/004880
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English (en)
Japanese (ja)
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寛 戸谷
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
    • H04N25/626—Reduction of noise due to residual charges remaining after image readout, e.g. to remove ghost images or afterimages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/0312—Inorganic materials including, apart from doping materials or other impurities, only AIVBIV compounds, e.g. SiC

Definitions

  • the present invention relates to a solid-state imaging device used for a video camera or a digital still camera, and more particularly to a back-illuminated solid-state imaging device.
  • a unit cell of a solid-state imaging device represented by a CMOS image sensor or a CCD image sensor is composed of a photoelectric conversion layer, a readout circuit for reading signal charges, and the like.
  • a so-called surface irradiation type solid-state imaging device having a structure in which a photoelectric conversion layer is provided on a surface side of a semiconductor substrate on which a device such as a readout circuit is formed, that is, on the surface side is the mainstream.
  • the unit cell size tends to be reduced due to the recent demand for downsizing of the solid-state imaging device, and there is a disadvantage that the opening area (opening ratio) of the photoelectric conversion layer with respect to the unit cell size is reduced accordingly.
  • a so-called back-illuminated solid-state imaging device in which a photoelectric conversion layer is provided on the surface opposite to the surface on which a device such as a circuit is formed, that is, on the back surface is actively researched (for example, patent References 1, 2).
  • FIG. 14 is a cross-sectional view of a main part of a unit cell of a solid-state imaging device according to Patent Document 2.
  • a wiring layer 56 is provided on the surface of the semiconductor substrate 51 (the side surface in the figure). Further, light is incident from the back surface (the lower side surface in the figure), and the p-type hole accumulation layer 55 and the n ⁇ diffusion layer 52 (corresponding to a photoelectric conversion layer) are formed from the back surface side to the front surface side in the semiconductor substrate 51. ), An n-type diffusion layer 54 and a storage diffusion layer 53 serving as a signal charge readout path are provided.
  • Each unit cell is partitioned and separated by a trench element isolation layer 58 and a p-type element isolation diffusion layer 59. Inside the element isolation diffusion layer 59, a p-type buried diffusion layer 57, which is a region having a high p-type impurity concentration, is formed.
  • the n ⁇ diffusion layer 52, the n-type diffusion layer 54 and the storage diffusion layer 53 are formed using the buried diffusion layer 57 as a gate electrode.
  • the embedded readout transistor is configured.
  • the transfer path from the photoelectric conversion layer (n ⁇ diffusion layer in Patent Document 2) to the charge storage layer (storage diffusion layer in Patent Document 2) is configured with the same polarity. It is difficult to form a potential gradient suitable for charge transfer. For this reason, there is a possibility that the signal charges accumulated in the photoelectric conversion layer cannot be completely transferred to the charge accumulation layer within a limited transfer period. If the signal charge remains in the photoelectric conversion layer, the image quality deteriorates due to the afterimage occurring when the signal charge of the next frame is accumulated.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state imaging device capable of suppressing image quality deterioration due to an afterimage as compared with the prior art.
  • a solid-state imaging device includes a back-illuminated solid-state imaging device in which a plurality of unit cells are arranged in a matrix on a semiconductor substrate and the back surface of the semiconductor substrate is a light-receiving surface.
  • Each unit cell is provided in the semiconductor substrate, photoelectrically converts light incident from the back surface, and accumulates signal charges obtained by the photoelectric conversion; and a first conductivity type photoelectric conversion layer;
  • a charge storage layer of a first conductivity type that is provided on the surface side of the semiconductor substrate relative to the photoelectric conversion layer in the semiconductor substrate and stores signal charges transferred from the photoelectric conversion layer;
  • a second conductivity type transfer path potential barrier layer interposed in a signal charge transfer path from the photoelectric conversion layer to the charge storage layer, and an insulating layer on the semiconductor substrate surface at a position corresponding to the charge storage layer When the transfer voltage for transferring the signal charge stored in the photoelectric conversion layer to the charge storage layer is applied, the potential on the back surface of the semiconductor substrate is higher than when the transfer voltage is not applied.
  • the transfer voltage is applied to the transfer electrode, thereby the potential well of the charge storage layer.
  • the depth of can be deepened.
  • the potential barrier of the transfer path potential barrier layer disappears, and the signal charge is transferred to the charge storage layer through this transfer path potential barrier layer.
  • the transfer speed is increased, and as a result, the transfer to the charge storage layer within the transfer time.
  • the signal charge can be transferred.
  • Each of the unit cells is further provided on the back surface side white scratch reducing layer of the second conductivity type provided on the back surface side of the photoelectric conversion layer in the semiconductor substrate, and on the back surface of the semiconductor substrate,
  • the transfer assist voltage for assisting the transfer of the signal charge to the charge storage layer is applied, the height of the potential barrier of the back side white scratch reducing layer is made higher than when the transfer assist voltage is not applied. It is good also as providing the auxiliary electrode to do.
  • the back side white scratch reducing layer can suppress dark current caused by interface states generated near the back side interface of the semiconductor substrate. Further, by providing the auxiliary electrode, the potential gradient of the transfer path at the time of charge transfer from the photoelectric conversion layer to the charge storage layer can be made steeper, and smoother charge transfer is possible.
  • Each unit cell is further provided in the semiconductor substrate so as to be separated from the charge storage layer in a direction orthogonal to the substrate thickness direction, and unnecessary signal charges transferred from the photoelectric conversion layer are transferred to the semiconductor substrate.
  • a discharge electrode that deepens the potential well of the charge discharge layer with respect to the potential of the back surface of the semiconductor substrate and extinguishes the potential barrier of the discharge path potential barrier layer may be provided. .
  • the auxiliary electrode further includes a discharge auxiliary voltage applied to assist the discharge of the signal charge to the charge discharge layer as the discharge voltage is applied to the discharge electrode.
  • the height of the potential barrier of the back side white scratch reducing layer may be made higher than when no discharge assist voltage is applied.
  • Unnecessary signal charges can be discharged smoothly by configuring a steeper discharge path not only in the transfer path from the photoelectric conversion layer to the charge storage layer but also in the discharge path from the photoelectric conversion layer to the charge discharge layer. Can do.
  • Each of the unit cells is further disposed between the charge storage layer and the charge discharge layer in a direction perpendicular to the substrate thickness direction in the semiconductor substrate, and spaced from the charge storage layer and the charge discharge layer.
  • a floating diffusion layer of a first conductivity type for storing signal charges transferred from the charge storage layer, and a position corresponding to the space between the charge storage layer and the floating diffusion layer on the surface of the semiconductor substrate The signal charge accumulated in the charge accumulation layer is applied to the floating diffusion layer when a read voltage is applied to the floating diffusion layer, and the signal charge accumulated in the charge accumulation layer is applied to the floating diffusion layer.
  • a readout electrode to be transferred to the floating diffusion layer may be provided.
  • the auxiliary electrode may be provided in a region excluding a portion corresponding to the photoelectric conversion layer on the back surface of the semiconductor substrate.
  • the auxiliary electrode can function as an auxiliary electrode without preventing light from entering the photoelectric conversion layer.
  • auxiliary electrode may be a metal film and also serves as a light shielding film.
  • the impurity concentration of the second conductivity type in the transfer path potential barrier layer may be higher than the impurity concentration in the discharge path potential barrier layer.
  • the potential barrier of the transfer path potential barrier layer can be made higher than the potential barrier of the discharge path potential barrier layer, and even when the signal charge is saturated in the photoelectric conversion layer, the signal charge is transferred to the charge storage layer. It can be configured to flow to the charge discharging layer without flowing. Therefore, the signal charge can be appropriately read without causing unnecessary signal charge to flow into the signal charge to be read stored in the charge storage layer.
  • Each unit cell may further include a second conductivity type surface-side white flaw reducing layer on the surface side of the charge storage layer in the semiconductor substrate. The dark current caused by the interface state generated near the interface on the surface side of the semiconductor substrate can be suppressed.
  • a second conductivity type photoelectric conversion layer separation zone is provided as a part of the unit cell between the photoelectric conversion layer and the photoelectric conversion layer in the unit cell adjacent to the unit cell including the photoelectric conversion layer. It is good.
  • a potential barrier can be formed between adjacent photoelectric conversion layers. It is possible to reduce crosstalk due to leakage of signal charges accumulated in the adjacent unit cells.
  • an insulating layer and a second conductivity type element isolation band are provided as part of the unit cell between the charge storage layer and the charge storage layer in the unit cell adjacent to the unit cell including the charge storage layer. It is good as well.
  • the element isolation band can reduce crosstalk caused by leakage of signal charges being transferred and signal charges accumulated in the charge accumulation layer to adjacent pixels.
  • the transfer path potential barrier layer and the discharge path potential barrier layer may be formed of a compound layer containing both silicon and germanium.
  • Germanium has an absorption coefficient of 10 times or more that of silicon with respect to light having a wavelength of 600 nm to 1000 nm. Therefore, by forming the transfer path potential barrier layer and the discharge path potential barrier layer with a compound layer containing silicon and germanium, long-wavelength visible light (around 600 nm to 780 nm) enters the charge storage layer beyond the photoelectric conversion layer. Can be suppressed. Thereby, generation
  • the region on the surface side of the photoelectric conversion layer in the semiconductor substrate may be formed of a compound layer containing both silicon and germanium.
  • the entire semiconductor substrate can be made thinner than when only the transfer path potential barrier layer and the discharge path potential barrier layer are formed of a compound layer containing silicon and germanium.
  • a part of the region on the surface side of the photoelectric conversion layer in the semiconductor substrate may be formed of a compound layer containing either strained silicon or strained germanium.
  • the camera according to the present invention includes the solid-state imaging device having the above-described configuration. Thereby, a camera capable of obtaining the same effect as described above can be configured.
  • a plurality of unit cells are arranged in a matrix on a semiconductor substrate, and the backside illuminated solid-state imaging device has a light receiving surface on the back surface of the semiconductor substrate, wherein each unit cell is in the semiconductor substrate.
  • a photoelectric conversion layer of a first conductivity type that photoelectrically converts light incident from the back surface and accumulates signal charges obtained by the photoelectric conversion, and the semiconductor substrate in the semiconductor substrate rather than the photoelectric conversion layer
  • a charge storage layer of a first conductivity type that is provided on the surface side of the substrate and stores signal charges transferred from the photoelectric conversion layer; and transfer of signal charges from the photoelectric conversion layer to the charge storage layer in the semiconductor substrate
  • the transfer voltage is applied to the transfer electrode to increase the potential well depth of the charge storage layer. Can do. As a result, the potential barrier of the transfer path potential barrier layer disappears, and the signal charge is transferred to the charge storage layer through this transfer path potential barrier layer.
  • the transfer speed is increased, and as a result, the transfer to the charge storage layer within the transfer time. The signal charge can be transferred. Therefore, it becomes difficult for signal charges to remain in the photoelectric conversion layer, so that image quality deterioration due to an afterimage can be suppressed.
  • 1 is an overall configuration diagram of a solid-state imaging device according to a first embodiment. Sectional drawing of the principal part of the unit cell of the solid-state image sensor concerning 1st Embodiment. 1 is an equivalent circuit diagram of a unit cell of a solid-state imaging device according to a first embodiment. 1 is a timing chart illustrating a method for driving a solid-state imaging device according to the first embodiment. Potential distribution diagram of solid-state imaging device according to first embodiment Timing chart showing a method for driving a solid-state imaging device according to the second embodiment Potential distribution diagram of solid-state imaging device according to second embodiment Sectional drawing of the principal part of the solid-state image sensor which concerns on 3rd Embodiment. Absorption spectrum near the absorption edge of semiconductors.
  • Equivalent circuit diagram of unit cell of solid-state imaging device according to sixth embodiment 1 is an overall configuration diagram of a camera including a solid-state imaging device according to the present invention Sectional view of the main part of a unit cell of a conventional solid-state image sensor
  • FIG. 1 is an overall configuration diagram illustrating an example of a solid-state imaging device according to the first embodiment.
  • the solid-state imaging device 100 includes an imaging region 1, a current source circuit 3, a vertical scanning circuit 4, a horizontal scanning circuit 5, a column readout circuit 6, a TG (timing generator) control unit 7, and an output circuit 8.
  • the imaging region 1 is a pixel array in which a plurality of unit cells 2 each composed of a CMOS sensor are arranged in a matrix in a row direction (left-right direction) and a column direction (up-down direction).
  • a pixel signal is generated by photoelectric conversion.
  • the current source circuit 3 is a circuit for supplying a constant current to the vertical signal lines VL1 to VLn.
  • the vertical scanning circuit 4 controls the horizontal signal lines L1 to Ln, sequentially selects each row, and reads out the pixel signal of each unit cell 2 in the selected row.
  • the read pixel signal of each unit cell 2 is sent to the column readout circuit 6 via the vertical signal lines VL1 to VLn.
  • the column readout circuit 6 sequentially outputs pixel signals sent from the unit cells 2 in the selected row to the output circuit 8 in units of pixels based on the control of the horizontal scanning circuit 5.
  • the TG control unit 7 supplies signals for driving the current source circuit 3, the vertical scanning circuit 4, the horizontal scanning circuit 5, and the column readout circuit 6 to each circuit.
  • the TG control unit 7 may be provided on the same semiconductor substrate as the imaging region, or may be provided on another semiconductor substrate.
  • the output circuit 8 outputs the pixel signal sent from the column readout circuit 6 to the subsequent stage.
  • FIG. 2 is a cross-sectional view of the main part of the cross-sectional view of the main part of the unit cell 2.
  • the solid-state imaging device of the present invention is a so-called back-illuminated type in which light enters from the back side (lower side of the drawing) of the semiconductor substrate 11.
  • a wiring layer 27 and a support substrate 29 bonded to the wiring layer 27 are provided on the front surface side (upper side in the drawing) of the semiconductor substrate 11.
  • a wiring 28 a readout electrode 24, a transfer electrode 25, a reset electrode 26, and a front side auxiliary electrode 35 are provided (details of these electrodes will be described later).
  • a metal such as aluminum or copper can be used.
  • the configuration of the unit cell 2 shown in FIG. 2 is common to the other unit cells 2.
  • the unit cell 2 in the semiconductor substrate 11 includes, in order from the back surface side in the thickness direction, a p-type back surface side white defect reducing layer 18, an n-type photoelectric conversion layer 12, a p-type transfer path potential barrier layer 19, n.
  • a type charge storage layer 13 and a p-type surface-side white defect reducing layer 17 are formed.
  • the upper and lower signs of n and p shown in the n-type and p-type regions indicate the density of the corresponding polar impurity concentration, and the n-type impurity concentration is expressed as n ⁇ ⁇ n ⁇ n. + , P-type impurity concentration is p ⁇ ⁇ p ⁇ p + .
  • the p-type back side white scratch reducing layer 18 suppresses dark current caused by interface states generated near the back side interface of the semiconductor substrate 11.
  • the n-type photoelectric conversion layer 12 photoelectrically converts received incident light and accumulates signal charges obtained by this photoelectric conversion.
  • the p-type transfer path potential barrier layer 19 forms a part of the signal charge transfer path from the photoelectric conversion layer 12 to the charge storage layer 13, and in a period other than when the signal charge is transferred to the charge storage layer 13, By forming a potential barrier against charges, signal charges are not transferred to the charge storage layer 13. On the other hand, in the period in which the signal charge is transferred to the charge storage layer 13, the signal charge can be transferred to the charge storage layer 13 by eliminating the potential barrier (detailed in FIG. 5).
  • the n-type charge accumulation layer 13 accumulates signal charges transferred from the photoelectric conversion layer 12 via the transfer path potential barrier layer 19.
  • the p-type surface-side white flaw reducing layer 17 suppresses dark current caused by interface states generated near the interface on the surface side of the semiconductor substrate 11.
  • a floating diffusion layer 15 (FD: Floating Diffusion) and a charge discharge layer 14 are formed from the charge storage layer 13 in a direction orthogonal to the substrate thickness direction.
  • the floating diffusion layer 15 accumulates signal charges transferred from the charge accumulation layer 13.
  • the charge discharge layer 14 discharges signal charges transferred from the floating diffusion layer 15 and the photoelectric conversion layer 12 to the pixel power supply (FIG. 3, PVDD) (details of a path from the photoelectric conversion layer 12 to the charge discharge layer 14 will be described later). To do).
  • a p-type discharge path potential barrier layer 20 is formed between the photoelectric conversion layer 12 and the charge discharge layer 14 in the direction orthogonal to the substrate thickness direction from the transfer path potential barrier layer 19 in the semiconductor substrate 11. ing.
  • the discharge path potential barrier layer 20 forms a part of a so-called discharge path that discharges unnecessary signal charges of the photoelectric conversion layer 12 to the charge discharge layer 14 and depletes the photoelectric conversion layer 12, and is not required for the charge discharge layer 14.
  • a potential barrier against the signal charge is formed so that the signal charge is not discharged to the charge discharge layer 14.
  • the signal charge can be discharged to the charge discharging layer 14 by eliminating the potential barrier (detailed in FIG. 5).
  • the path from the photoelectric conversion layer 12 through the transfer path potential barrier layer 19 to the charge storage layer 13 is a transfer path
  • the path from the charge storage layer 13 to the floating diffusion layer 15 is a read path
  • the floating diffusion layer 15 to the charge discharge layer is referred to as a reset route
  • a route from the photoelectric conversion layer 12 through the discharge route potential barrier layer 20 to the charge discharge layer 14 is referred to as a discharge route.
  • the p-type impurity concentration in the transfer path potential barrier layer 19 is higher than the p-type impurity concentration in the discharge path potential barrier layer 20.
  • the potential barrier formed in the transfer path potential barrier layer 19 can be made higher than the discharge path potential barrier layer 20, and the signal charge is charged even when the signal charge is saturated in the photoelectric conversion layer 12. Instead of flowing to the storage layer 13, it can flow to the charge discharging layer 14. Therefore, unnecessary signal charges can be discharged to the charge discharge layer 14 without flowing into the signal charges to be read stored in the charge storage layer 13.
  • the photoelectric conversion layer 12 included in each unit cell is partitioned and separated by a p-type photoelectric conversion layer separation zone 21.
  • each of the transistors such as the buried transfer transistor Q1 and the buried discharge transistor Q2 included in each unit cell is partitioned and separated by a trench element isolation layer (STI) 22 and an element isolation band 16 which are insulating layers.
  • the element isolation band 16 and the photoelectric conversion layer isolation band 21 are set to the ground potential (ground potential). Further, the front surface side white defect reducing layer 17 and the rear surface side white defect reducing layer 18 are electrically connected to the element isolation band 16 and the photoelectric conversion layer isolation band 21.
  • a back surface side auxiliary electrode 23 is provided in the region other than the portion corresponding to the photoelectric conversion layer 12 on the back surface of the semiconductor substrate 11.
  • the back-side auxiliary electrode 23 is a metal film that also serves as a light-shielding film. By providing this in the region of the unit cell boundary, the light incident on the back surface of the semiconductor substrate from an oblique direction enters the adjacent unit cell. Reduce the signal.
  • the member which comprises the back surface side auxiliary electrode 23 will not be limited to a metal film, if it is a member which functions as an electrode and a light shielding film.
  • the back side auxiliary electrode 23 is electrically connected to the back side white scratch reducing layer 18 through the photoelectric conversion layer separation band 21.
  • the surface side auxiliary electrode 35 is provided in the region corresponding to the element isolation band 16 on the surface of the semiconductor substrate 11.
  • the front surface side auxiliary electrode 35 is an electrode for fixing the potential of the p-type conductive layer such as the element separation band 16 and the photoelectric conversion layer separation band 21 and is electrically connected to the rear surface side auxiliary electrode 23 at the same potential.
  • the front-side auxiliary electrode 35 and the back-side auxiliary electrode 23 can more reliably fix the potentials of the p-type conductive layers such as the element isolation band 16 and the photoelectric conversion layer isolation band 21.
  • An insulating layer 30, a passivation insulating film 31, a color filter 32, and a microlens 33 are further provided in this order on the back surface of the semiconductor substrate 11. Light incident from the back surface of the semiconductor substrate is guided to the photoelectric conversion layer via the microlens 33 and the color filter 32.
  • the passivation insulating film 31 for example, a silicon nitride film (SiN) or the like can be used.
  • each conductivity type layer can be selectively formed by a combination of photolithography and ion implantation after epitaxial growth on the wafer.
  • CMP Chemical Mechanical Polishing
  • the back side white scratch reducing layer 18 it is desirable to form the back side white scratch reducing layer 18 with a thickness of 0.2 ⁇ m or less. By doing so, the sensitivity characteristic of the short wavelength light due to the absorption of the short wavelength visible light (around 380 nm to 460 nm) by the back side white defect reducing layer 18 before reaching the photoelectric conversion layer 12 is achieved. A decrease can be prevented.
  • FIG. 3 is a diagram illustrating an example of an equivalent circuit of the unit cell 2. 3, the photoelectric conversion layer 12, the charge accumulation layer 13, the charge discharge layer 14, the floating diffusion layer 15, the surface side white defect reducing layer 17, the back side white defect reducing layer 18, the back side auxiliary electrode 23, and the readout in FIG. 2.
  • the nodes corresponding to the electrode 24, the transfer electrode 25, and the reset electrode 26 are assigned the same numbers.
  • the n-type photoelectric conversion layer 12, the p-type transfer path potential barrier layer 19, and the n-type charge storage layer 13 form an npn-type embedded transfer transistor Q1, and a transfer electrode 25 for operating the npn-type embedded transfer transistor Q1.
  • the transfer electrode 25 is connected to the transfer wiring ⁇ TR. While the signal charge is accumulated in the photoelectric conversion layer 12, a low voltage is applied to the transfer wiring ⁇ TR, and when the signal charge is transferred from the photoelectric conversion layer 12 to the charge accumulation layer 13, a high voltage is applied to the transfer wiring ⁇ TR. A voltage is given.
  • the transfer path potential barrier layer 19 corresponding to the base of the embedded transfer transistor Q1 functions as a potential barrier against the signal charge by depletion except when the signal charge passes in the operating state of the solid-state imaging device.
  • the potential barrier is controlled by controlling the voltage applied to the transfer wiring ⁇ TR.
  • the n-type photoelectric conversion layer 12, the p-type drain path potential barrier layer 20, and the n-type charge drain layer 14 form an npn-type buried drain transistor Q2.
  • the voltage for operating the buried discharge transistor Q2 is given via the pixel power supply PVDD. While the signal charge is accumulated in the photoelectric conversion layer 12, the pixel power supply PVDD is set to low, and when the signal charge is discharged from the photoelectric conversion layer 12 to the charge discharge layer 14, so-called electronic shutter, the pixel power supply PVDD is set to high. .
  • a MOS type read transistor M1 is configured with the n type charge storage layer 13 as a source, the n type floating diffusion layer 15 as a drain, and the read electrode 24 as a gate.
  • the read transistor M1 reads the signal charge stored in the charge storage layer 13, and uses the signal charge as a pixel signal through the amplifying transistor M2 and the pixel selection transistor M3 via the vertical signal line VL (FIG. 1) and the column read circuit 6 (FIG. Send to 1).
  • the readout electrode 24 is connected to the readout wiring ⁇ RD, and a high voltage is applied to the readout wiring ⁇ RD during a signal charge readout period from the charge storage layer 13 to the floating diffusion layer 15, and during other periods the readout wiring is read out. A low voltage is applied to ⁇ RD.
  • a MOS-type reset transistor M4 is configured using the n-type floating diffusion layer 15 as a source, the n-type charge discharge layer 14 as a drain, and the reset electrode 26 as a gate.
  • the reset transistor M4 resets the potential of the floating diffusion layer 15 to the pixel power supply PVDD.
  • the reset electrode 26 is connected to the reset wiring ⁇ RS, and a high voltage is applied to the reset wiring ⁇ RS during a signal charge discharging period from the floating diffusion layer 15 to the charge discharging layer 14, and reset during other periods. A low voltage is applied to the wiring ⁇ RS.
  • the photoelectric conversion layer 12 constitutes a diode D1 with the back side white scratch reducing layer 18 and the p-type region around it.
  • the charge storage layer 13 and the surface side white defect reducing layer 17 constitute a diode D2.
  • the base resistances of the buried transfer transistor Q1 and the buried discharge transistor Q2 are indicated by R1 and R4, respectively, and an element isolation band 16 and a photoelectric conversion layer that connect between the front side white defect reducing layer 17 and the rear side white defect reducing layer 18
  • the separation band 21 is indicated by resistors R2 and R3.
  • the unit cell 2 is further provided with the above-described MOS type read transistor M1, and the read electrode ⁇ RD is applied to the read electrode 24.
  • the MOS type reset transistor M4 to which the reset wiring ⁇ RS for resetting the potential of the N type floating diffusion layer 15 to the potential of the pixel power supply PVDD is applied, and the floating diffusion layer 15 are connected to the gate.
  • the amplification transistor M2 and the pixel selection transistor M3 to which the selection wiring ⁇ SEL is applied are provided as a signal readout circuit.
  • a voltage is applied from the vertical scanning circuit 2 through the horizontal signal line L to the readout wiring ⁇ RD, the reset wiring ⁇ RS, and the selection wiring ⁇ SEL.
  • Both the drain of the reset transistor M4 and the drain of the amplification transistor M2 are connected to the pixel power supply PVDD, and the amplification transistor M2 constitutes the current source circuit 3 and the source follower in FIG.
  • the source of the amplification transistor M2 is connected to the drain of the pixel selection transistor M3, and the source of the pixel selection transistor M3 is connected to the column readout circuit 6 via the vertical signal line VL.
  • the amplification transistor M2 and the pixel selection transistor M3 are not shown in FIG. 2, they are formed in the region on the surface of the semiconductor substrate 11 in the same manner as the readout transistor M1 and the reset transistor M4.
  • the unit cell in FIG. 3 has a single pixel, a readout transistor, a floating diffusion layer, a reset transistor, and an amplifying transistor, that is, a so-called 1-pixel 1-cell structure, but the unit cell includes a plurality of pixels.
  • a so-called multi-pixel 1-cell structure may be used.
  • FIG. 4 is a timing chart showing a driving method of the solid-state imaging device.
  • the transfer wiring ⁇ TR, the back side auxiliary electrode 23 (AX), the pixel power supply PVDD, the selection wiring ⁇ SEL, the reset wiring ⁇ RS, the readout wiring ⁇ RD, and the floating diffusion layer 15 ( FD) Each potential fluctuation is shown.
  • the transfer wiring ⁇ TR, the back-side auxiliary electrode 23, and the pixel power supply PVDD are performed simultaneously for all pixels, and the selection wiring ⁇ SEL, the reset wiring ⁇ RS, the readout wiring ⁇ RD, and the floating diffusion layer 15 (FD) are each unit cell for one row. What is done about.
  • FIG. 4 shows only the timing from the first line to the second line.
  • Frame starts at time T1 and frame scanning is performed.
  • PVDD is set to the mid level and ⁇ RS and ⁇ RD are set to the high level, so that the signal charges that have been read out in the previous frame are discharged to PVDD, and the charge storage layer 13 to which the signal charges of the current frame are transferred. Depleted state.
  • the period from time T2 to T3 is a transfer period in which signal charges are transferred in the transfer path.
  • ⁇ TR to the high level
  • signal charges accumulated in the photoelectric conversion layer 12 in the accumulation period from time T19 in the previous frame to time T1 in the current frame are transferred to the charge accumulation layer 13.
  • PVDD to the low level
  • a row to be read is selected.
  • the reading period of the first row is started by setting ⁇ SEL of the unit cell belonging to the first row to a high level.
  • ⁇ SEL the drain potential of the amplification transistor M2 rises, and the amplification transistor M2 constitutes the current source circuit 3 and the source follower in FIG.
  • a pixel signal can be output to the vertical signal line VL. That is, when PVDD is at the mid level, a normal circuit operation for outputting a signal is performed.
  • the period from time T5 to T6 is a reset period.
  • ⁇ RS the potential of the floating diffusion layer 15 is reset to the voltage of the pixel power supply PVDD.
  • the period from time T7 to T8 is a reading period in which signal charges are read in the reading path.
  • ⁇ RD the signal charge stored in the charge storage layer 13 is read out to the floating diffusion layer 15.
  • a difference between the potential of the floating diffusion layer 15 after being reset at time T5 and the potential of the floating diffusion layer 15 after being read out at time T8 is detected by the column readout circuit 6 as a pixel signal.
  • the selection of the first row is completed by setting ⁇ SEL of the unit cell belonging to the first row to the low level.
  • the period from time T10 to T11 is a discharge period.
  • an electronic shutter that discharges unnecessary signal charges accumulated in the photoelectric conversion layer 12 to the charge discharging layer 14 is performed.
  • unnecessary charges generated in the photoelectric conversion layer 12 are removed from the charge discharging layer during a waiting time from when the signal charge is transferred to the charge storage layer 13 until reading to the floating diffusion layer 15 is started. 14 to discharge.
  • This electronic shutter is performed simultaneously for all pixels. Note that the number of electronic shutters performed in one frame is not particularly limited.
  • Reading of the second row is started from time T12, but the operation is the same as that of the first row, so the description is omitted.
  • FIG. 5 is a potential distribution diagram in one unit cell of the solid-state imaging device.
  • 5A to 5D show the potential distribution of the path from the transfer path shown in the AB section of FIG. 2 to the reset path
  • FIGS. 5A to 5D show FIGS.
  • the horizontal axis at the bottom of FIG. 5 indicates the position of each region from the back side white defect reducing layer 18 to the charge discharging layer 14 in FIG.
  • the vertical axis indicates the potential, and the potential is higher as it goes downward.
  • 5A and 5A ′ show the potential distribution during the accumulation period (FIG. 4, until time T1), and FIGS.
  • 5B and 5B ′ show the potential distribution during the transfer period (time T2 to T3 in FIG. 4).
  • (C) and (c) ′ are potential distributions in the readout period (time T7 to T8, T15 to T16 in FIG. 4), and
  • (d) and (d) ′ are electronic shutter periods (from time T10 in FIG. 4).
  • the potential distributions of T11, T18 to T19) are shown respectively. The operation of the solid-state imaging device of the present embodiment will be described with reference to these potential distribution diagrams.
  • the transfer wiring ⁇ TR is set to the high level (time T2 in FIG. 4), so that a high level voltage is applied to the transfer electrode 25.
  • the potential distribution of the transfer path changes from the dotted line to the solid line, and the bottom of the potential well formed in the charge storage layer 13 becomes deep.
  • the potential barrier of the transfer path potential barrier layer 19 disappears, and the signal charges accumulated in the photoelectric conversion layer 12 are transferred to the charge accumulation layer 13.
  • the potential gradient of the transfer path can be made steep, so that the signal charge can be transferred quickly.
  • the potential distribution of the discharge path does not change, and the potential barrier of the discharge path potential barrier layer 20 is maintained. Thereby, the signal charge accumulated in the photoelectric conversion layer 12 is transferred to the charge accumulation layer 13 without being discharged to the discharge path.
  • the readout wiring ⁇ RD is set to the high level (time T7 in FIG. 4), whereby a high level voltage is applied to the readout electrode 24.
  • the potential distribution of the read path changes from the dotted line to the solid line, and the potential barrier of the p-type diffusion layer 34 disappears. Accordingly, the signal charge stored in the charge storage layer 13 is read out to the floating diffusion layer 15.
  • the signal charge of the unit cell in the first row is read out until the signal charge of the unit cell in the last row is read out.
  • This is effective when signal charges are excessively accumulated in the photoelectric conversion layer 12 during the standby time.
  • this unnecessary signal charge can be discharged to the charge discharge layer 14 without flowing into the signal charge to be read stored in the charge storage layer 13.
  • the transfer path is formed by deepening the bottom of the potential well formed in the charge storage layer 13.
  • the potential gradient can be made steep. Therefore, it is difficult for signal charges to remain in the photoelectric conversion layer due to inability to transfer signal charges within the transfer time, and image quality degradation due to afterimages can be reduced.
  • the back side auxiliary electrode 23 is used as a light shielding film.
  • the back side auxiliary electrode 23 is used to further assist charge transfer and discharge during transfer and electronic shutter.
  • An example of using it as an electrode to which a voltage is applied is shown.
  • the description of the same content as the first embodiment is omitted.
  • FIG. 6 is a timing chart showing a driving method of the solid-state imaging device according to the second embodiment.
  • AX back-side auxiliary electrode 23
  • PVDD, ⁇ SEL, ⁇ RS, and ⁇ RD are set to high impedance.
  • FIG. 6 is a transfer period in which signal charges are transferred in the transfer path in the transfer period from time T2 to time T3 in FIG.
  • ⁇ TR is set to the high level
  • the potential of AX is set to the low level.
  • all of PVDD, ⁇ SEL, ⁇ RS, and ⁇ RD are set to high impedance (HiZ).
  • HiZ high impedance
  • the speed at which the potential of AX is set to the low level can be improved by electrically connecting AX (back surface side auxiliary electrode 23) with the front surface side auxiliary electrode 35 at the same potential. it can. Thereby, the charge transfer from the photoelectric conversion layer 12 to the charge storage layer 13 can be accelerated in the transfer period from the time T2 to the time T3.
  • the potential of AX is set to the low level during the discharge period from time T10 to T11.
  • ⁇ TR, ⁇ SEL, ⁇ RS, and ⁇ RD are all set to high impedance (HiZ).
  • HiZ high impedance
  • FIG. 7 is a potential distribution diagram in one unit cell of the solid-state imaging device according to the present embodiment.
  • 7A to 7D show potential distributions in the path from the transfer path shown in the AB cross section of FIG. 2 to the reset path, and FIGS. 7A to 7D show FIGS.
  • the horizontal axis at the bottom of FIG. 7 indicates the position of each region from the back side white defect reducing layer 18 to the charge discharging layer 14 in FIG.
  • the vertical axis indicates the potential, and the potential is higher as it goes downward.
  • 7 (a) and (a) ′ are accumulation periods (FIG.
  • a low level voltage is applied to the auxiliary electrode AX in accordance with the high level voltage being applied to the transfer electrode 25 (time T2 in FIG. 6).
  • the potential distribution of the transfer path changes from the dotted line to the solid line, the bottom of the potential well formed in the charge storage layer 13 becomes deeper, and the back side white that is electrically connected to the auxiliary electrode AX
  • the height of the potential barrier of the scratch reducing layer 18 is increased.
  • the potential gradient of the transfer path can be made steeper, so that signal charges can be transferred more quickly.
  • the readout period in FIGS. 7C and 7C is the same as that in the first embodiment.
  • the potential of the auxiliary electrode AX is set to the low level.
  • the potential distribution of the discharge path changes from the dotted line to the solid line, the bottom of the potential well formed in the charge discharging layer 14 becomes deeper, and the height of the potential barrier of the back side white defect reducing layer 18 increases. Get higher.
  • the potential gradient of the discharge path can be made steeper than that of the first embodiment, so that unnecessary signal charges can be discharged more quickly.
  • the operation of the auxiliary electrode AX is added at the time of discharging, it is possible to discharge the charge even at the mid level without changing the PVDD to the high level as in the first embodiment (time in FIG. 6). T10 to T11).
  • the voltage applied to the pixel power supply PVDD can be reduced, so that the oxide film covering each electrode such as the transfer electrode 25 provided on the front surface side of the semiconductor substrate 11 is destroyed, and the p-type / n-type region. It is possible to make the junction destruction between them difficult to occur. This makes it possible to reduce measures to ensure device reliability, such as increasing the oxide film thickness and relaxing the electric field between the p-type and n-type regions, allowing both device miniaturization and reliability to be achieved. It becomes.
  • ⁇ TR, ⁇ SEL, ⁇ RS, ⁇ RD, and FD are all high impedance. Therefore, the positions of the potential barrier and the potential well in the transfer path of FIG. 7D are increased because they are linked with the potential of the auxiliary electrode AX.
  • the back side auxiliary electrode 23 can be operated as a transfer auxiliary electrode and a discharge auxiliary electrode.
  • the height of the potential barrier of the back surface side white defect reducing layer 18 can be increased, and the potential gradient of the transfer path can be made steeper. Therefore, it is possible to further reduce the occurrence of afterimages as compared with the first embodiment.
  • it is possible to reduce the voltage applied to the pixel power supply PVDD at the time of charge discharge it is possible to reduce measures for ensuring the reliability of the element, and to achieve both miniaturization and reliability of the element. It becomes possible.
  • the present embodiment has been made to solve this problem, and a back-illuminated solid-state imaging device capable of reducing the generation of false signals due to photoelectric conversion occurring in the charge storage layer without providing a separate new configuration. It is to provide.
  • FIG. 8 shows the structure of the solid-state imaging device 130 according to this embodiment.
  • the transfer path potential barrier layer 19 and the discharge path potential barrier layer 20 are composed of a compound layer of silicon germanium (SiGe).
  • the transfer path potential barrier layer 19 and the discharge path potential barrier layer 20 are formed by, for example, SiGe 4 using a chemical vapor deposition method using SiH 4 as a Si material, GeH 4 as a Ge material, and B 2 H 6 as a p-type impurity material. It is possible to dope a p-type impurity in the layer simultaneously with the growth of the layer.
  • FIG. 9 shows absorption spectra near the absorption edges of silicon (Si) and germanium (Ge).
  • the horizontal axis represents light energy (eV), and the vertical axis represents the absorption coefficient (cm ⁇ 1 ).
  • Si exhibits an absorption coefficient of ⁇ 10 4 for light of 1.15 eV (1000 nm) to 2.7 eV (460 nm).
  • Ge exhibits an absorption coefficient of ⁇ 10 5 for light of 0.7 eV (1800 nm) to 2 eV (600 nm).
  • the absorption coefficient of Ge for light having a wavelength of 600 nm to 1000 nm is 10 times or more that of Si. That is, Ge means that light having a wavelength of 600 nm to 1000 nm is more easily absorbed than Si.
  • the transfer path potential barrier layer 19 and the discharge path potential barrier layer 20 with a compound layer containing Si and Ge, visible light having a long wavelength (around 600 nm to 780 nm) that has penetrated beyond the photoelectric conversion layer 12 is formed. Can be absorbed on the back side of the charge storage layer 13 and light incident on the charge storage layer 13 can be reduced. As a result, it is possible to suppress generation of a false signal due to photoelectric conversion occurring in the charge storage layer 13.
  • FIG. 10 shows the structure of the solid-state imaging device 140 according to this embodiment.
  • the difference from the third embodiment is that the region formed by the SiGe compound layer is extended from the transfer path potential barrier layer 19 and the discharge path potential barrier layer 20 to the end surface on the semiconductor substrate surface side.
  • the Ge concentration is gradually increased from the back surface side to the front surface side.
  • a compound layer with good crystallinity is formed by making the Ge concentration constant from the charge storage layer 13 to the substrate surface side. Even if the entire substrate is made thin by applying the SiGe layer to the region from the charge storage layer 13 to the substrate surface side, the light incident on the charge storage layer 13 as described in the third embodiment is used. It is possible to reduce the generation of false signals due to photoelectric conversion occurring in the charge storage layer 13.
  • the SiGe layer has a crystal lattice constant different from that of the Si layer, white defects due to lattice defects are more likely to occur compared to the Si layer. Therefore, in the regions of the transfer path potential barrier layer 19 and the discharge path potential barrier layer 20, it is necessary to increase the Ge concentration little by little so that lattice defects do not occur. Furthermore, in order to improve the reliability, when the photoelectric conversion layer 12 is formed in the n-type, it is desirable to form only the p-type region with the SiGe layer.
  • FIG. 11 shows the structure of the solid-state imaging device 150 according to this embodiment.
  • the difference from the fourth embodiment is that the SiGe compound layer is not formed up to the end surface on the substrate surface side, but the region in the vicinity of the substrate surface is formed of a compound layer of only Si or Ge.
  • the Ge concentration is gradually increased from the back surface side to the front surface side.
  • a compound layer with good crystallinity is formed by making the Ge concentration constant from the charge storage layer 13 to the substrate surface side.
  • region of the surface side from a SiGe layer is comprised with the compound layer of Si layer or Ge layer.
  • Si atoms grow while maintaining the lattice spacing of the SiGe layer. Since the Si layer has a smaller lattice constant than the SiGe layer, the Si layer is formed with a tensile stress applied. In the Si layer in this state, electron scattering is reduced and the effective mass of holes is reduced, so that the mobility of both is improved. Therefore, the mobility of signal charges is increased and the circuit operation speed is improved, so that signal charges can be read at high speed.
  • This configuration is effective, for example, for a next-generation high-definition television that requires a high-speed reading operation.
  • FIG. 12 shows an equivalent circuit diagram of a unit cell of the solid-state imaging device according to the sixth embodiment.
  • the difference from the first embodiment (FIG. 3) is that the pixel selection transistor M3 and the selection wiring ⁇ SEL are deleted.
  • FIG. 12 the same components as those in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted.
  • FIG. 13 shows an overall configuration diagram of a camera including a solid-state imaging device according to the present invention. A camera equipped with the solid-state imaging device described in the above embodiment will be described with reference to FIG.
  • the camera 700 is a camera represented by a digital still camera or a digital video camera.
  • the camera 700 includes a lens 40, an optical system 41, a solid-state image sensor 170, an image signal processing unit 43, and a timing control unit 42.
  • the lens 40 and the optical system 41 collect external light.
  • the solid-state image sensor 170 is a solid-state image sensor according to the first to sixth embodiments.
  • the solid-state imaging device 170 includes the TG control unit 7, the imaging area 1, and the output circuit 8 shown in FIG.
  • the solid-state imaging device 170 converts incident light into an image signal and outputs the image signal to the image signal processing unit 43.
  • the voltage pulses shown in the timing charts of FIGS. 4 and 6 are controlled by the TG control unit 7.
  • the image signal processing unit 43 includes a correlated double sampling circuit (CDS) 44, an OBC (Optical Black Clamp) 45, an AGC (Auto Gain Control) 46, an ADC (Analog Digital Converter) that receives the image signal output from the output circuit 8. ) 47, DSP (Digital Signal Processor) 48.
  • the image signal processing unit 43 processes the image signal output from the solid-state image sensor 170 and outputs the processed signal to an external device such as a display device.
  • the timing control unit 42 controls the timing of the circuit operation in the solid-state image sensor 170 and transfers signals between the solid-state image sensor 170 and the image signal processing unit 43.
  • the solid-state imaging device 170, the timing control unit 42, and the image signal processing unit 43 may be individually made into one chip, or may be made into one chip so as to include two or more.
  • the solid-state imaging device 170 and the image signal processing unit 43 may be formed on the same semiconductor chip, and the timing control unit 42 may be formed on one semiconductor chip.
  • FIG. 13 shows an example in which the image signal processing unit 43 is provided separately from the solid-state image sensor 170, the image signal processing unit 43 may be provided in the solid-state image sensor 170.
  • the signal charge is assumed to be an electron
  • the first conductivity type is assumed to be n-type
  • the second conductivity type is assumed to be p-type.
  • the same principle can be explained when the n-type is used as the type and the two conductivity types.
  • the present invention can be suitably used for electronic devices such as digital still cameras and digital video cameras that require high image quality, for example.

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Abstract

L'invention porte sur un dispositif capteur d'image à semi-conducteur du type à éclairage par l'arrière qui utilise la face arrière d'un substrat semi-conducteur à titre de face de réception de lumière incidente. Une détérioration de qualité d'image due à un effet de traînage est réduite. Le dispositif capteur d'image à semi-conducteur comprend une pluralité de cellules unitaires (2) disposées sous forme de matrice sur un substrat semi-conducteur (11), et la cellule unitaire (2) comprend : une couche de conversion photoélectrique du type n (12) ; une couche d'accumulation de charges électriques du type n (13) ; une couche barrière de potentiel de chemin de transfert du type p (19) ; et une électrode de transfert (25). L'électrode de transfert (25) est placée sur la surface du substrat semi-conducteur (11) à une position correspondant à la position de la couche d'accumulation de charges électriques (13), une couche isolante étant intercalée entre elles, ce qui rend la profondeur du puits de potentiel de la couche d'accumulation de charges électriques (13) par rapport au potentiel au niveau de la face arrière du substrat semi-conducteur (11) plus profonde lorsqu'une tension de transfert est appliquée que lorsqu'une tension de transfert n'est pas appliquée, ladite tension de transfert servant à transférer des charges électriques de signal accumulées au niveau de la couche de conversion photoélectrique (12) à la couche d'accumulation de charges électriques (13), et provoque l'extinction de la barrière de potentiel.
PCT/JP2010/004880 2009-12-14 2010-08-03 Dispositif capteur d'image à semi-conducteur et caméra le comprenant WO2011074156A1 (fr)

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