WO2011072016A1 - Procédé et système destinés à prendre en charge de multiples formats vidéo 3-d - Google Patents

Procédé et système destinés à prendre en charge de multiples formats vidéo 3-d Download PDF

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Publication number
WO2011072016A1
WO2011072016A1 PCT/US2010/059469 US2010059469W WO2011072016A1 WO 2011072016 A1 WO2011072016 A1 WO 2011072016A1 US 2010059469 W US2010059469 W US 2010059469W WO 2011072016 A1 WO2011072016 A1 WO 2011072016A1
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WIPO (PCT)
Prior art keywords
pixel data
view pixel
single frame
view
arrangement
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Application number
PCT/US2010/059469
Other languages
English (en)
Inventor
Darren Neuman
Jason Herrick
Christopher Payson
Qinghua Zhao
Original Assignee
Broadcom Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corporation filed Critical Broadcom Corporation
Priority to CN2010800296617A priority Critical patent/CN102474632A/zh
Priority to EP10836612.1A priority patent/EP2462748A4/fr
Publication of WO2011072016A1 publication Critical patent/WO2011072016A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/10—Processing, recording or transmission of stereoscopic or multi-view image signals
    • H04N13/106—Processing image signals
    • H04N13/139—Format conversion, e.g. of frame-rate or size
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N2213/00—Details of stereoscopic systems
    • H04N2213/007—Aspects relating to detection of stereoscopic image format, e.g. for adaptation to the display format

Definitions

  • Certain embodiments of the invention relate to video processing. More specifically, certain embodiments of the invention relate to a method and system for handling multiple 3-D video formats. BACKGROUND OF THE INVENTION
  • a system and/or method is provided for handling multiple 3-D video formats, substantially as illustrated by and/or described in connection with at least one of the figures, as set forth more completely in the claims.
  • FIG. 1 is diagram illustrating a video processing system, in accordance with an embodiment of the invention.
  • FIG. 2 is flow chart illustrating exemplary operation for converting between arrangements of 3-D pixel data, in accordance with an embodiment of the invention.
  • FIG. 3 is a diagram illustrating various arrangements of one or more frames comprising 3-D pixel data, in accordance with an embodiment of the invention.
  • FIG. 4A is a diagram illustrating reception and storage of a single-frame-left- right arrangement of 3-D pixel data, in accordance with an embodiment of the invention.
  • FIG. 4B is a diagram illustrating reception and storage of a single-frame-over- under arrangement of 3-D pixel data, in accordance with an embodiment of the invention.
  • FIG. 4C is a diagram illustrating reception and storage of a two-frame- sequential arrangement of 3-D pixel data, in accordance with an embodiment of the invention.
  • FIG. 5 A is a diagram illustrating reading 3-D pixel data from memory to generate a left-right- single-frame arrangement of 3-D pixel data, in accordance with an embodiment of the invention.
  • FIG. 5B is a diagram illustrating reading 3-D pixel data from memory to generate an over-under- single-frame arrangement of 3-D pixel data, in accordance with an embodiment of the invention.
  • FIG. 5C is a diagram illustrating reading 3-D pixel data from memory to generate a multi- frame arrangement of 3-D pixel data, in accordance with an embodiment of the invention.
  • FIG. 6 is a flow chart illustrating exemplary steps for 3-D video processing, in accordance with an embodiment of the invention.
  • a video processing system may receive one or more video frames comprising pixel data for a first 3- D view and pixel data for a second 3-D view, which may both be suitable for generating a three-dimensional (3-D) video frame.
  • the pixel data for the first 3-D view via may be referred to as the first 3-D view pixel data and the pixel data for the second 3-D view via may be referred to as the second 3-D view pixel data.
  • the video system may be operable to determine an arrangement of the first 3-D view pixel data and the second 3-D view pixel data in the one or more video frames.
  • the video processing system may be operable to convert the one or more video frames to the desired arrangement.
  • Either one or both of the determined arrangement and the desired arrangement may comprise a series of two single-view frames, and each of the single-view frames may comprise one of the first 3-D view pixel data and the second 3-D view pixel data.
  • Either or both of the determined arrangement and the desired arrangement may comprise a single frame comprising the first 3-D view pixel data and the second 3-D view pixel data.
  • the single frame may be arranged such that a left portion of the single frame comprises the first 3-D view pixel data and a right portion of the single frame comprises the second 3-D view pixel data.
  • the single frame may be arranged such that a top portion of the single frame comprises the first 3-D view pixel data and a bottom portion of the single frame comprises the second 3-D view pixel data.
  • the single frame may be arranged such that the first 3-D view pixel data is interleaved with the second 3-D view pixel data.
  • the converting may comprise writing the first 3-D view pixel data to one or more locations in memory identified by a first one or more pointers and/or writing the second 3-D view pixel data to one or more locations in memory identified by a second one or more pointers.
  • the converting may also comprise reading the first 3-D view pixel data and the second 3-D view pixel data from memory in an order that is different than an order in which the first 3-D view pixel data and the second 3-D view pixel data was written to memory.
  • the video system may receive the first 3-D view pixel data and second 3-D view pixel data via a first switching element that is operable to convey pixel data onto one or more of a plurality of data paths, and via a second switching element that is operable to convey pixel data from the plurality of data paths to memory, to the first switching element, and to a compositor. Which one or more of the data paths the left-view pixel data and the right-view pixel data is conveyed onto may be based on the determined arrangement and the desired arrangement.
  • 3-D view refers to one view (i.e., a left view or a right view) of a stereoscopic image
  • 3-D pixel data refers to pixel data of one or both views of a stereoscopic image
  • 3-D video refers to stereoscopic video.
  • FIG. 1 is diagram illustrating a video processing system, in accordance with an embodiment of the invention.
  • the video processing system 100 comprises video input interface 106, video feeder 108, MPEG feeder 110, multiplexers 112a and 112b, processing paths 114i - 114j, bypass paths 116i - 116 K , loopback paths 118i - 118L, capture module 120, compositor 122, memory 124, and the memory 126.
  • Each of J, K, and L is an integer greater than or equal to 1.
  • the system 100 may, for example, reside in a set-top box, a television, or a desktop or laptop computer.
  • the system 100 may be implemented in single semiconductor die or "chip."
  • a chip may comprise, for example, an ASIC or an FPGA.
  • the portion of the system 100 enclosed in the dashed line comprise a single-chip video processor.
  • Each of the the memory 124, and the memory 126 may comprise RAM, ROM, NVRAM, flash, a hard drive, or any other suitable memory device.
  • the memory 124, and memory 126 may be physically distinct memory elements of may be different portions and/or partitions of a single memory device.
  • the video input interface 106 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to receive a video stream and convey the pixel data of the video stream to the multiplexer 112a.
  • the video input interface 106 may comprise, for example, a VGA interface, composite video interface, component video interface, HDMI interface, DisplayPort interface, and/or other suitable interface and the video stream into the interface 106 may be formatted accordingly.
  • the received video stream may comprise monoscopic (2-D) video data and/or stereoscopic (3-D) video data. While this application focuses on processing of received 3-D video streams. Exemplary details of processing 2-D video streams are described in United States Patent Application No.
  • the video feeder 108 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to input pixel data corresponding to locally generated graphics to the multiplexer 112a.
  • the video feeder 108 may, for example, read pixel data out of the memory 126 and convey the pixel data to the multiplexer 112a.
  • the MPEG feeder 110 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to receive an MPEG stream and process the MPEG stream to output pixel data to the multiplexer 112a.
  • the MPEG stream may be received via a networking device (not shown).
  • Each of the multiplexers 112a and 112b may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to route pixel data between any one or more inputs of the multiplexer to any one or more outputs of the multiplexer. Pixel data input to the multiplexer 112a from any one of more of the interface 106, feeder 108, and the feeder 110 may be conveyed to any one or more of the processing paths 114i - 114j and/or any one or more of the bypass paths 116i - 116 ⁇ Each of the processing paths 114i - 114j may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to perform one or more processing functions.
  • Exemplary processing functions comprise scaling, subsampling, deinterlacing, blur/sharpen, color adjustment, and noise reduction.
  • Each of the bypass paths 116i - 116K may enable pixel data to be conveyed unchanged from the multiplexer 112a to the multiplexer 112b.
  • Each of the loopback paths 1181 - 118L may enable pixel data to be conveyed from the multiplexer 112b to the multiplexer 112a. In this manner, the loopback paths may, for example, enable processing the same pixel data via multiple ones of the processing paths 114i - 114j.
  • the capture module 120 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to write 3-D pixel data to the memory 126.
  • the capture module 120 may be operable to write first 3-D view pixel data to the memory 126 utilizing a first one or more memory pointers.
  • the capture module 120 may be operable to write second 3-D view pixel data to the memory 126 utilizing a second one or more memory pointers.
  • First 3-D view pixel data may be left-view data
  • second 3-D view pixel data may be right-view pixel data, or visa-versa.
  • left-view pixel data may be captured via a left lens of a video camera and right-view pixel data may be captured via a right lens of the video camera.
  • the compositor 122 may comprise suitable logic, circuitry, interfaces, and/or code that may be operable to generate an output video stream which may be output via, for example, a VGA output, composite video output, component video output, HDMI output, and/or DisplayPort output.
  • the output video stream may comprise pixel data received from the multiplexer 112b and/or pixel data read from memory 124.
  • the compositor 122 may be operable to concurrently present pixel data from the memory 124 and pixel data from the multiplexer 112b. For example, graphics from the memory 124 may be overlaid on the pixel data from the multiplexer 112b.
  • the output video stream may comprise monoscopic (2-D) video data and/or stereoscopic (3-D) video data. While this application focuses on outputting 3-D video streams. Exemplary details of processing 2-D video streams are described in United States Patent Application No. (Attorney Docket No.
  • one or more 3-D video frames may be input to the system 100 via one or more of the interface 106, the feeder 108, and the feeder 110.
  • Each of the one or more input frames may comprise live-action images and/or computer-generated images.
  • the input frame(s) may comprise left-view pixel data and right-view pixel data.
  • the arrangement of the input frame(s) may correspond to any one of the arrangements described below with respect to FIG. 3.
  • the arrangement of the input frame(s) may be determined in any of a variety of ways.
  • the system 100 may determine the arrangement of the input frame(s) based on the source from which the one or more frames was received, based on a state of one or more control signals in the system 100, and/or based on inspection the input frame(s).
  • the multiplexer 112a may convey the received frame(s) to the multiplexer 112b via one or more of the processing paths 1 14i - 114j and/or one or more of the bypass paths 116i - 116 ⁇
  • the frame(s) may make multiple passes from the multiplexer 112a to the multiplexer 112b and thus may traverse one or more of the loopback paths 118i - 118 L .
  • the frame(s) may be conveyed to the capture module 120.
  • the capture module 120 may write the left- view pixel data and right- view pixel data to the memory 126.
  • the left- view pixel data may be written to one or more memory locations identified by a first one or more pointers.
  • the right-view pixel data may be written to one or more memory locations identified by a second one or more pointers.
  • the feeder module 108 may read the left-view and right- view pixel data from the memory 126 to generate one or more output frames.
  • the first one or more pointers and the second one or more pointers may be utilized for reading the pixel data out from the memory 126.
  • the order in which the pixel data is read from memory may depend on the arrangement of the input frame(s) and the desired arrangement of the output frame(s). In this regard, the arrangement of the output frame read from the memory 126 may correspond to any of the arrangements described below with respect to FIG. 3.
  • the pixel data may be read out of the memory 126 in the same order in which it was written to the memory 126.
  • the pixel data may be read out of the memory 126 in a different order than which it was written to the memory 126.
  • the output frame(s) may be conveyed to the compositor 122. In some instances, prior to being conveyed to the compositor 122, the output frame(s) may be conveyed to the multiplexer 112a for one or more traversals of one or more of the processing paths 114i - 114j, bypass paths 116i - 116K, and/or loopback paths 118i— 118L.
  • the compositor 122 may process the output frame(s) to make the output frame(s) suitable for insertion into a video stream.
  • the video stream may be formatted so as to be compatible with one or more video standards such as VGA, composite video, component video, HDMI, and/or DisplayPort.
  • Processing of the output frame(s) may comprise combining the output frame(s) from the multiplexer 112b with pixel data from memory 124. For example, graphics may be read from the memory 124 and overlaid on the output frame(s) from the multiplexer 112b.
  • FIG. 2 is flow chart illustrating exemplary operation for converting between arrangements of 3-D pixel data, in accordance with an embodiment of the invention. Referring to FIG. 2, the exemplary steps begin with step 202 in which an input frame is conveyed to the multiplexer 112a.
  • step 204 it is determined whether the input frame(s) are to traverse one or more of the processing paths 114i - 114j or traverse one or more of the bypass paths 116i— 116 ⁇ In instances that the input frame(s) are to traverse one or more of the processing paths 114i — 114j, then in step 224, processing, such as scaling and/or deinterlacing, may occur.
  • processing such as scaling and/or deinterlacing
  • step 206 the input frame(s) are conveyed to the multiplexer 112b.
  • step 208 it is determined whether the input frame(s) are to be looped-back to multiplexer 112a for another traversal of one or more of the processing paths processing paths 114i - 114j and/or one or more of the bypass paths 116i - 116 ⁇
  • the exemplary steps may return to step 202.
  • the exemplary steps may advance to step 210.
  • the input frame(s) are captured to the memory 126.
  • the first 3-D pixel data of the input frame(s) may be stored to memory location(s) indicated by a first one or more memory pointers.
  • the second 3-D view pixel data of the input frame(s) may be stored to memory location(s) indicated by a second one or more memory pointers.
  • step 212 the left- view pixel data and right- view pixel data is read from the memory 126 to generate one or more output frame(s).
  • the order in which the data is read from the memory 126 may depend on the desired arrangement of the output frame(s).
  • step 214 it is determined whether the output frame(s) are be processed by one or more of the processing paths 114i - 114j. In instances that the output frame(s) are to be processed, then the exemplary steps may advance to step 226.
  • step 226 the output frame(s) are communicated to the multiplexer 112a.
  • step 228, the output frame(s) are conveyed onto one or more of the processing paths 114i - 114j for processing, such as scaling and/or noise reduction.
  • the output frame(s) may arrive at the multiplexer 112b.
  • step 232 it may be determined whether the output frame(s) are to be looped-back to multiplexer 112a for another traversal of one or more of the processing paths processing paths 114i - 114j and/or one or more of the bypass paths 116i - 116 ⁇ In instances that the output frame(s) are to be looped-back, the exemplary steps may return to step 226. In instances that the output frame(s) are not to be looped-back, the exemplary steps may advance to step 216.
  • step 216 the output frame(s) arrive at the multiplexer 112b.
  • step 218 the output frame(s) are conveyed to the compositor 122.
  • the compositor may process the output frame(s) to make them suitable for insertion into a video stream. Processing the output frame(s) may comprise combining the output frame(s) from the multiplexer 112b with pixel data from memory 124. For example, graphics may be read from the memory 124 and overlaid on the output frame(s) from the multiplexer 112b.
  • the video stream may be communicated to another video device, such as a television or monitor.
  • the video stream may, for example, be formatted in accordance with one or more video standards such as VGA, composite video, component video, HDMI, and/or DisplayPort.
  • FIG. 3 is a diagram illustrating various arrangements of one or more frames comprising 3-D pixel data, in accordance with an embodiment of the invention.
  • a two-frame-sequential arrangement 302 a left-right-single-frame arrangement 304, an over-under-single-frame arrangement 306, a vertically-interleaved- single-frame arrangement 308, a horizontally-interleaved-single-frame arrangement 310, and a vertically-and-horizontally-interleaved-single-frame arrangement 312.
  • each of N and M may be any positive integer.
  • the two-frame-sequential arrangement 302 comprises a first frame comprising first 3-D view pixel data and a second frame comprising second 3-D view pixel data.
  • the two frames may be received by the system 100 sequentially. That is, the first frame may be received earlier in time before the second frame.
  • the left portion of the left-right-single-frame arrangement 304 may comprise first 3-D view pixel data and the right portion of the left-right single-frame arrangement 304 may comprise second 3-D view pixel data.
  • An exemplary 4M x 4N left-right-single-frame arrangement is described in table 1 below.
  • the top portion of the over-under-single-frame arrangement 306 may comprise first 3-D view pixel data and the bottom portion of the over-under- single-frame arrangement 306 may comprise second 3-D view pixel data.
  • An exemplary 4M x 4N over- under-single-frame arrangement is described in table 2 below.
  • the vertically-interleaved-single-frame arrangement 308 may alternate between one or more lines of left-view pixel data and one or more lines of right-view pixel data.
  • An exemplary 4M x 4N vertically-interleaved-single-frame arrangement is described in table 3 below.
  • the horizontally-interleaved-single-frame arrangement 310 may alternate between one or more columns of left-view pixel data and one or more columns of right-view pixel data.
  • An exemplary 4M x 4N horizontally-interleaved-single-frame arrangement is described in table 4 below.
  • the first 3-D view and second 3-D view pixel data may be interleaved in both a vertical and horizontal direction.
  • An exemplary 4M x 4N horizontally-interleaved-single-frame arrangement is described in table 4 below.
  • Table 5 Vertically-and-Horizontally-Interleaved-Single-Frame Arrangement
  • FIG. 4A is a diagram illustrating reception and storage of a single-frame-left- right arrangement of 3-D pixel data, in accordance with an embodiment of the invention.
  • a 4x2 left-right-single-frame arrangement 402 being written to the memory 126.
  • the pixel data may be written to the memory 126 in the order in which it was received.
  • the pixel data may be received line by line with each line being received from left to right. That is, pixel data may arrive in the following order: column 1 line 1, column 2 line 1, column 3 line 1, column 4 line 1, column 1 line 2, column 2, line 2, column 3, line 3, column 4 line 4.
  • First 3-D view pixel data may be written to the location(s) 150a of the memory 126 and second 3-D view pixel data may be written to the location(s) 150b of the memory 126.
  • the location(s) 150a may be identified by a first one or more memory pointers and the location(s) 150b may be identified by a second one or more memory pointers.
  • first 3-D view pixel data and second 3-D view pixel data are depicted as being written to the same memory, the invention is not so restricted. For example, first 3-D view pixel data may be written to a first memory and second 3-D view pixel data may be written to a second memory.
  • FIG. 4B is a diagram illustrating reception and storage of a single-frame-over- under arrangement of 3-D pixel data, in accordance with an embodiment of the invention.
  • a 2x4 over-under-single-frame arrangement 406 being written to the memory 126.
  • the pixel data may be written to the memory 126 in the order in which it was received.
  • the pixel data may be received line by line, with each line being received from left to right. That is, pixel data may arrive in the following order: column 1 line 1, column 2 line 1, column 1 line 2, column 2 line 2, column 1 line 3, column 2, line 3, column 1, line 4, column 2 line 4.
  • First 3-D view pixel data may be written to the location(s) 150a of the memory 126 and second 3-D view pixel data may be written to the location(s) 150b of the memory 126.
  • the location(s) 150a may be identified by a first one or more memory pointers and the location(s) 150b may be identified by a second one or more memory pointers.
  • first 3-D view pixel data and second 3-D view pixel data are depicted as being written to the same memory, the invention is not so restricted. For example, first 3-D view pixel data may be written to a first memory and second 3-D view pixel data may be written to a second memory.
  • FIG. 4C is a diagram illustrating reception and storage of a two-frame- sequential arrangement of 3-D pixel data, in accordance with an embodiment of the invention.
  • a 2x2 frame 408a comprising first 3-D view pixel data
  • 2x2 frame 408b comprising second 3-D view pixel data being written to the memory 126.
  • the pixel data may be written to the memory 126 in the order in which it was received.
  • frame 408a may be received before frame 408b.
  • Each frame may be received line by line, with each line being received from left to right.
  • pixel data may arrive in the following order: column 1 line 1 of frame 408a, column 2 line 1 of frame 408a, column 1 line 2 of frame 408a, column 2 line 2 of frame 408a, column 1 line 1 of frame 408b, column 2 line 1 of frame 408b, column 1 line 2 of frame 408b, and column 2 line 2 of frame 408b.
  • First 3-D view pixel data may be written to the location(s) 150a of the memory 126 and second 3-D view pixel data may be written to the location(s) 150b of the memory 126.
  • the location(s) 150a may be identified by a first one or more memory pointers and the location(s) 150b may be identified by a second one or more memory pointers.
  • first 3-D view pixel data and second 3-D view pixel data are depicted as being written to the same memory, the invention is not so restricted.
  • first 3-D view pixel data may be written to a first memory and second 3-D view pixel data may be written to a second memory.
  • FIG. 5A is a diagram illustrating reading 3-D pixel data from memory to generate a left-right- single-frame arrangement of 3-D pixel data, in accordance with an embodiment of the invention.
  • a 4x2 left-right-single- frame arrangement 502 being read from the memory 126.
  • the pixel data may be read from memory line by line, with each line being read from left to right.
  • FIG. 5B is a diagram illustrating reading 3-D pixel data from memory to generate an over-under- single-frame arrangement of 3-D pixel data, in accordance with an embodiment of the invention. Referring to FIG. 5B, there is shown a 2x4 over-under-single- frame arrangement 506 being read from the memory 126.
  • the pixel data may be read from memory line by line, with each line being read from left to right. That is, pixel data may be read in the following order: first 3-D view pixel data may be read out for column 1 line 1, then column 2 line 1, then column 1 line 2, then column 2 line 2. Second 3-D view pixel data may then be read out for column 1 line 3, then column 2, line 3, then column 1, line 4, then column 2 line 4.
  • FIG. 5C is a diagram illustrating reading 3-D pixel data from memory to generate a two-frame-sequential arrangement of 3-D pixel data, in accordance with an embodiment of the invention.
  • 2x2 frames 508a and 508b being read from the memory 126.
  • the pixel data may be read from memory line by line, with each line being read from left to right. That is, pixel data may be read in the following order: first 3-D view pixel data may be read out for column 1 line 1 of frame 508a, then column 2 line 1 of frame 508a, then column 2 line 1 of frame 508a, then column 2 line 2 of frame 508a. Subsequently, second 3-D view pixel data may be read out for column 1 line 1 of frame 508b, then column 2 line 1 of frame 508b, then column 2 line 1 of frame 508b, then column 2 line 2 of frame 508b.
  • FIG. 6 is a flow chart illustrating exemplary steps for 3-D video processing, in accordance with an embodiment of the invention.
  • the system 100 may be configured to select an output frame arrangement.
  • the output frame arrangement may be selected based on, for example, the device(s) from which the system 100 receives a video stream and/or the device(s) to which the system 100 outputs a video stream.
  • the system 100 may receive one or more frames comprising 3-D pixel data.
  • the arrangement of the input frame(s) may be any of the arrangements described with respect to FIG. 3.
  • the system 100 may determine the arrangement of the input frame(s).
  • This determination may be based on, for example, an inspection of the input frame(s), the source from which the frame(s) were received, and/or based on a pre-configuration of the system 100.
  • the input frame(s) may be processed, if necessary. The processing may comprise, for example, scaling, de-interlacing, noise reduction, and/or chroma subsampling.
  • the pixel data of the input frame(s) may be stored to memory, with first 3-D view pixel data being stored to one or more locations identified by a first one or more pointers and second 3-D view pixel data being stored to one or more locations identified by a second one or more pointers.
  • the pixel data may be read from memory to generate one or more output frames.
  • the arrangement of the output frame(s) may be any of the arrangements described with respect to FIG. 3.
  • the output frame(s) may be processed, if necessary. The processing may comprise, for example, scaling, de- interlacing, noise reduction, and/or chroma subsampling.
  • the output frame may be processed for insertion into a video stream, and inserted into the video stream.
  • the video stream may be communicated to, for example, a television or monitor.
  • a video processing system 100 may receive one or more video frames, such one or more of the frames 402, 406, 408a and 408b, comprising first 3-D view pixel data and second 3-D view pixel data suitable for generating a three-dimensional (3-D) video frame.
  • the video system 100 may be operable to determine an arrangement of the first 3-D view pixel data and the second view pixel data in the one or more video frames, where the arrangement corresponds to one of the arrangements 302 - 312. In instances that the determined arrangement is not a desired arrangement, the video processing system 100 may be operable to convert the one or more video frames to the desired arrangement. Either or both of the determined arrangement and the desired arrangement may be the arrangement 302 and may comprise a series of two single-view frames, each of the single -view frames comprising one of the first 3-D view pixel data and the second 3-D view pixel data.
  • Either or both of the determined arrangement and the desired arrangement may be one of the arrangements 304 - 312 and comprise a single frame comprising the first 3-D view pixel data and the second 3-D view pixel data.
  • the single frame may be arranged as arrangement 304 and a left portion of the single frame may comprise the first 3-D view pixel data and a right portion of the single frame may comprise the second 3-D view pixel data.
  • the single frame may be arranged as arrangement 306 and a top portion of the single frame may comprise the first 3-D view pixel data and a bottom portion of the single frame may comprise the second 3-D view pixel data.
  • the single frame may be arranged as one of arrangements 308, 310, and 312 and may comprise the first 3-D view pixel data interleaved with the second 3-D view pixel data.
  • the converting may comprise writing the first 3-D view pixel data to one or more locations 150a in the memory 126 identified by a first one or more pointers.
  • the converting may comprise writing the second 3-D view pixel data to one or more locations 150b in the memory 126 identified by a second one or more pointers.
  • the converting may comprise reading the first 3-D view pixel data and the second 3-D view pixel data from memory in an order that is different than an order in which the first 3-D view pixel data and the second 3-D view pixel data was written to memory.
  • the video processing system 100 may receive the first 3-D view pixel data and second 3-D view pixel data via a first switching element 112a that is operable to convey pixel data onto one or more of a plurality of data paths 114i - 114j and/or 116i - 116K, and via a second switching element 112b that is operable to convey pixel data from the plurality of data paths 114i - 114j and/or 116i - 116K to the memory 126 (via capture module 120), to the first switching element 112a, and to the compositor 122.
  • a first switching element 112a that is operable to convey pixel data onto one or more of a plurality of data paths 114i - 114j and/or 116i - 116K
  • a second switching element 112b that is operable to convey pixel data from the plurality of data paths 114i - 114j and/or 116i - 116K to the memory 126 (via capture module 120
  • Which one or more of the data paths 114i - 114j, 116i - 116K and/or 118i - 118L and/or the left- view pixel data and the right- view pixel data is conveyed onto may be based on the determined arrangement and the desired arrangement.
  • FIG. 1 may depict a non-transitory computer readable medium and/or storage medium, and/or a non-transitory machine readable medium and/or storage medium, having stored thereon, a machine code and/or a computer program having at least one code section executable by a machine and/or a computer, thereby causing the machine and/or computer to perform the steps as described herein for handling multiple 3-D video formats.
  • the present invention may be realized in hardware, software, or a combination of hardware and software.
  • the present invention may be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited.
  • a typical combination of hardware and software may be a general-purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.
  • the present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods.
  • Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Television Systems (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
  • Studio Circuits (AREA)
  • Image Processing (AREA)

Abstract

Cette invention se rapporte à des aspects d'un procédé et d'un système destinés à prendre en charge de multiples formats vidéo 3-D. Un système de traitement vidéo peut recevoir une ou plusieurs trames vidéo qui comprennent des données de pixels d'une première vue 3-D et des données de pixel d'une seconde vue 3-D appropriées de façon à générer une trame vidéo tridimensionnelle (3-D). Le système vidéo peut être fonctionnel de façon à déterminer un agencement des données de pixel de la première vue 3-D et des données de pixel de la seconde vue 3-D dans la ou les trames vidéo. Dans des instances où l'agencement déterminé n'est pas un agencement désiré, le système de traitement vidéo peut être fonctionnel de façon à convertir la ou les images vidéo en un agencement souhaité. L'agencement déterminé et/ou l'agencement souhaité peuvent comprendre une série de deux trames à une seule vue. L'agencement déterminé et/ou l'agencement souhaité peuvent comprendre une seule trame qui comprend les données de pixels d'une première vue 3-D et des données de pixel d'une seconde vue 3-D.
PCT/US2010/059469 2009-12-08 2010-12-08 Procédé et système destinés à prendre en charge de multiples formats vidéo 3-d WO2011072016A1 (fr)

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CN2010800296617A CN102474632A (zh) 2009-12-08 2010-12-08 处理多个3-d视频格式的方法和系统
EP10836612.1A EP2462748A4 (fr) 2009-12-08 2010-12-08 Procédé et système destinés à prendre en charge de multiples formats vidéo 3-d

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US26772909P 2009-12-08 2009-12-08
US61/267,729 2009-12-08
US29685110P 2010-01-20 2010-01-20
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US20110134218A1 (en) 2011-06-09
US9307223B2 (en) 2016-04-05
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US20150341613A1 (en) 2015-11-26
US20110134217A1 (en) 2011-06-09
US20110134216A1 (en) 2011-06-09
EP2462748A4 (fr) 2013-11-13
US8947503B2 (en) 2015-02-03
US20110134212A1 (en) 2011-06-09
US9137513B2 (en) 2015-09-15
EP2462748A1 (fr) 2012-06-13

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