Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/02—Containers; Seals
  • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C3/00—Assembling of devices or systems from individually processed components
  • B81C3/001—Bonding of two components
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
  • B81B2203/00—Basic microelectromechanical structures
  • B81B2203/01—Suspended structures, i.e. structures allowing a movement
  • B81B2203/0118—Cantilevers
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C2203/00—Forming microstructural systems
  • B81C2203/01—Packaging MEMS
  • B81C2203/0118—Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C2203/00—Forming microstructural systems
  • B81C2203/03—Bonding two components
  • B81C2203/033—Thermal bonding
  • B81C2203/035—Soldering
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

• MEMS micro electromechanical systems
• MEMS have become very important in providing certain functions such as accelerometers and gyroscopes in a very small space.
• automotive applications where this is very useful from relatively simple applications such as air bags to very sophisticated guidance assist functions.
• precision can be important.
• the MEMS devices themselves have elements that move and this movement is detected through capacitive coupling.
• the predictability of this capacitive coupling is useful in providing precision to the function being performed.
• the capacitance coupling may not be just within the same MEMS layer but may include coupling to another layer which may be above or below the MEMS layer. In either case the other layer may be incorporated into a capping wafer.
• the MEMS wafer and the capping wafer work together in achieving the overall desired functionality. This working together may require both electrical connection by contact and capacitive coupling. Both are important and it is desirable for both to have all of the characteristics known to be important in manufacturing a product. This includes being reliable, manufacturable, low cost, and precise.
• FIG. 1 is a cross section of a portion of a MEMS device at a stage in processing according to an embodiment
• FIG. 2 is a cross section of the portion of the MEMS device of FIG. 1 at a subsequent stage in processing
• FIG. 3 is a cross section of the portion of the MEMS device of FIG. 2 at a subsequent stage in processing
• FIG. 4 is a cross section of the portion of the MEMS device of FIG. 3 at a subsequent stage in processing
• FIG. 5 is a cross section of the portion of the MEMS device of FIG. 4 at a subsequent stage in processing
• FIG. 6 is a cross section of the portion of the MEMS device of FIG. 5 at a subsequent stage in processing
• FIG. 7 is a cross section of the portion of the MEMS device of FIG. 6 at a subsequent stage in processing
• FIG. 8 is a cross section of the portion of the MEMS device of FIG. 7 at a subsequent stage in processing
• FIG. 9 is a cross section of the portion of the MEMS device of FIG. 8 and an additional portion of the MEMS device at a subsequent stage in processing;
• FIG. 10 is a cross section of the portion of the MEMS device of FIG. 9 and the additional portion of the MEMS device at a subsequent stage in processing;
• FIG. 1 1 is a cross section of the portion of the MEMS device of FIG. 10 and the additional portion of the MEMS device at a subsequent stage in processing.
• micro electromechanical systems include a contact that is for contacting a capping device.
• the contact has a center portion that includes a supporting portion above a top plane of the MEMS device with a bonding portion on it.
• the supporting portion is surrounded by a space stop also above the top plane of the MEMS device.
• the supporting portion and the space stop are the same height above the top plane.
• the space stop may be higher than the supporting portion. It is beneficial for the height of the space stop above the top plane be established by a deposition rather than an etch because an etch is more difficult to control.
• the space stop establishes a distance between the top plane and a subsequently attached capping device. By so doing the established distance is useful in controlling the amount of capacitance between a capacitor plate on the MEMS and a capacitor plate on the capping device.
• the semiconductor substrate described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon- on-insulator (SOI), polysilicon, monocrystalline silicon, the like, and combinations of the above.
• FIG. 1 Shown in FIG. 1 is a contact region 10 of a MEMS device comprising a substrate
• interconnect region 14 may be considered a top plane 15 of the MEMS device.
• Insulating layer 16 may be of oxide and relatively thin, for example 1000 Angstroms. In this example interconnect region 14 may be about 25 microns thick. Insulating layer 13 may be oxide about one micron thick.
• Substrate 12 is preferably silicon, is for mechanical support, and may be called a handle wafer, or more particularly from a handle wafer.
• etch stop regions 18 and 20 appear to be separate regions spaced apart but are one continuous region encircling the region as shown between etch stop regions 18 and 20. Outside of etch regions 18 and 20 are additional etch stop regions 19 and 21 left from the etch of insulating layer 16 which similarly are actually different cross sections of a continuous layer spaced from etch stop regions 18 and 20.
• contact region 10 Shown in FIG. 3 is contact region 10 after depositing a conductive layer 22 over interconnect region 14 and etch stop regions 18, 19, 20, and 21 which is doped to be conductive.
• Polysilicon layer 22 may be about 5 microns thick.
• Conductive layer 22 may be polysilicon that is doped. The doping may be in situ or by implanting or even both.
• SiGe layer 24 may be graded beginning with a very low concentration of germanium and ending with a significant higher, even 100 per cent, germanium concentration.
• Germanium layer 28 may be about a half of a micron thick.
• SiGe layer may be simply one concentration of Germanium, for example 50 percent by atomic weight.
• Polysilicon layer 24 is useful for being doped for optimizing the deposition of the subsequent layer, SiGe layer 24.
• SiGe layer 26 and germanium layer 28 are for use in making a contact by eutectic bonding.
• Germanium has sufficiently low temperature at which it will form a eutectic bond with aluminum to make it effective for the purpose of forming a contact in that manner.
• SiGe layer 26 provides a transition from contacting silicon at polysilicon layer 22 to the germanium at germanium layer 28.
• contact region 10 Shown in FIG. 5 is contact region 10 after removing a portion of SiGe layer 26 and germanium layer 28. The boundary of the remaining portion is aligned to etch stop regions 18 and 20. The primary purpose of this etch is that SiGe layer 26 and germanium layer 28 are removed from the areas immediately outside etch stop regions 18 and 20.
• FIG. 6 Shown in FIG. 6 is a contact region 10 after forming and patterning a photoresist layer to leave photoresist portions 30, 32, and 34. As shown, an opening 36 is formed between photoresist portions 30 and 32 and an opening 38 is formed between photoresist portions 32 and 34. In cross section openings 36 and 38 appear to be different openings, openings 36 and 38 are part of one continuous opening that surrounds photoresist portion 32. Photoresist portion 32 is nearly aligned to the inner edges of etch stop regions 18 and 20 but extends to being at least a small amount over etch stop regions 18 and 20.
• photoresist portions 30 and 34 have an outer edge that extends to being at least a small amount over etch stop regions 19 and 21 , respectively, and photoresist portions 30 and 34 have an inner edge that extends to being at least a small amount over etch stop regions 18 and 20, respectively.
• FIG. 7 Shown in FIG. 7 is contact region 10 after performing an etch to extend openings 36 and 38 into conductive region 22 to leave conductive portions 40, 42, and 44.
• Etch stop regions 18, 19, 20, and 21 prevent the etch from extending into interconnect region 14.
• the etch composition does etch germanium and SiGe so that the small portion of SiGe and germanium exposed from outside photoresist portion 32 is etched.
• Conductive portions 40 and 42 appear to be different regions in cross section but actually extend around conductive portion 42. Thus there is a continuous ring, which may be polysilicon, around conductive portion 42.
• Conductive portions 40 and 42 are the same height above top plane 15. This height above plane 15 is established by the deposition of layer 22.
• This height is not subsequently effected in a meaningful way by an subsequent etch.
• the etch that removes SiGe layer 26 and geramanium layer 28 is selective to polysilicon. During the overetch, there is some minimal etching, likely to be enough to remove the 100 Angstroms of layer 24, but 100 Angstroms out a thickness of 5 microns is only about 0.2 percent.
• contact region 10 after etching away etch stop regions 18, 19, 20, and 21 .
• This may be a wet etch or a vapor phase etch.
• Capacitor region 10 Shown in FIG. 9 is contact region 10 in addition to a capacitor region 46 that is adjacent to interconnect region 14.
• Capacitor region 76 comprises a cavity 48 over substrate 12 and a movable member 50, which may be polysilicon, connected to
• movable member 50 is held in place by
• interconnect region 14 is movable up and down in the vertical direction as viewed in FIG. 9.
• Contact region 10 and capacitor region 46 together may be considered a MEMS 49.
• MEMS 49 MEMS In a typical MEMS device there will be many more contact regions and capacitor regions. Also the proximity of contact and interconnect regions are unlikely to be as close as that suggested by FIG. 9.
• the particular way a movable member is arranged relative to other features is widely variable, but a movable member is will typically be in a cavity so that is movable but is also supported in some form.
• Capping wafer 51 comprises a functional region 52 having a bottom surface 53, a contact region 54 on bottom surface 53, and a capacitor plate 56 on bottom surface 53.
• Contact region 54 and capacitor plate 56 are preferably aluminum about 2 microns thick.
• Contact region 54 is aligned to be centered around conductive portion 42 and extending over conductive portions 40 and 44, and capacitor plate 56 is aligned to movable member 50.
• FIG. 1 1 Shown in FIG. 1 1 is a device 57 formed by connected MEMS 49 to capping wafer 51 using heat and pressure to form a eutectic bond 60 between contact region 54 and conductive portion 42 using a bonding material 58 resulting from SiGe layer 26, germanium layer 28 and a portion of contact region 54.
• the eutectic process results in bonding material 58 partially filling openings 36 and 38.
• the process distorts contact region 54.
• the process has minimal effect on the outer portions of contact region 54 that press down on conductive portions 40 and 44 of polysilicon.
• Movable member 50 when moving, will change its distance, and thus capacitance, from capacitor plate 56 and such change will be from distance 64, which is highly controllable as being set by a deposition of polysilicon.
• distance 64 is the same as height 64, but they could be different with benefits remaining the same.
• the top surface of movable member could be a known variation from top plane 15.
• the thickness of capacitor plate 56 could vary from the thickness of contact region 54 by a known amount with result of having the same predictability of distance 64.
• conductive portions 40 and 44 provide a seal around eutectic bond 60.
• Bond material 58 is contained within the distortion of contact region 60, conductive portions 40, 42, and 44, and the top surface of interconnect region 14.
• the method includes providing a cap substrate.
• the method further includes providing a support substrate.
• the method further includes depositing a conductive material over the support substrate.
• the method further includes patterning the conductive material to leave a conductive portion that forms a gap stop and a contact, wherein the gap stop is separated form the contact by an opening.
• the method further includes forming a bonding material over the contact and in the opening, wherein the gap stop and the contact prevent the bonding material from extending outside the opening.
• the method further includes attaching the cap substrate to the support substrate by the step of forming the bonding material.
• the method may have a further characterization by which forming the bonding material comprises forming a semiconductor layer over the conductive material and heating the cap substrate and the semiconductor layer to form the bonding material and bond the cap substrate to the support substrate.
• the method may forming a stack over the conductive portion wherein the step of forming the semiconductor layer is part of the step of forming the stack.
• the method may have a further characterization by which the step of forming the stack over the conductive portion further comprises forming a seed layer comprising silicon over the conductive portion and forming a first layer comprising silicon and germanium over the seed layer, and the step of forming the semiconductor layer, further comprises forming a second layer comprising germanium over the first layer.
• the method may further comprise patterning the stack before the step of patterning the conductive material.
• the method may further comprise forming an oxide over the conductive material, patterning the oxide before the step of forming the stack over the conductive material, and removing the oxide after the step of patterning the conductive material.
• the method may have a further characterization by which providing the cap substrate further comprises providing a cap substrate having an aluminum layer formed in contact with one surface of the cap substrate and wherein after the step of forming the bonding material, the aluminum layer is in contact with the bonding material.
• the method may have a further characterization by which the bonding material comprises a eutectic material comprising aluminum and germanium.
• the method may have a further characterization by which the step of depositing the conductive material further comprises depositing doped polysilicon.
• the method may have a further characterization by which the step of attaching the cap substrate to the support substrate further comprises forming a capacitor in an area of the cap substrate and the support substrate.
• the method includes providing a first structure, wherein the first structure comprises a cap wafer and a first conductive material formed on an edge of the cap wafer.
• the method further includes providing a second structure, wherein the step of providing the second structure comprises providing a support wafer, depositing a second conductive material over the support wafer, patterning the second conductive material to form an opening in the second conductive material, a gap stop, and a contact, wherein the opening is between the gap stop and the contact, and forming a semiconductor stack over the contact.
• the method further includes bonding the first structure to the second structure by heating the semiconductor layer so it flows into the opening and the gap stop and the contact stop the semiconductor layer from flowing outside of the opening.
• the method may have a further characterization by which the step of heating the semiconductor layer comprises heating the semiconductor stack to form a eutectic bonding material.
• the method may have a further characterization by which the step of forming the semiconductor stack comprises forming a seed layer comprising silicon over the second conductive material, forming a first semiconductor layer over the seed layer, wherein the first semiconductor layer comprises silicon and germanium, and forming a second semiconductor layer over the first
• the method may further comprise patterning the stack before the step of patterning the second conductive material.
• the method may further comprise forming an oxide over the second conductive material, patterning the oxide before the step of forming the semiconductor stack, and removing the oxide after the step of patterning the second conductive material.
• the method may have a further characterization by which the step of depositing the second conductive material further comprises depositing doped polysilicon.
• the method may have a further characterization by which after the step of bonding the first structure to the second structure, the first structure and the second conductive material are separated from each other by a dimension that is approximately equal to a height of the gap stop.
• the MEMS includes a support substrate.
• the MEMS further includes a contact formed over the support substrate at a predetermined level.
• the MEMS further includes a gap stop formed adjacent to and at the predetermined level.
• the MEMS further includes a bonding material formed over the contact and between the contact and the gap stop, wherein the contact and the gap stop prevent the bonding material from extending beyond the gap stop and the contact in the predetermined level.
• the MEMS further includes a metal layer in contact with the bonding material.
• the MEMS further includes a cap substrate over the metal layer.
• the MEMS may have a further characterization by which the bonding material comprises a eutectic material comprising aluminum and germanium.
• the MEMS may have a further characterization by which the contact and the gap stop comprise polysilicon.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Micromachines (AREA)
• Pressure Sensors (AREA)

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Publications (2)

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• 2009
  • 2009-12-08 US US12/632,940 patent/US8119431B2/en not_active Expired - Fee Related
• 2010
  • 2010-11-22 JP JP2012543137A patent/JP5794742B2/ja not_active Expired - Fee Related
  • 2010-11-22 WO PCT/US2010/057618 patent/WO2011071685A2/en not_active Ceased
  • 2010-11-22 CN CN201080055688.3A patent/CN102762490B/zh not_active Expired - Fee Related

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