WO2011070663A1 - Tft substrate inspection apparatus and tft substrate inspection method - Google Patents

Tft substrate inspection apparatus and tft substrate inspection method Download PDF

Info

Publication number
WO2011070663A1
WO2011070663A1 PCT/JP2009/070668 JP2009070668W WO2011070663A1 WO 2011070663 A1 WO2011070663 A1 WO 2011070663A1 JP 2009070668 W JP2009070668 W JP 2009070668W WO 2011070663 A1 WO2011070663 A1 WO 2011070663A1
Authority
WO
WIPO (PCT)
Prior art keywords
defect
short
detection
drive signal
substrate
Prior art date
Application number
PCT/JP2009/070668
Other languages
French (fr)
Japanese (ja)
Inventor
大輔 今井
Original Assignee
株式会社島津製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社島津製作所 filed Critical 株式会社島津製作所
Priority to CN200980162866XA priority Critical patent/CN102667507A/en
Priority to PCT/JP2009/070668 priority patent/WO2011070663A1/en
Priority to JP2011545022A priority patent/JP5590043B2/en
Publication of WO2011070663A1 publication Critical patent/WO2011070663A1/en

Links

Images

Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Definitions

  • the present invention relates to a TFT substrate inspection apparatus used for TFT substrate inspection in a manufacturing process of a TFT panel such as a liquid crystal substrate.
  • the present invention relates to a TFT substrate inspection apparatus suitable for short-circuit (short-circuit) defect inspection.
  • a TFT array inspection process is included in the manufacturing process, and the TFT array is inspected for defects in this TFT array inspection process.
  • the TFT array is used as a switching element for selecting a pixel (pixel electrode) of a liquid crystal display device, for example.
  • a substrate including a TFT array for example, a plurality of gate lines functioning as scanning lines are arranged in parallel, and a plurality of source lines described as signal lines are arranged orthogonal to the gate lines.
  • a TFT Thin film transistor
  • a TFT is disposed in the vicinity of the intersection of the lines, and a drive signal is supplied to the pixel (pixel electrode) through the TFT.
  • a liquid crystal display device is configured by sandwiching a liquid crystal layer between a substrate provided with the TFT array described above and a counter substrate, and a pixel capacitance is formed between a counter electrode and a pixel (pixel electrode) provided in the counter substrate. Is done.
  • an additional capacitance is connected to the pixel (pixel electrode).
  • One of the additional capacitors (Cs) is connected to a pixel (pixel electrode), and the other is connected to a common line or a gate line.
  • a TFT array configured to be connected to the common line is called a Cs on Com TFT array, and a TFT array configured to be connected to the gate line is called a Cs on Gate TFT array.
  • a scanning line (gate line) or a signal line (source line) is disconnected, a scanning line (gate line) and a signal line (source line) are short-circuited, or a pixel defect due to a characteristic defect of a TFT driving a pixel.
  • the counter electrode is grounded, a DC voltage of, for example, ⁇ 15 V to +15 V is applied to all or a part of the gate line at a predetermined interval, and a driving signal for inspection is applied to all or a part of the source line. Is performed by applying. (For example, the prior art of patent document 1 and patent document 2.)
  • the TFT substrate inspection apparatus can detect a defect by inputting a driving signal for inspection to the TFT array and detecting the voltage state at that time.
  • a pixel In a TFT substrate inspection apparatus using an electron beam, a pixel (pixel electrode) is irradiated with an electron beam, secondary electrons emitted by this electron beam irradiation are detected, and the intensity of the secondary electrons changes to change the pixel. Determine the presence or absence of defects in units.
  • the obtained secondary electron intensity signal is converted into an analog signal by a photomultiplier, etc., obtained by coordinate conversion, the data is allocated in units of pixels, defects are extracted by image processing, and the obtained defect data Perform defect inspection based on As the inspection signal used for this inspection, one type of inspection signal pattern is set for each substrate.
  • TFT array may have various defects during its manufacturing process.
  • the types of defects include, for example, a short-circuit defect (S-Dshort) between the pixel and the source line, a short-circuit defect between the pixel and the gate line (G-Dshort), and between the pixel and the common line (Cs line).
  • Short circuit defect (D-Cs short) line defect between source line and gate line, short circuit defect between source line and common line (Cs line), short circuit defect between gate line and common line (Cs line), etc. is there.
  • defects between the source line and the common line (Cs line), between the gate line and the common line (Cs line), and between the source line and the gate line are line defects, such as S-Dshort and G- Dshort and D-Cs short are known as point defects.
  • line defects can be detected by driving each panel using one type of inspection signal pattern set for the substrate.
  • FIG. 12 is a diagram for explaining line defects and point defects.
  • FIG. 12 shows a configuration example having a common line (Cs line).
  • the panel is provided with a TFT 35 in the vicinity of the intersection of the source line 31 and the gate line 32 arranged in a grid pattern, and a pixel electrode 34 is connected to the drain of the TFT 35.
  • the pixel electrode 34 is capacitively connected to the Cs line 33.
  • FIG. 12 (a) shows an example of a line defect.
  • a short defect may occur between the source line 31 and the Cs line (common line) 33, or between the gate line 32 and the Cs line (common line) 33, and appears as a line defect.
  • FIG. 12B shows an example of a point defect.
  • a short circuit defect (SD short) may occur between the pixel and the source line, a short circuit defect (GD short) between the pixel and the gate line may occur, and the pixel and Cs line.
  • D-Cs short short-circuit defect
  • short-circuit defects short-circuit defects between the source line and the common line (Cs line) or between the gate line and the common line (Cs line) are measured by changing the resistance value between the lines before scanning with the electron beam. Based on this resistance value, the presence / absence of a short circuit (short circuit) between the lines and which line is short-circuited are determined.
  • a prober is set on the board, and a short circuit is checked from the electrical continuity of the prober contacts.
  • This short check is performed depending on whether the resistance value between the pads is a small resistance, a large resistance, or an insulation.
  • the resistance value between the pads is a small resistance, it indicates the possibility of a large short-circuit between the lines connected to each pad, and the resistance value between the pads is within a predetermined resistance range. This case represents the possibility that a short defect (short circuit defect) exists between the lines to which the pads are connected.
  • a signal scan is performed by applying an inspection signal pattern to the panel, line defects are extracted by image processing from the voltage image obtained by the signal scan, and linked to the short check result.
  • defect information relating to the type and position of the defect is output (Patent Document 3).
  • the presence or absence of a defect can be detected in the defect inspection by the signal scan described above, but it may be difficult to determine the position of the line defect depending on the type of defect. For example, when the gate line and the Cs line are short-circuited, it is possible to determine which panel's gate line and the Cs line are short-circuited by a short check, and a defect occurs due to the signal image. It is possible to detect the lines that are present. It is possible to determine the short-circuit defect between the gate line and Cs line up to the occurrence range.
  • FIG. 13 is a diagram for explaining a line defect
  • FIG. 14 is a diagram showing a signal image due to the line defect.
  • FIG. 13A shows a case where the source line and the Cs line (common line) are short-circuited.
  • the pixels arranged along the source line are driven, so that they are displayed as the line 51 on the signal image. And determined as a line defect of the source line.
  • FIG. 13B shows a case where the gate line and the Cs line (common line) are short-circuited.
  • the pixels arranged along the gate line are driven, so that it is displayed as the line 52 on the signal image. And determined as a line defect of the gate line.
  • a method and a system for detecting an electrical short-circuit defect by applying a predetermined voltage to a plate structure of a flat display and obtaining a defect area from an infrared thermal map of a cathode has been proposed.
  • a defect region is determined by detecting a difference in radiance between a region including an electrical short-circuit defect of the cathode and a peripheral region by the first infrared array, and an infrared thermal map is formed by the first infrared array, A point is detected (Patent Document 4).
  • Patent Document 5 shows that in infrared thermography for defect detection and analysis, each part of a test target device is heated by a test vector, a thermograph image is acquired by an infrared device, and a defect position is specified.
  • defect detection can be performed as a line defect in units of lines, but the coordinates of the defect point are specified to identify which pixel is a defect. There is a problem that is difficult.
  • defect detection by heat detection it is possible to detect short defects that are difficult to detect by defect detection by electron beam irradiation.
  • the defect detection process by electron beam irradiation and the defect detection process by thermal detection can be performed in one processing process.
  • the detection time of the entire substrate is the time obtained by adding at least the detection time of each defect detection. There is a problem that the defect detection time becomes longer. As described above, when the defect detection time is increased, the time required for the manufacturing process of the TFT substrate is also increased.
  • the present invention solves the above-described problem and shortens the defect detection time of the entire substrate when performing defect detection by electron beam irradiation and short defect detection by thermal detection for a substrate on which a plurality of panels are formed. For the purpose.
  • the TFT substrate inspection when performing defect detection by electron beam irradiation and short-circuit defect detection by heat detection, a plurality of panels on the substrate are driven to detect the heat radiation of all the panels and the short-circuit defects are detected.
  • the defect detection time of the entire substrate is shortened by irradiating an electron beam to a panel sequentially selected from all the panels and detecting secondary electrons to detect defects.
  • the present invention can be configured as a TFT substrate inspection apparatus and a TFT substrate inspection method.
  • the TFT substrate inspection apparatus of the present invention includes a vacuum chamber for storing a substrate in a vacuum state, a drive signal supply unit for supplying a drive signal to the TFT array on the substrate, an electron beam source for irradiating the substrate with an electron beam, and an electron beam
  • a secondary electron detector for detecting secondary electrons emitted from the substrate by the irradiation of, a heat detector for detecting heat radiation emitted from the substrate to which the drive signal is supplied, a detection signal of the secondary electron detector, and
  • a defect detection unit that detects a defect of the TFT substrate based on a detection signal of the heat detector.
  • the defect detection unit includes a TFT array defect detection unit that detects a defect of the TFT array based on a scanning image obtained from the detection signal of the secondary electron detector, and a heat distribution image obtained from the detection signal of the heat detector. And a short defect detector for detecting a short defect.
  • the TFT array defect detection unit performs TFT array defect detection by sequentially selecting one panel from a plurality of panels included in the substrate.
  • the short defect detection unit simultaneously detects short defects for all the panels included in the substrate.
  • TFT array defect detection can be performed by comparing the signal intensity of the scanned image with a predetermined threshold value. This threshold value can be determined based on the signal intensity of the scanned image obtained when the TFT array has a defect.
  • short defect detection can be performed by comparing the signal intensity of the heat distribution image with a predetermined threshold value. This threshold value can be determined based on the signal intensity of the heat distribution image obtained when there is a short defect.
  • Detecting TFT array defects is sequentially performed for a plurality of panels, so that the detection time required to detect TFT array defects for all the panels is substantially the sum of the detection times of each panel.
  • the detection time required for detecting a short defect of each panel can be made the same by detecting the short defect simultaneously for all the panels.
  • secondary electron detection by electron beam scanning for TFT array defect detection and thermal detection for short defect detection can be performed independently without interfering with each other, so each of TFT array defect detection and short defect detection The time required for this can be arbitrarily determined according to the detection accuracy.
  • the detection time required for short defect detection can be set longer than the detection time required for TFT array defect detection, it can be determined according to the detection time required for TFT array defect detection for all panels.
  • the TFT array defect detection can be performed over the entire period.
  • the present invention by performing the TFT array defect detection and the short defect detection at the same time, the time required for the defect detection can be reduced as compared with the case where the TFT array defect detection and the short defect detection are sequentially performed.
  • the detection time for detecting the short defect of the present invention can be at least the detection time required for detecting the TFT array defects of all the panels, even if the amount of heat generated by the short defect portion is small and the temperature rise is small, By increasing the detection time, the detection accuracy can be increased.
  • the drive signal supply unit of the present invention applies a drive signal having a predetermined pattern for detecting a defect to a selected panel, and applies a drive signal having a predetermined pattern for detecting a short defect to a non-selected panel.
  • the predetermined pattern for performing defect detection can be set according to the defect type to be detected.
  • a panel for detecting a defect is selected, a drive signal of a predetermined pattern for detecting a defect is applied to this panel, and a panel for detecting a short defect for a panel not performing other defect detection.
  • a drive signal having a predetermined pattern is applied.
  • the detection time of the array defect detection is shorter than the detection time of the short defect detection, so even if there is a short defect in the array part to which the drive signal is supplied, The influence can be made negligible by not being heated at the time of defect detection.
  • the drive signal supply unit of the present invention interrupts the supply of the drive signal to the TFT array at the defect point of the short defect detected by the short defect detection unit during the defect detection of the short defect detection unit.
  • the short defect detection unit of the present invention evaluates the correctness of the detected short defect based on the detection signal of the heat detector after the supply of the drive signal is interrupted.
  • the heat generation at that point is stopped.
  • the location where the temperature has increased due to heat generation decreases after the heat generation stops after the heat generation stops.
  • This temperature change is detected based on the detection signal of the heat detector.
  • the drive signal supply unit of the present invention interrupts the supply of the drive signal to the TFT array at the defect point of the short defect detected by the short defect detection unit during the defect detection of the short defect detection unit, and after a predetermined time has elapsed.
  • the supply of drive signals to the TFT array is resumed.
  • the correctness of the detected short-circuit defect is evaluated based on the detection signal of the heat detector after the drive signal supply is reunited.
  • the temperature change at this time is detected based on the detection signal of the heat detector. If a rise in temperature is detected after the temperature has dropped, it can be confirmed that the detection position is a defect position of a short defect. On the other hand, when the temperature rise is not detected, it can be understood that the detection position is not the defect position of the short defect.
  • the TFT substrate inspection method of the present invention is a TFT substrate inspection method for inspecting a TFT substrate for a defect, and includes a drive signal supply step for supplying a drive signal to a TFT array of a substrate housed in a vacuum chamber, A TFT array defect that detects a defect of a TFT array based on a scanning image obtained from a detection signal of the secondary electron, by detecting secondary electrons emitted from the substrate by the electron beam irradiation. And a short defect detection step of detecting heat radiation radiated from the substrate supplied with the drive signal and detecting a short defect based on a heat distribution image obtained from the heat radiation detection signal.
  • one panel is sequentially selected from a plurality of panels included in the substrate to detect TFT array defects, and in the short defect detection step, short defect detection is performed simultaneously on all the panels included in the substrate.
  • a drive signal having a predetermined pattern for detecting a defect is applied to a selected panel, and a drive signal having a predetermined pattern for detecting a short defect is applied to a non-selected panel.
  • the supply of the drive signal to the TFT array at the defect point of the short defect detected in the short defect detection process is interrupted. This can prevent damage to the substrate due to heat generation.
  • the correctness of the detected short defect is evaluated based on the detection signal of heat dissipation after the supply of the drive signal is interrupted.
  • the supply of the drive signal to the TFT array at the defect point of the short defect detected by the short defect detection process is interrupted, and after the predetermined time has elapsed, the TFT The supply of the drive signal to the array is resumed, and the correctness of the detected short defect is evaluated based on the detection signal of the heat radiation after the drive signal supply is reunited.
  • the TFT substrate inspection method of the present invention it is possible to confirm whether or not the detected position of the detected short defect is correct.
  • the defect detection time of the entire substrate can be shortened.
  • FIG. 1 is a schematic view of a TFT substrate inspection apparatus of the present invention.
  • the TFT substrate inspection apparatus 1 detects an array defect and a short defect of the TFT substrate 20 placed on a stage 11 provided in a vacuum chamber (not shown).
  • an electron beam source 6 for irradiating the TFT substrate 20 with an electron beam, a stage 11 for moving the TFT substrate 20 in the x and y directions, an electron beam source 6 and the stage 11 are controlled to control the electron beam.
  • An array defect detection unit 2b for detecting defects is provided.
  • a heat detection unit 9 that detects heat radiation from the TFT substrate 20, a thermal frame image capturing unit 10 that forms a thermal frame image from a detection signal of the heat distribution detected by the heat detection unit 9, and a thermal image Are processed, and an image processing unit 2a for obtaining a coordinate position and a signal intensity at the position, and a short defect detecting unit 2c for detecting a short defect based on the obtained signal intensity are provided.
  • an infrared sensor or a thermography can be used for the heat detection unit.
  • an infrared sensor for example, an IR focal plane array thermal imaging camera using an InSb detector is known (Patent Document 5).
  • the defect detection unit 2 includes a defect position calibration unit 2d and a defect data storage unit 2e in addition to the image processing unit 2a, the array defect detection unit 2b, and the short defect detection unit 2c.
  • the defect position calibration unit 2d calibrates the coordinate position of the short defect at the same point based on the coordinate position of the array defect detected by the array defect detection unit 2b and the coordinate position of the short defect detected by the short defect detection unit 2c. .
  • the main control unit 3 and the scan control unit 5 include a CPU and storage means (not shown) such as a ROM for driving the CPU to execute a predetermined operation.
  • FIG. 1 shows an example of the configuration of the TFT substrate 20 shown in FIG.
  • a plurality of panels are provided on the TFT substrate 20, and a plurality of pixels 40 are arranged on each panel to form an array.
  • Each pixel 40 is provided with a source line 31, a gate line 32, and a common line 33.
  • the plurality of source lines 31 are connected to the source bar 21 and applied with the source signal supplied from the drive signal supply unit 4.
  • the plurality of gate lines 32 are connected to the gate bar 22 and a gate signal supplied from the drive signal supply unit 4 is applied thereto.
  • the plurality of common lines 33 are connected to the common bar 23, and a common signal supplied from the drive signal supply unit 4 is applied thereto.
  • the drive signal supply unit 43 generates and supplies a drive signal signal pattern for driving the TFT array formed on the TFT substrate 20.
  • the drive signal supply unit 4 can generate a plurality of types of drive patterns. For example, a signal pattern for supplying the same voltage to all pixels is generated as a signal pattern for detecting a point defect in the TFT array. Further, in order to determine the defect type of the TFT array, a signal pattern for supplying a voltage having a periodicity in pixel units is generated.
  • the image processing unit 2a converts the frame image into an image and forms a scanned image.
  • the array defect detection unit 2b compares with the potential state in the normal state based on the potential state of the pixel acquired by the image processing unit 2a, and a pixel in a potential state different from the potential in the normal state is connected to the pixel.
  • the TFT array is detected as defective. Further, the defect type of the detected defective pixel is determined.
  • the defect type determination stores at least two determination threshold values for determining the defect type of the defective pixel, and defect type data of the defective pixel in association with a plurality of intensity ranges set by the plurality of determination threshold values. .
  • the signal intensity of the scanned image obtained by applying the drive pattern is compared with the determination threshold value, and is classified into a plurality of intensity ranges based on the comparison result, and the defect type of the defective pixel is determined.
  • the position of the defective pixel is specified based on the position of the defective pixel detected by the point defect detection, the geometrical arrangement of the pixel detected by the defect type discrimination, the design position of the pixel formed on the substrate, and the like.
  • the short defect detection unit 2c compares the signal intensity representing the heat distribution acquired by the image processing unit 2a with the signal intensity of the heat distribution in the normal state. It is detected that the part has a short defect. In addition, the position of the short defect is specified based on the position of the detected short defect and the design position of the pixels and lines formed on the substrate.
  • the scanning control unit 5 controls the stage 11 and the electron beam source 6 in order to scan the inspection position of the TFT array on the TFT substrate 20.
  • the stage 11 moves the TFT substrate 20 to be placed in the XY direction, and the electron beam source 6 scans the irradiation position of the electron beam by shaking the electron beam irradiating the TFT substrate 20 in the XY direction.
  • the above-described configuration of the TFT array inspection apparatus is an example, and is not limited to this configuration.
  • FIGS. 2, 3 and 4 are a flowchart, a timing chart, and a panel operation diagram for explaining operations of array defect detection and short-circuit defect detection by the TFT substrate inspection apparatus.
  • Detecting array defects by irradiating and scanning an electron beam on a panel arranged on a TFT substrate.
  • a single panel is selected from a plurality of panels provided on the TFT substrate, and the selected panel is irradiated with an electron beam and scanned to detect secondary electrons, thereby detecting array defects.
  • Short defect detection is performed by detecting heat dissipation for all panels.
  • the timing chart of FIG. 3 shows the timing of performing array defect detection and the timing of performing short defect detection for each of the panels A to I arranged on the TFT substrate.
  • FIG. 3 (a) to 3 (i) show timings of array defect detection and short-circuit defect detection in panels A to I.
  • FIG. Here, an example in which array defect detection is performed in order from panel A is shown. Panel A performs array defect detection first in all panels (FIG. 3A), and panel B performs array defect detection second after the completion of array defect detection in panel A ( Similarly, as shown in FIG. 3B, array defect detection is performed in order for panels C to I. During this time, short defect detection is performed for all panels.
  • the time required for defect detection can be shortened by performing short defect detection for all the panels while performing array defect detection in order.
  • FIG. 4A shows panels A to I arranged on the TFT substrate. Array defect detection is performed in units of each panel, while short defect detection is performed simultaneously with array defects for all panels.
  • array defect detection is performed for panel A, and short defect detection is performed for all panels A to I.
  • array defect detection is performed for panel B, and short defect detection is performed for all panels A to I.
  • FIG. 4D array defect detection is performed for panel I, and short defect detection is performed for all panels A to I.
  • a panel for scanning an electron beam is selected (S2).
  • Array defect detection is performed for the selected panel (S3 to S7), and short defect detection is performed for the selected panel and the non-selected panel.
  • short defect detection a drive signal for detecting a short defect is applied to a non-selected panel, and a drive signal for detecting an array defect is supplied to the selected panel. Since the drive signal for detecting the array defect is applied to the selected panel instead of the drive signal for detecting the short defect, the drive signal may not be applied to the defective portion of the short defect depending on the signal pattern. .
  • the selected panel it is determined whether the selected panel is a panel that detects heat generation (S3). If the selected panel is a panel in which heat generation is being detected, application of a drive signal for detecting a short defect for measuring heat generation is interrupted, and it is determined in S5 whether or not the panel has already been selected. If the selected panel is not a panel for which heat generation is being detected, it is determined whether or not the panel has already been selected in S5.
  • step S5 If the selected panel is not already selected (S5), array defect detection processing by electron beam scanning is performed (S6). If the selected panel has already been selected (S5), the array defect detection process is skipped. Steps S3 to S6 are performed for all the panels, and array defect detection is performed for all the panels on the TFT substrate (S7).
  • Defective points detected by array defect detection may include defective points due to short-circuit defects depending on the drive signal pattern. Therefore, the coordinate position of the short defect detected by the array defect detection and the coordinate position of the short defect detected by the short defect detection process of S8 are collated (S9), and the coordinate position does not match for the same short defect To calibrate the coordinate position. Calibration of the coordinate position of the short defect can be performed based on the arrangement position information of the array and lines on the TFT substrate, the image image obtained by the array defect detection and the short defect detection, and the like (S10). The detected coordinate position of the short defect point is stored in the defect data storage unit 2e or the like (S11).
  • FIG. 5 is a flowchart for explaining the array defect detection operation by the TFT substrate inspection apparatus of the present invention.
  • the processing of this array defect detection operation corresponds to the step S6 in FIG.
  • the panel that irradiates the electron beam is selected (S101), and a drive signal for array defect detection is applied to the selected panel (S102).
  • the selected panel is scanned while being irradiated with an electron beam, and secondary electrons emitted from the TFT substrate are detected by a secondary electron detector (S103).
  • Image data related to the array defect is acquired from the detected secondary electron detection signal.
  • the image data includes the data of the detection signal intensity and the coordinate position (S104).
  • the defect detection can be performed by comparing the intensity of the detection signal with a predetermined threshold value (S105).
  • the coordinate position of the array defect point detected in step S105 is obtained (S106).
  • Steps S101 to S106 are performed for all the panels, and array defects are detected for all the panels on the TFT substrate (S107).
  • a drive signal for detecting a short defect is applied to all the panels on the TFT substrate.
  • a current flows through the defective point, and heat is generated by the electric resistance.
  • the amount of heat generation depends on the short state of the defect point.
  • the short defect is small, the amount of heat generated is small because of the high resistance.
  • the short-circuit defect is large, the amount of heat generation increases because of the low resistance.
  • the time from when the drive signal is applied to the TFT substrate until the short defect is detected is determined in advance, and the drive signal is continuously applied until the set time elapses (S202). After the set time has elapsed, the heat generation of all the panels on the TFT substrate is measured with a heat detector (S203).
  • the image data of the short defect is obtained from the detection signal measured by the thermal detector.
  • the image data includes the data of the detection signal intensity and the coordinate position (S204).
  • the defect detection can be performed by comparing the intensity of the detection signal with a predetermined threshold value (S205).
  • the coordinate position of the short defect point detected in step S205 is obtained (S206).
  • FIG. 7A shows the signal intensity and applied signal of a detection signal in a normal state without a short defect
  • FIGS. 7B and 7C show the signal intensity and applied signal of a detection signal in a state of a short defect
  • FIG. 7D shows the measurement timing.
  • FIG. 7B shows the case of a small short defect. In this case, since the short circuit current is small, the temperature increase rate is small.
  • FIG. 7C shows the case of a large short defect. In this case, since the short-circuit current is large, the rate of temperature rise increases.
  • the determination of the short defect can be performed by comparing the signal intensity of the detection signal with the threshold at the time of the measurement timing in FIG.
  • the application of the drive signal is interrupted to stop the temperature rise at the short defect point and prevent the damage due to heat at that point. Further, it can be evaluated whether or not the detection point of short defect detection is correctly detected.
  • a drive signal for detecting a short defect is applied to all the panels on the TFT substrate (S301).
  • heat generation is measured by the heat detector at the measurement timing (S302, S303).
  • Short defect image data is acquired from the detection signal of the thermal detector.
  • the image data includes data of the detection signal intensity and coordinate position (S304).
  • a short defect is detected using image data.
  • Defect detection can be performed by comparing the intensity of the detection signal with a predetermined threshold (S307).
  • the coordinate position of the short defect point detected in step S307 is obtained and recorded (S308).
  • S305 to S306 are processes for evaluating whether or not the position where the application of the drive signal is stopped is a short defect point.
  • the stop position is a short defect point
  • heat is not generated at the short defect point, and the temperature is lowered by heat dissipation.
  • it can be confirmed whether or not the detected point is a short defect point. If it is a correct short defect point, a temperature drop is detected, and if the detected point is incorrect, a temperature drop is not detected and heat generation is detected.
  • FIG. 8A shows the signal intensity and applied signal of a detection signal in a normal state without a short defect
  • FIG. 8B shows the signal intensity and applied signal of a detection signal in a state of a short defect
  • c) shows the measurement timing. 8 (a) and 8 (b), black dots indicate detection points measured at the measurement timing in FIG. 8 (c).
  • the intensity of the detection signal is determined in advance as a threshold for detecting a short defect, and the signal intensity of the detection signal is compared with the threshold. When the signal intensity of the detection signal exceeds the threshold value, the application of the drive signal corresponding to the position of the short defect is stopped.
  • the application of the drive signal is interrupted and then the drive signal is applied again to evaluate whether or not the short defect has been correctly detected. It is a form to do.
  • a drive signal for detecting a short defect is applied to all the panels on the TFT substrate (S401).
  • heat generation is measured by the heat detector at the measurement timing (S402, 403).
  • Short defect image data is acquired from the detection signal of the thermal detector.
  • the image data includes detection signal intensity and coordinate position data (S404).
  • a short defect is detected using image data.
  • the defect detection can be performed by comparing the intensity of the detection signal with a predetermined threshold value (S4052).
  • the coordinate position of the short defect point detected in step S405 is obtained and recorded (S406).
  • the drive signal is re-applied to the defective point where the application is stopped in S407, and the defective point is caused to generate heat (S409).
  • the temperature rises due to heat generation (S410), and then heat generation is measured by a heat detector (S411).
  • Short defect image data is acquired from the detection signal of the thermal detector.
  • the image data includes the data of the detection signal intensity and the coordinate position (S412).
  • the intensity of the defect point detection signal is compared with a predetermined threshold value (S413). If the detected signal intensity is greater than the threshold value, the detected position can be evaluated as a correct short defect detected position. On the other hand, if the detected signal intensity is less than the threshold value, the detected position is incorrect.
  • the detected position of the short defect is evaluated (S413), detected, and the coordinate position of the short defect position is deleted from the record (S414). The above steps S402 to S414 are repeated until the set time for short defect detection elapses (S415).
  • FIG. 11 (a) shows the signal intensity and applied signal of the detection signal in a state where there is a short defect
  • FIG. 11 (b) shows the measurement timing.
  • black dots indicate detection points measured at the measurement timing in FIG.
  • the intensity of the detection signal is determined in advance as a threshold for detecting a short defect, and the signal intensity of the detection signal is compared with the threshold. When the signal intensity of the detection signal exceeds the threshold value, the application of the drive signal corresponding to the position of the short defect is stopped.
  • the present invention can be applied not only to a TFT array inspection process in a liquid crystal manufacturing apparatus but also to a defect inspection of a TFT array provided in an organic EL or various semiconductor substrates.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

Disclosed is a TFT substrate inspection apparatus which is provided with a defect detecting unit, which detects a defect of a TFT substrate, on the basis of detection signals outputted from a secondary electron detector and detection signals outputted from a heat detector. The defect detecting unit is provided with: a TFT array defect detecting unit, which detects a defect of a TFT array on the basis of the detection signals outputted from the secondary electron detector; and a short-circuit defect detecting unit, which detects a short-circuit defect on the basis of the detection signals outputted from a heat detector. The TFT array defect detecting unit detects a TFT array defect by sequentially selecting each of a plurality of panels provided on the substrate, and the short-circuit defect detecting unit performs short-circuit defect detection at one time for all the panels provided on the substrate. At the time of detecting a defect by means of electron beam irradiation and a short-circuit defect by means of heat detection with respect to the substrate having the panels formed thereon, a defect detection time necessary for the whole substrate is shortened.

Description

TFT基板検査装置およびTFT基板検査方法TFT substrate inspection apparatus and TFT substrate inspection method
 本発明は、液晶基板等のTFTパネルの製造工程におけるTFT基板検査に用いられるTFT基板検査装置に関する。特に、ショート(短絡)欠陥検査に好適なTFT基板検査装置に関する。 The present invention relates to a TFT substrate inspection apparatus used for TFT substrate inspection in a manufacturing process of a TFT panel such as a liquid crystal substrate. In particular, the present invention relates to a TFT substrate inspection apparatus suitable for short-circuit (short-circuit) defect inspection.
 液晶基板や有機EL基板等のTFTアレイが形成された半導体基板の製造過程では、製造過程中にTFTアレイ検査工程を含み、このTFTアレイ検査工程において、TFTアレイの欠陥検査が行われている。 In the manufacturing process of a semiconductor substrate on which a TFT array such as a liquid crystal substrate or an organic EL substrate is formed, a TFT array inspection process is included in the manufacturing process, and the TFT array is inspected for defects in this TFT array inspection process.
 TFTアレイは、例えば液晶表示装置のピクセル(画素電極)を選択するスイッチング素子として用いられる。TFTアレイを備える基板は、例えば、走査線として機能する複数本のゲートラインが平行に配設されると共に、信号線として記載する複数本のソースラインがゲートラインに直交して配設され、両ラインが交差する部分の近傍にTFT(Thin film transistor)が配設され、このTFTを介してピクセル(画素電極)に駆動信号が供給される。 The TFT array is used as a switching element for selecting a pixel (pixel electrode) of a liquid crystal display device, for example. In a substrate including a TFT array, for example, a plurality of gate lines functioning as scanning lines are arranged in parallel, and a plurality of source lines described as signal lines are arranged orthogonal to the gate lines. A TFT (Thin film transistor) is disposed in the vicinity of the intersection of the lines, and a drive signal is supplied to the pixel (pixel electrode) through the TFT.
 液晶表示装置は、上記したTFTアレイが設けられた基板と対向基板との間に液晶層を挟むことで構成され、対向基板が備える対向電極とピクセル(画素電極)との間に画素容量が形成される。ピクセル(画素電極)には、上記の画素容量以外に付加容量(Cs)が接続される。この付加容量(Cs)の一方はピクセル(画素電極)に接続され、他方は共通ラインあるいはゲートラインに接続される。共通ラインに接続される構成のTFTアレイはCs on Com型TFTアレイと呼ばれ、ゲートラインに接続される構成のTFTアレイはCs on Gate型TFTアレイと呼ばれる。 A liquid crystal display device is configured by sandwiching a liquid crystal layer between a substrate provided with the TFT array described above and a counter substrate, and a pixel capacitance is formed between a counter electrode and a pixel (pixel electrode) provided in the counter substrate. Is done. In addition to the above-described pixel capacitance, an additional capacitance (Cs) is connected to the pixel (pixel electrode). One of the additional capacitors (Cs) is connected to a pixel (pixel electrode), and the other is connected to a common line or a gate line. A TFT array configured to be connected to the common line is called a Cs on Com TFT array, and a TFT array configured to be connected to the gate line is called a Cs on Gate TFT array.
 このTFTアレイにおいて、走査線(ゲートライン)や信号線(ソースライン)の断線、走査線(ゲートライン)と信号線(ソースライン)の短絡、画素を駆動するTFTの特性不良による画素欠陥等の欠陥検査は、例えば、対向電極を接地し、ゲートラインの全部あるいは一部に、例えば、-15V~+15Vの直流電圧を所定間隔で印加し、ソースラインの全部あるいは一部に検査用の駆動信号を印加することによって行っている。(例えば、特許文献1の従来技術、特許文献2。) In this TFT array, a scanning line (gate line) or a signal line (source line) is disconnected, a scanning line (gate line) and a signal line (source line) are short-circuited, or a pixel defect due to a characteristic defect of a TFT driving a pixel. In the defect inspection, for example, the counter electrode is grounded, a DC voltage of, for example, −15 V to +15 V is applied to all or a part of the gate line at a predetermined interval, and a driving signal for inspection is applied to all or a part of the source line. Is performed by applying. (For example, the prior art of patent document 1 and patent document 2.)
 TFT基板検査装置は、TFTアレイに検査用の駆動信号を入力し、そのときの電圧状態を検出することで欠陥検出を行うことができる。 The TFT substrate inspection apparatus can detect a defect by inputting a driving signal for inspection to the TFT array and detecting the voltage state at that time.
 電子線を用いたTFT基板検査装置では、ピクセル(画素電極)に対して電子線を照射し、この電子線照射によって放出される二次電子を検出し、この二次電子の強度変化によって、画素単位での欠陥有無を判別する。ここで、得られる二次電子強度の信号は、フォトマルチプライヤなどでアナログ信号に変換し、座標変換によって得られてデータを画素単位に割付け、画像処理によって欠陥を抽出し、得られた欠陥データに基づいて欠陥検査を行う。この検査に用いる検査信号は、基板を単位として1種類の検査信号パターンが設定されている。 In a TFT substrate inspection apparatus using an electron beam, a pixel (pixel electrode) is irradiated with an electron beam, secondary electrons emitted by this electron beam irradiation are detected, and the intensity of the secondary electrons changes to change the pixel. Determine the presence or absence of defects in units. Here, the obtained secondary electron intensity signal is converted into an analog signal by a photomultiplier, etc., obtained by coordinate conversion, the data is allocated in units of pixels, defects are extracted by image processing, and the obtained defect data Perform defect inspection based on As the inspection signal used for this inspection, one type of inspection signal pattern is set for each substrate.
 TFTアレイには、その製造プロセス中に様々な欠陥が発生する可能性がある。欠陥の種類としては、例えば、ピクセルとソースラインとの間の短絡欠陥(S-Dshort)、ピクセルとゲートライン間の短絡欠陥(G-Dshort)、ピクセルと共通ライン(Csライン)との間の短絡欠陥(D-Cs short)、ソースラインとゲートラインとの間のライン欠陥、ソースライン-共通ライン(Csライン)間の短絡欠陥、ゲートライン-共通ライン(Csライン)間の短絡欠陥等がある。 TFT array may have various defects during its manufacturing process. The types of defects include, for example, a short-circuit defect (S-Dshort) between the pixel and the source line, a short-circuit defect between the pixel and the gate line (G-Dshort), and between the pixel and the common line (Cs line). Short circuit defect (D-Cs short), line defect between source line and gate line, short circuit defect between source line and common line (Cs line), short circuit defect between gate line and common line (Cs line), etc. is there.
 これら欠陥の内、ソースライン-共通ライン(Csライン)間、ゲートライン-共通ライン(Csライン)間、およびソースラインとゲートラインとの間の欠陥はライン欠陥であり、S-DshortやG-DshortやD-Cs shortは点欠陥として知られている。 Among these defects, defects between the source line and the common line (Cs line), between the gate line and the common line (Cs line), and between the source line and the gate line are line defects, such as S-Dshort and G- Dshort and D-Cs short are known as point defects.
 通常、基板に対して設定された1種類の検査信号パターンを用いて各パネルを駆動することによって、ライン欠陥を検出が可能となる。 Usually, line defects can be detected by driving each panel using one type of inspection signal pattern set for the substrate.
 図12は、ライン欠陥および点欠陥を説明するための図である。図12は、共通ライン(Csライン)を備える構成例を示している。パネルには、格子状に配置されたソースライン31とゲートライン32の交差位置の近傍にTFT35が設けられ、TFT35のドレインには画素電極34が接続される。画素電極34はCsライン33に容量接続されている。 FIG. 12 is a diagram for explaining line defects and point defects. FIG. 12 shows a configuration example having a common line (Cs line). The panel is provided with a TFT 35 in the vicinity of the intersection of the source line 31 and the gate line 32 arranged in a grid pattern, and a pixel electrode 34 is connected to the drain of the TFT 35. The pixel electrode 34 is capacitively connected to the Cs line 33.
 図12(a)は、ライン欠陥の例を示している。ソースライン31とCsライン(共通ライン)33の間や、ゲートライン32とCsライン(共通ライン)33の間は、ショート欠陥(短絡欠陥)が発生する可能性があり、ライン欠陥として現れる。 FIG. 12 (a) shows an example of a line defect. A short defect (short circuit defect) may occur between the source line 31 and the Cs line (common line) 33, or between the gate line 32 and the Cs line (common line) 33, and appears as a line defect.
 図12(b)は、点欠陥の例を示している。ピクセルとソースラインとの間は短絡欠陥(S-Dshort)が発生する可能性があり、ピクセルとゲートライン間の短絡欠陥(G-Dshort)が発生する可能性があり、また、ピクセルとCsライン(共通ライン)間の短絡欠陥(D-Cs short)が発生する可能性がある。これらの欠陥は点欠陥として現れる。 FIG. 12B shows an example of a point defect. A short circuit defect (SD short) may occur between the pixel and the source line, a short circuit defect (GD short) between the pixel and the gate line may occur, and the pixel and Cs line. There is a possibility that a short-circuit defect (D-Cs short) between (common lines) occurs. These defects appear as point defects.
 従来、このソースライン-共通ライン(Csライン)間やゲートライン-共通ライン(Csライン)間のショート欠陥(短絡欠陥)は、電子線による走査を実行する前に、各ライン間の抵抗値を測定し、この抵抗値に基づいて各ライン間のショート(短絡)の有無やどのラインがショート(短絡)しているかの判定を行っている。 Conventionally, short-circuit defects (short-circuit defects) between the source line and the common line (Cs line) or between the gate line and the common line (Cs line) are measured by changing the resistance value between the lines before scanning with the electron beam. Based on this resistance value, the presence / absence of a short circuit (short circuit) between the lines and which line is short-circuited are determined.
 従来のショート欠陥検出では、基板にプローバをセットし、このプローバの接点の電気的な導通状態からショート(短絡)をチェックしている。 In conventional short defect detection, a prober is set on the board, and a short circuit is checked from the electrical continuity of the prober contacts.
 このショートチェックは、パッド間の抵抗値が小抵抗であるか、あるいは大抵抗であるか、もしくは絶縁とみなせるかによって行う。パッド間の抵抗値が小抵抗である場合は、各パッドが接続されるライン間がショート(短絡)している大ショートである可能性を表し、パッド間の抵抗値が所定の抵抗範囲である場合は、各パッドが接続されるライン間にショート欠陥(短絡欠陥)が存在する可能性を表している。 This short check is performed depending on whether the resistance value between the pads is a small resistance, a large resistance, or an insulation. When the resistance value between the pads is a small resistance, it indicates the possibility of a large short-circuit between the lines connected to each pad, and the resistance value between the pads is within a predetermined resistance range. This case represents the possibility that a short defect (short circuit defect) exists between the lines to which the pads are connected.
 ショート欠陥を判定した場合には、さらに、パネルに検査信号パターンを印加してシグナルスキャンを行い、シグナルスキャンで得られた電圧イメージから、画像処理によってライン欠陥を抽出し、ショートチェックの結果とリンクさせて、欠陥の種類と位置に係わる欠陥情報を出力している(特許文献3)。 When a short defect is determined, a signal scan is performed by applying an inspection signal pattern to the panel, line defects are extracted by image processing from the voltage image obtained by the signal scan, and linked to the short check result. Thus, defect information relating to the type and position of the defect is output (Patent Document 3).
 上記したシグナルスキャンにより欠陥検査では、欠陥の有無を検出することができるが、欠陥の種類によっては、ライン欠陥の欠陥位置を求めることは困難な場合がある。例えばゲートライン-Csライン間が短絡している場合には、ショートチェックによって、どのパネルのゲートライン-Csライン間が短絡しているかを判定することができ、また、シグナルイメージによって欠陥が発生しているラインを検出することは可能である。ゲートライン-Csライン間でのショート欠陥について、発生範囲までの判別は可能である The presence or absence of a defect can be detected in the defect inspection by the signal scan described above, but it may be difficult to determine the position of the line defect depending on the type of defect. For example, when the gate line and the Cs line are short-circuited, it is possible to determine which panel's gate line and the Cs line are short-circuited by a short check, and a defect occurs due to the signal image. It is possible to detect the lines that are present. It is possible to determine the short-circuit defect between the gate line and Cs line up to the occurrence range.
 しかしながら、ゲートラインとCsラインは並行して配設されているため、シグナルイメージ上において、短絡している位置を求めることは極めて困難であり、通常は欠陥ラインとして判別できるにとどまっている。 However, since the gate line and the Cs line are arranged in parallel, it is extremely difficult to determine the short-circuited position on the signal image, and it can usually be determined as a defective line.
 図13は、ライン欠陥を説明するための図であり、図14は、ライン欠陥によるシグナルイメージを示す図である。図13(a)はソースラインとCsライン(共通ライン)との間が短絡した場合を示している。この場合には、図14(a)に示すように、欠陥点50が1カ所の場合であっても、ソースラインに沿って配列される画素が駆動するため、シグナルイメージ上ではライン51として表示され、ソースラインのライン欠陥として判定される。 FIG. 13 is a diagram for explaining a line defect, and FIG. 14 is a diagram showing a signal image due to the line defect. FIG. 13A shows a case where the source line and the Cs line (common line) are short-circuited. In this case, as shown in FIG. 14 (a), even if there is only one defect point 50, the pixels arranged along the source line are driven, so that they are displayed as the line 51 on the signal image. And determined as a line defect of the source line.
 また、図13(b)はゲートラインとCsライン(共通ライン)との間が短絡した場合を示している。この場合には、図14(b)に示すように、欠陥点50bが1カ所の場合であっても、ゲートラインに沿って配列される画素が駆動するため、シグナルイメージ上ではライン52として表示され、ゲートラインのライン欠陥として判定される。 FIG. 13B shows a case where the gate line and the Cs line (common line) are short-circuited. In this case, as shown in FIG. 14B, even if there is only one defect point 50b, the pixels arranged along the gate line are driven, so that it is displayed as the line 52 on the signal image. And determined as a line defect of the gate line.
 また、フラットディスプレイのプレート構造に所定電圧を印加し、陰極の赤外線熱地図から欠陥領域を求めることによって電気短絡欠陥を検出する方法およびシステムが提案されている。第1の赤外線アレイによって、陰極の電気短絡欠陥を含む領域と周辺領域との間の放射輝度の差を検出して欠陥領域を決定し、第1の赤外線アレイによって赤外線熱地図を形成し、欠陥点を検出している(特許文献4)。 Also, a method and a system for detecting an electrical short-circuit defect by applying a predetermined voltage to a plate structure of a flat display and obtaining a defect area from an infrared thermal map of a cathode has been proposed. A defect region is determined by detecting a difference in radiance between a region including an electrical short-circuit defect of the cathode and a peripheral region by the first infrared array, and an infrared thermal map is formed by the first infrared array, A point is detected (Patent Document 4).
 また、特許文献5には、欠陥検出および解析用赤外線サーモグラフィにおいて、テストベクタによってテスト対象デバイスの各部を加熱して赤外線装置によってサームグラフ画像を取得し欠陥位置を特定する点が示されている。 Further, Patent Document 5 shows that in infrared thermography for defect detection and analysis, each part of a test target device is heated by a test vector, a thermograph image is acquired by an infrared device, and a defect position is specified.
特開平5-307192号公報JP-A-5-307192 特開2008-058767号公報JP 2008-058767 A 特開2007-271585号公報JP 2007-271585 A 特表2005-503532号公報JP 2005-503532 A 特表2006-505764号公報JP-T-2006-50564
 上記したように、電子線照射による欠陥検出では、ラインを単位とするライン欠陥として欠陥検出を行うことができるが、欠陥ポイントの座標を特定して、どの画素が欠陥であるかを識別することは困難であるという問題がある。 As described above, in defect detection by electron beam irradiation, defect detection can be performed as a line defect in units of lines, but the coordinates of the defect point are specified to identify which pixel is a defect. There is a problem that is difficult.
 欠陥ポイントの座標を特定するには、上記した通常の検査信号パターンに代えて、欠陥ポイントを検出する専用の検査信号パターンを用いて、基板上に形成されたパネルを再度駆動する必要がある。 In order to specify the coordinates of the defect point, it is necessary to drive the panel formed on the substrate again using a dedicated inspection signal pattern for detecting the defect point instead of the above-described normal inspection signal pattern.
 したがって、従来のTFT基板装置による欠陥検査では、欠陥の種類によって、欠陥位置を特定することが困難であるため、欠陥位置を特定するには、通常の欠陥検査で用いる検査信号パターンとは別に、欠陥に応じた特殊な検査信号パターンが必要となり、その分、検査のタスクが増加するという問題がある。 Therefore, in the defect inspection by the conventional TFT substrate device, it is difficult to specify the defect position depending on the type of defect. Therefore, in order to specify the defect position, apart from the inspection signal pattern used in the normal defect inspection, There is a problem that a special inspection signal pattern corresponding to the defect is required, and the inspection task increases accordingly.
 また、一つの基板上に複数種のパネルが形成されている場合には、各パネル種に対応した検査信号パターンを用いて基板上に全パネルを駆動して欠陥検査を行う操作を、パネルの種類数分だけ繰り返さなければ成らず、検査のタスクが増加するという問題もある。 In addition, when multiple types of panels are formed on a single substrate, an operation for performing defect inspection by driving all the panels on the substrate using an inspection signal pattern corresponding to each panel type is performed. There is also a problem that inspection tasks increase because the number of types must be repeated.
 一方、熱検出による欠陥検出によれば、電子線照射による欠陥検出では検出が難しいショート欠陥を検出することができる。 On the other hand, according to defect detection by heat detection, it is possible to detect short defects that are difficult to detect by defect detection by electron beam irradiation.
 しかしながら、各種の欠陥検出とショート欠陥とを一つの欠陥検出工程で行う場合には、電子線照射による欠陥検出の工程と、熱検出による欠陥検出の工程とを一つの処理工程で行うことができず、各欠陥検出工程を時系列に並べて行う必要がある。 However, when various defect detections and short defects are performed in one defect detection process, the defect detection process by electron beam irradiation and the defect detection process by thermal detection can be performed in one processing process. First, it is necessary to perform each defect detection process side by side in time series.
 そのため、複数のパネルが搭載された基板について、電子線照射による欠陥検出と熱検出によるショート欠陥検出とを行う場合には、基板全体の検出時間は、少なくとも各欠陥検出の検出時間を加算した時間が必要となり、欠陥検出時間が長時間化するという問題がある。このように欠陥検出時間が長くなると、TFT基板の製造工程に要する時間も長くなることにもなる。 Therefore, when performing defect detection by electron beam irradiation and short defect detection by heat detection for a substrate on which a plurality of panels are mounted, the detection time of the entire substrate is the time obtained by adding at least the detection time of each defect detection There is a problem that the defect detection time becomes longer. As described above, when the defect detection time is increased, the time required for the manufacturing process of the TFT substrate is also increased.
 そこで、本発明は上記課題を解決して、複数のパネルが形成された基板について、電子線照射による欠陥検出と熱検出によるショート欠陥検出とを行う際において、基板全体の欠陥検出時間を短縮することを目的とする。 Therefore, the present invention solves the above-described problem and shortens the defect detection time of the entire substrate when performing defect detection by electron beam irradiation and short defect detection by thermal detection for a substrate on which a plurality of panels are formed. For the purpose.
 本発明は、TFT基板検査において、電子線照射による欠陥検出と、熱検出によるショート欠陥検出とを行うに際して、基板上の複数の全パネルを駆動して全パネルの放熱を検出してショート欠陥を検出するとともに、全パネルから順次選択したパネルに対して電子線を照射して二次電子を検出して欠陥検出を行うことによって、基板全体の欠陥検出時間を短縮する。 In the TFT substrate inspection, when performing defect detection by electron beam irradiation and short-circuit defect detection by heat detection, a plurality of panels on the substrate are driven to detect the heat radiation of all the panels and the short-circuit defects are detected. In addition to detection, the defect detection time of the entire substrate is shortened by irradiating an electron beam to a panel sequentially selected from all the panels and detecting secondary electrons to detect defects.
 本発明はTFT基板検査装置の態様とTFT基板の検査方法の態様とすることができる。 The present invention can be configured as a TFT substrate inspection apparatus and a TFT substrate inspection method.
 本発明のTFT基板検査装置は、基板を真空状態に収納する真空チャンバと、基板のTFTアレイに駆動信号を供給する駆動信号供給部と、基板に電子線を照射する電子線源と、電子線の照射によって基板から放出される二次電子を検出する二次電子検出器と、駆動信号が供給された基板から放射される放熱を検出する熱検出器と、二次電子検出器の検出信号および前記熱検出器の検出信号に基づいてTFT基板の欠陥を検出する欠陥検出部とを備える。 The TFT substrate inspection apparatus of the present invention includes a vacuum chamber for storing a substrate in a vacuum state, a drive signal supply unit for supplying a drive signal to the TFT array on the substrate, an electron beam source for irradiating the substrate with an electron beam, and an electron beam A secondary electron detector for detecting secondary electrons emitted from the substrate by the irradiation of, a heat detector for detecting heat radiation emitted from the substrate to which the drive signal is supplied, a detection signal of the secondary electron detector, and A defect detection unit that detects a defect of the TFT substrate based on a detection signal of the heat detector.
 欠陥検出部は、二次電子の検出器の検出信号から得られる走査画像に基づいてTFTアレイの欠陥を検出するTFTアレイ欠陥検出部と、熱検出器の検出信号から得られる熱分布画像に基づいてショート欠陥を検出するショート欠陥検出部とを備える。 The defect detection unit includes a TFT array defect detection unit that detects a defect of the TFT array based on a scanning image obtained from the detection signal of the secondary electron detector, and a heat distribution image obtained from the detection signal of the heat detector. And a short defect detector for detecting a short defect.
 TFTアレイ欠陥検出部は、基板が備える複数のパネルから一つのパネルを順に選択してTFTアレイ欠陥検出を行う。ショート欠陥検出部は、基板が備える全パネルについて同時にショート欠陥検出を行う。 The TFT array defect detection unit performs TFT array defect detection by sequentially selecting one panel from a plurality of panels included in the substrate. The short defect detection unit simultaneously detects short defects for all the panels included in the substrate.
 TFTアレイ欠陥検出は、走査画像の信号強度をあらかじめ定めておいた閾値と比較することによって行うことができる。この閾値は、TFTアレイに欠陥があるときに得られる走査画像の信号強度に基づいて定めることができる。 TFT array defect detection can be performed by comparing the signal intensity of the scanned image with a predetermined threshold value. This threshold value can be determined based on the signal intensity of the scanned image obtained when the TFT array has a defect.
 また、ショート欠陥検出は、熱分布画像の信号強度をあらかじめ定めておいた閾値と比較することによって行うことができる。この閾値は、ショート欠陥があるときに得られる熱分布画像の信号強度に基づいて定めることができる。 Also, short defect detection can be performed by comparing the signal intensity of the heat distribution image with a predetermined threshold value. This threshold value can be determined based on the signal intensity of the heat distribution image obtained when there is a short defect.
 TFTアレイ欠陥検出は複数のパネルについて順次行うことにより、全パネルをTFTアレイ欠陥検出するに要する検出時間は、ほぼ各パネルの検出時間を加算したものとなる。一方、ショート欠陥検出は全パネルについて同時に行うことにより、各パネルのショート欠陥検出に要する検出時間は同一とすることができる。 Detecting TFT array defects is sequentially performed for a plurality of panels, so that the detection time required to detect TFT array defects for all the panels is substantially the sum of the detection times of each panel. On the other hand, the detection time required for detecting a short defect of each panel can be made the same by detecting the short defect simultaneously for all the panels.
 また、TFTアレイ欠陥検出の電子線走査による二次電子検出と、ショート欠陥検出の熱検出とは、互いに干渉することなく独立して行うことができるため、TFTアレイ欠陥検出およびショート欠陥検出のそれぞれに要する時間は、検出精度に応じて任意に定めることができる。 Also, secondary electron detection by electron beam scanning for TFT array defect detection and thermal detection for short defect detection can be performed independently without interfering with each other, so each of TFT array defect detection and short defect detection The time required for this can be arbitrarily determined according to the detection accuracy.
 ショート欠陥検出に要する検出時間は、TFTアレイ欠陥検出に要する検出時間よりも長く設定することができるため、全パネルのTFTアレイ欠陥検出に要する検出時間に合わせて定めることができ、ショート欠陥検出は、TFTアレイ欠陥検出を行う全期間にわたって行うことができる。 Since the detection time required for short defect detection can be set longer than the detection time required for TFT array defect detection, it can be determined according to the detection time required for TFT array defect detection for all panels. The TFT array defect detection can be performed over the entire period.
 したがって、本発明によれば、TFTアレイ欠陥検出とショート欠陥検出とを同時に行うことによって、TFTアレイ欠陥検出とショート欠陥検出とを順次行う場合よりも欠陥検出に要する時間を短縮することができる。 Therefore, according to the present invention, by performing the TFT array defect detection and the short defect detection at the same time, the time required for the defect detection can be reduced as compared with the case where the TFT array defect detection and the short defect detection are sequentially performed.
 また、本発明のショート欠陥検出の検出時間を、少なくとも全パネルのTFTアレイ欠陥検出に要する検出時間とすることができるため、ショート欠陥部分の発熱量が小さく温度上昇が小さい場合であっても、検出時間を長くすることによって検出精度を高めることができる。 In addition, since the detection time for detecting the short defect of the present invention can be at least the detection time required for detecting the TFT array defects of all the panels, even if the amount of heat generated by the short defect portion is small and the temperature rise is small, By increasing the detection time, the detection accuracy can be increased.
 本発明の駆動信号供給部は、選択したパネルに欠陥検出を行うための所定パターンの駆動信号を印加し、非選択のパネルにショート欠陥検出を行うための所定パターンの駆動信号を印加する。欠陥検出を行うための所定パターンは、検出する欠陥種に応じて設定することができる。 The drive signal supply unit of the present invention applies a drive signal having a predetermined pattern for detecting a defect to a selected panel, and applies a drive signal having a predetermined pattern for detecting a short defect to a non-selected panel. The predetermined pattern for performing defect detection can be set according to the defect type to be detected.
 基板上の全パネルにおいて、欠陥検出を行うパネルを選択し、このパネルに対して欠陥検出用の所定パターンの駆動信号を印加し、他の欠陥検出を行わないパネルに対してショート欠陥検出用の所定パターンの駆動信号を印加する。 In all the panels on the substrate, a panel for detecting a defect is selected, a drive signal of a predetermined pattern for detecting a defect is applied to this panel, and a panel for detecting a short defect for a panel not performing other defect detection. A drive signal having a predetermined pattern is applied.
 このとき、欠陥検出を行うパネルには欠陥検出用の駆動信号が供給されるため、パネルの全アレイについてショート欠陥検出は行われないものの、駆動信号が供給されたアレイについてはショート欠陥検出を行うことができる。 At this time, since a drive signal for defect detection is supplied to the panel that performs defect detection, short defect detection is not performed for the entire array of the panel, but short defect detection is performed for the array to which the drive signal is supplied. be able to.
 また、選択されたパネルについては、アレイ欠陥検出の検出時間はショート欠陥検出の検出時間よりも短時間であるため、駆動信号が供給されたアレイ部分にショート欠陥がある場合であっても、アレイ欠陥検出時に加熱されないことにより影響は無視できる程度とすることができる。 Also, for the selected panel, the detection time of the array defect detection is shorter than the detection time of the short defect detection, so even if there is a short defect in the array part to which the drive signal is supplied, The influence can be made negligible by not being heated at the time of defect detection.
 また、本発明の駆動信号供給部は、ショート欠陥検出部の欠陥検出中に、ショート欠陥検出部が検出したショート欠陥の欠陥点のTFTアレイへの駆動信号の供給を中断する。 Further, the drive signal supply unit of the present invention interrupts the supply of the drive signal to the TFT array at the defect point of the short defect detected by the short defect detection unit during the defect detection of the short defect detection unit.
 特定のTFTアレイへの駆動信号の供給を中断することによって、その箇所に対する電圧の印加を中断する。この箇所にショート欠陥がある場合には、発熱作用が停止するため、温度が低下する。これによって、基板上に設けられたアレイやラインの加熱による損傷を防ぐことができる。 * By interrupting the supply of the drive signal to a specific TFT array, the voltage application to that location is interrupted. If there is a short defect at this location, the heat generation action stops and the temperature drops. This can prevent damage to the array or line provided on the substrate due to heating.
 また、本発明のショート欠陥検出部は、駆動信号の供給中断後の熱検出器の検出信号に基づいて、検出したショート欠陥の正否を評価する。ショート欠陥の欠陥点のTFTアレイへの駆動信号の供給を中断するとその箇所の発熱が停止する。発熱で温度が上昇していた箇所は、発熱が停止した後、放熱によって温度が低下する。この温度変化を熱検出器の検出信号に基づいて検出する。温度低下が検出された場合には、検出位置がショート欠陥の欠陥位置であったことを確認することができる。一方、温度低下が検出されない場合には、検出位置がショート欠陥の欠陥位置でなかったことが分かる。 Also, the short defect detection unit of the present invention evaluates the correctness of the detected short defect based on the detection signal of the heat detector after the supply of the drive signal is interrupted. When the supply of the drive signal to the TFT array at the defective point of the short defect is interrupted, the heat generation at that point is stopped. The location where the temperature has increased due to heat generation decreases after the heat generation stops after the heat generation stops. This temperature change is detected based on the detection signal of the heat detector. When a temperature drop is detected, it can be confirmed that the detection position is a defect position of a short defect. On the other hand, when the temperature drop is not detected, it can be seen that the detection position was not the defect position of the short defect.
 また、本発明の駆動信号供給部は、ショート欠陥検出部の欠陥検出中に、ショート欠陥検出部が検出したショート欠陥の欠陥点のTFTアレイへの駆動信号の供給を中断し、所定時間経過後にTFTアレイへの駆動信号の供給を再開する。駆動信号の供給再会後の熱検出器の検出信号に基づいて、検出したショート欠陥の正否を評価する。 The drive signal supply unit of the present invention interrupts the supply of the drive signal to the TFT array at the defect point of the short defect detected by the short defect detection unit during the defect detection of the short defect detection unit, and after a predetermined time has elapsed. The supply of drive signals to the TFT array is resumed. The correctness of the detected short-circuit defect is evaluated based on the detection signal of the heat detector after the drive signal supply is reunited.
 TFTアレイへの駆動信号の供給中断することによって欠陥箇所の加熱を停止し、放熱によって温度が低下した後、駆動信号の供給を再開する。このときの温度変化を熱検出器の検出信号に基づいて検出する。温度低下した後、温度の再上昇が検出された場合には、検出位置がショート欠陥の欠陥位置であったことを確認することができる。一方、温度の再上昇が検出されないた場合には、検出位置がショート欠陥の欠陥位置でなかったことが分かる。 加熱 Stop supplying the drive signal to the TFT array to stop the heating of the defective part, and restart the supply of the drive signal after the temperature decreases due to heat dissipation. The temperature change at this time is detected based on the detection signal of the heat detector. If a rise in temperature is detected after the temperature has dropped, it can be confirmed that the detection position is a defect position of a short defect. On the other hand, when the temperature rise is not detected, it can be understood that the detection position is not the defect position of the short defect.
 また、本発明のTFT基板検査方法は、TFT基板の欠陥を検査するTFT基板の検査方法であって、真空チャンバ内に収納した基板のTFTアレイに駆動信号を供給する駆動信号供給工程と、基板に電子線を照射し、前記電子線の照射によって基板から放出される二次電子を検出し、前記二次電子の検出信号から得られる走査画像に基づいてTFTアレイの欠陥を検出するTFTアレイ欠陥工程と、駆動信号が供給された基板から放射される放熱を検出し、前記放熱の検出信号から得られる熱分布画像に基づいてショート欠陥を検出するショート欠陥検出工程とを備える。 The TFT substrate inspection method of the present invention is a TFT substrate inspection method for inspecting a TFT substrate for a defect, and includes a drive signal supply step for supplying a drive signal to a TFT array of a substrate housed in a vacuum chamber, A TFT array defect that detects a defect of a TFT array based on a scanning image obtained from a detection signal of the secondary electron, by detecting secondary electrons emitted from the substrate by the electron beam irradiation. And a short defect detection step of detecting heat radiation radiated from the substrate supplied with the drive signal and detecting a short defect based on a heat distribution image obtained from the heat radiation detection signal.
 TFTアレイ欠陥検出工程は、基板が備える複数のパネルから一つのパネルを順に選択してTFTアレイ欠陥検出を行い、ショート欠陥検出工程は、基板が備える全パネルについて同時にショート欠陥検出を行う。 In the TFT array defect detection step, one panel is sequentially selected from a plurality of panels included in the substrate to detect TFT array defects, and in the short defect detection step, short defect detection is performed simultaneously on all the panels included in the substrate.
 本発明の駆動信号供給工程は、選択したパネルに欠陥検出を行うための所定パターンの駆動信号を印加し、非選択のパネルにショート欠陥検出を行うための所定パターンの駆動信号を印加する。 In the drive signal supply process of the present invention, a drive signal having a predetermined pattern for detecting a defect is applied to a selected panel, and a drive signal having a predetermined pattern for detecting a short defect is applied to a non-selected panel.
 本発明の駆動信号供給工程は、ショート欠陥検出工程中に、そのショート欠陥検出工程で検出したショート欠陥の欠陥点のTFTアレイへの駆動信号の供給を中断する。これによって、発熱による基板の損傷を防ぐことができる。 In the drive signal supply process of the present invention, during the short defect detection process, the supply of the drive signal to the TFT array at the defect point of the short defect detected in the short defect detection process is interrupted. This can prevent damage to the substrate due to heat generation.
 本発明のショート欠陥検出工程は、駆動信号の供給中断後の放熱の検出信号に基づいて、検出したショート欠陥の正否を評価する。 In the short defect detection step of the present invention, the correctness of the detected short defect is evaluated based on the detection signal of heat dissipation after the supply of the drive signal is interrupted.
 また、本発明の駆動信号供給工程は、ショート欠陥検出工程中に、そのショート欠陥検出工程が検出したショート欠陥の欠陥点のTFTアレイへの駆動信号の供給を中断し、所定時間経過後に前記TFTアレイへの駆動信号の供給を再開し、駆動信号の供給再会後の放熱の検出信号に基づいて、検出したショート欠陥の正否を評価する。 In the drive signal supply process of the present invention, during the short defect detection process, the supply of the drive signal to the TFT array at the defect point of the short defect detected by the short defect detection process is interrupted, and after the predetermined time has elapsed, the TFT The supply of the drive signal to the array is resumed, and the correctness of the detected short defect is evaluated based on the detection signal of the heat radiation after the drive signal supply is reunited.
 本発明のTFT基板検査方法によれば、検出したショート欠陥の検出位置が正しいか否かを確認することができる。 According to the TFT substrate inspection method of the present invention, it is possible to confirm whether or not the detected position of the detected short defect is correct.
 本発明によれば、複数のパネルが形成された基板について、電子線照射による欠陥検出と熱検出によるショート欠陥検出とを行う際において、基板全体の欠陥検出時間を短縮することができる。 According to the present invention, when performing defect detection by electron beam irradiation and short defect detection by thermal detection for a substrate on which a plurality of panels are formed, the defect detection time of the entire substrate can be shortened.
本発明の基板検査装置の概略図である。It is the schematic of the board | substrate inspection apparatus of this invention. 本発明のTFT基板検査装置によるアレイ欠陥検出およびショート欠陥検出の動作を説明するためのフローチャートである。It is a flowchart for demonstrating operation | movement of the array defect detection by the TFT substrate test | inspection apparatus of this invention, and a short defect detection. 本発明のTFT基板検査装置によるアレイ欠陥検出およびショート欠陥検出の動作を説明するためのタイミングチャートである。It is a timing chart for demonstrating the operation | movement of the array defect detection by the TFT substrate test | inspection apparatus of this invention, and a short defect detection. 本発明のTFT基板検査装置によるアレイ欠陥検出およびショート欠陥検出の動作を説明するためのパネル動作図である。It is a panel operation | movement figure for demonstrating operation | movement of the array defect detection by the TFT substrate test | inspection apparatus of this invention, and a short defect detection. 本発明のTFT基板検査装置によるアレイ欠陥検出動作を説明するためのフローチャートである。It is a flowchart for demonstrating the array defect detection operation | movement by the TFT substrate test | inspection apparatus of this invention. 本発明のTFT基板検査装置によるショート欠陥検出の第1の形態を説明するためのフローチャートである。It is a flowchart for demonstrating the 1st form of the short defect detection by the TFT substrate test | inspection apparatus of this invention. 本発明のTFT基板検査装置によるショート欠陥検出の第1の形態を説明するためのタイミングチャートである。It is a timing chart for demonstrating the 1st form of the short defect detection by the TFT substrate test | inspection apparatus of this invention. 本発明のTFT基板検査装置によるショート欠陥検出の第2の形態を説明するためのフローチャートである。It is a flowchart for demonstrating the 2nd form of the short defect detection by the TFT substrate test | inspection apparatus of this invention. 本発明のTFT基板検査装置によるショート欠陥検出の第2の形態を説明するためのタイミングチャートである。It is a timing chart for demonstrating the 2nd form of the short defect detection by the TFT substrate test | inspection apparatus of this invention. 本発明のTFT基板検査装置によるショート欠陥検出の第3の形態を説明するためのフローチャートである。It is a flowchart for demonstrating the 3rd form of the short defect detection by the TFT substrate test | inspection apparatus of this invention. 本発明のTFT基板検査装置によるショート欠陥検出の第3の形態を説明するためのタイミングチャートである。It is a timing chart for demonstrating the 3rd form of the short defect detection by the TFT substrate test | inspection apparatus of this invention. ライン欠陥および点欠陥を説明するための図である。It is a figure for demonstrating a line defect and a point defect. ライン欠陥を説明するための図である。It is a figure for demonstrating a line defect. ライン欠陥によるシグナルイメージを示す図である。It is a figure which shows the signal image by a line defect.
 1 基板検査装置
 2 欠陥検出部
 2a 画像処理部
 2b アレイ欠陥検出部
 2c ショート欠陥検出部
 2d 欠陥位置校正部
 2e 欠陥データ格納部
 3 主制御部
 4 駆動信号供給部
 5 走査制御部
 6 電子線源
 7 二次電子検出部
 8 二次電子フレーム画像取り込み部
 9 熱検出部
 10 熱フレーム画像取り込み部
 11 ステージ
 20 基板
 21 ソースバー
 22 ゲートバー
 23 共通バー
 31 ソースライン
 32 ゲートライン
 33 共通ライン
 34 画素電極
 40 画素
 51 ライン
 52 ライン
DESCRIPTION OF SYMBOLS 1 Board | substrate inspection apparatus 2 Defect detection part 2a Image processing part 2b Array defect detection part 2c Short defect detection part 2d Defect position calibration part 2e Defect data storage part 3 Main control part 4 Drive signal supply part 5 Scan control part 6 Electron source 7 Secondary electron detection unit 8 Secondary electron frame image capturing unit 9 Thermal detection unit 10 Thermal frame image capturing unit 11 Stage 20 Substrate 21 Source bar 22 Gate bar 23 Common bar 31 Source line 32 Gate line 33 Common line 34 Pixel electrode 40 Pixel 51 Line 52 line
 以下、本発明の実施の形態について、図を参照しながら詳細に説明する。図1は、本発明のTFT基板検査装置の概略図である。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic view of a TFT substrate inspection apparatus of the present invention.
 TFT基板検査装置1は、真空チャンバ(図示していない)内に設けられたステージ11に載置されたTFT基板20のアレイ欠陥およびショート欠陥を検出する。 The TFT substrate inspection apparatus 1 detects an array defect and a short defect of the TFT substrate 20 placed on a stage 11 provided in a vacuum chamber (not shown).
 アレイ欠陥を検出する構成として、TFT基板20上に電子線を照射する電子線源6、TFT基板20をx,y方向に移動させるステージ11、電子線源6およびステージ11を制御して電子線をTFT基板20上で走査させる走査制御部5、TFT基板20から放出される二次電子を検出する二次電子検出部7、二次電子検出部7で検出した二次電子の検出信号から二次電子フレーム画像を形成する二次電子フレーム画像取り込み部8、二次電子フレーム画像を画像処理して、座標位置とその位置の信号強度を求める画像処理部2a、求めた信号強度に基づいてアレイ欠陥を検出するアレイ欠陥検出部2bを備える。 As a configuration for detecting an array defect, an electron beam source 6 for irradiating the TFT substrate 20 with an electron beam, a stage 11 for moving the TFT substrate 20 in the x and y directions, an electron beam source 6 and the stage 11 are controlled to control the electron beam. From the secondary electron detection signal detected by the secondary electron detection unit 7, the secondary electron detection unit 7 for detecting secondary electrons emitted from the TFT substrate 20, and the secondary electron detection unit 7. A secondary electron frame image capturing unit 8 for forming a secondary electron frame image; an image processing unit 2a for performing image processing on the secondary electron frame image to obtain a coordinate position and a signal intensity at the position; and an array based on the obtained signal intensity. An array defect detection unit 2b for detecting defects is provided.
 ショート欠陥を検出する構成として、TFT基板20からの放熱を検出する熱検出部9、熱検出部9で検出した熱分布の検出信号から熱フレーム画像を形成する熱フレーム画像取り込み部10、熱画像を画像処理して、座標位置とその位置の信号強度を求める画像処理部2a、求めた信号強度に基づいてショート欠陥を検出するショート欠陥検出部2cを備える。熱検出部は、例えば、赤外線センサーやサーモグラフィを用いることができる。赤外線センサーとして、例えば、InSb検出器を用いたIR焦点面アレイ熱撮像カメラが知られている(特許文献5)。 As a configuration for detecting a short defect, a heat detection unit 9 that detects heat radiation from the TFT substrate 20, a thermal frame image capturing unit 10 that forms a thermal frame image from a detection signal of the heat distribution detected by the heat detection unit 9, and a thermal image Are processed, and an image processing unit 2a for obtaining a coordinate position and a signal intensity at the position, and a short defect detecting unit 2c for detecting a short defect based on the obtained signal intensity are provided. For example, an infrared sensor or a thermography can be used for the heat detection unit. As an infrared sensor, for example, an IR focal plane array thermal imaging camera using an InSb detector is known (Patent Document 5).
 欠陥検出部2は、前記した画像処理部2a、アレイ欠陥検出部2b、およびショート欠陥検出部2cの他に、欠陥位置校正部2d、欠陥データ格納部2eを備える。欠陥位置校正部2dは、アレイ欠陥検出部2bで検出したアレイ欠陥の座標位置と、ショート欠陥検出部2cで検出したショート欠陥の座標位置に基づいて、同一点のショート欠陥の座標位置を校正する。 The defect detection unit 2 includes a defect position calibration unit 2d and a defect data storage unit 2e in addition to the image processing unit 2a, the array defect detection unit 2b, and the short defect detection unit 2c. The defect position calibration unit 2d calibrates the coordinate position of the short defect at the same point based on the coordinate position of the array defect detected by the array defect detection unit 2b and the coordinate position of the short defect detected by the short defect detection unit 2c. .
 欠陥検出部2、駆動信号供給部4,走査制御部5等の各部は、主制御部3によって制御される。主制御部3および走査制御部5は、CPUおよびこのCPUを駆動して所定の動作を実行させるためプログラムをROM等の記憶手段(図示していない)を備えている。 Each unit such as the defect detection unit 2, the drive signal supply unit 4, and the scan control unit 5 is controlled by the main control unit 3. The main control unit 3 and the scan control unit 5 include a CPU and storage means (not shown) such as a ROM for driving the CPU to execute a predetermined operation.
 図1中に示すTFT基板20の構成は一例を示している。図示する構成では、TFT基板20上に複数のパネルが設けられ、各パネルには複数の画素40が配置されてアレイが構成されている。 1 shows an example of the configuration of the TFT substrate 20 shown in FIG. In the illustrated configuration, a plurality of panels are provided on the TFT substrate 20, and a plurality of pixels 40 are arranged on each panel to form an array.
 各画素40には、ソースライン31、ゲートライン32、および共通ライン33が配されている。複数のソースライン31はソースバー21に接続され、駆動信号供給部4から供給されるソース信号が印加される。複数のゲートライン32はゲートバー22に接続され、駆動信号供給部4から供給されるゲート信号が印加される。また、複数の共通ライン33は共通バー23に接続され、駆動信号供給部4から供給される共通信号が印加される。 Each pixel 40 is provided with a source line 31, a gate line 32, and a common line 33. The plurality of source lines 31 are connected to the source bar 21 and applied with the source signal supplied from the drive signal supply unit 4. The plurality of gate lines 32 are connected to the gate bar 22 and a gate signal supplied from the drive signal supply unit 4 is applied thereto. The plurality of common lines 33 are connected to the common bar 23, and a common signal supplied from the drive signal supply unit 4 is applied thereto.
 駆動信号供給部43、TFT基板20上に形成されるTFTアレイを駆動する駆動信号の信号パターンを生成し供給する。駆動信号供給部4は、複数種の駆動パターンを生成することができる。例えば、TFTアレイの点欠陥を検出する信号パターンとして、全ピクセルに同一の電圧を供給する信号パターンを生成する。また、TFTアレイの欠陥種を判別するために、ピクセル単位の周期性を有する電圧を供給する信号パターンを生成する。 The drive signal supply unit 43 generates and supplies a drive signal signal pattern for driving the TFT array formed on the TFT substrate 20. The drive signal supply unit 4 can generate a plurality of types of drive patterns. For example, a signal pattern for supplying the same voltage to all pixels is generated as a signal pattern for detecting a point defect in the TFT array. Further, in order to determine the defect type of the TFT array, a signal pattern for supplying a voltage having a periodicity in pixel units is generated.
 画像処理部2aは、フレーム画像を信号処理してイメージ化し走査画像を形成する。アレイ欠陥検出部2bは、画像処理部2aで取得したピクセルの電位状態に基づいて正常状態における電位状態と比較し、正常状態の電位と異なる電位状態にあるピクセルについては、そのピクセルに接続されるTFTアレイに欠陥があるものとして検出する。また、検出した欠陥ピクセルについて、その欠陥ピクセルの欠陥種を判別する。 The image processing unit 2a converts the frame image into an image and forms a scanned image. The array defect detection unit 2b compares with the potential state in the normal state based on the potential state of the pixel acquired by the image processing unit 2a, and a pixel in a potential state different from the potential in the normal state is connected to the pixel. The TFT array is detected as defective. Further, the defect type of the detected defective pixel is determined.
 欠陥種判別は、欠陥ピクセルの欠陥種を判別する少なくとも2つの判定閾値、および、この複数の判定閾値で設定される複数の強度範囲に対応付けて欠陥ピクセルの欠陥種のデータを記憶している。駆動パターンの印加で得られる走査画像の信号強度をこの判定閾値と比較し、比較結果に基づいて複数の強度範囲に仕分けし、欠陥ピクセルの欠陥種を判定する。 The defect type determination stores at least two determination threshold values for determining the defect type of the defective pixel, and defect type data of the defective pixel in association with a plurality of intensity ranges set by the plurality of determination threshold values. . The signal intensity of the scanned image obtained by applying the drive pattern is compared with the determination threshold value, and is classified into a plurality of intensity ranges based on the comparison result, and the defect type of the defective pixel is determined.
 また、点欠陥検出で検出した欠陥ピクセルの位置、欠陥種判別で検出したピクセルの幾何的配置、および基板上に形成されるピクセルの設計上の位置等に基づいて欠陥ピクセルの位置を特定する。 Also, the position of the defective pixel is specified based on the position of the defective pixel detected by the point defect detection, the geometrical arrangement of the pixel detected by the defect type discrimination, the design position of the pixel formed on the substrate, and the like.
 ショート欠陥検出部2cは、画像処理部2aで取得した熱分布を表す信号強度と正常状態にある熱分布の信号強度と比較し、正常状態の信号強度と異なる信号強度にある部位については、その部位にショート欠陥があるものとして検出する。また、検出したショート欠陥の位置、および基板上に形成されるピクセルやラインの設計上の位置等に基づいてショート欠陥の位置を特定する The short defect detection unit 2c compares the signal intensity representing the heat distribution acquired by the image processing unit 2a with the signal intensity of the heat distribution in the normal state. It is detected that the part has a short defect. In addition, the position of the short defect is specified based on the position of the detected short defect and the design position of the pixels and lines formed on the substrate.
 走査制御部5は、TFT基板20上のTFTアレイの検査位置を走査するために、ステージ11や電子線源6を制御する。ステージ11は、載置するTFT基板20をXY方向に移動し、また、電子線源6はTFT基板20に照射する電子線をXY方向に振ることで、電子線の照射位置を走査する。 The scanning control unit 5 controls the stage 11 and the electron beam source 6 in order to scan the inspection position of the TFT array on the TFT substrate 20. The stage 11 moves the TFT substrate 20 to be placed in the XY direction, and the electron beam source 6 scans the irradiation position of the electron beam by shaking the electron beam irradiating the TFT substrate 20 in the XY direction.
 なお、上記したTFTアレイ検査装置の構成は一例であり、この構成に限られるものではない。 The above-described configuration of the TFT array inspection apparatus is an example, and is not limited to this configuration.
  [TFT基板検査装置の欠陥検出動作]
 以下、図2~図4を用いて、本発明のTFT基板検査装置によるアレイ欠陥検出およびショート欠陥検出の動作について説明する。図2,3,4は、TFT基板検査装置によるアレイ欠陥検出およびショート欠陥検出の動作を説明するためのフローチャート、タイミングチャート、およびパネル動作図である。
[Defect detection operation of TFT substrate inspection equipment]
Hereinafter, the array defect detection and short defect detection operations by the TFT substrate inspection apparatus of the present invention will be described with reference to FIGS. 2, 3 and 4 are a flowchart, a timing chart, and a panel operation diagram for explaining operations of array defect detection and short-circuit defect detection by the TFT substrate inspection apparatus.
 なお、ここでは、TFT基板上に9枚のパネル(パネルA~パネルI)が設けられた例を用いて説明するが、TFT基板上に設けるパネルの枚数、各パネルのサイズ、および配置位置は任意に設定することができる。 Here, an example in which nine panels (panel A to panel I) are provided on the TFT substrate will be described. However, the number of panels provided on the TFT substrate, the size of each panel, and the arrangement position are as follows. It can be set arbitrarily.
 TFT基板上の配置されたパネルに電子線を照射して走査することによってアレイ欠陥検出を行う。ここでは、TFT基板上に設けられた複数のパネルの内から一枚のパネルを選択し、選択したパネルに電子線を照射して走査し二次電子を検出することによってアレイ欠陥検出を行い、全パネルについて放熱を検出することによってショート欠陥検出を行う。 Detecting array defects by irradiating and scanning an electron beam on a panel arranged on a TFT substrate. Here, a single panel is selected from a plurality of panels provided on the TFT substrate, and the selected panel is irradiated with an electron beam and scanned to detect secondary electrons, thereby detecting array defects. Short defect detection is performed by detecting heat dissipation for all panels.
 図3のタイミングチャートはTFT基板上に配置されたパネルA~パネルIの各パネルについて、アレイ欠陥検出を行うタイミングとショート欠陥検出を行うタイミングを示している。 The timing chart of FIG. 3 shows the timing of performing array defect detection and the timing of performing short defect detection for each of the panels A to I arranged on the TFT substrate.
 図3(a)~図3(i)は、パネルA~パネルIにおけるアレイ欠陥検出とショート欠陥検出の各タイミングを示している。ここでは、パネルAから順にアレイ欠陥検出を行う例を示している。パネルAは全パネルの内で第1番目にアレイ欠陥検出を行い(図3(a))、パネルBは、パネルAのアレイ欠陥検出が終了した後、第2番目にアレイ欠陥検出を行い(図3(b))、同様に、パネルC~パネルIについて順にアレイ欠陥検出を行う。この間、全パネルについてショート欠陥検出を行う。 3 (a) to 3 (i) show timings of array defect detection and short-circuit defect detection in panels A to I. FIG. Here, an example in which array defect detection is performed in order from panel A is shown. Panel A performs array defect detection first in all panels (FIG. 3A), and panel B performs array defect detection second after the completion of array defect detection in panel A ( Similarly, as shown in FIG. 3B, array defect detection is performed in order for panels C to I. During this time, short defect detection is performed for all panels.
 本発明によれば、アレイ欠陥検出を順に行っている間に、全パネルについてショート欠陥検出を行うことによって、欠陥検出に要する時間を短縮することができる。 According to the present invention, the time required for defect detection can be shortened by performing short defect detection for all the panels while performing array defect detection in order.
 図4(a)は、TFT基板上に配置されたパネルA~パネルIを示している。アレイ欠陥検出は各パネルを単位として行い、一方、ショート欠陥検出は全パネルについてアレイ欠陥と同時に行う。 FIG. 4A shows panels A to I arranged on the TFT substrate. Array defect detection is performed in units of each panel, while short defect detection is performed simultaneously with array defects for all panels.
 図4(b)において、パネルAについてアレイ欠陥検出を行い、パネルA~パネルIの全パネルについてショート欠陥検出を行う。図4(c)において、パネルBについてアレイ欠陥検出を行い、パネルA~パネルIの全パネルについてショート欠陥検出を行う。同様に、図4(d)において、パネルIについてアレイ欠陥検出を行い、パネルA~パネルIの全パネルについてショート欠陥検出を行う。 4B, array defect detection is performed for panel A, and short defect detection is performed for all panels A to I. In FIG. 4C, array defect detection is performed for panel B, and short defect detection is performed for all panels A to I. Similarly, in FIG. 4D, array defect detection is performed for panel I, and short defect detection is performed for all panels A to I.
 図2のフローチャートにおいて、はじめに、TFT基板上の全パネルに駆動信号を印加してアレイを駆動する。これによってショート欠陥検出の準備が開始し、ショート欠陥部分は短絡電流によって発熱が始まる(S1)。 In the flowchart of FIG. 2, first, a drive signal is applied to all the panels on the TFT substrate to drive the array. As a result, preparation for short-circuit defect detection starts, and the short-circuit defect portion starts to generate heat due to a short-circuit current (S1).
 アレイ欠陥検出を行うために、電子線を走査するパネルを選択する(S2)。選択したパネルについてアレイ欠陥検出を行い(S3~S7)、選択パネルおよび非選択パネルについてショート欠陥検出を行う。なお、ショート欠陥検出において、非選択パネルにはショート欠陥を検出するための駆動信号が印加され、選択パネルにはアレイ欠陥を検出するための駆動信号が供給される。選択パネルには、ショート欠陥を検出するための駆動信号ではなく、アレイ欠陥を検出するための駆動信号が印加されるため、信号パターンによってはショート欠陥の欠陥部分に駆動信号が印加されない場合がある。 In order to detect array defects, a panel for scanning an electron beam is selected (S2). Array defect detection is performed for the selected panel (S3 to S7), and short defect detection is performed for the selected panel and the non-selected panel. In short defect detection, a drive signal for detecting a short defect is applied to a non-selected panel, and a drive signal for detecting an array defect is supplied to the selected panel. Since the drive signal for detecting the array defect is applied to the selected panel instead of the drive signal for detecting the short defect, the drive signal may not be applied to the defective portion of the short defect depending on the signal pattern. .
 しかしながら、次のパネルを選択したときには前回選択されたパネルにはショート欠陥検出用の駆動信号が供給されることになり、また、アレイ欠陥検出用の駆動信号を印加する期間は、全パネルについてアレイ欠陥検出を行う全期間と比較すると短期間であり、ショート欠陥検出用の信号が印加されないことによる影響は無視することができる程度に小さいとすることができる(S8)。 However, when the next panel is selected, a drive signal for short-circuit defect detection is supplied to the previously selected panel, and the period for applying the drive signal for array defect detection is the array for all the panels. Compared to the entire period in which defect detection is performed, the period is shorter, and the influence of not applying a signal for short defect detection can be made small enough to be ignored (S8).
 選択パネルについて、その選択したパネルが発熱を検出しているパネルであるかを判定する(S3)。選択パネルが発熱検出中のパネルである場合には、発熱を測定するためのショート欠陥検出用の駆動信号の印加を中断し、S5でパネルが既選択であるか否かを判定する。また、選択パネルが発熱検出中のパネルでない場合には、そのままS5でパネルが既選択であるか否かを判定する。 For the selected panel, it is determined whether the selected panel is a panel that detects heat generation (S3). If the selected panel is a panel in which heat generation is being detected, application of a drive signal for detecting a short defect for measuring heat generation is interrupted, and it is determined in S5 whether or not the panel has already been selected. If the selected panel is not a panel for which heat generation is being detected, it is determined whether or not the panel has already been selected in S5.
 選択したパネルが既選択でない場合には(S5)、電子線走査によるアレイ欠陥検出処理を行う(S6)。選択したパネルが既選択済みである場合には(S5)、アレイ欠陥検出処理をスキップする。S3~S6の工程を全パネルについて行って、TFT基板上の全パネルについてアレイ欠陥検出を行う(S7)。 If the selected panel is not already selected (S5), array defect detection processing by electron beam scanning is performed (S6). If the selected panel has already been selected (S5), the array defect detection process is skipped. Steps S3 to S6 are performed for all the panels, and array defect detection is performed for all the panels on the TFT substrate (S7).
 アレイ欠陥検出で検出した欠陥点の中には、駆動信号パターンによってショート欠陥による欠陥点が含まれる場合がある。そこで、アレイ欠陥検出で検出されたショート欠陥の座標位置と、S8のショート欠陥検出処理で検出されたショート欠陥の座標位置とを照合し(S9)、同一のショート欠陥について座標位置が一致ない場合には、座標位置を校正する。ショート欠陥の座標位置の校正は、TFT基板上のアレイやラインの配置位置情報、アレイ欠陥検出やショート欠陥検出で得られたイメージ画像等に基づいて行うことができる(S10)。検出したショート欠陥点の座標位置を、欠陥データ格納部2e等に記憶する(S11)。 Defective points detected by array defect detection may include defective points due to short-circuit defects depending on the drive signal pattern. Therefore, the coordinate position of the short defect detected by the array defect detection and the coordinate position of the short defect detected by the short defect detection process of S8 are collated (S9), and the coordinate position does not match for the same short defect To calibrate the coordinate position. Calibration of the coordinate position of the short defect can be performed based on the arrangement position information of the array and lines on the TFT substrate, the image image obtained by the array defect detection and the short defect detection, and the like (S10). The detected coordinate position of the short defect point is stored in the defect data storage unit 2e or the like (S11).
  [アレイ欠陥検出動作] 
 次に、アレイ欠陥検出の動作について、図5のフローチャートを用いて説明する。図5は本発明のTFT基板検査装置によるアレイ欠陥検出動作を説明するためのフローチャートである。このアレイ欠陥検出動作の処理は、図2中のS6の工程に相当するものである。
[Array defect detection operation]
Next, the array defect detection operation will be described with reference to the flowchart of FIG. FIG. 5 is a flowchart for explaining the array defect detection operation by the TFT substrate inspection apparatus of the present invention. The processing of this array defect detection operation corresponds to the step S6 in FIG.
 電子線を照射するパネルを選択し(S101)、選択したパネルにアレイ欠陥検出用の駆動信号を印加する(S102)。選択したパネル上に電子線を照射しながら走査し、TFT基板から放出される二次電子を二次電子検出器で検出する(S103)。検出した二次電子の検出信号からアレイ欠陥に係る画像データを取得する。画像データは、検出信号の強度と座標位置のデータを含んでいる(S104)。 The panel that irradiates the electron beam is selected (S101), and a drive signal for array defect detection is applied to the selected panel (S102). The selected panel is scanned while being irradiated with an electron beam, and secondary electrons emitted from the TFT substrate are detected by a secondary electron detector (S103). Image data related to the array defect is acquired from the detected secondary electron detection signal. The image data includes the data of the detection signal intensity and the coordinate position (S104).
 欠陥画像データを用いてアレイ欠陥を検出する。欠陥検出は、検出信号の強度をあらかじめ定めておいた閾値と比較することで行うことができる(S105)。S105の工程で検出したアレイ欠陥点の座標位置を求める(S106)。 Detect array defects using defect image data. The defect detection can be performed by comparing the intensity of the detection signal with a predetermined threshold value (S105). The coordinate position of the array defect point detected in step S105 is obtained (S106).
 S101~S106の工程を全パネルについて行って、TFT基板の全パネルについてアレイ欠陥を検出する(S107)。 Steps S101 to S106 are performed for all the panels, and array defects are detected for all the panels on the TFT substrate (S107).
  [ショート欠陥検出動作] 
 次に、本発明のTFT基板検査装置によるショート欠陥検出動作について、図6~図11について説明する。以下、ショート欠陥検出動作について第1の形態~第3の形態について説明する。第2,3の形態は、検出したショート欠陥の正否を評価する形態である。
[Short defect detection operation]
Next, a short defect detection operation by the TFT substrate inspection apparatus of the present invention will be described with reference to FIGS. Hereinafter, first to third embodiments of the short defect detection operation will be described. In the second and third forms, the correctness of the detected short defect is evaluated.
  [ショート欠陥検出動作の第1の形態]
 図6,7を用いて本発明のTFT基板検査装置によるショート欠陥検出の第1の形態について説明する。
[First form of short defect detection operation]
A first embodiment of short defect detection by the TFT substrate inspection apparatus of the present invention will be described with reference to FIGS.
 図6のフローチャートにおいて、はじめに、TFT基板上の全パネルにショート欠陥検出用の駆動信号を印加する。この駆動信号の印加によって、ライン間にショート欠陥がある場合にはその欠陥点に電流が流れ、電気抵抗によって発熱が生じる。発熱量は欠陥点のショート状態に依存する。ショート欠陥が小さい場合には、高抵抗であるため発熱量は少ない。ショート欠陥が大きい場合には、低抵抗であるため発熱量は多くなる。 In the flowchart of FIG. 6, first, a drive signal for detecting a short defect is applied to all the panels on the TFT substrate. When there is a short defect between the lines due to the application of the drive signal, a current flows through the defective point, and heat is generated by the electric resistance. The amount of heat generation depends on the short state of the defect point. When the short defect is small, the amount of heat generated is small because of the high resistance. When the short-circuit defect is large, the amount of heat generation increases because of the low resistance.
 発熱量が小さい場合には、温度の上昇速度が小さいため、所定の温度に達するまでに要する時間は長くなる。一方、発熱量が大きい場合には、温度の上昇速度が大きいため、所定の温度に達するまでに要する時間は短くなる(S201)。 When the calorific value is small, the time required to reach a predetermined temperature becomes long because the rate of temperature rise is small. On the other hand, when the calorific value is large, the temperature rise rate is large, so that the time required to reach the predetermined temperature is short (S201).
 TFT基板に駆動信号を印加してからショート欠陥を検出するまでの時間をあらかじめ定めておき、この設定時間が経過するまで駆動信号の印加を続ける(S202)。設定時間が経過した後、TFT基板上の全パネルの発熱を熱検出器で測定する(S203)。熱検出器で測定した検出信号からショート欠陥の画像データを所得する。画像データは、検出信号の強度と座標位置のデータを含んでいる(S204)。 The time from when the drive signal is applied to the TFT substrate until the short defect is detected is determined in advance, and the drive signal is continuously applied until the set time elapses (S202). After the set time has elapsed, the heat generation of all the panels on the TFT substrate is measured with a heat detector (S203). The image data of the short defect is obtained from the detection signal measured by the thermal detector. The image data includes the data of the detection signal intensity and the coordinate position (S204).
 画像データを用いてショート欠陥を検出する。欠陥検出は、検出信号の強度をあらかじめ定めておいた閾値と比較することで行うことができる(S205)。S205の工程で検出したショート欠陥点の座標位置を求める(S206)。 Detect short defects using image data. The defect detection can be performed by comparing the intensity of the detection signal with a predetermined threshold value (S205). The coordinate position of the short defect point detected in step S205 is obtained (S206).
 図7(a)はショート欠陥が無い正常状態の検出信号の信号強度と印加信号を示し、図7(b),(c)はショート欠陥がある状態の検出信号の信号強度と印加信号を示し、図7(d)は測定タイミングを示している。 7A shows the signal intensity and applied signal of a detection signal in a normal state without a short defect, and FIGS. 7B and 7C show the signal intensity and applied signal of a detection signal in a state of a short defect. FIG. 7D shows the measurement timing.
 ショート欠陥が無い正常状態では、短絡電流による発熱が無いためほぼ一定温度を維持する(図7(a))。 In a normal state with no short-circuit defect, there is no heat generation due to a short-circuit current, and thus a substantially constant temperature is maintained (FIG. 7 (a)).
 これに対して、ショート欠陥がある状態では、短絡電流によって発熱が発生し、温度が時間と共に上昇する。図7(b)は、小さなショート欠陥の場合を示している。この場合には、短絡電流が小さいため、温度の上昇速度は小さい。一方、図7(c)は、大きなショート欠陥の場合を示している。この場合には、短絡電流が大きいため、温度の上昇速度は大きくなる。 In contrast, when there is a short circuit defect, heat is generated by the short circuit current, and the temperature rises with time. FIG. 7B shows the case of a small short defect. In this case, since the short circuit current is small, the temperature increase rate is small. On the other hand, FIG. 7C shows the case of a large short defect. In this case, since the short-circuit current is large, the rate of temperature rise increases.
 ショート欠陥の判定は、図7(d)の測定タイミングの時点において、検出信号の信号強度と閾値と比較することで行うことができる。 The determination of the short defect can be performed by comparing the signal intensity of the detection signal with the threshold at the time of the measurement timing in FIG.
  [ショート欠陥検出動作の第2の形態]
 図8,9を用いて本発明のTFT基板検査装置によるショート欠陥検出の第2の形態について説明する。
[Second form of short defect detection operation]
A second embodiment of short defect detection by the TFT substrate inspection apparatus of the present invention will be described with reference to FIGS.
 第2の形態は、ショート欠陥による温度上昇が所定温度に達したときに、駆動信号の印加を中断することによって、ショート欠陥点の温度上昇を停止させて、その箇所の熱による損傷を防ぐ形態であり、さらに、ショート欠陥検出の検出点が正しく検出されたか否かを評価することもできる。 In the second form, when the temperature rise due to the short defect reaches a predetermined temperature, the application of the drive signal is interrupted to stop the temperature rise at the short defect point and prevent the damage due to heat at that point. Further, it can be evaluated whether or not the detection point of short defect detection is correctly detected.
 図8のフローチャートにおいて、はじめに、TFT基板上の全パネルにショート欠陥検出用の駆動信号を印加する(S301)。以下、測定タイミングで熱検出器によって発熱を測定する(S302,S303)。熱検出器の検出信号からショート欠陥画像データを取得する。画像データは、検出信号の強度と座標位置のデータを含んでいる(S304)。 In the flowchart of FIG. 8, first, a drive signal for detecting a short defect is applied to all the panels on the TFT substrate (S301). Hereinafter, heat generation is measured by the heat detector at the measurement timing (S302, S303). Short defect image data is acquired from the detection signal of the thermal detector. The image data includes data of the detection signal intensity and coordinate position (S304).
 前記したS205、S206と同様に、画像データを用いてショート欠陥を検出する。欠陥検出は、検出信号の強度をあらかじめ定めておいた閾値と比較することで行うことができる(S307)。S307の工程で検出したショート欠陥点の座標位置を求めて記録する(S308)。 In the same manner as S205 and S206 described above, a short defect is detected using image data. Defect detection can be performed by comparing the intensity of the detection signal with a predetermined threshold (S307). The coordinate position of the short defect point detected in step S307 is obtained and recorded (S308).
 次に、検出したショート欠陥点への駆動信号の印加を停止する。ショート欠陥点への駆動信号の印加を停止することによって、ショート欠陥点の温度上昇を停止させ、ショート欠陥点付近が熱によって損傷することを防ぐ(S309)。 Next, application of the drive signal to the detected short defect point is stopped. By stopping the application of the drive signal to the short defect point, the temperature rise of the short defect point is stopped and the vicinity of the short defect point is prevented from being damaged by heat (S309).
 S305~S306は、駆動信号の印加を停止した位置が、ショート欠陥点であるか否かを評価する工程である。駆動信号の印加を停止すると、その停止位置がショート欠陥点である場合には、ショート欠陥点での発熱が無くなり、放熱によって温度が低下する。この温度変化を検出することによって、検出した点がショート欠陥点であるか否かを確認することができる。正しいショート欠陥点である場合には温度低下が検出され、検出した点が誤りである場合には温度低下は検出されず、発熱が検出される。 S305 to S306 are processes for evaluating whether or not the position where the application of the drive signal is stopped is a short defect point. When the application of the drive signal is stopped, if the stop position is a short defect point, heat is not generated at the short defect point, and the temperature is lowered by heat dissipation. By detecting this temperature change, it can be confirmed whether or not the detected point is a short defect point. If it is a correct short defect point, a temperature drop is detected, and if the detected point is incorrect, a temperature drop is not detected and heat generation is detected.
 S305において、駆動信号の印加を停止した位置の検出信号の強度をあらかじめ定めておいた閾値と比較し、検出信号の強度が閾値よりも小さく、温度低下が確認された場合には、正しいショート欠陥点であることが確認される。一方、検出信号の強度が閾値よりも大きく、温度低下が確認されない場合には、検出した点はショート欠陥点でないことが確認される。検出した点がショート欠陥点でない場合には、その点への駆動信号の印加を再開し、次の測定タイミングでショート欠陥検出を繰り返す(S306,S310)。 In S305, if the intensity of the detection signal at the position where the application of the drive signal is stopped is compared with a predetermined threshold, and if the intensity of the detection signal is smaller than the threshold and a temperature drop is confirmed, the correct short defect It is confirmed that it is a point. On the other hand, when the intensity of the detection signal is larger than the threshold value and no temperature decrease is confirmed, it is confirmed that the detected point is not a short defect point. If the detected point is not a short defect point, the application of the drive signal to the point is restarted, and short defect detection is repeated at the next measurement timing (S306, S310).
 図8(a)はショート欠陥が無い正常状態の検出信号の信号強度と印加信号を示し、図8(b)はショート欠陥がある状態の検出信号の信号強度と印加信号を示し、図8(c)は測定タイミングを示している。図8(a),(b)において、黒点は図8(c)の測定タイミングで測定される検出点を示している。 FIG. 8A shows the signal intensity and applied signal of a detection signal in a normal state without a short defect, and FIG. 8B shows the signal intensity and applied signal of a detection signal in a state of a short defect. c) shows the measurement timing. 8 (a) and 8 (b), black dots indicate detection points measured at the measurement timing in FIG. 8 (c).
 ショート欠陥が無い正常状態では、短絡電流による発熱が無いためほぼ一定温度を維持する(図8(a))。 In a normal state with no short-circuit defect, there is no heat generation due to a short-circuit current, so that a substantially constant temperature is maintained (FIG. 8A).
 これに対して、ショート欠陥がある状態では、短絡電流によって発熱が発生し、温度が時間と共に上昇する。図8(b)において、ショート欠陥の短絡電流によって発熱し、温度が上昇する。ここで、ショート欠陥を検出する閾値として、あらかじめ検出信号の強度を定めており、検出信号の信号強度と閾値とを比較する。検出信号の信号強度が閾値を越えた時点で、そのショート欠陥の位置に対応する駆動信号の印加を停止する。 In contrast, when there is a short circuit defect, heat is generated by the short circuit current, and the temperature rises with time. In FIG. 8B, heat is generated by the short-circuit current of the short defect, and the temperature rises. Here, the intensity of the detection signal is determined in advance as a threshold for detecting a short defect, and the signal intensity of the detection signal is compared with the threshold. When the signal intensity of the detection signal exceeds the threshold value, the application of the drive signal corresponding to the position of the short defect is stopped.
  [ショート欠陥検出動作の第3の形態]
 図10,11を用いて本発明のTFT基板検査装置によるショート欠陥検出の第2の形態について説明する。
[Third form of short defect detection operation]
A second embodiment of short defect detection by the TFT substrate inspection apparatus of the present invention will be described with reference to FIGS.
 第3の形態は、ショート欠陥による温度上昇が所定温度に達したときに、駆動信号の印加を中断した後、再度駆動信号を印加することによって、ショート欠陥検出が正しく行われたか否かを評価する形態である。
 図10のフローチャートにおいて、はじめに、TFT基板上の全パネルにショート欠陥検出用の駆動信号を印加する(S401)。以下、測定タイミングで熱検出器によって発熱を測定する(S402,403)。熱検出器の検出信号からショート欠陥画像データを取得する。画像データは、検出信号の強度と座標位置のデータを含んでいる(S404)。
In the third mode, when the temperature rise due to the short defect reaches a predetermined temperature, the application of the drive signal is interrupted and then the drive signal is applied again to evaluate whether or not the short defect has been correctly detected. It is a form to do.
In the flowchart of FIG. 10, first, a drive signal for detecting a short defect is applied to all the panels on the TFT substrate (S401). Hereinafter, heat generation is measured by the heat detector at the measurement timing (S402, 403). Short defect image data is acquired from the detection signal of the thermal detector. The image data includes detection signal intensity and coordinate position data (S404).
 前記したS307、S308と同様に、画像データを用いてショート欠陥を検出する。欠陥検出は、検出信号の強度をあらかじめ定めておいた閾値と比較することで行うことができる(S4052)。S405の工程で検出したショート欠陥点の座標位置を求めて記録する(S406)。 In the same manner as S307 and S308 described above, a short defect is detected using image data. The defect detection can be performed by comparing the intensity of the detection signal with a predetermined threshold value (S4052). The coordinate position of the short defect point detected in step S405 is obtained and recorded (S406).
 次に、検出したショート欠陥点への駆動信号の印加を停止する。ショート欠陥点への駆動信号の印加を停止することによって、ショート欠陥点の温度上昇を停止させ、ショート欠陥点付近が熱によって損傷することを防ぐことができる(S407)。 Next, application of the drive signal to the detected short defect point is stopped. By stopping the application of the drive signal to the short defect point, the temperature rise of the short defect point can be stopped and the vicinity of the short defect point can be prevented from being damaged by heat (S407).
 測定タイミングにおいて(S408)、S407で印加を停止した欠陥点に駆動信号を再印加し、欠陥点に発熱させる(S409)。所定時間が経過して、発熱によって温度が上昇した後(S410)、熱検出器によって発熱を測定する(S411)。熱検出器の検出信号からショート欠陥画像データを取得する。画像データは、検出信号の強度と座標位置のデータを含んでいる(S412)。 At the measurement timing (S408), the drive signal is re-applied to the defective point where the application is stopped in S407, and the defective point is caused to generate heat (S409). After a predetermined time has elapsed, the temperature rises due to heat generation (S410), and then heat generation is measured by a heat detector (S411). Short defect image data is acquired from the detection signal of the thermal detector. The image data includes the data of the detection signal intensity and the coordinate position (S412).
 欠陥点の検出信号の強度をあらかじめ決めておいた閾値と比較する(S413)。検出信号の強度が閾値よりも大きい場合には、検出位置が正しいショート欠陥検出位置であると評価することができ、一方、検出信号の強度が閾値よりも小さい場合には、検出した位置は誤ったショート欠陥検出位置であると評価し(S413)、検出してショート欠陥位置の座標位置を記録から削除する(S414)。上記S402~S414の工程をショート欠陥検出の設定時間が経過するまで繰り返す(S415)。 The intensity of the defect point detection signal is compared with a predetermined threshold value (S413). If the detected signal intensity is greater than the threshold value, the detected position can be evaluated as a correct short defect detected position. On the other hand, if the detected signal intensity is less than the threshold value, the detected position is incorrect. The detected position of the short defect is evaluated (S413), detected, and the coordinate position of the short defect position is deleted from the record (S414). The above steps S402 to S414 are repeated until the set time for short defect detection elapses (S415).
 図11(a)はショート欠陥がある状態の検出信号の信号強度と印加信号を示し、図11(b)は測定タイミングを示している。図11(a)において、黒点は図11(b)の測定タイミングで測定される検出点を示している。 FIG. 11 (a) shows the signal intensity and applied signal of the detection signal in a state where there is a short defect, and FIG. 11 (b) shows the measurement timing. In FIG. 11A, black dots indicate detection points measured at the measurement timing in FIG.
 ショート欠陥による短絡電流が流れ、ショート欠陥点に発熱すると、温度が時間と共に上昇する。図8(b)において、ショート欠陥の短絡電流によって発熱し、温度が上昇する。ここで、ショート欠陥を検出する閾値として、あらかじめ検出信号の強度を定めており、検出信号の信号強度と閾値とを比較する。検出信号の信号強度が閾値を越えた時点で、そのショート欠陥の位置に対応する駆動信号の印加を停止する。 When a short-circuit current due to a short defect flows and heat is generated at the short defect point, the temperature rises with time. In FIG. 8B, heat is generated by the short-circuit current of the short defect, and the temperature rises. Here, the intensity of the detection signal is determined in advance as a threshold for detecting a short defect, and the signal intensity of the detection signal is compared with the threshold. When the signal intensity of the detection signal exceeds the threshold value, the application of the drive signal corresponding to the position of the short defect is stopped.
 本発明の態様によれば、検出したショート欠陥点への駆動信号の停止、再印加を行うことによって、正しくショート欠陥を検出したか否かを確認することができる。 According to the aspect of the present invention, it is possible to confirm whether or not the short defect is correctly detected by stopping and reapplying the drive signal to the detected short defect point.
 本発明は、液晶製造装置におけるTFTアレイ検査工程の他、有機ELや種々の半導体基板が備えるTFTアレイの欠陥検査に適用することができる。 The present invention can be applied not only to a TFT array inspection process in a liquid crystal manufacturing apparatus but also to a defect inspection of a TFT array provided in an organic EL or various semiconductor substrates.

Claims (10)

  1.  基板を真空状態に収納する真空チャンバと、
     前記基板のTFTアレイに駆動信号を供給する駆動信号供給部と、
     前記基板に電子線を照射する電子線源と、
     前記電子線の照射によって基板から放出される二次電子を検出する二次電子検出器と、
     前記駆動信号が供給された基板から放射される放熱を検出する熱検出器と、
     前記二次電子検出器の検出信号および前記熱検出器の検出信号に基づいてTFT基板の欠陥を検出する欠陥検出部とを備え、
     前記欠陥検出部は、
     前記二次電子の検出器の検出信号から得られる走査画像に基づいてTFTアレイの欠陥を検出するTFTアレイ欠陥検出部と、
     前記熱検出器の検出信号から得られる熱分布画像に基づいてショート欠陥を検出するショート欠陥検出部とを備え、
     前記TFTアレイ欠陥検出部は、基板が備える複数のパネルから一つのパネルを順に選択してTFTアレイ欠陥検出を行い、
     前記ショート欠陥検出部は、基板が備える全パネルについて同時にショート欠陥検出を行うことを特徴とする、TFT基板検査装置。
    A vacuum chamber for storing the substrate in a vacuum state;
    A drive signal supply unit for supplying a drive signal to the TFT array of the substrate;
    An electron beam source for irradiating the substrate with an electron beam;
    A secondary electron detector for detecting secondary electrons emitted from the substrate by irradiation of the electron beam;
    A heat detector for detecting heat radiation radiated from the substrate to which the drive signal is supplied;
    A defect detection unit that detects a defect of the TFT substrate based on a detection signal of the secondary electron detector and a detection signal of the heat detector;
    The defect detection unit
    A TFT array defect detector for detecting defects in the TFT array based on a scanning image obtained from a detection signal of the secondary electron detector;
    A short defect detector for detecting a short defect based on a heat distribution image obtained from a detection signal of the heat detector;
    The TFT array defect detection unit performs TFT array defect detection by sequentially selecting one panel from a plurality of panels included in the substrate,
    The short-circuit defect detection unit performs short-circuit defect detection simultaneously on all the panels included in the substrate.
  2.  前記駆動信号供給部は、
     前記選択したパネルに欠陥検出を行うための所定パターンの駆動信号を印加し、
     非選択のパネルにショート欠陥検出を行うための所定パターンの駆動信号を印加することを特徴とする、請求項1に記載のTFT基板検査装置。
    The drive signal supply unit
    Applying a predetermined pattern drive signal to detect defects to the selected panel,
    2. The TFT substrate inspection apparatus according to claim 1, wherein a drive signal having a predetermined pattern for detecting a short defect is applied to a non-selected panel.
  3.  前記駆動信号供給部は、
     前記ショート欠陥部の欠陥検出中に、当該ショート欠陥検出部が検出したショート欠陥の欠陥点のTFTアレイへの駆動信号の供給を中断することを特徴とする、請求項1又は2に記載のTFT基板検査装置。
    The drive signal supply unit
    3. The TFT according to claim 1, wherein during the defect detection of the short defect portion, the supply of the drive signal to the TFT array at the defect point of the short defect detected by the short defect detection portion is interrupted. Board inspection equipment.
  4.  前記ショート欠陥検出部は、
     前記駆動信号の供給中断後の熱検出器の検出信号に基づいて、前記検出したショート欠陥の正否を評価することを特徴とする、請求項3に記載のTFT基板検査装置。
    The short defect detection unit
    4. The TFT substrate inspection apparatus according to claim 3, wherein the correctness of the detected short-circuit defect is evaluated based on a detection signal of a heat detector after the supply of the driving signal is interrupted.
  5.  前記駆動信号供給部は、
     前記ショート欠陥検出部の欠陥検出中に、当該ショート欠陥検出部が検出したショート欠陥の欠陥点のTFTアレイへの駆動信号の供給を中断し、
     所定時間経過後に前記TFTアレイへの駆動信号の供給を再開し、
     前記駆動信号の供給再会後の熱検出器の検出信号に基づいて、前記検出したショート欠陥の正否を評価することを特徴とする、請求項3に記載のTFT基板検査装置。
    The drive signal supply unit
    During the defect detection of the short defect detection unit, the supply of the drive signal to the TFT array of the defect point of the short defect detected by the short defect detection unit is interrupted,
    Restart the supply of drive signals to the TFT array after a predetermined time,
    4. The TFT substrate inspection apparatus according to claim 3, wherein the correctness of the detected short-circuit defect is evaluated based on a detection signal of a heat detector after resupply of the drive signal.
  6.  TFTアレイの欠陥を検査するTFT基板の検査方法であって、
     真空チャンバ内に収納した基板のTFTアレイに駆動信号を供給する駆動信号供給工程と、
     前記基板に電子線を照射し、前記電子線の照射によって基板から放出される二次電子を検出し、前記二次電子の検出信号から得られる走査画像に基づいてTFTアレイの欠陥を検出するTFTアレイ欠陥工程と、
     前記駆動信号が供給された基板から放射される放熱を検出し、前記放熱の検出信号から得られる熱分布画像に基づいてショート欠陥を検出するショート欠陥検出工程とを備え、
     前記TFTアレイ欠陥検出工程は、基板が備える複数のパネルから一つのパネルを順に選択してTFTアレイ欠陥検出を行い、
     前記ショート欠陥検出工程は、基板が備える全パネルについて同時にショート欠陥検出を行うことを特徴とする、TFT基板検査方法。
    A method of inspecting a TFT substrate for inspecting a defect of a TFT array,
    A drive signal supplying step for supplying a drive signal to the TFT array of the substrate housed in the vacuum chamber;
    A TFT that irradiates the substrate with an electron beam, detects secondary electrons emitted from the substrate by the irradiation of the electron beam, and detects defects in the TFT array based on a scanning image obtained from the detection signal of the secondary electrons An array defect process;
    A short defect detection step of detecting heat radiation radiated from the substrate supplied with the drive signal, and detecting a short defect based on a heat distribution image obtained from the heat radiation detection signal,
    The TFT array defect detection step performs TFT array defect detection by sequentially selecting one panel from a plurality of panels included in the substrate,
    The method for inspecting a TFT substrate, wherein the short-circuit defect detecting step performs short-circuit defect detection simultaneously for all the panels included in the substrate.
  7.  前記駆動信号供給工程は、
     前記選択したパネルに欠陥検出を行うための所定パターンの駆動信号を印加し、
     非選択のパネルにショート欠陥検出を行うための所定パターンの駆動信号を印加することを特徴とする、請求項6に記載のTFT基板検査方法。
    The drive signal supplying step includes
    Applying a predetermined pattern drive signal to detect defects to the selected panel,
    The TFT substrate inspection method according to claim 6, wherein a drive signal having a predetermined pattern for detecting a short defect is applied to a non-selected panel.
  8.  前記駆動信号供給工程は、
     前記ショート欠陥検出工程中に、当該ショート欠陥検出工程で検出したショート欠陥の欠陥点のTFTアレイへの駆動信号の供給を中断することを特徴とする、請求項6又は7に記載のTFT基板検査方法。
    The drive signal supplying step includes
    The TFT substrate inspection according to claim 6 or 7, wherein during the short defect detection step, supply of a drive signal to the TFT array at the defect point of the short defect detected in the short defect detection step is interrupted. Method.
  9.  前記ショート欠陥検出工程は、
     前記駆動信号の供給中断後の放熱の検出信号に基づいて、前記検出したショート欠陥の正否を評価することを特徴とする、請求項8に記載のTFT基板検査方法。
    The short defect detection step includes
    9. The TFT substrate inspection method according to claim 8, wherein the correctness of the detected short-circuit defect is evaluated based on a detection signal for heat dissipation after the supply of the drive signal is interrupted.
  10.  前記駆動信号供給工程は、
     前記ショート欠陥検出工程中に、当該ショート欠陥検出工程が検出したショート欠陥の欠陥点のTFTアレイへの駆動信号の供給を中断し、
     所定時間経過後に前記TFTアレイへの駆動信号の供給を再開し、
     前記駆動信号の供給再会後の放熱の検出信号に基づいて、前記検出したショート欠陥の正否を評価することを特徴とする、請求項8に記載のTFT基板検査方法。
    The drive signal supplying step includes
    During the short defect detection process, the supply of the drive signal to the TFT array at the defect point of the short defect detected by the short defect detection process is interrupted,
    Restart the supply of drive signals to the TFT array after a predetermined time,
    9. The TFT substrate inspection method according to claim 8, wherein the correctness of the detected short-circuit defect is evaluated based on a heat dissipation detection signal after the drive signal supply is reunited.
PCT/JP2009/070668 2009-12-10 2009-12-10 Tft substrate inspection apparatus and tft substrate inspection method WO2011070663A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN200980162866XA CN102667507A (en) 2009-12-10 2009-12-10 TFT substrate inspection apparatus and tft substrate inspection method
PCT/JP2009/070668 WO2011070663A1 (en) 2009-12-10 2009-12-10 Tft substrate inspection apparatus and tft substrate inspection method
JP2011545022A JP5590043B2 (en) 2009-12-10 2009-12-10 TFT substrate inspection apparatus and TFT substrate inspection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2009/070668 WO2011070663A1 (en) 2009-12-10 2009-12-10 Tft substrate inspection apparatus and tft substrate inspection method

Publications (1)

Publication Number Publication Date
WO2011070663A1 true WO2011070663A1 (en) 2011-06-16

Family

ID=44145234

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/070668 WO2011070663A1 (en) 2009-12-10 2009-12-10 Tft substrate inspection apparatus and tft substrate inspection method

Country Status (3)

Country Link
JP (1) JP5590043B2 (en)
CN (1) CN102667507A (en)
WO (1) WO2011070663A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104795339B (en) * 2015-03-09 2017-10-20 昆山龙腾光电有限公司 The detection means and detection method of thin-film transistor array base-plate
CN106067477B (en) * 2016-06-27 2019-10-11 昆山国显光电有限公司 Substrate manufacturing system and method for testing substrate
CN106125357B (en) * 2016-06-27 2019-06-25 京东方科技集团股份有限公司 A kind of array substrate detection method and detection system
TWI633300B (en) * 2017-03-06 2018-08-21 興城科技股份有限公司 Method for detecting defects of thin-film transistor panel and device thereof
CN108847182A (en) * 2018-08-16 2018-11-20 北京蜃景光电科技有限公司 display control unit and display system
CN110161729B (en) * 2019-05-17 2021-08-03 深圳市华星光电半导体显示技术有限公司 Display panel testing method and system
CN113075230A (en) * 2021-03-26 2021-07-06 重庆烯宇新材料科技有限公司 Large-size lighting display appearance inspection method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0651011A (en) * 1991-07-30 1994-02-25 Hitachi Ltd Method and device for inspecting liquid crystal substrate of thin film transistor type
JP2008058767A (en) * 2006-09-01 2008-03-13 Shimadzu Corp Inspection method and apparatus of tft array

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3150324B2 (en) * 1990-07-13 2001-03-26 株式会社日立製作所 Method of inspecting thin film transistor substrate and method of repairing wiring of thin film transistor substrate
KR960002145B1 (en) * 1991-07-30 1996-02-13 가부시기가이샤 히다찌세이사구쇼 Detection method of tft lcd panel and the device
CN100356166C (en) * 2005-03-04 2007-12-19 广辉电子股份有限公司 Method and apparatus for detecting liquid crystal displaying device array
TWI313142B (en) * 2005-06-14 2009-08-01 Tft substrate inspection apparatus
JPWO2008015738A1 (en) * 2006-08-01 2009-12-17 株式会社島津製作所 Substrate inspection / correction device and substrate evaluation system
JP2008096143A (en) * 2006-10-06 2008-04-24 Shimadzu Corp Tft array substrate inspection device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0651011A (en) * 1991-07-30 1994-02-25 Hitachi Ltd Method and device for inspecting liquid crystal substrate of thin film transistor type
JP2008058767A (en) * 2006-09-01 2008-03-13 Shimadzu Corp Inspection method and apparatus of tft array

Also Published As

Publication number Publication date
JPWO2011070663A1 (en) 2013-04-22
JP5590043B2 (en) 2014-09-17
CN102667507A (en) 2012-09-12

Similar Documents

Publication Publication Date Title
JP5590043B2 (en) TFT substrate inspection apparatus and TFT substrate inspection method
US7330583B2 (en) Integrated visual imaging and electronic sensing inspection systems
JPWO2012147807A1 (en) Wiring defect inspection method, wiring defect inspection apparatus, and semiconductor substrate manufacturing method
JP5224194B2 (en) TFT array inspection method and TFT array inspection apparatus
WO2012120973A1 (en) Defect inspection method, defect inspection apparatus, and method for manufacturing substrate
US20050174140A1 (en) Thin film transistor array inspection device
JP2007334262A (en) Method for detecting defect of tft array substrate, and defect detector of tft array substrate
JP4831525B2 (en) TFT array inspection method and TFT array inspection apparatus
JP2008058767A (en) Inspection method and apparatus of tft array
WO2013128738A1 (en) Defect detection method, defect detection device, and method for producing semiconductor substrate
JP5459469B2 (en) TFT array inspection method and TFT array inspection apparatus
JP4748392B2 (en) TFT array substrate inspection equipment
JP5077544B2 (en) TFT array inspection method and TFT array inspection apparatus
JP5077538B2 (en) TFT array inspection equipment
JP5007925B2 (en) Electron beam scanning method in TFT array inspection
JP2013250098A (en) Method and apparatus for detecting wiring defect, and method for manufacturing wiring board
JP5316977B2 (en) Electron beam scanning method and TFT array inspection apparatus for TFT array inspection
JP2012078127A (en) Tft array inspection device and tft array inspection method
KR102070056B1 (en) System and method of testing organic light emitting display device
JP5029826B2 (en) Probe pin contact inspection method and TFT array inspection apparatus
JP5163948B2 (en) Scanning beam inspection apparatus and defect detection signal processing method
JP2007114124A (en) Method and device for inspecting array substrate
JP5423664B2 (en) TFT array inspection equipment
JP5893436B2 (en) Tip position specifying method and tip position specifying device for specifying the tip position of a line area displayed as an image, and position specifying method and position specifying device for specifying the position of a short-circuit defect
JP4788904B2 (en) Defect detection method and TFT array defect detection apparatus for TFT array

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200980162866.X

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 09852059

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2011545022

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 09852059

Country of ref document: EP

Kind code of ref document: A1