WO2011069231A1 - Amplificateur sans charge - Google Patents

Amplificateur sans charge Download PDF

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Publication number
WO2011069231A1
WO2011069231A1 PCT/CA2009/001819 CA2009001819W WO2011069231A1 WO 2011069231 A1 WO2011069231 A1 WO 2011069231A1 CA 2009001819 W CA2009001819 W CA 2009001819W WO 2011069231 A1 WO2011069231 A1 WO 2011069231A1
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WO
WIPO (PCT)
Prior art keywords
amplifier
input
stages
voltage
load
Prior art date
Application number
PCT/CA2009/001819
Other languages
English (en)
Inventor
Martin Mallinson
Original Assignee
Ess Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ess Technology, Inc. filed Critical Ess Technology, Inc.
Priority to PCT/CA2009/001819 priority Critical patent/WO2011069231A1/fr
Publication of WO2011069231A1 publication Critical patent/WO2011069231A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
    • H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
    • H03F3/3022—CMOS common source output SEPP amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45237—Complementary long tailed pairs having parallel inputs and being supplied in series
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45674—Indexing scheme relating to differential amplifiers the LC comprising one current mirror

Definitions

  • This invention relates to operational amplifiers.
  • this invention relates to configurations of operational amplifiers to effectively eliminate the conventional load network in the amplifier.
  • CMOS gate amplifier commonly a “current mirror” that performs the task of converting a differential current difference into a voltage difference, that difference being either single-ended or differential.
  • the CMOS gate amplifier has no such network: no load is needed since the complementary device can be considered as the load. Additionally, that complementary device that occupies the position of the canonical load network also accepts the input signal at its controlling terminal and therefore beneficially adds to the gain. This observation leads one to ask whether the canonical op-amp configuration can be modified such that it also has no identifiable load network, and whether additional devices receiving the input to their controlling nodes can substitute for the now absent load network. This is indeed possible and this disclosure describes how the advantages resulting from the absence of the load network in the CMOS gate amplifier can also be achieved with a conventional op-amp.
  • the invention comprises a differential amplifier comprising two input stages.
  • Each of the input stages comprises at least a pair of active devices adapted to amplify an input signal at at least one of its terminals.
  • One of the stages is configured as the load for the other stage and the differential outputs of the amplifier are at the nodes between the two stages.
  • the active input devices of one of the stages comprise PMOS FETs and those of the other stage comprise NMOS FETs.
  • the output nodes are biased such that the drain-source voltage of each of the FETs is lower than its gate-source voltage but higher than its saturation voltage.
  • the active devices are bipolar junction transistors wherein the base-collector is slightly forward biased but not such that the collector-emitter voltage falls below the saturation voltage.
  • Fig. 1 is a circuit diagram of a prior art canonical op-amp configuration
  • Fig. 2 is a circuit diagram of a prior art common CMOS inverter
  • Fig. 3 is a circuit diagram representing a CMOS inverter wherein the inputs to the NMOS and PMOS devices have been conceptually recharacterized;
  • Fig. 4 is a circuit diagram of the prototypical version of the preferred embodiment of the invention.
  • Fig. 5 is a circuit diagram of a version of the preferred embodiment for optimizing the signal level at the output
  • Fig. 6 is a circuit diagram showing a configuration and component values for an implementation of the same current consumption and gain as the circuit of Fig. 5 but using a canonical op amp configuration
  • Fig. 7a is a plot of the noise for the circuit of Fig. 5 of the preferred embodiment and for the implementation of Fig. 6;
  • Fig. 7b is a plot of the gain for the circuit of Fig. 5 of the preferred embodiment and for the implementation of Fig. 6.
  • a canonical form of op-amp is shown in Fig. 1.
  • M1 and M2 are the input devices and M3 and M4 form the load network - a current mirror in this case.
  • the operation of the load is such that a current difference between M1 and M2 drain causes a change in voltage on the gate of M6 and this in turn causes the output (Vo) to change in response to an input difference between the '-' and '+' terminals.
  • This output change in response to an applied input difference voltage is the essence of an operational amplifier and this design is ubiquitous within many electronic systems.
  • Fig. 2 represents the common CMOS inverter: a very simple circuit consisting of just one NMOS device (M2) and one PMOS device (M1 ). Together these devices operate to make the output go low if the input is high, or conversely go high if the input is low.
  • “Low” and “High” refer to the voltage relative to the supply Vneg and Vpos: Vneg is “low” and Vpos is “high”. Consequently, at some intermediary input voltage the output is in transition, and a small incremental change to the voltage at the node “In” typically causes a significantly larger change, in the opposite direction, to the voltage at the node "Out". This is therefore viable as an inverting amplifier for that range of voltages where the output is neither completely high nor completely low.
  • CMOS gate amplifier despite its simplicity has at least one interesting aspect: we cannot identify either device as a load network for the other, indeed the circuit is symmetrical; we can consider M2 to be the input device operating to deliver various currents as a result of its gate voltage change, into the output resistance provided by M1 , or vice versa.
  • G g m2 - R ⁇ R, 2
  • g m2 is the trans-conductance of M2 and fl ol and R u2 are the output impedances of M1 and M2 respectively at their drain nodes.
  • is used to indicate parallel connection.
  • CMOS inverter of Fig. 2 (where "Bias” is the same node as "In") can be thought of as the circuit of Fig. 3 but where the designer has used the input as the bias node for the PMOS device. In comparison to Fig. 3, this has firstly increased the gain, and secondly, reduced the noise. In detail, the gain is now
  • G (8 m , + g m2 ) - R lA II R, and there is no noise from any node named "Bias" - that node no longer exists.
  • FIG. 4 A conceptualized circuit according to the invention is shown in Fig. 4.
  • the circuit includes two sets of input devices: M1 and M2 make a pair of PMOS input devices; M3 and M4 make a pair of NMOS input devices.
  • No load network is needed if we can arrange the operating condition such that one pair operates as the load for the other pair.
  • the benefits of the simple CMOS gate amplifier then apply to this circuit: namely lower noise and higher gain.
  • the circuit can be biased in this way, but as long as the output nodes are biased such that each device operates with drain-source voltage lower than the gate-source voltage, but higher than the saturation voltage, then high gain operation is possible.
  • the input and input bar i.e. "In” and “Inb”
  • the output and output bar (“Out” and “Outb”
  • the output can move down until it reaches the saturation voltage of M4, or up until it reaches the saturation voltage of M2.
  • the gate-source voltage can be arranged to be approximately 0.7v and the saturation voltage approximately 0.2v.
  • the voltage excursion on the output node can be 1v (that is, it can move down by 0.5v and up by 0.5v). Measured differentially, this means a signal of 2Vppd (volts peak-to- peak differential) can be generated at the output.
  • Fig. 5 is the preferred embodiment of the invention, showing how the operating point may be derived to optimize the signal level at the output.
  • the component values of the preferred embodiment and in the circuit of Fig. 6 are as shown.
  • the values shown adjacent the FETs include specifications of their length and width in nanometers ("3u” next to the gate of M4 refers to 3 micrometers and "350n” next to the drain of M4 refers to 350 nanometers).
  • additional devices M5 and M6 form a common mode feedback loop that sets the output to approximately the input voltage (in the illustrated embodiment, the input is 1.0V and the output is 985.11 mV).
  • Fig. 6 shows how an amplifier with the same current consumption and gain as the circuit of Fig. 5 would be implemented using a conventional op-amp configuration.
  • a current mirror of the conventional type is used as the load network and the same output impedance (the pair of 100k resistors) is connected across the output to ensure that the comparison to the disclosed approach is accurate.
  • the AC response and the noise referred to the input signal are shown in the graphs of Fig. 7.
  • Fig. 7a shows the noise in volts per square root hertz
  • Fig. 7b shows the gain in decibels. As can clearly be seen the noise is substantially lower and the gain substantially higher when the "no load" circuit of the preferred embodiment is used.
  • active devices other than FETs, that are similarly designed to amplify signals at at least one of their terminals, may be used to implement the invention, indeed all such devices for which a suitable operating point can be found.
  • the active devices may consists of Bipolar Junction Transistors (BJTs) each of whose base-collector is slightly forward biased but not such that the collector-emitter voltage falls below the saturation voltage (at which the current gain would degrade).
  • BJTs Bipolar Junction Transistors
  • Two input stages operating against one another are a viable and improved means to make a differential op-amp because the noise of the load network that a single input stage requires is removed, and the fact that the other input stage also amplifies the signal causes the gain to increase.
  • Circuits employing this invention are therefore characterized by the absence of a load network and the presence of a second input stage.
  • This invention differs from the known CMOS Gate Amplifier because it operates differentially and consequently has a common mode range and corresponds to the operational amplifier configuration rather than the constrained virtual ground configuration that is a necessary consequence of the CMOS Gate Amplifier configuration.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un amplificateur différentiel comprenant au moins deux paires de composants actifs, une paire étant branchée en tant que charge de l'autre paire. Les sorties sont connectées au niveau des noeuds entre les deux paires d'amplificateurs. Avec une polarisation appropriée, cet amplificateur offre des performances de bruit et de gain améliorées.
PCT/CA2009/001819 2009-12-11 2009-12-11 Amplificateur sans charge WO2011069231A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CA2009/001819 WO2011069231A1 (fr) 2009-12-11 2009-12-11 Amplificateur sans charge

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CA2009/001819 WO2011069231A1 (fr) 2009-12-11 2009-12-11 Amplificateur sans charge

Publications (1)

Publication Number Publication Date
WO2011069231A1 true WO2011069231A1 (fr) 2011-06-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA2009/001819 WO2011069231A1 (fr) 2009-12-11 2009-12-11 Amplificateur sans charge

Country Status (1)

Country Link
WO (1) WO2011069231A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2944968A1 (fr) * 2012-09-26 2015-11-18 Broadcom Corporation Amplificateur de fréquence radio de classe ab pour détecteur d'enveloppe
US11349446B2 (en) 2020-03-10 2022-05-31 SiliconIntervention Inc. Amplifier bias control using tunneling current

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5936466A (en) * 1997-08-04 1999-08-10 International Business Machines Corporation Differential operational transconductance amplifier
US6642790B2 (en) * 2000-08-15 2003-11-04 Infineon Technologies Ag Differential, complementary amplifier
US6937071B1 (en) * 2004-03-16 2005-08-30 Micrel, Incorporated High frequency differential power amplifier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5936466A (en) * 1997-08-04 1999-08-10 International Business Machines Corporation Differential operational transconductance amplifier
US6642790B2 (en) * 2000-08-15 2003-11-04 Infineon Technologies Ag Differential, complementary amplifier
US6937071B1 (en) * 2004-03-16 2005-08-30 Micrel, Incorporated High frequency differential power amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2944968A1 (fr) * 2012-09-26 2015-11-18 Broadcom Corporation Amplificateur de fréquence radio de classe ab pour détecteur d'enveloppe
US11349446B2 (en) 2020-03-10 2022-05-31 SiliconIntervention Inc. Amplifier bias control using tunneling current

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