WO2011043794A3 - Dispositifs ferroélectriques comprenant une couche ayant deux configurations stables ou davantage - Google Patents

Dispositifs ferroélectriques comprenant une couche ayant deux configurations stables ou davantage Download PDF

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Publication number
WO2011043794A3
WO2011043794A3 PCT/US2010/002642 US2010002642W WO2011043794A3 WO 2011043794 A3 WO2011043794 A3 WO 2011043794A3 US 2010002642 W US2010002642 W US 2010002642W WO 2011043794 A3 WO2011043794 A3 WO 2011043794A3
Authority
WO
WIPO (PCT)
Prior art keywords
ferroelectric
layer
devices including
layers
stable configurations
Prior art date
Application number
PCT/US2010/002642
Other languages
English (en)
Other versions
WO2011043794A2 (fr
Inventor
Alexie M. Kolpak
Fred J. Walker
James W. Reiner
Charles H. Ahn
Sohrab Ismail-Beigi
Original Assignee
Yale University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yale University filed Critical Yale University
Priority to US13/498,989 priority Critical patent/US20130001809A1/en
Publication of WO2011043794A2 publication Critical patent/WO2011043794A2/fr
Publication of WO2011043794A3 publication Critical patent/WO2011043794A3/fr
Priority to US14/745,457 priority patent/US9536975B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40111—Multistep manufacturing processes for data storage electrodes the electrodes comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/36—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of semiconductors, not otherwise provided for
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors

Abstract

L'invention porte sur des dispositifs semi-conducteurs ferroélectriques qui sont obtenus par inclusion d'une couche ferroélectrique dans le dispositif qui est fait d'un matériau qui n'est pas ferroélectrique dans sa masse. De telles couches peuvent être disposées aux interfaces pour favoriser une commutation ferroélectrique dans un dispositif semi-conducteur. Une commutation de conduction dans le semi-conducteur est effectuée par la polarisation d'un matériau mécaniquement bistable. Ce matériau n'est pas ferroélectrique dans sa masse mais peut être considéré comme l'étant lorsque l'épaisseur est suffisamment réduite en descendant jusqu'à quelques couches atomiques. Des dispositifs comprenant de telles couches ferroélectriques sont appropriés pour diverses applications, telles que des transistors et des cellules de mémoire (à la fois volatile et non volatile).
PCT/US2010/002642 2009-09-29 2010-09-29 Dispositifs ferroélectriques comprenant une couche ayant deux configurations stables ou davantage WO2011043794A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US13/498,989 US20130001809A1 (en) 2009-09-29 2010-09-29 Ferroelectric Devices including a Layer having Two or More Stable Configurations
US14/745,457 US9536975B2 (en) 2009-09-29 2015-06-21 Ferroelectric devices including a layer having two or more stable configurations

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US24668809P 2009-09-29 2009-09-29
US61/246,688 2009-09-29

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US13/498,989 A-371-Of-International US20130001809A1 (en) 2009-09-29 2010-09-29 Ferroelectric Devices including a Layer having Two or More Stable Configurations
US14/745,457 Continuation US9536975B2 (en) 2009-09-29 2015-06-21 Ferroelectric devices including a layer having two or more stable configurations

Publications (2)

Publication Number Publication Date
WO2011043794A2 WO2011043794A2 (fr) 2011-04-14
WO2011043794A3 true WO2011043794A3 (fr) 2011-06-16

Family

ID=43857325

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/002642 WO2011043794A2 (fr) 2009-09-29 2010-09-29 Dispositifs ferroélectriques comprenant une couche ayant deux configurations stables ou davantage

Country Status (2)

Country Link
US (2) US20130001809A1 (fr)
WO (1) WO2011043794A2 (fr)

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JP6145756B2 (ja) * 2013-09-18 2017-06-14 国立研究開発法人産業技術総合研究所 不揮発性記憶素子
JP2017505324A (ja) 2014-02-07 2017-02-16 ゴジョ・インダストリーズ・インコーポレイテッド 胞子及び他の生物に対する効力を有する組成物及び方法
WO2018125118A1 (fr) * 2016-12-29 2018-07-05 Intel Corporation Dispositifs à transistors à effet de champ ferroélectriques d'étage de sortie
US10340447B2 (en) * 2017-06-07 2019-07-02 International Business Machines Corporation Three-terminal metastable symmetric zero-volt battery memristive device
US10614868B2 (en) 2018-04-16 2020-04-07 Samsung Electronics Co., Ltd. Memory device with strong polarization coupling

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US20020117702A1 (en) * 1999-09-30 2002-08-29 Reinhard Stengl Ferroelectric transistor and memory cell configuration with the ferroelectric transistor
US20030094638A1 (en) * 1999-08-26 2003-05-22 Micron Technology, Inc. Weak ferroelectric transistor
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US20060091434A1 (en) * 2004-10-29 2006-05-04 Chang-Beom Eom Strain-engineered ferroelectric thin films
US20080025063A1 (en) * 2006-07-27 2008-01-31 Hynix Semiconductor Inc. Nonvolatile ferroelectric memory device using silicon substrate, method for manufacturing the same, and refresh method thereof

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US6255121B1 (en) * 1999-02-26 2001-07-03 Symetrix Corporation Method for fabricating ferroelectric field effect transistor having an interface insulator layer formed by a liquid precursor
US6407435B1 (en) * 2000-02-11 2002-06-18 Sharp Laboratories Of America, Inc. Multilayer dielectric stack and method
EP1213745A1 (fr) * 2000-12-05 2002-06-12 Sony International (Europe) GmbH Procédé de fabrication d'une mémoire ferroélectrique et dispositif de mémoire
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US20030094638A1 (en) * 1999-08-26 2003-05-22 Micron Technology, Inc. Weak ferroelectric transistor
US20020117702A1 (en) * 1999-09-30 2002-08-29 Reinhard Stengl Ferroelectric transistor and memory cell configuration with the ferroelectric transistor
US20020021544A1 (en) * 2000-08-11 2002-02-21 Hag-Ju Cho Integrated circuit devices having dielectric regions protected with multi-layer insulation structures and methods of fabricating same
US20030119242A1 (en) * 2001-03-27 2003-06-26 Sharp Laboratories Of America, Inc. MFMOS capacitors with high dielectric constant materials
US20060091434A1 (en) * 2004-10-29 2006-05-04 Chang-Beom Eom Strain-engineered ferroelectric thin films
US20080025063A1 (en) * 2006-07-27 2008-01-31 Hynix Semiconductor Inc. Nonvolatile ferroelectric memory device using silicon substrate, method for manufacturing the same, and refresh method thereof

Also Published As

Publication number Publication date
US9536975B2 (en) 2017-01-03
US20150311309A1 (en) 2015-10-29
WO2011043794A2 (fr) 2011-04-14
US20130001809A1 (en) 2013-01-03

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