WO2011018780A1 - Processus de fabrication d’un substrat hybride - Google Patents

Processus de fabrication d’un substrat hybride Download PDF

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Publication number
WO2011018780A1
WO2011018780A1 PCT/IE2010/000049 IE2010000049W WO2011018780A1 WO 2011018780 A1 WO2011018780 A1 WO 2011018780A1 IE 2010000049 W IE2010000049 W IE 2010000049W WO 2011018780 A1 WO2011018780 A1 WO 2011018780A1
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Prior art keywords
substrate
donor substrate
patterned
host
donor
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PCT/IE2010/000049
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English (en)
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Cynthia Anne Colinge
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National University Of Ireland, Cork
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Publication of WO2011018780A1 publication Critical patent/WO2011018780A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256

Definitions

  • This invention relates to a hybrid substrate. More specifically, this invention relates to a process of manufacturing a hybrid substrate.
  • Epitaxial growth of dissimilar materials with dissimilar lattice constants requires large graded buffer layers which may contain threading dislocations and other defects.
  • a large graded buffer layer must be grown due to the lattice mismatch of Ge and Si.
  • these graded buffer layers contain threading dislocations which may degrade device performance.
  • bonding techniques do not require high temperature epitaxial growth.
  • the bonded material may have similar crystalline perfection, and hence similar qualities as the starting single crystal bulk material, for example similar mobility and light emitting properties and similar defect densities.
  • 170-172 describes a method of bonding two heterogenous materials using a non-planar pressure block.
  • the pressure block and host substrate are independently patterned.
  • a second transfer substrate, with an epitaxially grown device layer, is then positioned between the patterned host substrate and the patterned pressure block.
  • the stack is then aligned and bonded.
  • the epitaxial layer of the transfer substrate is thus "pushed" into the pattern of the host substrate by applying pressure to the patterned pressure block.
  • This process requires thinning of the transfer substrate to 100 microns prior to bonding to allow the transfer substrate to bend during the bonding.
  • the size and spacing of the transferred material is limited due to the mechanical constraints caused by bending the transfer substrate.
  • the growth structure consisted of a six micron p- type GaAs layer with a 100 nm sacrificial AIAs layer buried between the six micron layer and the GaAs substrate.
  • the growth substrate was patterned into pillars by wet etching.
  • the host substrate was n-type GaAs and metal films were deposited on it by thermal evaporation without breaking vacuum: 120 nm Pd, 80 nm Sn, and 120 nm Pd.
  • the host and growth substrates were then aligned using an IR aligner, brought into contact, and bonded with an applied pressure.
  • the samples were then heated in a graphite-strip annealer at 365 0 C for 80 min in a forming gas atmosphere -95% N2, 5% H2.
  • the bonded substrates were placed in a 25% HF bath to selectively etch away the AIAs sacrificial layer, thus releasing the growth substrate and leaving device pillars bonded to the host substrate.
  • this process requires growth to make the sacrificial lift off layer.
  • This paper discloses a way to integrate Ill/V- optoelectronic devices into standard CMOS by low temperature bonding via a so-called spin-on-glass (SOG).
  • the device layers are grown on the GaAs substrate after deposition of a thin AIAs etch-stop layer.
  • the fully processed CMOS wafer is passivated with SiO 2 using plasma enhanced chemical vapour deposition (PECVD) followed by chemical mechanical polishing (CMP).
  • PECVD plasma enhanced chemical vapour deposition
  • CMP chemical mechanical polishing
  • the CMOS wafer is then coated with spin-on-glass (SOG) which is then bonded to the epitaxial Ill/V-layers on the GaAs wafer at room temperature.
  • the bonding is further strengthened by annealing at 200 0 C.
  • the GaAs substrate is removed by a combination of grinding and selective chemical etching down to the AIAs etch-stop layer.
  • This paper discloses another example of using epitaxial growth to transfer a device layer to a host substrate.
  • this method limits the application of the method to transferring layers that have a high exfoliation temperature and the method is not suitable for transfer of layers with a low exfoliation temperature, such as Germanium (Ge). Furthermore, this method uses hydrophilic bonding which means that there is an insulator at the bond interface which is not always desirable.
  • a process for manufacturing a hybrid substrate comprising the steps of:
  • a pattern of a donor substrate is bonded to a host substrate.
  • this circumvents the need to perform etching steps on the donor substrate while it is bonded to the host substrate. This obviates the possibility of causing damage to the underlying semiconductor material or devices on the host substrate during etching.
  • the bonding substrate and the host substrate can interlock and it is therefore possible to provide a planar hybrid substrate. This is seen as particularly advantageous as the planar substrate may be used in the known CMOS processing machinery.
  • the planar hybrid substrate can be used in subsequent processing steps such as lithography and metallization steps.
  • each initial substrate may be applied to each substrate independently before assembling the two materials by bonding. It is likely that the two materials to be bonded will have differing coefficients of thermal expansion (CTEs) and therefore it could be advantageous to preprocess the starting materials prior to bond and anneal. For example, source and drain implantation and activation (a high temperature step) could be performed on the host or donor substrate prior to bonding. Furthermore, the host substrate could be fully processed (CMOS processed) prior to bonding.
  • CTEs coefficients of thermal expansion
  • the step of patterning the host substrate comprises forming a plurality of cavities in the host substrate.
  • the step of patterning the donor substrate comprises forming a plurality of mesas on the donor substrate.
  • the step of interlocking the patterned host substrate and the patterned donor substrate comprises inserting the mesas in the cavities.
  • the step of patterning of the host substrate comprises patterning the host substrate to a depth shallower than the ion implantation depth of the donor substrate.
  • the first donor substrate material may comprise a silicon carbide (SiC) which is useful for power devices and the second donor substrate material may comprise indium phosphide (InP) which is useful for optical devices, both of which may be mounted on a Si substrate.
  • SiC silicon carbide
  • InP indium phosphide
  • the step of splitting the donor substrate at the ion implantation depth further comprises delaminating the donor substrate.
  • the donor layer is delaminated by heating the donor substrate to an ion expansion temperature.
  • Figure 2 is a perspective view of a host substrate for use in the process according to the invention.
  • Figure 3 is a side view of the donor substrate after patterning
  • Figure 4 is a side view of the donor substrate of Figure 3 being brought into contact with the host substrate;
  • Figure 5 is a side view of the host substrate with a transplant layer pattern bonded thereto;
  • Figure 6 is a side view of a second donor substrate after patterning
  • Figure 7 is a side view of the second donor substrate of Figure 6 being brought into contact with the host substrate with the transplant layer pattern as shown in Figure 5;
  • Figure 8 is a side view of the host substrate with the transplant layer pattern and the patterned transplant layer bonded thereto;
  • Figure 9 is a plan view of an alternative embodiment of host substrate for use in the process according to the present invention.
  • Figure 10 is a side cross-sectional view along the lines A-A of the host substrate shown in Figure 9;
  • Figure 11 is a side cross-sectional view of a donor substrate after patterning;
  • Figure 12 is a side view of the donor substrate of Figure 11 being brought into contact with the host substrate of Figure 10;
  • Figure 13 is a side view of the donor substrate of Figure 11 and the host substrate of Figure 10 after bonding and splitting has taken place;
  • Figure 14 is a side cross-sectional view along the lines A-A of the host substrate shown in Figure 9;
  • Figure 15 is a side view of the donor substrate after patterning
  • Figure 16 is a side view of the donor substrate of Figure 15 being brought into contact with the host substrate of Figure 14;
  • Figure 17 is a side view of the donor substrate of Figure 15 and the host substrate of Figure 14 after bonding and splitting has taken place;
  • Figure 18 is a side view of a donor substrate and a host wafer substrate used in the process according to the invention.
  • Figure 19 is a diagrammatic representation of the ramp-up rate sequence for the bond and anneal (bond strengthening step) of the donor and host substrates;
  • Figures 20(a) and 20(b) are enlarged views of the host substrate after splitting;
  • Figure 21 is an enlarged view of the donor substrate after splitting;
  • Figure 22 is a plane view from an SEM inspection of the host substrate;
  • Figures 23(a) and 23(b) are angled views taken at a tilt angle of 35 degrees from an SEM inspection of the host substrate with the donor pattern bonded to it;
  • Figure 24 is an angled view taken at a tilt angle of 45 degrees from an SEM inspection of the host substrate;
  • Figure 25 is a side cross-sectional view of a donor substrate for use in an alternative process according to the present invention.
  • Figure 26 is a side view of a further embodiment of hybrid substrate according to the invention.
  • Figure 27 is a side view of another embodiment of hybrid substrate according to the invention.
  • Figure 28 is a magnified view of a Germanium (Ge) substrate pattern bonded to a Silicon (Si) substrate with a thick Silicon Oxide (SiO 2 ) layer; and Figure 29 is a magnified view of a Ge substrate pattern bonded to a Si substrate with a thin SiO 2 layer;
  • FIG. 1 there is shown a perspective view of a donor substrate, indicated generally by the reference numeral 1 , for use in the process according to the invention.
  • the donor substrate 1 is a Germanium (Ge) substrate implanted with ions, in this case hydrogen ions (H + ), which form an ion implantation layer 3 in the donor substrate.
  • the ion implantation layer 3 is substantially coplanar with the contact surface 5 of the donor substrate.
  • the depth, R p of the ion implantation layer 3 depends on the ion used, the ion dose and the implantation energy used.
  • FIG 2 there is shown a perspective view of a host substrate, indicated generally by the reference numeral 7.
  • the host substrate 7 is a silicon (Si) substrate.
  • the top surface 9 of the host substrate has been treated by chemical- mechanical polishing (CMP) techniques to provide a relatively planar top surface 9 free of impurities.
  • CMP chemical- mechanical polishing
  • FIG. 3 there is shown a side view of the donor substrate, indicated by the reference numeral 10, after patterning.
  • the patterning is performed by etching techniques.
  • the donor substrate 10 has been etched to a level in the donor substrate deeper than the ion implantation layer 3 depth. In this way, a pattern comprising a plurality of mesas 11 is formed on the donor substrate.
  • photolithography is used to define a pattern.
  • the wafer is then etched to make the mesas.
  • the etching can be either dry or wet etching.
  • the donor substrate 10 as shown in Figure 3 is turned upside down and the contact surface 5 is brought into contact with the top surface 9 of the host substrate 7.
  • the donor substrate 10 and the host substrate 7 are then bonded together.
  • the donor substrate and the host substrate are bonded together and subsequently annealed in an oven or furnace to strengthen the bond.
  • the term bond and variations thereof are used and these will be understood to mean a direct bond according to the commonly understood definition in the art. More specifically, a direct bond is when two materials are brought into contact with each other and a bond is formed between the two surfaces of the materials as opposed to an indirect bond in which an adhesive or other material is used to bond the two materials together.
  • the present invention is concerned with direct bonding and is not concerned with indirect bonding.
  • the wafers are heated to a higher temperature which causes the donor substrate to split at the ion implantation layer 3 depth. This is achieved by raising the temperature in the oven to the point where the ions in the ion implantation layer 3 begin to coalesce to form a gas thereby expanding to create voids (not shown) in the donor substrate which in turn cause the donor substrate to delaminate and split at the ion implantation depth.
  • This ion implantation layer splitting technique is described in more detail in US5, 374,564 to Bruel and is also commonly used in the so-called Smart- Cut ® technique.
  • transplant layer pattern 13 comprises that portion of the mesas 11 between the contact surface 5 and the ion implantation layer 3.
  • FIG. 6 there is shown a side view of a second donor substrate, indicated generally by the reference numeral 20, after patterning by etching has taken place.
  • the second donor substrate 20 is preferably a different material to the host substrate and the first donor substrate 1 , 10.
  • the second donor substrate has also been ion implanted and etched to a level below the ion implantation layer 21 of the second donor substrate.
  • the second donor substrate comprises a plurality of mesas 23 spaced apart across the second donor substrate, each mesa terminating in a contact surface 25. Between the mesas are cavities 27.
  • the second donor substrate 20 is turned upside down and aligned with the host substrate 7 as shown in Figure 5 having the patterned transplant layer 13 bonded thereto.
  • aligning what is meant is that the mesas 23 on the second donor substrate 20 are positioned in line with the gaps (cavities) between the mesas 11 on the host substrate 7.
  • the second donor substrate 20 and the patterned host substrate 7 are interlocked together and the second donor substrate is brought into contact with the patterned host substrate and they are bonded together.
  • the second donor substrate 20 is split at the ion implantation layer 21 depth using the same technique described above.
  • the second donor substrate 20 splits at the ion implantation layer 21 depth the second donor substrate is removed and a patterned transplant layer, comprising a plurality of mesas 23, is left bonded to the host substrate 7, as shown in Figure 8.
  • the patterned transplant layer comprises that portion of the mesas 23 that was between the contact surface 25 and the ion implantation layer 21.
  • the above technique could be repeated a number of times, space permitting, to place a plurality of different material patterns on the host substrate 7.
  • the ion implantation layer 21 depth can be chosen so that the mesas 23, when transferred to the host substrate 7, are taller than, substantially the same height as, or shorter than the mesas 11 already on the host substrate.
  • FIG. 9 there is shown various stages of a particularly preferred process according to the present invention, where like parts have been given the same reference numeral as before.
  • FIG 9 there is shown a plan view of a host substrate, indicated generally by the reference numeral 30.
  • the host substrate comprises a plurality of cavities 31 extending downwards from a top surface 33 of the host substrate 30.
  • FIG 10 there is shown a side cross sectional view along the lines A-A of the substrate 30 of Figure 9 showing a plurality of cavities 31 in cross section.
  • the host substrate 30 is a silicon-on-insulator (SOI) substrate produced for example in accordance with the Smart Cut ® technique developed by the French company, SOITEC.
  • SOI silicon-on-insulator
  • the SOI substrate has a buried silicon oxide (SiO 2 ) layer 35, commonly referred to as a buried oxide layer.
  • the cavity 31 is etched into a silicon layer 37 and the buried oxide layer 35 acts as an etch stop. This ensures a smooth surface at the base of the cavity 31 and provides trench isolation.
  • Each cavity 31 has a depth, D, and a width, W.
  • a donor substrate 10 comprising an ion implantation layer 3 and a plurality of mesas 11.
  • the donor substrate is patterned with the mesas 11 by etching the substrate to a level below the hydrogen ion implantation layer 3.
  • the width, W m , of the mesas is narrower than the width, W, of the cavity 31 of the host substrate 30.
  • the depth, R p , of the ion implantation layer 3 is greater than the depth, D, of the cavity.
  • the height of the mesa is greater than the depth, D, of the cavity.
  • the width, W, of the cavity will be of the order of greater than 100nm.
  • the depth, D, of the cavity will be of the order of 1 micron or less.
  • the depth of the ion implantation layer, R p is of the order of 1 micron or less.
  • the width, W m , of the mesa is of the order of less than 100nm.
  • the height of the mesa is of the order of
  • the height of the mesa will however be greater than the depth, D, of the cavity and the depth, R p , of the ion implantation layer.
  • the donor substrate 10 is turned upside down and the mesas 11 are aligned with the cavities 31 in the host substrate 30.
  • the donor substrate 10 and the host substrate 30 are brought together by moving the donor substrate in the direction of the arrow 39 and interlocked together by inserting the mesas
  • the donor substrate and the host substrate are bonded together and annealed to strengthen the bond.
  • the donor substrate 10 is split by heating the donor 10 and the host 30 substrates up to implantation species, in this case ion, expansion temperature.
  • implantation species in this case ion, expansion temperature.
  • the donor substrate 10 will delaminate at the ion implantation layer 3 and in this case most of the donor substrate 10 will break away from the host substrate 30, leaving only the portion of the mesas that were between the ion implantation layer 3 and the contact surface 5 in contact with the host substrate ( Figure 13). In this way, a patterned transplant layer 13 is left on the host substrate 30.
  • the bond may be further strengthened using annealing techniques.
  • annealing techniques For example, in the case of an Si Ge combination of host substrate and donor substrate, the host wafer and patterned transplant layer could be heated to a temperature of the order of 200 0 C for a period of 120 minutes. The temperature and duration of the annealing step will depend on the two or three different materials being bonded. This is a result of each material having its own thermal expansion coefficient.
  • CMP chemical mechanical polishing
  • planar hybrid substrate will be usable in standard CMOS fabrication equipment and other equipment that requires planar substrates.
  • the planar substrate could for example comprise a combination of Si and Ge which could be processed on the same CMOS production lines without changing the process steps of the production line.
  • the process described above could be used to fabricate hybrid oriented (100) Si with (111 ) Si in the same way on the CMOS production lines.
  • additional processing steps such as lithography and/or metallization techniques can be performed on the planar substrate.
  • FIG. 14 there is shown various stages of another process according to the present invention, where like parts have been given the same reference numeral as before.
  • FIG 14 there is shown a side cross sectional view along the lines A-A of the substrate 30 of Figure 9 showing a plurality of cavities 31 in cross section.
  • the host substrate 30 is a silicon-on-insulator (SOI) substrate produced for example in accordance with the Smart Cut ® technique developed by the French company, SOITEC.
  • SOI substrate has a buried silicon oxide (SiO 2 ) layer 35, commonly referred to as a buried oxide layer.
  • the cavity 31 is etched into a silicon layer 37 and the buried oxide layer 35 acts as an etch stop. This ensures a smooth surface at the base of the cavity 31 and provides trench isolation.
  • Each cavity 31 has a depth, D, and a width, W.
  • a donor substrate 70 comprising an ion implantation layer 3 and a plurality of mesas 11.
  • the donor substrate is patterned with the mesas 11 by etching the substrate to a level below the hydrogen ion implantation layer 3.
  • the width, W m , of the mesas is narrower than the width, W, of the cavity 31 of the host substrate.
  • the depth, R p , of the ion implantation layer 3 is less than the depth, D, of the cavity.
  • the height of the resulting bound mesa will be less than the depth, D, of the cavity.
  • the depth of the ion implantation layer in Figure 15 is shallower than the depth of the ion implantation layer in Figure 11. Therefore, the height of the mesa that will be transferred from the donor substrate 70 (Figure 15) will be less than the height of the mesa that will be transferred from the donor substrate 10 ( Figure 11).
  • the donor substrate 70 is turned upside down and the mesas 11 are aligned with the cavities 31 in the host substrate 30. When aligned, the donor substrate 70 and the host substrate 30 are brought together by moving the donor substrate in the direction of the arrow 39 and interlocked together by inserting the mesas 11 into the cavities until the contact surface 5 of the mesas come into contact with the base of the cavity 31.
  • the donor substrate 70 and the host substrate 30 are bonded together and annealed to strengthen the bond.
  • the donor substrate 70 is split by heating the donor 70 and the host 30 substrates up to implantation species (ion) expansion temperature.
  • implantation species ion
  • the donor substrate 70 will delaminate at the ion implantation layer 3 and most of the donor substrate 70 will break away from the host substrate 30, leaving only the portion of the mesas that were between the ion implantation layer 3 and the contact surface 5 in contact with the host substrate ( Figure 17). In this way, a patterned transplant layer 13 is left on the host substrate 30.
  • the bond may be further strengthened using annealing techniques.
  • the transferred layer 13 will be below the plane (top surface 33) of the host wafer.
  • the host substrate 30 with the patterned transplant layer 13 as shown in Figure 17 is subjected to chemical mechanical polishing (CMP) or equivalent technique to remove the portions of the host substrate 30 that protrude upwardly above the top surfaces of the mesas.
  • CMP chemical mechanical polishing
  • the planar hybrid substrate will be usable in standard CMOS fabrication equipment and other equipment that requires planar substrates.
  • the depth of the ion implantation layer could be the same as the depth of the cavity.
  • no cleaning or CMP would be required however in practice, in such an instance, it may be preferable to provide a CMP or other cleaning technique in order to ensure that the top surfaces of the mesas are co-planar with the top surfaces of the host substrate.
  • FIGS. 18 to 24 inclusive there are shown various sketches, graphs and images representative of an experiment to demonstrate the feasibility of bonding a pattern from a donor substrate onto a host substrate.
  • a patterned Si wafer 41 is used as a donor substrate and another blanket Si wafer 43 is used as the host substrate.
  • the wafers 41 , 43 are shown schematically bonded together prior to splitting of the donor substrate 41.
  • the donor substrate 41 and the host substrate 43 both comprise a single side polished 4 inch p-type (100) Si wafer.
  • the surface of the donor substrate 41 and the surface of the host substrate 43 that are to oppose each other when the two substrates come into contact with each other are pre-treated.
  • the donor substrate 41 has an SPM (Sulphuric-peroxide mixture, H 2 SO 4 IH 2 O 2 , typically in a 2:1 ratio mixture) clean and a 100nm thermal oxide growth.
  • the donor substrate was ion implanted with H 2+ with a 5x10 16 atoms/cm 2 dose at 180keV energy. From SRIM (Stopping and Range of Ions in Matter) simulations, the projected range of the ion implants is approximately 700nm.
  • the oxide layer was removed in a 5:1 BOE (Buffered Oxide Etch) solution before pattern transfer using a mask with a depth of etch of the order of 2 ⁇ m.
  • a lithography rework was performed after resist coating. However, this lithography rework step would normally not have to be done. Furthermore, in some instances it may be preferable to not remove the oxide layer as it may assist in the bonding process.
  • the surface of the host substrate 43 is cleaned with a Piranha solution (Sulphuric- peroxide mixture, H 2 SO 4 )H 2 O 2 , typically in a 3:1 or 2:1 ratio mixture), followed by a deionised (Dl) water rinse with a resistivity of 18 Mohms.
  • the host substrate is then spin rinse dried in a Semitool ®.
  • a Piranha solution was used for the purposes of the example but other types of cleaning techniques known in the art would also be suitable.
  • the bonding chamber is cleaned first of all by performing an oxygen radical exposure for 10 minutes. This step is not necessary for generic bonding and may be omitted in certain circumstances.
  • the donor substrate and the host substrate are then loaded into the chamber and the internal pressure in the chamber is reduced down to 1 mbar.
  • a further oxygen radical exposure is performed for 10 minutes using a distance between substrates of 7mm.
  • the substrates are brought into contact with each other and bonded together.
  • the wafers were loaded into a commercial bonder, activated using a remote oxygen plasma and bonded in vacuum. It will be understood that the times and temperatures for bonding are dependent on the substrates chosen for the process and will vary depending on the substrates chosen.
  • Both wafers were loaded into a commercial bonder and the system was pumped down to a chamber pressure set to 1mbar. An oxygen radical exposure was performed for 10 minutes using a distance between wafers of seven mm. After exposure, the wa
  • FIG. 19 there is shown a ramp up sequence used after in-situ direct bonding in a furnace chamber.
  • the bonded pair of donor substrate and host substrate is encapsulated in a glass Petri dish and loaded in a furnace chamber (SMT lab).
  • the bonded pair of substrates were annealed at a temperature below the splitting temperature to strengthen the initial bond.
  • the sample is heated very slowly up to 200 0 C with a ramp up rate shown in the diagram. All of the time periods shown are of 40 minutes duration except the time period for the increment from 170 ° C to 185 ° C and the time period for the increment from 185 ° C to 200°C, both of which are of 60 minutes duration. Once the temperature reaches 200 0 C, the temperature is kept steady for of the order of 24 hours.
  • Figures 20(a) and 20(b) there is shown some images taken from an optical microscope of the host wafer 43 after donor substrate splitting.
  • Figure 20(a) shows evidence of pattern transfer.
  • Figure 20(b) shows a close up view of areas where pattern transfer has occurred as well as views showing rounded corners on both inner and outer corners. Some of the defects shown are in fact particles on the microscope lens. Inspection of the host wafer 43 by optical microscopy confirms the successful bonding and transfer of Silicon features from the donor substrate to the host substrate.
  • Figures 20(a) and 20(b) show features 51 , 53 that have been successfully transferred. A high defect density is observed in the vicinity of the transferred features, probably Si pits due to incomplete bonding.
  • FIG. 21 there is shown an image taken of the donor wafer 41 under the optical microscope after donor substrate splitting. The figure shows insufficiently high bond strength at the edges of the patterned features which result in tearing of the Si from the edge of the small square. However, this is almost certainly a result of the lithography step in the cleanroom and could be eradicated by a more precise lithography step.
  • FIG. 22 there is shown a scanning electron microscope (SEM) inspection of the host substrate 43 after wafer (donor substrate) splitting in plane view at the bonded site.
  • SEM inspection confirms that patterned bonding can lead to transfer of straight and small (of the order of 100 ⁇ m in size) patterns. However, sharp features like corners are rounded. This is unlikely to have been caused by the H ion implant as the corners are rounded the same way from the top to the bottom of the transferred layer. It is envisaged that the reason for this is in fact caused by the lithography and/or Si etch steps.
  • Figures 23(a) and 23(b) there is shown an SEM inspection of the host substrate 43 after donor substrate splitting, at a tilt angle of 35 degrees.
  • Figure 23(a) shows the outer edge of the larger square 51
  • Figure 23(b) shows the outer corner of the large square 51.
  • the rounding is a function of relatively imprecise lithography which is rectifiable in a relatively straightforward manner.
  • Figures show a typical surface roughness degradation caused by the splitting process. Si polishing is usually performed after the splitting operation.
  • the height (thickness) is approximately 610nm rather than 700nm as expected from the SRIM simulations and estimated using Monte-Carlo simulations. This thickness corresponds to a H 2+ implant with a 5x10 16 atoms/cm 2 dose at 180keV energy.
  • the bond strength could be improved by using other pre-bonding treatments including cleans and radical or plasma exposures.
  • a buried SiO 2 layer is used in the host substrate to stop the etch process.
  • Si 3 N 4 Silicon nitride
  • the donor substrate 81 comprises a plurality of mesas 83 and a plurality of cavities 85.
  • the mesas are each provided with an etch stop layer 87 and a contact surface 89.
  • the donor substrate 81 with an etch stop layer 87 is patterned and is then bonded to a host substrate (not shown) in a manner such as that described above.
  • the donor substrate is patterned to a level below the etch stop layer using dry etching techniques.
  • the mesas 83 on the donor substrate 81 will the same material as the donor substrate.
  • a protective material may have to be infused between the donor substrate 81 and the mesas 83 to prevent the pattern of mesas 83 being etched away.
  • the mesas 83 will be a different material to the donor substrate 81 and will have been grown on the donor substrate 81. In this case, it may be possible to choose a suitable selective etching solution that does not damage either of the patterned transplant layer (mesas 83) and the host substrate (not shown).
  • the planar hybrid substrate comprises a host substrate 93 and three patterned transplant layers 95, 97 and 99. This is achieved by bonding a first patterned transplant layer to the host substrate and thereafter sequentially bonding a second and a third transplant layer to the host substrate using the techniques described above.
  • the three patterned transplant layers 95, 97, 99 are shown alternating however this is only for the purposes of illustration only and the patterned transplant layers need not follow such a strict sequential pattern.
  • the patterned transplant layers may predominantly comprise two patterned transplant layers and the third transplant layer may comprise fewer mesas.
  • the hybrid substrate 101 comprises a host substrate 103 and a first patterned transplant layer 105, a second patterned transplant layer 107 and a third patterned transplant layer 109. Either of the first and second patterned transplant layers 105 or 107 may be bonded to the host substrate 103 first. If the first patterned transplant layer 105 is bonded to the host substrate 103 first, the second transplant layer 107 is then bonded to the host substrate and thereafter the third patterned transplant layer 109 is bonded to the second patterned transplant layer 107.
  • the second patterned transplant layer 107 is bonded to the host substrate 103 first, then either the first patterned transplant layer 105 is bonded to the host substrate 103 before the third patterned transplant layer 109 is bonded to the patterned transplant layer 107 or alternatively the third patterned transplant layer 109 is bonded to the second patterned transplant layer 107 before the first patterned transplant layer is bonded to the host substrate 103.
  • the bonding steps for bonding the third patterned transplant layer 109 to the second pattered transplant layer 107 are performed using the same techniques described above for bonding a patterned transplant layer from a donor substrate to a host substrate. Again, although only three patterned transplant layers are shown, the present invention is not limited to only three transplant layers and more or less patterned transplant layers may be provided.
  • the mesas of the first patterned transplant layer 105 could instead be mesas of the host substrate that were formed through etching of the host substrate (the SiO 2 layer has been omitted for clarity).
  • the mesas of the second patterned transplant layer 107 could instead be mesas of the host substrate that were formed through etching of the host substrate (the SiO 2 layer has been omitted for clarity).
  • a fourth transplant layer (not shown) may be stacked on top of either the first patterned transplant layer 105 or the third patterned transplant layer 109.
  • FIGs 28 and 29 there are shown a pair of magnified views of a Germanium (Ge) substrate pattern 111 bonded to a Silicon (Si) substrate 113.
  • a relatively thick boundary layer 115 of Silicon Oxide (SiO 2 ) which is of the order of 100nm thick. This is important in that it shows that it is possible to bond the Ge with the Si even in the presence of the thick SiO 2 boundary layer.
  • the boundary layer 115 is relatively thin, of the order of 2nm in thickness and in turn comprises an SiO 2 oxidation layer 117, a GeO 2 oxidation layer 119 and a hydroxidation (OH-) layer 121.
  • the boundary layer is activated using a free radical activation using O 2 prior to bonding. This is important as it shows that as well as hydrophilic bonding, it is possible to provide hydrophobic bonding between the pattern (Ge) and the substrate (Si).
  • the donor substrate comprises Ge, however the donor substrate could be taken from one of gallium arsenide GaAs, SiC, InP, (110) Si, (100) Si or any other substrate that may be delaminated using ion cut techniques.
  • the implantation ions are H + ions but equally well could be H 2+ , Helium or noble gases, for example.
  • the host substrate could comprise any of the materials mentioned above for the donor substrate as well as any flat substrate such as polycrystalline AIN (good for heat conduction).
  • Various experiments have been carried out to reduce the exfoliation temperature of the Ge (the temperature at which the Ge will split). This is achieved by applying different temperatures for different durations. By reducing the exfoliation temperature, it is possible to combine materials with significantly different coefficients of thermal expansion (CTE). It is advantageous to provide a splitting temperature significantly lower than 350 0 C.
  • a pair of anneal stages were performed, a first anneal stage at a temperature of 13O 0 C for 24 hours followed by a second anneal stage at a temperature of 300 0 C for 5 minutes. After the pair of anneal stages, a micro-crack had formed in the splitting layer.
  • a pair of anneal stages were performed, a first anneal stage at a temperature of 100 0 C for 24 hours followed by a second anneal stage at a temperature of 300 0 C for 5 minutes. In this experiment, it was found that the hydrogen coalesces even at 100 0 C.
  • a pair of anneal stages were performed, a first anneal stage at a temperature of 200 0 C for 24 hours followed by a second anneal stage at a temperature of 300 0 C for 10 minutes.
  • the donor substrate and the host substrate were subjected to a free radical activation using O 2 for 15 minutes and clamped together in a bonder with an applied force of 1 KN. The applied force was maintained for of the order of 5 minutes. The donor substrate and the host substrate were then annealed.
  • a pattern comprising one or more mesas could be transferred on top of another pattern.
  • the mesas could be built up in a piecewise fashion and comprise a number of different layers.
  • the layers would preferably comprise two or more different materials.
  • the mesas and cavities have been cuboid in shape however it will be understood that the mesas and cavities are not limited to being cuboid and could be more complex shapes.
  • a mechanically weakened layer could be provided instead of the ion implantation layer.
  • a mechanically weakened layer could be provided instead of the ion implantation layer.
  • Such an embodiment would appear identical to the embodiment illustrated in Figures 3 and 25 with the exception that the ion implantation layer 3 and the etch stop layer 87 respectively would be replaced by a mechanically weakened layer.
  • a mechanically weakened layer it is possible to pattern the donor substrate with a mechanically weakened layer to a depth below the weakened layer and thereafter bond the patterned donor substrate to a host substrate. Once bonded, the part of the donor substrate other than the pattern may be removed mechanically by severing the donor substrate at the mechanically weakened layer.
  • the porous layer may be provided by applying a voltage across the donor material. This applied voltage would result in a number of pores or bubbles forming in a thin layer at the surface of the substrate. This thin layer is the mechanically weakened layer.
  • a donor layer may then be grown on top of the mechanically weakened layer. After patterning, the donor substrate can be bonded to the host substrate and the donor substrate may be split at the mechanically weakened layer. Although mechanically weakened, the porous layer still retains is crystal structure and therefore it is still possible to grow high quality materials on the mechanically weakened layer.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

L'invention concerne un processus de fabrication d’un substrat hybride et un substrat hybride ainsi produit. Le processus comporte les étapes consistant à implanter des ions dans un substrat donneur ; à texturer le substrat donneur jusqu’à une profondeur supérieure à la profondeur d’implantation des ions ; à texturer un substrat hôte jusqu’à une profondeur inférieure à la profondeur de texture du substrat donneur ; à imbriquer le substrat hôte texturé et le substrat donneur texturé ; à coller le substrat donneur texturé au substrat hôte et à fractionner le substrat donneur à la profondeur d’implantation des ions de manière à laisser une couche de transplant texturée sur le substrat hôte. On produit ainsi un substrat hybride plan de manière simple et efficiente. Ceci est particulièrement avantageux, car le substrat plan peut être utilisé dans les machines connues de transformation de CMOS et lors des étapes ultérieures de transformation telles que la lithographie et la métallisation. De manière analogue, des étapes de transformation de dispositifs spécifiques à chaque substrat peuvent être appliquées indépendamment au substrat en question avant de coller les substrats l’un à l’autre.
PCT/IE2010/000049 2009-08-14 2010-08-16 Processus de fabrication d’un substrat hybride WO2011018780A1 (fr)

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Publication number Priority date Publication date Assignee Title
WO2012110591A1 (fr) * 2011-02-18 2012-08-23 Commissariat à l'énergie atomique et aux énergies alternatives Procede de realisation d'un support de substrat
FR2971885A1 (fr) * 2011-02-18 2012-08-24 Commissariat Energie Atomique Procédé de réalisation d'un support de substrat
US9321636B2 (en) 2011-02-18 2016-04-26 Commissariat à l'énergie atomique et aux énergies alternatives Method for producing a substrate holder

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