WO2011004591A1 - Filter circuit and optical disc device provided with same - Google Patents
Filter circuit and optical disc device provided with same Download PDFInfo
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- WO2011004591A1 WO2011004591A1 PCT/JP2010/004421 JP2010004421W WO2011004591A1 WO 2011004591 A1 WO2011004591 A1 WO 2011004591A1 JP 2010004421 W JP2010004421 W JP 2010004421W WO 2011004591 A1 WO2011004591 A1 WO 2011004591A1
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- 230000003287 optical effect Effects 0.000 title claims description 15
- 239000003990 capacitor Substances 0.000 claims abstract description 17
- 238000012545 processing Methods 0.000 claims description 11
- 230000005669 field effect Effects 0.000 claims description 7
- 238000012546 transfer Methods 0.000 description 20
- 238000010586 diagram Methods 0.000 description 17
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 239000000470 constituent Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000010606 normalization Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/34—DC amplifiers in which all stages are DC-coupled
- H03F3/343—DC amplifiers in which all stages are DC-coupled with semiconductor devices only
- H03F3/347—DC amplifiers in which all stages are DC-coupled with semiconductor devices only in integrated circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
- H03H11/12—Frequency selective two-port networks using amplifiers with feedback
- H03H11/1213—Frequency selective two-port networks using amplifiers with feedback using transistor amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/20—Disc-shaped record carriers
- G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
- G11B2220/2537—Optical discs
- G11B2220/2541—Blu-ray discs; Blue laser DVR discs
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/20—Disc-shaped record carriers
- G11B2220/25—Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
- G11B2220/2537—Optical discs
- G11B2220/2562—DVDs [digital versatile discs]; Digital video discs; MMCDs; HDCDs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/91—Indexing scheme relating to amplifiers the amplifier has a current mode topology
Definitions
- the present invention relates to a filter circuit, and more particularly, to a current mode filter circuit composed of a field effect transistor and an optical disk apparatus provided with this in a signal processing path.
- the filter circuit is an indispensable function block that constitutes various signal processing systems.
- the analog filter circuit is a high-frequency noise remover for shaping the signal waveform before analog-to-digital conversion and preventing aliasing in analog / digital mixed LSIs. It plays an important role.
- a Gm-C filter composed of a transconductance circuit (hereinafter referred to as a Gm circuit) and a capacitive element.
- the Gm-C filter as described in Non-Patent Document 1 and Non-Patent Document 2, 1. Since the parasitic pole of the Gm circuit constituting the filter is close to the pole of the filter, it is difficult to realize accurate frequency characteristics particularly in a high frequency region.
- the recent miniaturized low-voltage digital CMOS process has a problem that it is difficult to ensure a wide dynamic range and linearity in a Gm-C filter operating in a voltage mode.
- Non-Patent Document 1 and Non-Patent Document 2 propose filter circuits that operate in a current mode.
- Non-Patent Document 1 it is realized by a method of feeding back an output current as shown in FIG. 2 (a) in the same document, but in Non-Patent Document 2, it is shown in FIG.
- a filter circuit is realized by adding a capacitive element to the grounded gate mirror circuit, and the circuit is realized with a smaller number of elements than in Non-Patent Document 1.
- FIG. 15 shows the configuration of the current mode filter described in Non-Patent Document 2. In the current mode filter of FIG.
- N-channel transistors M200 and M203 form a current mirror pair, and each is driven by a bias current Ib0 from a current source.
- the source of a P-channel transistor M201 that functions as a grounded gate circuit whose gate is fixed at a constant voltage Vb0 and is driven by a bias current Ic0 is connected to the drain of the N-channel transistor M200, and the drain of the P-channel transistor M201 is N
- the N-channel transistor M200 and the P-channel transistor M201 constitute a negative feedback loop.
- capacitive elements Ci and Cg are connected to the drain and gate of the N-channel transistor M200, respectively.
- gmn represents the gm of the N-channel transistors M200 and M203
- gmp represents the gm of the P-channel transistor M201
- ⁇ n represents the transconductance parameter of the N-channel transistor
- ⁇ p represents the transconductance parameter of the P-channel transistor.
- Equation 3 is a transfer function of a secondary low-pass filter (hereinafter referred to as LPF), and indicates that the circuit configuration of FIG. 15 functions as a current mode secondary LPF. It can also be seen that the ⁇ 0 and Q values indicating the frequency characteristics are determined by gmp, gmn, Ci, and Cg.
- LPF secondary low-pass filter
- the frequency band required for analog signal processing exceeds 100 MHz for high-speed reproduction, and is generally used for conventional DVD recording / reproducing apparatuses.
- Gm-C filter it is difficult to achieve both broadening of the bandwidth, ensuring linearity, and dynamic range, and a current mode filter that can achieve both of these is attracting attention.
- the filter characteristics need to be adjusted in a filter circuit that requires strict accuracy in frequency characteristics. This adjustment is carried out in various steps, such as when it is carried out during product shipment inspection or when the LSI is started up, but the common point is that adjustment is carried out only once. For this reason, only the amount of variation in the manufacturing process is adjusted. For example, a temperature-dependent parameter variation cannot be absorbed only by the above-described process adjustment. In general, it is known that the capacitance element formed by the CMOS process has a small temperature dependency, but the transconductance parameter has a large temperature dependency and the influence on the filter characteristics cannot be ignored. Although means for automatically compensating for temperature fluctuations is required, Non-Patent Document 1 and Non-Patent Document 2 do not describe how to implement this means.
- a transconductance adjustment circuit is required for each of the N-channel transistor and the P-channel transistor, and the circuit mounting area is large.
- the present invention has been made in order to solve the above-mentioned problems related to mounting area, applicability, and low voltage operation, and its purpose is to achieve a current mode filter that can be realized with a minimum configuration, and to reduce or reduce the voltage. It is an object to provide a transconductance adjustment circuit suitable for area increase, and a high-pass filter and a band-pass filter that operate in a current mode, which is not provided in the conventional example.
- the above-mentioned problem relating to the compensation of the temperature variation of the transconductance parameter can be solved by combining the transconductance adjustment circuit described in Patent Document 1 and the filter circuit shown in FIG. FIG. 16 shows a transconductance adjustment circuit described in Patent Document 1.
- the transconductance adjustment circuit of FIG. 16 subtracts the potential difference generation circuit for applying voltages V0a + V1a / 2 and V0a ⁇ V1a / 2 to the gates of the ninth and tenth transistors M106 and M107, respectively, and the drain currents of the transistors M107 and M106.
- the current mirror circuit that outputs the resulting current ⁇ Ia, the resistor Re that performs current-voltage conversion of the current mirror output, the voltage that is current-voltage converted by the resistor Re, and the reference voltage V2a are compared, and the comparison result Is output as a current value I1c, and a means for converting the current value I1c into a current-voltage and returning the output voltage as V0a to the gate inputs of the transistors M106 and M107.
- the current mirror output of I1c becomes the bias current Ib shown in FIG. To connect. Assuming that the transistors M107 and M106 are operating in the saturation region, the drain currents I1a and I1b of the transistors M106 and M107 are respectively expressed by the following equations.
- ⁇ n represents the transconductance parameter of the N-channel transistor
- Vtn represents the threshold voltage of the N-channel transistor
- the output voltage V0a is expressed by the following equation from the equations 4 and 5.
- Equation 1 the gm of the N-channel transistor included in the current mode filter circuit can be obtained without including the transconductance parameter as shown in the following equation.
- Equation 8 The above equation represents the gm of the N-channel transistor. However, in the circuit of FIG. 16, by replacing the N-channel transistor with the P-channel transistor and the P-channel transistor with the N-channel transistor, the gm of the P-channel transistor is similar. Is obtained in the same manner as Equation 8.
- ⁇ 0 and Q described in Expression 3 do not depend on the transconductance parameter, and ⁇ 0 and Q can be arbitrarily controlled by changing V2a, V1a, and Re.
- the filter circuit according to the first aspect of the present invention is a current mirror circuit including field effect transistors, and includes first, second, and third transistors having the same channel polarity,
- the drain of the first transistor is connected to the source of a second transistor that functions as a grounded gate circuit, the drain of the second transistor is connected to the gates of the first transistor and the third transistor,
- Current supply means wherein one or both of the drain and the gate of the first transistor is used as an input terminal, and an output signal is supplied to the first transistor. Wherein the retrieving from the drain current of the transistor.
- the filter circuit of the invention according to claim 2 is a current mirror circuit composed of field effect transistors, and includes first, second, third, and fourth transistors having the same channel polarity,
- the fourth transistor operates as an I / V converter that converts an input current signal into a voltage signal, and a drain of the first transistor functions as a source follower that receives the output of the I / V converter.
- the drain of the second transistor Connected to the source of the second transistor, the drain of the second transistor is connected to the gate of the first transistor and the gate of the third transistor, and the gate and the drain of the first transistor, A first capacitive element and a second capacitive element are connected, and a bias current is supplied to each of the first and second transistors.
- a bias current supply means for supplying a bias current to the fourth transistor, and either or both of the drain of the first transistor and the drain of the fourth transistor are input terminals. The output signal is extracted from the drain current of the third transistor.
- the filter circuit according to the third aspect of the present invention is a current mirror circuit including field effect transistors, and includes first, second, and third transistors having the same channel polarity.
- a drain of the first transistor is connected to a gate of a second transistor functioning as a source follower, and a source of the second transistor is connected to gates of the first transistor and the third transistor.
- the first capacitor and the second capacitor are connected to the drain and gate of the first transistor, respectively, and a bias current is supplied to each of the first and second transistors.
- the transistors that determine the filter characteristics all have the same channel polarity, that is, all N-channel transistors or all P-channel transistors can form a circuit. Only one adjustment circuit is required.
- a feedback loop from the drain to the gate is provided in the filter circuit according to claim 3.
- a bias current supply means for supplying a bias current to the fourth transistor, wherein the first capacitor element includes a gate of the fourth transistor and a drain of the first transistor. And the gate of the fourth transistor is used as an input terminal, and an output signal is extracted from the drain current of the third transistor.
- the filter circuit according to claim 5 further comprises a feedback loop from the drain to the gate. And a bias current supply means for supplying a bias current to the fourth transistor.
- the second capacitor element includes a gate of the fourth transistor and a gate of the first transistor. And the gate of the fourth transistor is used as an input terminal, and an output signal is extracted from the drain current of the third transistor.
- the first, second, third transistor, and the fourth transistor are supplied to each of the first, second, and fourth transistors.
- the bias current is variable.
- the variable bias current is supplied from a transconductance adjusting circuit, and the transconductance adjusting circuit has a source connected in common.
- a voltage-current converter that performs voltage-current conversion on the feedback voltage, and includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Bias current supplied people, said voltage - characterized in that it is provided as a current mirror output of the output of the current converter.
- the invention according to claim 8 is adopted as a feedforward type transconductance adjustment circuit that does not include a feedback loop, does not require a large capacitance element for ensuring stability, and can reduce the area.
- the invention described in claim 8 is the filter circuit described in claim 6, further comprising a translinear loop circuit including fifth, sixth, seventh, and eighth transistors, Amplifying means for multiplying the current flowing through each of the transistor and the eighth transistor and supplying the current to the fifth and sixth transistors; and a current source circuit for supplying a bias current of the seventh transistor; The current mirror output of the current flowing through the eighth transistor is connected so as to be the bias current of the first, second, third transistor and fourth transistor.
- the current source circuit for supplying the bias current of the seventh transistor includes the ninth and tenth transistors whose sources are commonly connected.
- a potential difference generating circuit connected to generate a potential difference between the gates of the ninth and tenth transistors and to apply an average voltage of the gate voltages of the ninth and tenth transistors to the gate of the eleventh transistor;
- the current obtained by subtracting the current obtained by doubling the drain current flowing through the eleventh transistor from the sum of the drain currents is the first and second Characterized in that the bias current of the third transistor and the fourth transistor.
- an optical disc apparatus is characterized in that the filter circuit according to any one of the first to ninth aspects is provided in a signal processing path.
- the optical disk apparatus is provided with the above-described filter circuit in the signal processing path, recording / reproduction of a high-speed, high-density recording disk with low cost, low power consumption can be realized.
- the reason for this is that a current mode filter capable of achieving both wide bandwidth, linearity, and dynamic range can be mounted in a small area, and low voltage operation is possible.
- the filter circuit of the present invention since all the transistors that determine the filter characteristics can be configured by transistors having the same channel polarity of N channel or P channel, the transconductance adjustment circuit One is sufficient, and the mounting area of the circuit can be reduced.
- FIG. 1 is a diagram showing a low-pass filter circuit according to a first embodiment of the present invention.
- FIG. 2 is a diagram showing a filter circuit in which the constituent transistors of the filter circuit are replaced with P-channel transistors.
- FIG. 3 is a diagram showing a filter circuit configured by changing the input terminal of the filter circuit.
- FIG. 4 is a diagram showing a band-pass filter circuit configured by changing the input terminal of the filter circuit.
- FIG. 5 is a diagram showing a low-pass filter circuit according to the second embodiment of the present invention.
- FIG. 6 shows a filter circuit in which the constituent transistors of the filter circuit are replaced with P-channel transistors.
- FIG. 7 is a diagram showing a filter circuit configured by changing the input terminal of the filter circuit.
- FIG. 1 is a diagram showing a low-pass filter circuit according to a first embodiment of the present invention.
- FIG. 2 is a diagram showing a filter circuit in which the constituent transistors of the filter circuit are replaced with P-channel transistors.
- FIG. 8 is a diagram showing a band-pass filter circuit configured by changing the input terminal of the filter circuit.
- FIG. 9 is a diagram showing a bandpass filter circuit according to a third embodiment of the present invention.
- FIG. 10 is a diagram showing a high-pass filter circuit according to the fourth embodiment of the present invention.
- FIG. 11 is a diagram showing a transconductance adjusting circuit according to the fifth embodiment of the present invention.
- FIG. 12 is a diagram showing a transconductance adjusting circuit according to the sixth embodiment of the present invention.
- FIG. 13 is a diagram showing a configuration example of the optical disc apparatus.
- FIG. 14 is a diagram showing a configuration example of an analog front end unit of a data signal generation circuit provided in the optical disc apparatus.
- FIG. 15 is a diagram showing a conventional current mode filter circuit.
- FIG. 16 is a diagram showing a conventional transconductance adjustment circuit provided in the current mode filter circuit.
- FIG. 17 is a diagram showing a modification of the low-pass filter circuit of FIG.
- FIG. 18 is a diagram showing another modification of the low-pass filter circuit of FIG.
- FIG. 1 is a current mode filter circuit according to a first embodiment of the present invention.
- 1 is a filter circuit according to claim 1, wherein all N-channel transistors are used as constituent transistors of the current mode filter circuit.
- the first transistor M1 and the second transistor M2 are cascode-connected, and the drain of the transistor M2 is connected to the gate of the transistor M1, and both the transistors M1 and M2 are connected to a current source (bias). Biased with a current Icnt7 supplied from a current supply means 7).
- the gate of the transistor M2 is connected to the voltage generation circuit 8 that outputs the voltage Vb obtained by supplying the current Icnt53 output from the current source (bias current supply means) 53 to the fourth transistor M52 that is diode-connected.
- the gate is grounded in an alternating manner.
- the capacitive element C2 and the capacitive element C1 are connected to the ground point at the source of the transistor M2 commonly connected to the current input terminal 9 and the gate of the transistor M1 commonly connected to the gate of the third transistor M3, respectively.
- a transistor M51 is cascode-connected to the drain of the transistor M3 in order to reduce the drain voltage difference between the transistors M1 and M3, and the difference between the drain current of the transistor M51 and the bias current Icnt6 supplied from the current source 6 Is connected in common with the output terminal 10 so as to be output as an output.
- the transconductances gm1, gm2, and gm3 of the transistors M1, M2, and M3 are expressed by the following equations.
- Expression 10 is a transfer function of a second-order low-pass filter (hereinafter referred to as LPF), and the filter parameters ⁇ 0 and gm1 and gm2 for determining the Q value can all be realized by the transconductance of the N-channel transistor. Only one conductance adjustment circuit is required.
- LPF low-pass filter
- the current mode filter of FIG. 1 can change the transfer gain independently of ⁇ 0 and Q by changing not only ⁇ 0 and Q but also A0. . Since A0 is determined by the ratio of gm1 and gm3 as described above, it can be changed by switching Icnt6 and ⁇ 3 from Equation 9, that is, the bias current and transistor size of the transistor M3.
- the dynamic range of the current mode filter of FIG. 1 is determined by the current source 7 and the transistor M1.
- the current source 7 is composed of a P-channel transistor
- the overdrive voltage is Vodp
- the threshold voltage of the transistor M1 is Vtn
- the overdrive voltage is Vodn
- the power supply voltage Vdd that can operate in FIG. Is done.
- the filter circuit can be realized with a power supply voltage as low as that of the digital circuit.
- FIG. 1 shows an embodiment of a current mode filter composed of N-channel transistors, but it can also be realized by replacing the N-channel transistors with P-channel transistors as shown in FIG.
- the transistor M51 in FIG. 1 is inserted in order to obtain a more accurate current mirror ratio of the transistors M1 and M3, and even if omitted, the filter parameters ⁇ 0 and Q are not affected.
- FIG. 3 shows a configuration in which the connection of the input terminal 9 in the configuration of FIG. 1 is changed from the source of the transistor M2 to the drain of the transistor M2.
- ⁇ 0, Q, and A0 are as in Expression 11, and A1 is expressed by the following expression.
- the first term on the right side of Equation 13 represents the same second-order LPF transfer function as in Equation 10, and the second term on the right side represents a transfer function representing a second-order bandpass filter (hereinafter referred to as BPF). That is, the current mode filter having the configuration of FIG. 3 can obtain an output signal obtained by adding the characteristics of the second-order LPF and the second-order BPF characteristics.
- BPF bandpass filter
- the transfer function of Equation 15 can also be obtained by taking the output current signal from the output terminal 10 using the drain of the transistor M52 as the input terminal 9 instead of the source of the transistor M2 in FIG. it can.
- the configuration of the second aspect is shown in FIG. As shown in FIG. 18, when the output current signal is taken out from the output terminal 10 using both the source of the transistor M2 and the drain of the transistor M52 as the input terminals 12 and 9, the transfer characteristic of Expression 13 can be obtained.
- FIG. 5 is a current mode filter circuit according to the second embodiment of the present invention.
- N-channel transistors are used as constituent transistors of the current mode filter circuit.
- the transistor M1 has a configuration in which a drain voltage is fed back to the gate via a source follower including a transistor M2 and a current source 11 that supplies a current Icnt11.
- the transistor M1 is supplied from a current source 7. Biased with the current Icnt7.
- a capacitive element C2 and a capacitive element C1 are connected to the ground point at the source of the transistor M2 connected to the current input terminal 9 and the drain of the transistor M1, respectively.
- a transistor M51 is cascode-connected to the drain of the transistor M3 in order to reduce the drain voltage difference between the transistors M1 and M3, and the difference between the drain current of the transistor M51 and the bias current Icnt6 supplied from the current source 6 Is connected in common with the output terminal 10 so as to be output as an output.
- the gate of the transistor M51 is connected to the voltage generation circuit 8 that outputs a voltage Vb obtained by supplying the current Icnt53 output from the current source 53 to the diode-connected transistor M52, and the gate is grounded in an AC manner. Yes.
- the transconductances gm1, gm2, and gm3 of the transistors M1, M2, and M3 are expressed by the following equations.
- the current values supplied from the current source 7 and the current source 11 are independent.
- gm1 and gm2 can be adjusted independently.
- the current mode filter with a high freedom degree of filter parameter adjustment can be mounted in a small area.
- the dynamic range of the current mode filter of FIG. 5 is determined by the current source 7 and the transistors M1 and M2.
- the current source 7 is composed of a P-channel transistor
- the overdrive voltage is Vodp
- the threshold voltages of the transistors M1 and M2 are Vtn
- the overdrive voltage is Vodn
- Vdd> 2 (0.4 + 0.4) + 0.4 2V
- a higher power supply voltage than that of the first embodiment is required.
- FIG. 5 shows an embodiment of a current mode filter composed of N-channel transistors, but it can also be realized by replacing the N-channel transistors with P-channel transistors as shown in FIG.
- the transistor M51 in FIG. 5 is inserted in order to obtain a more accurate current mirror ratio between the transistors M1 and M3, and even if omitted, the filter parameters ⁇ 0 and Q are not affected.
- FIG. 7 shows a configuration in which the connection of the input terminal 9 in the configuration of FIG. 5 is changed from the source of the transistor M2 to the drain of the transistor M1.
- the signal Ii is input from the drain of the transistor M1, and the signal -Ii whose phase is inverted by 180 ° is input from the source of the transistor M2, thereby obtaining the transfer characteristic shown in Equation 13. be able to.
- This configuration is shown in FIG.
- Whether to select the configuration of the first embodiment shown in FIG. 1 or the selection of the second embodiment shown in FIG. 2 can be selected by those skilled in the art according to the power supply voltage specification of the LSI and the adjustment specification of the filter characteristics. it can.
- FIG. 9 shows a third embodiment corresponding to the fourth aspect.
- ⁇ 13 represents a transconductance parameter of the transistor M13
- Icnt14 represents a bias current supplied from the current source 14.
- the transfer characteristic Io / Ii of the configuration of FIG. 9 is obtained as shown in the following equation, and the transfer characteristic of the secondary BPF can be obtained.
- the method for realizing the secondary BPF is shown in FIG. 8 described in the second embodiment.
- two terminals, the input terminal 9 and the input terminal 12 are required.
- the expression 15 The BPF characteristic shown in FIG. 6 cannot be obtained, and the transfer characteristic is as shown in Expression 23.
- the secondary BPF characteristic can be realized with one input terminal by adding the transistor M13 and the current source. Therefore, the above-mentioned error factors can be eliminated, and a BPF having a good low frequency region attenuation characteristic can be obtained.
- FIG. 10 shows a fourth embodiment corresponding to the fifth aspect.
- the transconductance gm13 is expressed by Equation 20.
- FIG. 11 shows a fifth embodiment corresponding to claims 6 and 7.
- FIG. 11 is a configuration example of the bias current sources 6, 7, 53, and 14 in the current mode filter circuits described in the first to fourth embodiments, and is configured by the transconductance adjustment circuit 29.
- the configuration and operation of the circuit will be described.
- the drain currents of the transistors M106 and M107 in which the voltages Vga + ⁇ V / 2 and Vga ⁇ V / 2 generated by the potential difference generation circuit 21 are applied to the respective gates are supplied to the difference current generation circuit 22 configured by a current mirror circuit. input.
- a current source 24 that outputs a constant current Id and a voltage buffer circuit 23 are connected to the output of the difference current generation circuit 22, and the output of the voltage buffer circuit 23 is fed back as an input Vga of the potential difference generation circuit 21, so that the feedback circuit 31 is constituted.
- the voltage Vga is input to the gate of the transistor M108 operating as the voltage-current conversion circuit 25, the drain current of the transistor M108 is input to the current mirror circuit 26, and the current mirror output is the bias current described in each of the first to fourth embodiments.
- the outputs of the sources 6, 7, 53, and 14 are used.
- Reference numeral Cc shown in FIG. 11 is a stability compensation capacitor for ensuring the stability of the above-described feedback loop.
- the transistors M110, M111, and M112 each reduce the voltage difference between the drain voltages of the transistors M108, M106, and M107. This is a cascode transistor added for the purpose.
- the transistors M106 and M107 have the same transistor size, and the drain currents are Ida and Idb, respectively, the equation 26 is obtained.
- ⁇ n represents the transconductance parameter of the N-channel transistor
- Vtn represents the threshold voltage of the N-channel transistor
- the drain current Icnt0 is expressed by the following equation from Equation 28.
- k1, k2, and k3 represent transistor size ratios of the transistors M1, M2, and M3 illustrated in FIG. 1 with respect to the transistors M106, M107, and M108, respectively.
- Equation 11 do not depend on the transconductance parameters, and ⁇ 0, Q, and A0 can be arbitrarily controlled by changing Id and ⁇ V.
- this effect can also be obtained by the transconductance adjustment circuit shown in FIG. 16, but as is apparent from a comparison between FIG. 11 and FIG. 16, FIG.
- the element Re, the voltage sources V2a, and Vref are not required, and the circuit can be realized with a smaller number of parts, and the operational amplifier is unnecessary, which is advantageous over the conventional example in FIG. is there.
- the voltage buffer circuit 23 can be omitted if a bias voltage that allows each transistor to operate in the saturation region can be secured, and the gate of the transistor M108 and the drain of the transistor M111 can be directly connected. good.
- FIG. 11 shows a configuration example of the bias current sources 6, 7, 53, and 14 of the filter circuit composed of N-channel transistors.
- the bias current source can be realized by replacing the N-channel transistor of FIG. 11 with a P-channel transistor.
- FIG. 12 shows a sixth embodiment corresponding to claims 8 and 9.
- FIG. 12 shows a configuration example of the bias current sources 6, 7, 53, and 14 in the current mode filter circuit described in the first to fourth embodiments, which is configured by the transconductance adjustment circuit 29.
- the circuit configuration and operation will be described below.
- the fifth transistor M101, the sixth transistor M102, the seventh transistor M103, and the eighth transistor M104 operating in the saturation region constitute a translinear loop circuit 32, and the drain current of the transistor M103 and the transistor M104
- the current value obtained by adding the output current Id of the current source 24 by the current mirror circuit (amplifying means) 26 and the output current Id of the current source 24 becomes the bias current of M101 and M102. It is connected.
- the voltage Vga obtained by supplying the output current Ia of the current source 27 to the eleventh transistor M105 that is diode-connected is input to the potential difference generation circuit 21. Then, the drain currents of the ninth transistor M106 and the tenth transistor M107 to which the output voltages Vga + ⁇ V / 2 and Vga ⁇ V / 2 of the potential difference generating circuit 21 are applied to the respective gates are added by the wiring (adding means) 34.
- the current source (amplifying means) 28 doubles the drain current Ia flowing through the eleventh transistor M105 and outputs the output of the current source 28 from the sum of the drain currents of the ninth and tenth transistors M106 and M107.
- the current obtained by subtracting the current 2 ⁇ Ia is configured to be the bias current Ib of the seventh transistor M103.
- the current mirror output of the drain current of the eighth transistor M104 is configured to be the output of the bias current sources 6, 7, 53, 14 described in the first to fourth embodiments.
- the currents flowing through the transistors have the following relationship.
- drain currents Ida and Idb of the transistors M106 and M107 are expressed by the following equation 33 when the transistor sizes of the transistors M106 and M107 are the same, the transconductance parameter is ⁇ n, and the threshold voltage is Vtn.
- k1, k2, and k3 represent transistor size ratios of the transistors M1, M2, and M3 illustrated in FIG. 1 with respect to the transistors M106 and M107, respectively.
- Equation 11 do not depend on the transconductance parameter, and ⁇ 0, Q, and A0 can be arbitrarily controlled by changing Id and ⁇ V.
- the configuration of FIG. 12 does not include a feedback loop in the circuit as compared with the configuration of FIG. 11 described in the fifth embodiment. Therefore, the design is easy, and no capacitive element for stability compensation is required. There is an advantage that can be reduced.
- FIG. 12 shows a configuration example of the bias current sources 6, 7, 53, and 14 of the filter circuit configured by N-channel transistors.
- the bias current source can be realized by replacing the N-channel transistor in FIG. 11 with a P-channel transistor.
- FIG. 13 shows an optical disc apparatus according to the seventh embodiment.
- this optical disc apparatus includes a spindle motor 501, an optical pickup 502, an address signal generation circuit 503, an address decoder 504, a servo controller 505, a servo error signal generation circuit 506, and a data signal generation circuit 507. , A decoder 508, a CPU 509, and a laser power control circuit 510.
- the current mode filter circuit of the present invention is applied to the data signal generation circuit 507 in FIG. 13 as one example of application of the current mode filter circuit of the present invention.
- the current mode filter of the present invention can also be applied to the error signal generation circuit 506 and the laser power control circuit 510.
- FIG. 14 shows the internal configuration of the data signal generation circuit 507, particularly the configuration of the analog front end unit.
- the data signal obtained from the optical disk 500 is subjected to amplitude normalization in accordance with the full-scale input D range of the AD converter 514 and noise removal for preventing aliasing in the analog front end unit.
- a variable transconductance amplifier 511, a low-pass filter 512 of the present invention, and a transimpedance amplifier 513 are provided in front of the AD converter 514 as shown in FIG.
- the variable transconductance amplifier 511 has a function of converting a voltage signal input from the optical pickup 502 into a current signal, and a DA converter 516 and a gain control circuit according to the signal amplitude value detected by the digital signal processing circuit 519. Via 518, its transconductance is controlled to normalize the output current amplitude.
- the low-pass filter 512 of the present invention is supplied from the digital signal processing circuit 519 via the DA converter 515 and the band control circuit 517 so that optimum noise removal can always be performed according to the medium of the optical disc 500 and the reproduction double speed. The cut-off frequency is controlled.
- the output current signal of the low-pass filter 512 of the present invention is converted into a voltage signal by the transimpedance amplifier 513 and input to the AD converter 514.
- the D / A converters 515 and 516 are configured by current steering type D / A converters, and the gain control circuit 518 and the band control circuit 517 are realized by current signal processing by a current mirror circuit. All analog signal processing can be realized in the current mode except for the places where it is necessary to pass voltage signals between the input unit and the output unit, and an analog circuit that conventionally requires a power supply voltage of about 3 V is, for example, 1 It can be realized with a low power supply voltage of about 5 V, and the power consumed by the analog front end can be reduced by about 50%.
- the current mode filter circuit according to the present invention can be applied not only to a filter circuit in an optical disk apparatus typified by Blu-ray Disc and DVD, but also to any product field in which an analog filter circuit is mounted. It is.
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Abstract
Description
1.フィルタを構成するGm回路が持つ寄生極がフィルタの極に近接するため、特に高周波領域での正確な周波数特性の実現が難しい。 However, the Gm-C filter, as described in
1. Since the parasitic pole of the Gm circuit constituting the filter is close to the pole of the filter, it is difficult to realize accurate frequency characteristics particularly in a high frequency region.
(1)Nチャネルトランジスタ、Pチャネルトランジスタの各々にトランスコンダクタンス調整回路が必要であり、回路の実装面積が大きい。 To realize a current mode filter,
(1) A transconductance adjustment circuit is required for each of the N-channel transistor and the P-channel transistor, and the circuit mounting area is large.
(3)電圧比較動作が必要なため、オペアンプが必要となり、低電圧化が難しい。 Furthermore, the conventional transconductance adjustment circuit shown in FIG.
(3) Since a voltage comparison operation is required, an operational amplifier is required, and it is difficult to reduce the voltage.
図1は本発明の第1の実施形態による電流モードフィルタ回路である。 (Embodiment 1)
FIG. 1 is a current mode filter circuit according to a first embodiment of the present invention.
図5は、本発明の第2の実施形態による電流モードフィルタ回路である。 (Embodiment 2)
FIG. 5 is a current mode filter circuit according to the second embodiment of the present invention.
図9に請求項4に対応する第3の実施形態を示す。 (Embodiment 3)
FIG. 9 shows a third embodiment corresponding to the fourth aspect.
図10に請求項5に対応する第4の実施形態を示す。 (Embodiment 4)
FIG. 10 shows a fourth embodiment corresponding to the fifth aspect.
図11に請求項6及び請求項7に対応する第5の実施形態を示す。 (Embodiment 5)
FIG. 11 shows a fifth embodiment corresponding to
図12に請求項8及び請求項9に対応する第6の実施形態を示す。 (Embodiment 6)
FIG. 12 shows a sixth embodiment corresponding to
図13は第7の実施形態による光ディスク装置を示している。 (Embodiment 7)
FIG. 13 shows an optical disc apparatus according to the seventh embodiment.
M2 第2のトランジスタ
M3 第3のトランジスタ
M13、M52 第4のトランジスタ
M101 第5のトランジスタ
M102 第6のトランジスタ
M103 第7のトランジスタ
M104 第8のトランジスタ
M106 第9のトランジスタ
M107 第10のトランジスタ
M105 第11のトランジスタ
C1 第1の容量素子
C2 第2の容量素子
6 バイアス電流源
7、14 バイアス電流源(バイアス電流供給手段)
8 電圧生成回路
9、12 信号入力端子1
10 信号出力端子1
11 バイアス電流源
12 信号入力端子2
21 電位差発生回路
22 差電流生成回路
23 電圧バッファ回路(帰還手段)
24 基準電流源
25 電圧-電流変換回路
26 カレントミラー回路(増幅手段)
27 バイアス電流源
28 バイアス電流源(増幅手段)
29 トランスコンダクタンス調整回路
31 帰還回路
32 トランスリニアループ回路
33 電流源回路
34 配線(加算手段)
50 電源端子
53 バイアス電流源(バイアス電流供給手段)
60 オペアンプ M1 1st transistor M2 2nd transistor M3 3rd transistor M13, M52 4th transistor M101 5th transistor M102 6th transistor M103 7th transistor M104 8th transistor M106 9th transistor M107 10th Transistor M105 eleventh transistor C1 first capacitor element C2
8
10
11 Bias
21 Potential
24 reference
27 Bias
29
50
60 operational amplifier
Claims (10)
- 電界効果トランジスタで構成されるカレントミラー回路であって、
チャネル極性が全て同一である第1、第2、第3のトランジスタ(M1、M2、M3)を含み、
前記第1のトランジスタのドレインが、ゲート接地回路として機能する第2のトランジスタのソースに接続され、
前記第2のトランジスタのドレインが前記第1のトランジスタのゲートと前記第3のトランジスタのゲートとに接続され、
前記第1のトランジスタのゲート及びドレインに、各々、第1の容量素子(C1)と第2の容量素子(C2)とが接続された構成であって、
前記第1及び第2のトランジスタの各々にバイアス電流を供給するバイアス電流供給手段(7)を備え、
前記第1のトランジスタのドレイン又はゲートの何れか一方又は両方を入力端子とし、出力信号を前記第3のトランジスタのドレイン電流から取り出す
ことを特徴とするフィルタ回路。 A current mirror circuit composed of field effect transistors,
Including first, second, and third transistors (M1, M2, M3) having the same channel polarity;
The drain of the first transistor is connected to the source of a second transistor that functions as a grounded gate circuit;
The drain of the second transistor is connected to the gate of the first transistor and the gate of the third transistor;
The first capacitor element (C1) and the second capacitor element (C2) are connected to the gate and drain of the first transistor, respectively.
Bias current supply means (7) for supplying a bias current to each of the first and second transistors;
One of or both of the drain and gate of the first transistor is used as an input terminal, and an output signal is extracted from the drain current of the third transistor. - 電界効果トランジスタで構成されるカレントミラー回路であって、
チャネル極性が全て同一である第1、第2、第3、第4のトランジスタ(M1、M2、M3、M52)を含み、
前記第4のトランジスタは入力電流信号を電圧信号に変換するI/V変換器として動作し、
前記第1のトランジスタのドレインが、前記I/V変換器出力を入力とするソースフォロワとして機能する第2のトランジスタのソースに接続され、
前記第2のトランジスタのドレインが前記第1のトランジスタのゲートと前記第3のトランジスタのゲートとに接続され、
前記第1のトランジスタのゲート及びドレインに、各々、第1の容量素子(C1)と第2の容量素子(C2)とが接続された構成であって、
前記第1及び第2のトランジスタの各々にバイアス電流を供給するバイアス電流供給手段(7)と、
前記第4のトランジスタにバイアス電流を供給するバイアス電流供給手段(53)とを備え、
前記第1のトランジスタのドレイン及び前記第4のトランジスタのドレインの何れか一方又は両方を入力端子とし、出力信号を前記第3のトランジスタのドレイン電流から取り出す
ことを特徴とするフィルタ回路。 A current mirror circuit composed of field effect transistors,
Including first, second, third and fourth transistors (M1, M2, M3, M52) having the same channel polarity;
The fourth transistor operates as an I / V converter that converts an input current signal into a voltage signal;
A drain of the first transistor is connected to a source of a second transistor functioning as a source follower having the I / V converter output as an input;
The drain of the second transistor is connected to the gate of the first transistor and the gate of the third transistor;
The first capacitor element (C1) and the second capacitor element (C2) are connected to the gate and drain of the first transistor, respectively.
Bias current supply means (7) for supplying a bias current to each of the first and second transistors;
Bias current supply means (53) for supplying a bias current to the fourth transistor;
One of or both of the drain of the first transistor and the drain of the fourth transistor is used as an input terminal, and an output signal is extracted from the drain current of the third transistor. - 電界効果トランジスタで構成されるカレントミラー回路であって、
チャネル極性が全て同一である第1、第2、第3のトランジスタ(M1、M2、M3)を含み、
前記第1のトランジスタのドレインが、ソースフォロワとして機能する第2のトランジスタのゲートに接続され、
前記第2のトランジスタのソースが前記第1のトランジスタのゲートと前記第3のトランジスタのゲートとに接続され、
前記第1のトランジスタのドレイン及びゲートに、各々、第1の容量素子(C1)と第2の容量素子(C2)とが接続された構成であって、
前記第1及び第2のトランジスタの各々にバイアス電流を供給するバイアス電流供給手段(7)を備え、
前記第1のトランジスタのドレイン又はゲートの何れか一方又は両方を入力端子とし、出力信号を前記第3のトランジスタのドレイン電流から取り出す
ことを特徴とするフィルタ回路。 A current mirror circuit composed of field effect transistors,
Including first, second, and third transistors (M1, M2, M3) having the same channel polarity;
The drain of the first transistor is connected to the gate of a second transistor functioning as a source follower;
A source of the second transistor is connected to a gate of the first transistor and a gate of the third transistor;
The first transistor (C1) and the second capacitor (C2) are connected to the drain and gate of the first transistor, respectively.
Bias current supply means (7) for supplying a bias current to each of the first and second transistors;
One of or both of the drain and gate of the first transistor is used as an input terminal, and an output signal is extracted from the drain current of the third transistor. - 前記請求項3記載のフィルタ回路において、
ドレインからゲートへの帰還ループを有する第4のトランジスタ(M13)と、
前記第4のトランジスタにバイアス電流を供給するバイアス電流供給手段(14)とを更に備え、
前記第1の容量素子は、前記第4のトランジスタのゲートと前記第1のトランジスタのドレインとの間に接続され、
前記第4のトランジスタのゲートを入力端子とし、出力信号を前記第3のトランジスタのドレイン電流から取り出す
ことを特徴とするフィルタ回路。 The filter circuit according to claim 3, wherein
A fourth transistor (M13) having a feedback loop from the drain to the gate;
Bias current supply means (14) for supplying a bias current to the fourth transistor;
The first capacitive element is connected between a gate of the fourth transistor and a drain of the first transistor,
A filter circuit, wherein the gate of the fourth transistor is used as an input terminal, and an output signal is extracted from the drain current of the third transistor. - 前記請求項3記載のフィルタ回路において、
ドレインからゲートへの帰還ループを有する第4のトランジスタ(M13)と、
前記第4のトランジスタにバイアス電流を供給するバイアス電流供給手段(14)とを更に備え、
前記第2の容量素子は、前記第4のトランジスタのゲートと前記第1のトランジスタのゲートとの間に接続され、
前記第4のトランジスタのゲートを入力端子とし、出力信号を前記第3のトランジスタのドレイン電流から取り出す
ことを特徴とするフィルタ回路。 The filter circuit according to claim 3, wherein
A fourth transistor (M13) having a feedback loop from the drain to the gate;
Bias current supply means (14) for supplying a bias current to the fourth transistor;
The second capacitor element is connected between a gate of the fourth transistor and a gate of the first transistor,
A filter circuit, wherein the gate of the fourth transistor is used as an input terminal, and an output signal is extracted from the drain current of the third transistor. - 前記請求項1~5の何れか1項に記載のフィルタ回路において、
前記第1、第2、第3のトランジスタ及び前記第4のトランジスタの各々に供給するバイアス電流は、可変である
ことを特徴とするフィルタ回路。 The filter circuit according to any one of claims 1 to 5,
The filter circuit, wherein a bias current supplied to each of the first, second, third transistor and the fourth transistor is variable. - 前記請求項6記載のフィルタ回路において、
前記可変バイアス電流は、トランスコンダクタンス調整回路(29)から供給され、
前記トランスコンダクタンス調整回路は、
ソースが共通接続された第9、第10のトランジスタ(M106、M107)と、
前記第9、第10のトランジスタのゲートに電位差を発生させる電位差発生回路(21)と、
前記第9、第10のトランジスタのドレイン電流の差を出力する差電流生成回路(22)と、
前記差電流生成回路の出力電流値と基準電流源(24)との出力電流値が一致するように制御電圧を生成し、この制御電圧を前記第9、第10のトランジスタのゲートに帰還する帰還手段(31)と、
前記帰還電圧を電圧―電流変換する電圧―電流変換器(25)とを備え、
前記第1、第2、第3のトランジスタ及び前記第4のトランジスタの各々に供給するバイアス電流は、前記電圧―電流変換器の出力のカレントミラー出力として供給される
ことを特徴とするフィルタ回路。 The filter circuit according to claim 6, wherein
The variable bias current is supplied from a transconductance adjustment circuit (29),
The transconductance adjustment circuit is:
Ninth and tenth transistors (M106, M107) whose sources are commonly connected;
A potential difference generating circuit (21) for generating a potential difference at the gates of the ninth and tenth transistors;
A difference current generation circuit (22) for outputting a difference between drain currents of the ninth and tenth transistors;
The control voltage is generated so that the output current value of the difference current generation circuit and the output current value of the reference current source (24) coincide, and the control voltage is fed back to the gates of the ninth and tenth transistors. Means (31);
A voltage-current converter (25) for converting the feedback voltage into voltage-current,
A filter circuit, wherein a bias current supplied to each of the first, second, third transistor and the fourth transistor is supplied as a current mirror output of an output of the voltage-current converter. - 前記請求項6記載のフィルタ回路において、
前記可変バイアス電流は、トランスコンダクタンス調整回路(29)から供給され、
前記トランスコンダクタンス調整回路は、
第5、第6、第7及び第8のトランジスタ(M101、M102、M103、M104)で構成されるトランスリニアループ回路(32)を含み、
前記第7のトランジスタと前記第8のトランジスタの各々に流れる電流を数倍して前記第5及び第6のトランジスタに供給する増幅手段(26)と、
前記第7のトランジスタのバイアス電流を供給する電流源回路(33)とを備え、
前記第8のトランジスタに流れる電流のカレントミラー出力が前記第1、第2、第3のトランジスタ及び前記第4のトランジスタのバイアス電流となるように接続された
ことを特徴とするフィルタ回路。 The filter circuit according to claim 6, wherein
The variable bias current is supplied from a transconductance adjustment circuit (29),
The transconductance adjustment circuit is:
Including a translinear loop circuit (32) composed of fifth, sixth, seventh and eighth transistors (M101, M102, M103, M104);
Amplifying means (26) for multiplying the current flowing through each of the seventh transistor and the eighth transistor several times and supplying the current to the fifth and sixth transistors;
A current source circuit (33) for supplying a bias current of the seventh transistor,
A filter circuit, wherein a current mirror output of a current flowing through the eighth transistor is connected so as to be a bias current of the first, second, third transistor, and fourth transistor. - 前記請求項8記載のフィルタ回路において、
前記第7のトランジスタのバイアス電流を供給する電流源回路(33)は、
ソースが共通接続された第9、第10のトランジスタ(M106、M107)と、
前記第9、第10のトランジスタのゲートに電位差を発生させ、前記第9、第10のトランジスタのゲート電圧の平均電圧が第11のトランジスタ(M105)のゲートに印加されるよう接続された電位差発生回路(21)と、
前記第9、第10のトランジスタの各々に流れるドレイン電流を加算する加算手段(34)と、
前記第11のトランジスタに流れるドレイン電流を2倍する増幅手段(28)とを備え、
前記第9、第10のトランジスタのドレイン電流の加算値から前記第11のトランジスタに流れるドレイン電流を2倍した電流を引き算した電流が、前記第1、第2、第3のトランジスタ及び前記第4のトランジスタのバイアス電流となる
ことを特徴とするフィルタ回路。 9. The filter circuit according to claim 8, wherein
A current source circuit (33) for supplying a bias current of the seventh transistor includes:
Ninth and tenth transistors (M106, M107) whose sources are commonly connected;
A potential difference is generated by generating a potential difference between the gates of the ninth and tenth transistors, and an average voltage of the gate voltages of the ninth and tenth transistors is applied to the gate of the eleventh transistor (M105). A circuit (21);
Adding means (34) for adding drain currents flowing through the ninth and tenth transistors;
Amplifying means (28) for doubling the drain current flowing in the eleventh transistor;
A current obtained by subtracting a current obtained by doubling the drain current flowing through the eleventh transistor from the sum of the drain currents of the ninth and tenth transistors is the first, second, third transistor, and fourth A filter circuit characterized by having a bias current of the transistor. - 請求項1~9の何れか1項に記載のフィルタ回路を信号処理経路に備えた
ことを特徴とする光ディスク装置。 An optical disc apparatus comprising the filter circuit according to any one of claims 1 to 9 in a signal processing path.
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JPH09261004A (en) * | 1996-03-19 | 1997-10-03 | Hitachi Ltd | Integrated filter circuit |
JP2000514980A (en) * | 1996-07-19 | 2000-11-07 | テレフオンアクチーボラゲツト エル エム エリクソン(パブル) | Method and apparatus for continuous time filtering in a digital CMOS process |
JP2002299971A (en) * | 2001-03-28 | 2002-10-11 | Council Scient Ind Res | Simulated circuit layout for low voltage, low power and high performance type ii current conveyor |
JP2005094091A (en) * | 2003-09-12 | 2005-04-07 | Sony Corp | Transconductance adjustment circuit |
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US7049882B2 (en) * | 2004-02-03 | 2006-05-23 | Broadcom Corporation | Transmitter IF section and method enabling IF output signal amplitude that is less sensitive to process, voltage, and temperature |
US7298221B2 (en) * | 2005-02-22 | 2007-11-20 | Integrated Device Technology, Inc. | Phase-locked loop circuits with current mode loop filters |
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2010
- 2010-02-09 WO PCT/JP2010/000798 patent/WO2011004512A1/en active Application Filing
- 2010-07-06 WO PCT/JP2010/004421 patent/WO2011004591A1/en active Application Filing
- 2010-07-06 JP JP2011521818A patent/JP5635506B2/en not_active Expired - Fee Related
- 2010-07-06 CN CN2010800306021A patent/CN102474240A/en active Pending
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2011
- 2011-12-28 US US13/338,787 patent/US8350619B2/en active Active
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JPH09261004A (en) * | 1996-03-19 | 1997-10-03 | Hitachi Ltd | Integrated filter circuit |
JP2000514980A (en) * | 1996-07-19 | 2000-11-07 | テレフオンアクチーボラゲツト エル エム エリクソン(パブル) | Method and apparatus for continuous time filtering in a digital CMOS process |
JP2002299971A (en) * | 2001-03-28 | 2002-10-11 | Council Scient Ind Res | Simulated circuit layout for low voltage, low power and high performance type ii current conveyor |
JP2005094091A (en) * | 2003-09-12 | 2005-04-07 | Sony Corp | Transconductance adjustment circuit |
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Title |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104092360A (en) * | 2014-06-30 | 2014-10-08 | 成都芯源系统有限公司 | Transconductance adjusting circuit, transconductance error amplifying unit and switching power converter |
Also Published As
Publication number | Publication date |
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US20120098574A1 (en) | 2012-04-26 |
WO2011004512A1 (en) | 2011-01-13 |
CN102474240A (en) | 2012-05-23 |
US8350619B2 (en) | 2013-01-08 |
JP5635506B2 (en) | 2014-12-03 |
JPWO2011004591A1 (en) | 2012-12-20 |
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