JP2006314059A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To relax operation frequency band restrictions, by enabling removal of DC offset and gain control and raise the cut-off frequency. <P>SOLUTION: A semiconductor device has an input terminal 101; and a CMOS inverter circuit 107 in which a bias current supply circuit 102, a PMOS transistor 103, an NMOS transistor 104 and an NMOS transistor 105 are connected in series between a VDD and the GND and which has a DC offset correction circuit 106 for supplying optimal voltage to the gate of the NMOS transistor 105. In the circuits, a capacitor 108 is connected between the connecting point of the drain of the PMOS transistor 103 and that of the NMOS transistor 104 and the connecting point of the drain of the NMOS transistor of a gate ground circuit 115 and the source of an NMOS transistor 114. The gate ground circuit 115 is constituted of an NMOS transistor 113, having control voltage Vg1 supplied to its gate; and an NMOS transistor 111, where the source to which control voltage Vg2 is supplied to a gate is connected to the drain of the NMOS transistor 113. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and in particular, a semiconductor that constitutes an amplifier circuit that removes a DC offset generated due to variations in element characteristics generated in each manufacturing process of an NMOS transistor and a PMOS transistor constituting a CMOS and controls gain. Relates to the device.

  2. Description of the Related Art In recent years, CMOS integrated circuits have come to be used greatly in semiconductor devices provided in digital devices in accordance with the increase in digital device manufacturing accompanying the advancement of digital signal processing technology. However, high-frequency signals, video signals, audio signals, etc. may be easier to process as analog signals, and in order to realize A / D conversion circuits, D / A conversion circuits, clock oscillation circuits, etc., analog signals Processing is required.

  An amplifier circuit using a CMOS inverter circuit is suitable for the above-described analog signal processing circuit because high gain performance can be obtained with a simple configuration. However, in order to use the output DC bias in an optimum state, it is necessary that the operating parameters such as the threshold voltage and saturation current of the NMOS transistor and the PMOS transistor constituting the CMOS inverter circuit are completely the same. It is impossible to make the operating parameters of the PMOS transistors completely coincide with each other, and it is necessary to devise a circuit.

  Patent Document 1 discloses an example of an amplifier circuit that can set an output DC bias of a CMOS inverter circuit to an optimum bias state. FIG. 12 shows a circuit diagram of the amplifier circuit disclosed in Patent Document 1. This amplifying circuit can control the operating current flowing in the NMOS transistor 2 and the PMOS transistor 3 constituting the CMOS inverter by the control voltage VC23 which gives the operating current of the NMOS transistor and the PMOS transistor CMOS inverter circuit to the gate of the PMOS transistor 21. it can. Since the operating parameters such as the threshold voltage and the saturation current of the NMOS transistor 2 and the PMOS transistor 3 do not coincide with each other due to manufacturing variations, the optimum output DC bias of the CMOS inverter circuits 22, 15, 16, and 17 having the same shape is obtained. A DC offset which is an error from a bias state (for example, an intermediate voltage between the GND voltage and the VDD voltage) is detected, the gate voltage of the NMOS transistor 17 is set so as to minimize this, and this voltage is set to the previous CMOS inverter 2. , 3, 21, and 13 are applied to the gate voltage of the NMOS transistor 13 so that the output DC bias of the CMOS inverters 2, 3, 21, and 13 is in an optimum bias state.

Japanese Patent No. 3613232

  In the example of the amplifier circuit disclosed in Patent Document 1, the gain of the amplifier can be adjusted by setting the output bias potential to an optimum value and making the bias current variable. Need to be reduced. If the gain is decreased when the current value of the input signal is large, the bias current decreases and the distortion of the output signal increases. Therefore, when used in an amplifier of an RF system, characteristic deterioration such as deterioration of intermodulation characteristics occurs. Is concerned. In addition, when a large amount of operating current is supplied in order to reduce noise and distortion, it is necessary to increase the size of the MOS transistor to be configured, and parasitic capacitance increases. When the parasitic capacitance is increased, the cutoff frequency of the LPF constituted by the parasitic capacitance and the load resistance is reduced, and as a result, the usable frequency band is limited.

  Therefore, the present invention has been proposed in view of the above-described conventional situation, and an amplifier circuit that can remove a DC offset and enable gain control, and can increase the cut-off frequency and relax the operating frequency band limitation. An object of the present invention is to provide a semiconductor device.

  In order to achieve the above-described object, a semiconductor device according to the present invention is connected to an input terminal to which an AC signal voltage is input, a PMOS transistor, a first NMOS transistor, and a power supply voltage side of the PMOS transistor. DC offset correction that makes the gate voltage value of the second NMOS transistor variable so as to remove the DC offset, the bias current supply circuit, the second NMOS transistor connected to the ground side of the first NMOS transistor A CMOS inverter circuit having a circuit, a third NMOS transistor to which the first control voltage is supplied to the gate, a second control voltage to the gate, and a source connected to the drain of the third NMOS transistor A grounded gate circuit having a fourth NMOS transistor and a PMOS transistor; And a capacitor connected between a connection point of the drain of the first NMOS transistor and a connection point of the drain of the third NMOS transistor and the source of the fourth NMOS transistor, and a drain of the fourth NMOS transistor And a load circuit connected between the power supply voltage, a drain of the fourth NMOS transistor, and an output terminal connected to the connection point of the load circuit, the conductance of the CMOS inverter circuit and the conductance of the gate ground circuit are independent. The gain control is possible by setting the output impedance, and the output frequency of the CMOS inverter is set lower by the conductance value of the grounded gate circuit, so that the cutoff frequency determined by the parasitic capacitance and the output impedance is increased and the operating frequency is increased. Bandwidth limitation can be relaxed.

  In the CMOS inverter circuit, the bias current supply circuit is connected to the ground side of the first NMOS transistor, the second PMOS transistor is connected to the power supply voltage side of the first PMOS transistor, and the DC offset correction circuit is the second PMOS. A configuration in which the gate voltage value of the transistor can be made variable is also possible.

  The grounded gate circuit includes a third PMOS transistor to which the first control voltage is supplied to the gate, and a fourth PMOS transistor to which the second control voltage is supplied to the gate and the source is connected to the drain of the third PMOS transistor. The PMOS transistor can also be configured.

  The semiconductor device according to the present invention can perform gain control by setting the conductance of the CMOS inverter circuit and the conductance of the gate ground circuit independently of each other. This also prevents degradation of the intermodulation characteristics when used in an amplifier circuit of an RF system without increasing the distortion of the output signal even when the gain is reduced at the time of a large input signal. Also, by setting the output impedance of the CMOS inverter circuit low according to the conductance value of the grounded gate circuit, the cutoff frequency determined by the parasitic capacitance and the output impedance can be increased, and the operating frequency band limitation can be relaxed.

  In addition, the semiconductor device according to the present invention is configured such that the bias current of the grounded gate circuit and the current of the load means are automatically controlled by the DC offset correction means as a variable type using a MOS transistor as the load means, so that the bias of the output terminal is predetermined. The value is determined and an optimum operation can be realized. Also, by controlling the bias current of the gate grounding circuit and the current value of the load means as a variable load using a MOS transistor as the load means, the bias current at the output terminal is set to a predetermined value, thereby realizing an optimum operation. be able to.

  Hereinafter, specific examples of the present invention will be described in detail with reference to the drawings. FIG. 1 to FIG. 11 are diagrams for explaining a semiconductor device that constitutes an amplifier circuit that removes a DC offset, enables gain control, raises a cutoff frequency, and relaxes an operating frequency band limitation.

  As shown in FIG. 1, a semiconductor device 100 shown as a first specific example of the present invention includes an input terminal 101 to which an AC signal voltage Vin is input, a PMOS transistor 103, a first NMOS transistor 104, and a PMOS transistor. 103, a bias current supply circuit 102 connected to the power supply voltage (hereinafter referred to as VDD) side, and a second NMOS transistor 105 connected to the ground (hereinafter referred to as GND) side of the first NMOS transistor 104. And a CMOS inverter circuit 107 having a DC offset correction function including a DC offset correction circuit 106 that supplies an optimum voltage to the gate of the second NMOS transistor 105.

  In the semiconductor device 100, the third NMOS transistor 113 is supplied with the control voltage Vg1 from the input terminal 114 to the gate, and the control voltage Vg2 is supplied from the input terminal 112 to the gate, and the source is the drain of the third NMOS transistor 113. A grounded gate circuit 115 including a fourth NMOS transistor 111 connected to the first NMOS transistor 111.

  The semiconductor device 100 includes a connection point between the drain of the PMOS transistor 103 and the drain of the first NMOS transistor 104, and a connection point between the drain of the third NMOS transistor 113 and the source of the fourth NMOS transistor 111. A capacitor 108 is connected. In addition, a load circuit 109 is connected between the drain of the fourth NMOS transistor 111 and VDD, and an output terminal 110 is connected to a connection point between the drain of the fourth NMOS transistor 111 and the load circuit 109 to output voltage. Vout is output.

  The load circuit 109 can use an active load such as a MOS transistor in addition to a passive element such as a resistor. In this case, in the CMOS inverter circuit 107, the optimum bias current Id1 is set by the bias current supply circuit 102, and the optimum voltage is set by the DC offset correction circuit 106 at the gate of the second NMOS transistor 105. Vn1 set in the DC offset correction circuit 106 satisfies the condition of the following expression (1).

  The output AC current i0 from the connection point between the drain of the PMOS transistor 103 and the drain of the first NMOS transistor 104 is expressed by the following equation (2), which can be controlled by the bias current Id1. Recognize.

  i 0 is supplied to the source of the fourth NMOS transistor 111 and the drain of the third NMOS transistor 113 through the capacitor 108. i0 is shunted by the source conductance gm2 of the fourth NMOS transistor 111 and the drain conductance gd1 of the third NMOS transistor 113 determined by the bias current Id2 of the fourth NMOS transistor 111 and the third NMOS transistor 113, and is loaded into the load circuit. 109 and output from the output terminal 110 as the voltage Vout.

  Here, the source of the fourth NMOS transistor 111 and the drain of the third NMOS transistor 113 are controlled so that the fourth NMOS transistor 111 operates in the saturation region and the third NMOS transistor 113 operates in the triode region. The potential Vs at the connection point is determined so as to satisfy the voltage condition of the following expression (3).

  gm2 and gd1 are controlled by the following expression (4) by the control voltages Vg1 and Vg2.

  Thus, the semiconductor device 100 enables gain control by setting the conductance of the CMOS inverter circuit 107 and the conductance of the gate ground circuit 115 independently, and the output impedance of the CMOS inverter is set to the conductance value of the gate ground circuit. Accordingly, the amplifier circuit is configured to increase the cut-off frequency determined by the parasitic capacitance and the output impedance by setting the value lower, thereby relaxing the operating frequency band limitation.

  Note that the bias current supply circuit 102 is connected to the VDD side of the CMOS inverter circuit 107 and the second NMOS transistor 105 and the DC offset correction circuit 106 are connected to the GND side. Conversely, the bias current supply is supplied to the GND side. The same operation can be realized by connecting the circuit 102 and connecting the PMOS transistor 103 and the DC offset correction circuit 106 to the VDD side. In the semiconductor device 100, the grounded gate circuit 115 includes two NMOS transistors, and the load circuit 109 is inserted between the NMOS transistor and the power supply Vdd. The grounded gate circuit 115 includes two PMOS transistors. However, the same operation can be realized by connecting a load circuit between this and GND.

  Next, an operation in the case of a small signal in the semiconductor device 100 shown as the first specific example will be described with reference to FIG.

  In the CMOS inverter circuit 107, the AC signal voltage Vin at the input terminal 101 is converted into a current i 0 by a conversion coefficient gm 0 and supplied to the source of the fourth NMOS transistor 111 and the drain of the third NMOS transistor 113 via the capacitor 108. Is done.

  In the third NMOS transistor 113, i0 is an AC current i1 determined by an AC voltage vs generated at the connection point between gd1, the source of the fourth NMOS transistor 111, and the drain of the third NMOS transistor 113, and the fourth NMOS transistor 113. In the transistor 111, the current is shunted as shown in the following equation (5) by the alternating current i2 determined by gm2 and vs.

  Since i2 flows through the load circuit 109 and the output AC voltage Vout is generated, if the conductance of the load circuit 109 is gL, the input / output gain G (Gain in the equation) is determined by the following equation (6). Since not only gm0 but also gd1 and gm2 can be controlled by the control voltages Vg1 and Vg2 shown in the equation (4), the input / output gain can be controlled.

  Therefore, the semiconductor device 100 can perform gain control by setting the conductance of the CMOS inverter circuit and the conductance of the gate ground circuit 115 independently. For this reason, even if the gain is reduced for a large input signal, there is no increase in distortion of the output signal, and deterioration of the cross modulation characteristics when used in an amplifier circuit of an RF system can be avoided.

  In addition, in the semiconductor device 100, even if a large operating current of the CMOS inverter is passed to reduce noise and distortion, the cut-off frequency of the LPF constituted by the load resistance and the parasitic capacitance is reduced, and the usable frequency band. There is no risk of being restricted. The cutoff frequency when the resistance value Rs at the output point of the CMOS inverter circuit 107 and the parasitic capacitance is Cs is determined by the following equation (7).

  According to Expression (7), the cutoff frequency can be set regardless of the load circuit 109, and therefore, the reduction in the cutoff frequency of the LPF can be mitigated and the limitation of the frequency band can be avoided.

  As in the case of a small signal, the semiconductor device 100 has a bias current supply circuit 102 connected to the VDD side of the CMOS inverter circuit 107 and a second NMOS transistor 105 and a DC offset correction circuit 106 connected to the GND side. However, conversely, the same operation can be realized by connecting the bias current supply circuit 102 to the GND side and connecting the PMOS transistor 103 and the DC offset correction circuit 106 to the VDD side. In the semiconductor device 100, the grounded gate circuit 115 includes two NMOS transistors, and the load circuit 109 is inserted between the NMOS transistor and the power supply Vdd. The grounded gate circuit 115 includes two PMOS transistors. However, the same operation can be realized by connecting a load circuit between this and GND.

  Next, a semiconductor device 200 shown as a second specific example of the present invention will be described with reference to FIG. In the semiconductor device 1 shown in FIG. 1, the bias current supply circuit 102 is connected to the VDD side of the CMOS inverter circuit 107 and the NMOS transistor and the DC offset correction circuit 106 are connected to the GND side. The same action is realized by connecting a bias current supply circuit to the GND side and connecting a PMOS transistor and a DC offset correction circuit to the VDD side. 3 having the same functions and effects as those of the semiconductor device 100 described above are denoted by the same reference numerals and detailed description thereof is omitted.

  The semiconductor device 200 includes an input terminal 101 to which an AC signal voltage Vin is input, a PMOS transistor 103 configured as a CMOS inverter, a first NMOS transistor 104, and a bias current connected to the GND side of the first NMOS transistor 104. CMOS inverter circuit including a supply circuit 302, a PMOS transistor 305 connected to the VDD side of the PMOS transistor 103, and a DC offset correction circuit 306 for supplying an optimum voltage to the gate of the PMOS transistor 305 and having a DC offset correction function 307.

  In the semiconductor device 200, the third NMOS transistor 113 is supplied with the control voltage Vg1 from the input terminal 114 to the gate, and the control voltage Vg2 is supplied from the input terminal 112 to the gate, and the source is the drain of the third NMOS transistor 113. A gate ground circuit 115 including a fourth NMOS transistor 111 connected to the first NMOS transistor 111.

  The semiconductor device 200 includes a connection point between the drain of the PMOS transistor 103 and the drain of the first NMOS transistor 104, and a connection point between the drain of the third NMOS transistor 113 and the source of the fourth NMOS transistor 111. A capacitor 108 is connected. In addition, a load circuit 109 is connected between the drain of the fourth NMOS transistor 111 and VDD, and an output terminal 110 is connected to a connection point between the drain of the fourth NMOS transistor 111 and the load circuit 109 to output voltage. Vout is output.

  As described above, the semiconductor device 200 is characterized in that the bias current supply circuit 302 is connected to the GND side, and the PMOS transistor 104 and the DC offset correction circuit 306 are connected to the VDD side.

  The semiconductor device 200 enables gain control by setting the conductance of the CMOS inverter circuit 307 and the conductance of the gate ground circuit 115 independently, and the output impedance of the CMOS inverter circuit 307 can be controlled by the conductance of the gate ground circuit 115. By setting the value lower depending on the value, an amplifier circuit is configured that can increase the cutoff frequency determined by the parasitic capacitance and the output impedance and relax the operating frequency band limitation.

  Next, a third specific example of the present invention will be described with reference to FIG. A semiconductor device 300 shown as the third specific example is similar in that a load circuit is connected to the GND side of two PMOS transistors to which a control voltage is supplied with the gate ground circuit 115 in the semiconductor device 100 shown in FIG. The action is realized.

  The semiconductor device 300 has a bias current supply connected to the VDD side of the input terminal 101 to which the AC signal voltage Vin is input, the first PMOS transistor 103, the first NMOS transistor 104, and the first PMOS transistor 103. The circuit 102, a second NMOS transistor 105 connected to the GND side of the first NMOS transistor 104, and a DC offset correction circuit 106 for supplying an optimum voltage to the gate of the second NMOS transistor 105 are provided. A CMOS inverter circuit 107 having a correction function is included.

  The semiconductor device 300 has a third PMOS transistor 413 to which the control voltage Vg1 is supplied from the input terminal 414 to the gate, and a source from which the control voltage Vg2 is supplied to the gate from the input terminal 412 and the source is the drain of the third PMOS transistor 413. And a fourth PMOS transistor 411 connected to the gate grounding circuit 415.

  The semiconductor device 300 includes a capacitor 108 between a connection point of the drain of the first PMOS transistor 103 and the drain of the first NMOS transistor 104 and a connection point of the third PMOS transistor 413 and the fourth PMOS transistor 411. Is connected. In addition, a load circuit 409 is connected between the drain of the fourth PMOS transistor 411 and GND, and an output terminal 410 is connected to a connection point between the drain of the fourth PMOS transistor 411 and the load circuit 409. Vout is output.

  As described above, the semiconductor device 300 is configured such that the conductance of the CMOS inverter circuit 107 and the conductance of the gate ground circuit 415 are set independently, thereby enabling gain control. Further, by setting the output impedance of the CMOS inverter circuit 107 low by the conductance value of the grounded gate circuit 415, an amplification circuit that can increase the cutoff frequency determined from the parasitic capacitance and the output impedance and relax the operating frequency band limitation. Can be configured.

  Next, a fourth specific example of the present invention will be described with reference to FIG. In the semiconductor device 100 shown in FIG. 1, the CMOS inverter circuit 107 is configured by connecting the bias current supply circuit 102 to the VDD side and connecting the NMOS transistor and the DC offset correction circuit 106 to the GND side. On the contrary, the semiconductor device 400 shown as a specific example is characterized in that a bias current supply circuit is connected to the GND side, and a PMOS transistor and a DC offset correction circuit are connected to the VDD side. In addition, the gate grounding circuit is composed of two PMOS transistors 413 and 414 whose gates are supplied with control voltages Vg1 and Vg2, and the load circuit 409 is connected to the GND side of the gate grounding circuit to achieve the same operation. It is a thing.

  The semiconductor device 400 has a bias current supply connected to the input terminal 101 to which the AC signal voltage Vin is input, the first PMOS transistor 103, the first NMOS transistor 104, and the GND side of the first NMOS transistor 104. A DC offset includes a circuit 302, a second PMOS transistor 305 connected to the VDD side of the first PMOS transistor 103, and a DC offset correction circuit 306 that supplies an optimum voltage to the gate of the second PMOS transistor 305. A CMOS inverter circuit 307 having a correction function is provided.

  In the semiconductor device 400, the third PMOS transistor 413 is supplied with the control voltage Vg1 from the input terminal 414 to the gate, and the source is supplied with the control voltage Vg2 from the input terminal 412 to the gate, and the source is the drain of the third PMOS transistor 413. And a fourth PMOS transistor 411 connected to the gate grounding circuit 415.

  The semiconductor device 400 includes a capacitor 108 between a connection point of the drain of the first PMOS transistor 103 and the drain of the first NMOS transistor 104 and a connection point of the third PMOS transistor 413 and the fourth PMOS transistor 411. Is connected. In addition, a load circuit 409 is connected between the drain of the fourth PMOS transistor 411 and GND, and an output terminal 410 is connected to a connection point between the drain of the fourth PMOS transistor 411 and the load circuit 409. Vout is output.

  As described above, the semiconductor device 400 is configured such that the conductance of the CMOS inverter circuit 307 and the conductance of the gate ground circuit 415 are set independently, thereby enabling gain control. In addition, by setting the output impedance of the CMOS inverter circuit 307 to be low by the conductance value of the gate ground circuit 415, an amplifier circuit that can increase the cutoff frequency determined from the parasitic capacitance and the output impedance and relax the operating frequency band limitation. Can be configured.

  Next, a fifth specific example of the present invention will be described with reference to FIG. This semiconductor device 500 enables voltage control of the bias current supply circuit 102 in the semiconductor device 100 shown in FIG. 1 using a PMOS transistor and a control voltage, and the DC offset correction circuit 106 shown in FIG. This is an example constituted by an amplifier.

  The semiconductor device 500 includes an input terminal 101 to which an AC signal voltage Vin is input, a first PMOS transistor 103, a first NMOS transistor 104, and a second NMOS connected to the GND side of the first NMOS transistor 104. A CMOS inverter circuit 107 having a DC offset correction function including a DC offset correction circuit 106 having a high frequency elimination circuit and an operational amplifier for the purpose of supplying an optimum voltage to the gate of the NMOS transistor 105 and the second NMOS transistor 105. It has. Here, the bias current supply circuit 102 includes a second PMOS transistor 617, a gate-VDD voltage 616.

  In addition, the semiconductor device 500 includes a third NMOS transistor 113 to which the control voltage Vg1 is supplied from the input terminal 114 to the gate, and a source from which the control voltage Vg2 is supplied to the gate from the input terminal 112. The source is the drain of the third NMOS transistor 113. And a fourth NMOS transistor 111 connected to the gate ground circuit 115.

  The semiconductor device 500 includes a connection point between the drain of the first PMOS transistor 103 and the drain of the first NMOS transistor 104, a connection point between the drain of the third NMOS transistor 113 and the source of the fourth NMOS transistor 111. A capacitor 108 is connected between the two. A load circuit 109 is connected between the drain of the fourth NMOS transistor 111 and VDD, and an output terminal 110 is connected to a connection point between the drain of the fourth NMOS transistor 111 and the load circuit 109 to output voltage. Vout is output.

  Here, the bias current supply circuit 102 applied to the semiconductor device 500 will be described.

  The bias current supply circuit 102 has a circuit configuration in which a control voltage 616 is applied to the gate of the second PMOS transistor 617 whose source is connected to VDD. At this time, assuming that the source-gate voltage of the second PMOS transistor 617 is Vc1, the supply bias current Id1 is determined as shown in the following equation (8). A current proportional to the square of the difference between Vc1 and the threshold voltage is supplied.

  The bias current supply circuit 102 applied to the semiconductor device 500 is configured using a PMOS transistor to be applied to the configuration based on the semiconductor device 100 illustrated in FIG. 1, but if an NMOS transistor is used, the semiconductor illustrated in FIG. The present invention can be applied to the circuit configuration based on the device 200 and the semiconductor device 400 shown in FIG.

  Next, the DC offset correction circuit 106 applied to the semiconductor device 500 will be described.

  The DC offset correction circuit 106 connects the output of the CMOS inverter circuit 107 to a low-pass filter (LPF) composed of a resistor 626 (R1 in FIG. 6) and a capacitor 625 (C1 in FIG. 6) to remove high-frequency components. To the non-inverting input of the operational amplifier 620. The reference voltage 624 (Vref in FIG. 6) is connected to the inverting input of the operational amplifier 620, and the output of the operational amplifier 620 is supplied to the gate of the second NMOS transistor 105 of the CMOS inverter circuit 107. The feedback loop 106 operates so as to minimize the DC offset, and the correction voltage Vn1 is set. Here, the capacitor 618 (C2 in FIG. 6) connected between the output of the operational amplifier 620 and GND functions to stabilize the feedback operation. If the feedback operation is stable, the capacitor 618 is deleted. May be.

  Note that the DC offset correction circuit 106 applied to the semiconductor device 500 has been described as a configuration applicable to a circuit based on the semiconductor device 100 shown in FIG. 1, but if the input polarity of the operational amplifier 620 is reversed, FIG. The present invention can be applied to a circuit configuration based on the semiconductor device 200 shown in FIG. 5 and the semiconductor device 400 shown in FIG.

  As described above, the semiconductor device 500 enables gain control by setting the conductance of the CMOS inverter circuit 107 and the conductance of the gate ground circuit 115 independently. In addition, by setting the output impedance of the CMOS inverter circuit 107 low by the conductance value of the grounded gate circuit 115, an amplifier circuit that can increase the cutoff frequency determined from the parasitic capacitance and the output impedance and relax the operating frequency band limitation. Can be configured.

  Next, a sixth example of the present invention will be described with reference to FIG. This semiconductor device 600 is an example in which the load circuit 109 in the semiconductor device 100 shown in FIG. 1 is voltage-controllable using a PMOS transistor and a control voltage.

  The semiconductor device 600 includes an input terminal 101 to which an AC signal voltage Vin is input, a PMOS transistor 103, a first NMOS transistor 104, a bias current supply circuit 102 connected to the VDD side of the PMOS transistor 103, a first A CMOS having a DC offset correction function, which includes a second NMOS transistor 105 connected to the GND side of the NMOS transistor 104 and a DC offset correction circuit 106 for supplying an optimum voltage to the gate of the second NMOS transistor 105. And an inverter circuit 107.

  In the semiconductor device 600, the third NMOS transistor 113 is supplied with the control voltage Vg1 from the input terminal 114 to the gate, and the source is supplied with the control voltage Vg2 from the input terminal 112 to the gate, and the source is the drain of the third NMOS transistor 113. And a fourth NMOS transistor 111 connected to the gate ground circuit 115.

  The semiconductor device 600 includes a connection point between the drain of the first PMOS transistor 103 and the drain of the first NMOS transistor 104, a connection point between the drain of the third NMOS transistor 113 and the source of the fourth NMOS transistor 111. A capacitor 108 is connected between the two.

  In the semiconductor device 600, an active load circuit is configured by the PMOS transistor 709 to which the control voltage Vg3 is supplied from the input terminal 710. An output terminal 110 is connected to a connection point between the drain of the fourth NMOS transistor 111 and the drain of the PMOS transistor 709, and an output voltage Vout is output.

  A bias current Id3 supplied from a load circuit applied to the semiconductor device 600 is determined by the following equation (9). Id3 is a value proportional to the square of the difference between the VDD voltage (Vdd in the equation), the control voltage Vg3, and the threshold voltage Vthp.

  In this load circuit, when Id2 and Id3 supplied from the grounded gate circuit 115 coincide with each other, the bias of the output terminal 110 is determined to be a predetermined value, and an optimum operation can be realized.

  As described above, the semiconductor device 600 has a circuit configuration in which the conductance of the CMOS inverter circuit 107 and the conductance of the gate ground circuit 115 are independently set, thereby enabling gain control. Further, by setting the output impedance of the CMOS inverter circuit 107 to be low by the conductance value of the grounded gate circuit 115, an amplifier circuit that can increase the cutoff frequency determined by the parasitic capacitance and the output impedance and relax the operating frequency band limitation. Can be configured.

  Next, a seventh example of the present invention will be described with reference to FIG. In the semiconductor device 700 shown in FIG. 7, Id2 supplied from the grounded gate circuit 115 and Id3 supplied from the PMOS transistor 709 constituting the load means are made to coincide with each other, and the bias of the output terminal 110 is predetermined. In this example, a second DC offset correction circuit 816 is added so that the control voltage Vg3 can be controlled so as to be fixed to a value.

  The semiconductor device 700 includes an input terminal 101 to which an AC signal voltage Vin is input, a PMOS transistor 103, a first NMOS transistor 104, a bias current supply circuit 102 connected to the Vdd side of the PMOS transistor 103, a first Having a DC offset correction function comprising a second NMOS transistor 105 connected to the GND side of the NMOS transistor 104 and a DC offset correction circuit 106 for supplying an optimum voltage to the gate of the second NMOS transistor 105. A CMOS inverter circuit 107 is provided.

  In the semiconductor device 700, the third NMOS transistor 113 is supplied with the control voltage Vg1 from the input terminal 114 to the gate, and the source is supplied with the control voltage Vg2 from the input terminal 112 to the gate, and the source is the drain of the third NMOS transistor 113. And a fourth NMOS transistor 111 connected to the gate ground circuit 115.

  The semiconductor device 700 includes a connection point between the drain of the first PMOS transistor 103 and the drain of the first NMOS transistor 104, a connection point between the drain of the third NMOS transistor 113 and the source of the fourth NMOS transistor 111. A capacitor 108 is connected between the two.

  In addition, the semiconductor device 700 includes load means using a PMOS transistor 709 to which the control voltage Vg3 from the DC offset correction circuit 816 is supplied to the gate, and a connection point between the drain of the fourth NMOS transistor 111 and the PMOS transistor 709. The output voltage Vout is output from the output terminal 110 connected to the.

  Note that the DC offset correction circuit 816 has a circuit configuration in which the DC offset detection point is set as the output terminal 110 and the control voltage Vg3 input from the input terminal 710 is controlled, so that the DC offset correction of the semiconductor device 500 illustrated in FIG. Circuit 106 can be applied.

  As described above, the semiconductor device 700 enables gain control by setting the conductance of the CMOS inverter circuit 107 and the conductance of the gate ground circuit 115 independently. In addition, by setting the output impedance of the CMOS inverter circuit 107 low according to the conductance value of the grounded gate circuit 115, an amplifier circuit that can increase the cutoff frequency determined by the parasitic capacitance and the output impedance and relax the operating frequency band limitation. Can be configured.

  Next, an eighth specific example of the present invention will be described with reference to FIG. In the semiconductor device 800 shown in FIG. 7, the Id2 supplied from the grounded gate circuit 115 and the Id3 supplied from the PMOS transistor 709 constituting the load means are matched with each other in the semiconductor device 600 shown in FIG. In this example, a second DC offset correction circuit 816 is added so that the control voltage Vg2 can be controlled so as to be fixed to a value.

  The semiconductor device 800 includes an input terminal 101 to which an AC signal voltage Vin is input, a PMOS transistor 103, a first NMOS transistor 104, a bias current supply circuit 102 connected to the VDD side of the PMOS transistor 103, a first A CMOS having a DC offset correction function, which includes a second NMOS transistor 105 connected to the GND side of the NMOS transistor 104 and a DC offset correction circuit 106 for supplying an optimum voltage to the gate of the second NMOS transistor 105. An inverter circuit 107 is included.

  In the semiconductor device 800, the third NMOS transistor 113 is supplied with the control voltage Vg1 from the input terminal 114 to the gate, and the control voltage Vg2 is supplied from the DC offset correction circuit 816 to the gate, and the source is the third NMOS transistor 113. A grounded gate circuit 115 including a fourth NMOS transistor 111 connected to the drain of the first NMOS transistor 111.

  The semiconductor device 800 includes a connection point between the drain of the first PMOS transistor 103 and the drain of the first NMOS transistor 104, a connection point between the drain of the third NMOS transistor 113 and the source of the fourth NMOS transistor 111. A capacitor 108 is connected between the two.

  The semiconductor device 800 includes a load unit using a PMOS transistor 709 to which a control voltage Vg3 is supplied to the gate from an input terminal 710, and is connected to a connection point between the drain of the fourth NMOS transistor 111 and the PMOS transistor 709. The output voltage Vout is output from the output terminal 110.

  As described above, the semiconductor device 800 enables gain control by setting the conductance of the CMOS inverter circuit 107 and the conductance of the gate ground circuit 115 independently. In addition, by setting the output impedance of the CMOS inverter circuit 107 low according to the conductance value of the grounded gate circuit 115, an amplifier circuit that can increase the cutoff frequency determined by the parasitic capacitance and the output impedance and relax the operating frequency band limitation. Can be configured.

  Note that the DC offset correction circuit 816 has a circuit configuration in which the DC offset correction point of the semiconductor device 500 shown in FIG. 6 is controlled by controlling the control voltage Vg2 input from the input terminal 112 using the DC offset detection point as the output terminal 110. Although the circuit 106 can be applied, it is not limited to this structure.

  Next, a ninth example of the present invention will be described with reference to FIG. In the semiconductor device 900 shown in FIG. 7, the Id2 supplied from the grounded gate circuit 115 and the Id3 supplied from the PMOS transistor 709 constituting the load means are made to coincide with each other, and the bias of the output terminal 110 is predetermined. In this example, a second DC offset correction circuit 816 is added so that the control voltage Vg1 can be controlled so as to be fixed to a value.

  The semiconductor device 900 includes an input terminal 101 to which an AC signal voltage Vin is input, a PMOS transistor 103, a first NMOS transistor 104, a bias current supply circuit 102 connected to the VDD side of the PMOS transistor 103, a first A CMOS having a DC offset correction function, which includes a second NMOS transistor 105 connected to the GND side of the NMOS transistor 104 and a DC offset correction circuit 106 for supplying an optimum voltage to the gate of the second NMOS transistor 105. An inverter circuit 107 is included.

  The semiconductor device 900 also includes a third NMOS transistor 113 and a fourth NMOS transistor 111 whose control voltage Vg2 is supplied from the input terminal 112 to the gate and whose source is connected to the drain of the third NMOS transistor 113. It has a gate grounding circuit 115 and is characterized in that a control voltage Vg1 is supplied to the third NMOS transistor 113 from the DC offset correction circuit 816 to the gate.

  The semiconductor device 900 includes a connection point between the drain of the first PMOS transistor 103 and the drain of the first NMOS transistor 104, a connection point between the drain of the third NMOS transistor 113 and the source of the fourth NMOS transistor 111. A capacitor 108 is connected between the two.

  In addition, the semiconductor device 900 includes a load unit using a PMOS transistor 709 to which the control voltage Vg3 is supplied to the gate from the input terminal 710, and is connected to a connection point between the drain of the fourth NMOS transistor 111 and the PMOS transistor 709. The output voltage Vout is output from the output terminal 110.

  As described above, the semiconductor device 900 enables gain control by setting the conductance of the CMOS inverter circuit 107 and the conductance of the gate ground circuit 115 independently. In addition, by setting the output impedance of the CMOS inverter circuit 107 low according to the conductance value of the grounded gate circuit 115, an amplifier circuit that can increase the cutoff frequency determined by the parasitic capacitance and the output impedance and relax the operating frequency band limitation. Can be configured.

  Note that, as a circuit configuration of the DC offset correction circuit 816, the DC offset correction point of the semiconductor device 500 shown in FIG. 6 is controlled by controlling the control voltage Vg1 input from the input terminal 114 with the DC offset detection point as the output terminal 110. Although the circuit 106 can be applied, it is not limited to this structure.

  Next, a tenth example of the present invention will be described with reference to FIG. In the semiconductor device 1000 shown in FIG. 7, the Id2 supplied from the grounded gate circuit 115 and the Id3 supplied from the PMOS transistor 709 constituting the load means are matched with each other in the semiconductor device 600 shown in FIG. In this example, the second DC offset correction circuit 816 is added so that the control voltage Vg1 and the control voltage Vg2 can be controlled simultaneously.

  The semiconductor device 1000 includes an input terminal 101 to which an AC signal voltage Vin is input, a PMOS transistor 103, a first NMOS transistor 104, a bias current supply circuit 102 connected to the VDD side of the PMOS transistor 103, a first A CMOS having a DC offset correction function, which includes a second NMOS transistor 105 connected to the GND side of the NMOS transistor 104 and a DC offset correction circuit 106 for supplying an optimum voltage to the gate of the second NMOS transistor 105. An inverter circuit 107 is included.

  In the semiconductor device 1000, the third NMOS transistor 113 to which the control voltage Vg1 is supplied from the DC offset correction circuit 816 to the gate, and the control voltage Vg2 from the DC offset correction circuit 816 to the gate and the source is the third NMOS transistor. It is characterized in that it has a grounded gate circuit 115 including a fourth NMOS transistor 111 connected to the drain of the transistor 113.

  The semiconductor device 1000 includes a connection point between the drain of the first PMOS transistor 103 and the drain of the first NMOS transistor 104, a connection point between the drain of the third NMOS transistor 113 and the source of the fourth NMOS transistor 111. A capacitor 108 is connected between the two.

  In addition, the semiconductor device 1000 includes load means using a PMOS transistor 709 whose gate is supplied with a control voltage Vg3 from an input terminal 710, and is connected to a connection point between the drain of the fourth NMOS transistor 111 and the PMOS transistor 709. The output voltage Vout is output from the output terminal 110.

  At this time, the control voltages Vg1 and Vg2 can be set as shown in the following equation (10). In particular, when K = 0, the control voltage Vg1 and the control voltage Vg2 are the same voltage.

  As described above, the semiconductor device 1000 enables gain control by setting the conductance of the CMOS inverter circuit 107 and the conductance of the gate ground circuit 115 independently. In addition, by setting the output impedance of the CMOS inverter circuit 107 low according to the conductance value of the grounded gate circuit 115, an amplifier circuit that can increase the cutoff frequency determined by the parasitic capacitance and the output impedance and relax the operating frequency band limitation. Can be configured.

  Note that the DC offset correction circuit 816 is configured such that the DC offset detection circuit 106 of the semiconductor device 500 shown in FIG. 6 is controlled by controlling the control voltage Vg1 and the control voltage Vg2 using the DC offset detection point as the output terminal 110. Although applicable, it is not limited to this structure.

1 is a circuit diagram illustrating a semiconductor device shown as a first specific example of the present invention; It is a circuit diagram explaining the case where a small signal flows in into the said semiconductor device. It is a circuit diagram explaining the semiconductor device shown as the 2nd example of this invention. It is a circuit diagram explaining the semiconductor device shown as the 3rd example of this invention. It is a circuit diagram explaining the semiconductor device shown as the 4th example of this invention. It is a circuit diagram explaining the semiconductor device shown as the 5th example of this invention. It is a circuit diagram explaining the semiconductor device shown as the 6th example of this invention. It is a circuit diagram explaining the semiconductor device shown as the 7th example of this invention. It is a circuit diagram explaining the semiconductor device shown as the 8th example of this invention. It is a circuit diagram explaining the semiconductor device shown as the 9th example of this invention. It is a circuit diagram explaining the semiconductor device shown as a 10th example of this invention. It is a circuit diagram explaining the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 101 Input terminal 102 Bias current supply circuit 103 PMOS transistor 104 First NMOS transistor 105 Second NMOS transistor 105 DC offset correction circuit 107 CMOS inverter circuit 108 Capacitor 109 Load circuit 110 output terminal, 111 fourth NMOS transistor, 112 input terminal, 113 third NMOS transistor, 114 input terminal, 115 gate ground circuit

Claims (15)

An input terminal to which an AC signal voltage is input;
A PMOS transistor, a first NMOS transistor, a bias current supply circuit connected to the power supply voltage side of the PMOS transistor, a second NMOS transistor connected to the ground side of the first NMOS transistor, and a DC offset A CMOS inverter circuit having a DC offset correction circuit that makes the gate voltage value of the second NMOS transistor variable so as to eliminate
A gate having a third NMOS transistor to which the first control voltage is supplied to the gate, and a fourth NMOS transistor to which the second control voltage is supplied to the gate and the source is connected to the drain of the third NMOS transistor A ground circuit;
A capacitor connected between a connection point of the drain of the PMOS transistor and the drain of the first NMOS transistor, and a connection point of the drain of the third NMOS transistor and the source of the fourth NMOS transistor;
A load circuit connected between the drain of the fourth NMOS transistor and a power supply voltage;
A drain of the fourth NMOS transistor and an output terminal connected to a connection point of the load circuit;
A semiconductor device characterized in that a conductance of the CMOS inverter circuit and a conductance of the grounded gate circuit are set independently.   2. The bias current supply circuit according to claim 1, further comprising: a second PMOS transistor having a source connected to a power supply voltage, and applying a third control voltage to a gate of the second PMOS transistor. Semiconductor device.   2. The semiconductor device according to claim 1, wherein the bias current supply circuit is connected to a power supply voltage side of the CMOS inverter circuit, and the second NMOS transistor and the DC offset correction circuit are connected to a ground side.   2. The semiconductor device according to claim 1, wherein the bias current supply circuit is connected to a ground side of the CMOS inverter circuit, and the PMOS transistor and the DC offset correction circuit are connected to a power supply voltage side.   The DC offset correction circuit includes a low-pass filter composed of a resistor and a capacitor, and an operational amplification means. The output of the CMOS inverter circuit is input to the low-pass filter, and the output of the low-pass filter is The operational amplifier is connected to a non-inverting input, a reference voltage is connected to the inverting input of the operational amplifier, and the output of the operational amplifier is supplied to the gate of the second NMOS transistor. The semiconductor device according to claim 1.   The grounded gate circuit includes a third NMOS transistor to which the first control voltage is supplied to the gate, and a second NMOS transistor to which the second control voltage is supplied to the gate and a source is connected to the drain of the third NMOS transistor. 2. The semiconductor device according to claim 1, wherein the load circuit is inserted between the third NMOS transistor and the fourth NMOS transistor and a power supply voltage. .   2. The semiconductor device according to claim 1, wherein the grounded gate circuit has two PMOS transistors, and the load circuit is inserted between the two PMOS transistors and the ground.   2. The semiconductor device according to claim 1, wherein the load circuit comprises a PMOS transistor whose gate is supplied with a third control voltage.   9. The semiconductor device according to claim 8, further comprising a DC offset correction circuit that makes the value of the first control voltage variable.   9. The semiconductor device according to claim 8, further comprising a DC offset correction circuit that makes the value of the second control voltage variable.   9. The semiconductor device according to claim 8, further comprising a DC offset correction circuit that makes the value of the third control voltage variable.   9. The semiconductor device according to claim 8, further comprising a DC offset correction circuit that makes the values of the second control voltage and the third control voltage variable. An input terminal to which an AC signal voltage is input;
A first PMOS transistor; a first NMOS transistor; a bias current supply circuit connected to the ground side of the first NMOS transistor; and a second PMOS transistor connected to the power supply voltage side of the first PMOS transistor. A CMOS inverter circuit having a PMOS transistor and a DC offset correction circuit that makes the gate voltage value of the second PMOS transistor variable;
A gate having a third NMOS transistor to which the first control voltage is supplied to the gate, and a fourth NMOS transistor to which the second control voltage is supplied to the gate and the source is connected to the drain of the third NMOS transistor A ground circuit;
A capacitor connected between a connection point of the drain of the PMOS transistor and the drain of the first NMOS transistor, and a connection point of the drain of the third NMOS transistor and the source of the fourth NMOS transistor;
A load circuit connected between the drain of the fourth NMOS transistor and a power supply voltage;
A drain of the fourth NMOS transistor and an output terminal connected to a connection point of the load circuit;
A semiconductor device characterized in that a conductance of the CMOS inverter circuit and a conductance of the grounded gate circuit are set independently. An input terminal to which an AC signal voltage is input;
A PMOS transistor, a first NMOS transistor, a bias current supply circuit connected to the power supply voltage side of the PMOS transistor, a second NMOS transistor connected to the ground side of the first NMOS transistor, and a DC offset A CMOS inverter circuit having a DC offset correction circuit that makes the gate voltage value of the second NMOS transistor variable so as to eliminate
A gate having a third PMOS transistor to which the first control voltage is supplied to the gate, and a fourth PMOS transistor to which the second control voltage is supplied to the gate and whose source is connected to the drain of the third PMOS transistor A ground circuit;
A capacitor connected between a connection point of the drain of the first PMOS transistor and the drain of the first NMOS transistor, and a connection point of the third PMOS transistor and the fourth PMOS transistor;
A load circuit connected between the drain of the fourth PMOS transistor and a power supply voltage;
A drain of the fourth PMOS transistor and an output terminal connected to a connection point of the load circuit;
A semiconductor device characterized in that a conductance of the CMOS inverter circuit and a conductance of the grounded gate circuit are set independently. An input terminal to which an AC signal voltage is input;
A first PMOS transistor; a first NMOS transistor; a bias current supply circuit connected to the ground side of the first NMOS transistor; and a second PMOS transistor connected to the power supply voltage side of the first PMOS transistor. A CMOS inverter circuit having a PMOS transistor and a DC offset correction circuit that makes the gate voltage value of the second PMOS transistor variable;
A gate having a third PMOS transistor to which the first control voltage is supplied to the gate, and a fourth PMOS transistor to which the second control voltage is supplied to the gate and whose source is connected to the drain of the third PMOS transistor A ground circuit;
A capacitor connected between a connection point of the drain of the first PMOS transistor and the drain of the first NMOS transistor, and a connection point of the third PMOS transistor and the fourth PMOS transistor;
A load circuit connected between the drain of the fourth PMOS transistor and a power supply voltage;
A drain of the fourth PMOS transistor and an output terminal connected to a connection point of the load circuit;
A semiconductor device characterized in that a conductance of the CMOS inverter circuit and a conductance of the grounded gate circuit are set independently.

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