KR101072465B1 - Operational Trans-conductance Amplifier Circuit - Google Patents

Abstract

The disclosed operational cross-conductance amplifying circuit is connected between a power supply terminal and a ground terminal to convert a first input voltage and a second input voltage into a current to amplify and amplify a main amplifier and a common mode voltage input to the main amplifier. And a common mode feedforward unit for generating a common mode current from the detected common mode voltage and providing it to the main amplifier.

OTA, linearity

Description

Operational Transconductance Amplifier Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly to an operational transconductance amplifier (OTA) circuit.

OTA circuit converts input voltage into proportional output current, amplifies and outputs it, and is applied to various fields such as an active filter, an analog / digital converter, an integrator, and the like.

Since the OTA is a voltage controlled current source (VCCS), the linearity of the amount of change of the current with respect to the voltage change is greatly limited due to the characteristics of the MOSFET constituting the OTA.

1 is a configuration diagram of a general OTA circuit, and FIG. 2 is a graph showing a linear section of a differential input.

More specifically, the OTA circuit shown in FIG. 1 is a differential input OTA circuit, and receives a differential input voltage V _id (see Equation 1) and outputs an output current I _o (see Equation 2). It can be seen that the linear section D of the present OTA circuit is limited as shown in FIG. 2.

[Equation 1]

[Equation 2]

Here, ΔV = V _GS -V _TH . In Equation 2, if the relationship between I _o and V _id is linear, the condition of Equation 3 must be satisfied. For example, if ΔV is 200 mV, V _id (max) is about 340 mV.

&Quot; (3) "

In addition, since the fixed bias current I _D (= 0.5 I _B ) flows in the morph transistor constituting the OTA, as shown in [Equation 4], the ratio of the channel width and the length of the MOS transistor to increase V _id (W / L ) Can be made small. However, when the W / L is reduced, there is a problem that the transconductance (Gm) is reduced.

&Quot; (4) "

In order to improve the linearity of the OTA, a scheme like FIG. 3 has been proposed.

3A to 3C are exemplary views of a general OTA circuit with improved linearity.

First, FIG. 3A illustrates a case where a source degeneration resistor Rs is used. These OTA circuits increase in area with the introduction of source degeneration resistors (Rs), and due to the process change rate of the resistors, it is difficult to obtain accurate transconductance.

Next, FIG. 3B shows an OTA circuit using a MOS transistor operating in a triode region. Although the OTA circuit of FIG. 3B has excellent linearity, it is inadequate for use at low voltage and has a disadvantage of poor frequency characteristics.

3C shows an OTA circuit based on an inverter. Inverter-based OTA circuits can achieve relatively large transconductance values compared to other OTA circuits and are suitable for use at low voltages and high frequencies. In addition, there is an advantage that the transconductance can be easily adjusted by using the external supply voltage V _DD .

In FIG. 3C, the input voltages V _{in +} , V _in− are as follows.

[Equation 5]

When the first input voltage V _{in +} is input to the first PMOS transistor P11 and the first NMOS transistor N11, currents shown in Equations 6 and 7 are generated, respectively.

&Quot; (6) "

[Equation 7]

Equations 6 and 7 assume that V _DD = -V _SS , V _TH = V _THn = │V _THp │, K = K _n = K _p , and V _CM = 0, and at node Vout + By applying Kirchhoffs current law (KCL), the output current I of the OTA can be calculated as shown in [Equation 8]. Here, K _n and K _p mean constants determined from process variables (carrier mobility, gate capacitance, etc.), channel length, and width of the NMOS transistor and the PMOS transistor, respectively.

[Equation 8]

The output current I shows a very linear characteristic with a slope of G _m on the input voltage.

By the way, the result of [Equation 8] shows a case when it is assumed that V _CM = 0. V _CM is an input common voltage equal to the input bias voltage. Therefore, the value may not be fixed. Therefore, if V _DD = -V _SS , V _TH = V _THn = V _Vp , K = K _n = K _p and V _CM ≠ 0, the output current I is calculated as shown in [Equation 9].

[Equation 9]

In this manner, if the _CM V ≠ 0, the output current can be seen that the non-linear current produced by the _{4K (V DD -V TH) V} CM according to the change of V _CM.

That is, since the linearity is determined by the common mode voltage V _{CM in the} inverter-based OTA circuit, the linearity is degraded at the common mode voltage other than V _DD / 2.

The present invention has been made to solve the above-mentioned disadvantages and problems, there is a technical problem to provide an OTA circuit that can ensure linearity even at voltages other than the common mode voltage.

The OTA circuit according to an embodiment of the present invention for achieving the above technical problem is connected between the power supply voltage terminal and the ground terminal, and converts and amplifies the first input voltage and the second input voltage into a current to generate an output voltage Main amplifier; And a common mode feedforward unit configured to detect the common mode voltage input to the main amplifier, generate a common mode current from the detected common mode voltage, and provide the common mode current to the main amplifier.

According to the present invention, it is possible to effectively remove the nonlinear current generated in the OTA circuit, thereby improving the linearity of the OTA circuit.

The Operational Transconductance Amplifier (OTA) circuit of the present invention detects an input common-mode (CM) voltage in a CMOS inverter type. In addition, by using the common mode feed-forward (CMFF) method which feeds forward to the output node to adjust the load current using the detected common mode voltage, the nonlinearity caused by the input common mode voltage is improved. do. Accordingly, the OTA circuit proposed in the present invention maintains linearity even with a change in the input common mode voltage.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

4 is a block diagram of an OTA circuit according to an embodiment of the present invention.

As illustrated, the OTA circuit 100 according to the present invention includes a main amplifier 110 and a common mode feed forward (CMFF) unit 120.

First, the main amplifier 110 is connected between the power supply voltage terminal (V _DD ) and the ground terminal (V _SS ), and converts and amplifies the first and second input voltages (V _{in +} , V _in− ) into current and outputs them. Generate the voltage (I).

In a preferred embodiment of the present invention, the main amplifier 110 may be configured based on an inverter, and a detailed configuration thereof will be described later.

Meanwhile, the CMFF unit 120 generates the common mode currents I _x and I _y which detect the input common mode voltage V _CM to remove the non-linear current generated by the main amplifier 110.

In this way, the current I output from the main amplifier 110 has a linear characteristic regardless of the level of the common mode voltage.

FIG. 5 is a detailed configuration diagram of the CMFF unit shown in FIG. 4.

As illustrated, the CMFF unit 120 is connected between the power supply voltage terminal V _DD and the ground terminal V _SS to receive the first drain current from the first and second input voltages V _{in +} and V _in− . First current generating means 122 for generating, First current detecting means 124 for detecting the first common mode current I _x from the first drain current generated in the first current generating means 122, Power supply voltage Second current generating means 126 connected between the terminal V _DD and the ground terminal V _SS to generate a second drain current from the first and second input voltages V _{in +} and V _in− , and And second current detecting means 128 for detecting the second common mode current I _y from the second drain current generated by the second current generating means 126.

In addition, the detected first and second common mode currents I _x and I _y are provided to the output node of the main amplifier 110 to cancel the nonlinear current generated in the main amplifier 110.

FIG. 6 is a detailed circuit diagram of the OTA circuit shown in FIG. 4.

First, the main amplifier 110 is connected between the power supply voltage terminal V _DD and the ground terminal V _SS and driven by the first input voltage V _{in +} , the first inverters P21 and N21 and the power supply voltage terminal. Second inverters P22 and N22 connected between a V _DD and a ground terminal V _SS and driven by a second input voltage V _in- , and a first node K11 that is an output terminal of the first inverter. It includes a load resistor (R) connected between the second node (K12) which is the output terminal of the second inverter.

Here, the first inverter may be configured by connecting the first PMOS transistor P21 and the first NMOS transistor N21 in series, and the second inverter may include the second PMOS transistor P22 and the second NMOS transistor N22. Can be configured by serial connection.

On the other hand, the CMFF unit 120 is composed of the first current generating means 122, the first current detecting means 124, the second current generating means 126 and the second current detecting means 128, each of the configuration The detailed description is as follows.

First, the first current generating unit 122 includes a first terminal having a drain terminal connected to the third node K13, a source terminal connected to the ground terminal V _SS , and a first input voltage V _{in +} supplied to the gate terminal. third NMOS transistor (N23) and the drain stage is connected to the third node (K13) and the source end is connected to the ground terminal (V _SS) first NMOS transistor 4 which is a second input voltage (V _in-) is supplied to the gate terminal (N24).

The first current detecting means 124 includes a third PMOS transistor P23 having a source terminal connected to a power supply voltage terminal V _DD and a drain terminal connected to a first node K11, and a source terminal having a power supply voltage terminal V. FIG. _DD ) and the fourth PMOS transistor P24 and the drain terminal connected to the second node K12 and the source terminal connected to the power supply voltage terminal V _DD , and the drain terminal connected to the third node K13. A fifth PMOS transistor P25 is included. Here, the gate terminals of the third to fifth PMOS transistors P23, P24, and P25 are commonly connected to the drain terminals of the fifth PMOS transistor P25.

On the other hand, the second current generating means 126 has a source terminal connected to the power supply voltage terminal V _DD , a drain terminal connected to the fourth node K14, and the first input voltage V _{in +} supplied to the gate terminal. a sixth PMOS transistor which is the seventh (P26) and the source end connected to a power supply voltage terminal (V _DD) and the drain stage is connected to the fourth node (K14) and the second input voltage (V _in-) is supplied to the gate terminal PMOS transistor P27 is included.

The second current detecting unit 128 includes a fifth NMOS transistor N25 having a drain terminal connected to the first node K11 and a source terminal connected to the ground terminal V _SS , and the drain terminal having a second node ( A sixth NMOS transistor N26 connected to K12, a source terminal connected to a ground terminal V _SS , a drain terminal connected to a fourth node K14, and a source terminal connected to a ground terminal V _SS ; 7 NMOS transistor N27. Here, the gate terminal of the fifth to seventh NMOS transistors N25, N26, and N27 is commonly connected to the drain terminal of the seventh NMOS transistor N27.

The CMFF unit 120 configured as described above has a common mode current I _x , I _y generated by detecting the common mode voltage V _CM to remove the nonlinear current generated from the main amplifier 110 based on the inverter. To remove the nonlinear current.

Referring to FIG. 6, the first common mode current I _x detected by the first current detecting means 124 is the third NMOS transistor N23 and the fourth NMOS transistor N24 of the first current generating unit 122. It is half the sum of the current flowing through That is, half of the sum of the drain currents I _d1 ^* and I _d2 ^{* of the} 3 NMOS transistors N23 and the fourth NMOS transistors N24 may be expressed as I _x .

Similarly, the second common mode current I _y detected by the second current detection means 128 is the drain current I _d3 of the sixth and seventh PMOS transistors P26 and P27 of the second current generating unit 126. ^* , I _d4 ^* ).

Assuming that V _DD = -V _SS , V _TH = V _THn = │V _THp │, K = K _n = K _p , calculate I _x , I _y in a similar manner as in Equations 6 and 7 Is as follows.

[Equation 10]

If KCL is applied at the second node K12 of FIG. 6 and Equation 9, which represents the output current I when the common mode voltage V _CM is not 0, is represented by another expression, the following may be obtained. .

[Equation 11]

From this, the following Equation 12 can be obtained.

[Equation 12]

As such, when the CMFF unit 120 is used, the output current I may be output regardless of the common mode voltage V _CM . That is, even when V _CM ≠ 0, the OTA circuit can be designed such that a linear output is generated with respect to the input voltage.

In addition, the transconductance Gm of the OTA circuit according to the present invention can be tuned using V _DD as shown in Equation 12.

7 and 8 are graphs for comparing the linearity of the output current according to the common mode voltage variation in a typical inverter-based OTA circuit and the OTA circuit according to the present invention.

First, Figure 7 shows the load current and transconductance (gm) change according to the differential input voltage (Vd) in a typical OTA circuit.

When the common mode voltage Vcm is (V _DD -V _SS ) / 2, for example, 0.9V, it can be seen that the load current A1 has linearity over the entire interval of the differential input voltage Vd. However, when the common mode voltage Vcm is not (V _DD -V _SS ) / 2, for example, when the common mode voltage Vcm is changed to 1.1 V, the linearity of the load current B1 is lowered and thus linearity is obtained only in some sections.

Comparing this to the transconductance value, when the common mode voltage (Vcm) is 0.9 V, the transconductance (C1) has almost the same value over the entire interval of the differential input voltage (Vd), while the common mode voltage (Vcm) It can be seen that the transconductance (D1) in the case of changing to this 1.1V is very fluctuating.

As such, the general OTA circuit is sensitive to the change of the common mode voltage (Vcm) and cannot guarantee the linearity of the load current.

8 illustrates a change in load current and transconductance (gm) according to the differential input voltage Vd in the OTA circuit according to the present invention.

When the common mode voltage (Vcm) is (V _DD -V _SS ) / 2, for example 0.9V, and the load current (A2) and the common mode voltage (Vcm) are not (V _DD -V _SS ) / 2 For example, the load current B2 when it is changed to 1.1V is the same. That is, even if the common mode voltage Vcm is varied, the linearity of the OTA circuit is guaranteed in the entire period of the differential input voltage Vd. In the graph of Fig. 8, the graphs A2 and B2 in the case where the common mode voltage Vcm is 0.9V and 1.1V are overlapped with each other.

On the other hand, when comparing the transconductance according to the variation of the common mode voltage (Vcm), the differential input voltage when the common mode voltage (Vcm) is 0.9V (C2) and when the common mode voltage (Vcm) is changed to 1.1V It can be seen that the values are almost the same in all sections of (Vd).

As described above, it can be seen that the output current of the OTA circuit according to the present invention has a relatively wide linear section regardless of the value of V _CM .

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical concept or essential characteristics. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The OTA circuit according to the present invention is very excellent in linear characteristics. Therefore, when applied to a multi standard receiver such as a Gm-C filter, the cutoff frequency can be easily adjusted and the stopband attenuation characteristics can be improved. In addition, multiple standard receivers with low power consumption can be configured.

1 is a configuration diagram of a general OTA circuit,

2 is a graph showing a linear section of a differential input in the OTA circuit shown in FIG.

3a to 3c are exemplary views of a general OTA circuit with improved linearity,

4 is a block diagram of an OTA circuit according to an embodiment of the present invention;

5 is a detailed configuration diagram of the CMFF unit shown in FIG. 4;

6 is a detailed circuit diagram of the OTA circuit shown in FIG. 4;

7 and 8 are graphs for comparing the linearity of the output current according to the common mode voltage variation in a typical inverter-based OTA circuit and the OTA circuit according to the present invention.

Description of the Related Art [0002]

100: OTA circuit 110: main amplifier

120: CMFF section 122: first current generating means

124: first current detecting means 126: second current generating means

128: second current detection means

Claims (8)

A main amplifier connected between a power supply voltage terminal and a ground terminal, converting and amplifying a first input voltage and a second input voltage into a current to generate an output voltage, the main amplifier comprising an inverter-based operational transconductor amplifier; And A common-mode feed-forward unit configured to detect a common mode voltage input to the main amplifier, generate a common mode current from the detected common mode voltage, and provide the common mode current to the main amplifier; Operational interconductance amplification circuit comprising a. delete The method of claim 1, The main amplifier may include: a first inverter connected between the power supply voltage terminal and the ground terminal to invert and output the first input voltage; A second inverter connected between the power supply voltage terminal and the ground terminal to invert and output the second input voltage; And A load resistor connected between the first node, which is an output terminal of the first inverter, and the second node, which is an output terminal of the second inverter; Operational interconductance amplification circuit comprising a. The method of claim 3, wherein The common mode feedforward section may include: first current generation means connected in parallel between the power supply voltage terminal and the ground terminal to generate a first drain current according to the common mode voltage; First current detecting means for generating a first common mode current from the first drain current and providing the first common mode current to the first node; Second current generating means connected in parallel between the power supply voltage terminal and the ground terminal to generate a second drain current by the common mode voltage; And Second current detection means for generating a second common mode current from the second drain current and providing it to the second node; Operational interconductance amplification circuit comprising a. The method of claim 4, wherein The first current generating means includes: a first transistor having a drain terminal connected to a third node, a source terminal connected to the ground terminal, and the first input voltage supplied to a gate terminal; And a second transistor having a drain terminal connected to the third node, a source terminal connected to the ground terminal, and the second input voltage supplied to a gate terminal. The first current detecting means includes: a third transistor having a source terminal connected to the power supply voltage terminal and a drain terminal connected to the first node; A fourth transistor having a source terminal connected to the power supply voltage terminal and a drain terminal connected to the second node; And a fifth transistor having a source terminal connected to the power supply voltage terminal and a drain terminal connected to the third node, wherein the gate terminal of the third to fifth transistors is commonly connected to the drain terminal of the fifth transistor. Operational interconductance amplification circuit, characterized in that. The method of claim 5, Wherein said first and second transistors are NMOS transistors, and said third to fifth transistors are PMOS transistors. The method of claim 5, The second current generating means includes: a sixth transistor having a source terminal connected to the power supply voltage terminal, a drain terminal connected to a fourth node, and the first input voltage supplied to a gate terminal; And a seventh PMOS transistor having a source terminal connected to the power supply voltage terminal, a drain terminal connected to the fourth node, and the second input voltage supplied to a gate terminal. The second current detecting means includes: an eighth transistor having a drain terminal connected to the first node and a source terminal connected to the ground terminal; A ninth transistor having a drain terminal connected to the second node and a source terminal connected to the ground terminal; And a tenth transistor having a drain terminal connected to the fourth node and a source terminal connected to the ground terminal, wherein the gate terminal of the eighth to tenth transistors is commonly connected to the drain terminal of the tenth transistor. Operational interconductance amplification circuit, characterized in that. The method of claim 7, wherein And the sixth and seventh transistors are PMOS transistors, and the eighth to tenth transistors are NMOS transistors.

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