CN116032283A - Programmable gain amplifying circuit with DCOC calibration and implementation method - Google Patents
Programmable gain amplifying circuit with DCOC calibration and implementation method Download PDFInfo
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Abstract
The invention discloses a programmable gain amplifying circuit with DCOC calibration and an implementation method, wherein the programmable gain amplifying circuit with DCOC calibration comprises the following components: the input end of the programmable gain amplifying circuit is connected with the signal input end through a resistor, the in-phase output end of the programmable gain amplifying circuit is connected with the positive input end of the DCOC direct current offset eliminating circuit, the reverse output end of the programmable gain amplifying circuit is connected with the negative input end of the DCOC direct current offset eliminating circuit, and the output end of the DCOC direct current offset eliminating circuit is respectively connected with the input end of the programmable gain amplifying circuit and the signal input end. The invention realizes the overall 12bits adjustable and dynamic gain range of 1-4096 times by using the PGA cascade form with two-stage gain adjustable, and can eliminate the DC offset voltage at the input end of the programmable amplifying circuit.
Description
Technical Field
The invention belongs to the field of operational amplifiers, and particularly relates to a programmable gain amplifying circuit with DCOC calibration and an implementation method.
Background
In the macroscopic world, physical phenomena such as acoustic waves and electromagnetic waves containing information are continuous analog signals, so that processing these continuous signals can generate different degrees of difficulty and even error data for digital modules, and thus, a special module for discretely sampling analog signals and effectively quantizing the analog signals into digital signals is required to process the information, that is, a special analog-to-digital converter is used as a conversion function module necessary for connecting the analog module and the digital module information path. However, there are also limitations to the performance of ADCs because the information acquisition end typically uses sensors to convert various physical quantities into electrical signals containing information. First, these electrical signals are typically limited by the output power of the sensor, making the output signal very weak, which is a significant challenge for accurate quantization of the ADC. Secondly, the state of the sensor is easy to be interfered by external environment, so that the power of interference information such as noise, offset and the like in an output signal can be very high, and therefore, an amplifier is needed to be added between the sensor and the ADC to amplify the output signal of the sensor, so that the design pressure caused by the quantization precision of the ADC is relieved, and meanwhile, the sensor can be amplified for different applications to adapt to the performances of the ADC, and meanwhile, the offset of the sensor is needed to be processed, the occasion and the precision are improved, the adjustment of multiple amplification factors is realized, and the universality is improved. Therefore, the programmable gain operational amplifier is used for carrying out signal processing precision with different degrees on the signal intensity, and can well meet the design requirement. The programmable amplifier is increasingly applied to acquisition circuits of various sensors, and is a vital link in a signal processing chain. For a programmable gain operational amplifier, one of the core functions is that the amplification factor is adjustable, so that the division is mainly divided into transconductance programmable, load programmable and feedback network programmable by adjusting the amplification factor implementation mode.
The conventional programmable gain amplifier uses an operational amplifier with a conventional structure as gain supply, and has the defects that the input voltage swing is narrow, large signals cannot be acquired, and the large signals cannot be output and transmitted to a later-stage circuit under the condition of no distortion. Resulting in certain requirements on the range of the input signal. In addition, in the aspect of output voltage swing, the collected weak signals cannot be amplified to larger and more ideal amplitude output due to the limitation of the traditional operational amplifier.
Meanwhile, the programmable amplifier is used as a branch of the amplifier, the problem of offset voltage commonly existing in the amplifier exists, the occurrence of the offset voltage can cause errors in the whole circuit, and the input value cannot be truly reflected. The programmable gain amplifier uses a set of circuits to realize the amplification of different gain multiples for different signals in a programmable way, and the problem of offset voltage is more remarkable.
Disclosure of Invention
The invention aims to provide a programmable gain amplifier circuit with DCOC calibration and an implementation method thereof, which eliminate direct current offset voltage at the input end of the programmable gain amplifier circuit.
In one aspect, the present invention provides a programmable gain amplifying circuit with DCOC calibration, comprising: the input end of the programmable gain amplifying circuit is connected with the signal input end through a resistor, the in-phase output end of the programmable gain amplifying circuit is connected with the positive input end of the DCOC direct current offset eliminating circuit, the reverse output end of the programmable gain amplifying circuit is connected with the negative input end of the DCOC direct current offset eliminating circuit, and the output end of the DCOC direct current offset eliminating circuit is respectively connected with the input end of the programmable gain amplifying circuit and the signal input end.
Optionally, the programmable gain amplifying circuit includes a first variable gain operational amplifier module and a second variable gain operational amplifier module;
the non-inverting output end of the first variable gain operational amplifier module is connected with the non-inverting input end of the second variable gain operational amplifier module, and the inverting output end of the first variable gain operational amplifier module is connected with the inverting input end of the second variable gain operational amplifier module.
Optionally, the connection of the input end of the programmable gain amplifying circuit with the signal input end through a resistor includes:
the non-inverting input end of the programmable gain amplifying circuit is connected with the positive signal input end through a first resistor R1, and the inverting input end of the programmable gain amplifying circuit is connected with the negative signal input through a second resistor R2.
Optionally, the first variable gain operational amplifier and the second variable gain operational amplifier have the same structure and each consist of a plurality of operational amplifiers and a plurality of variable resistors;
the operational amplifiers comprise a first operational amplifier OTA1, a second operational amplifier OTA2, a third operational amplifier OTA3 and a fourth operational amplifier OTA4;
the output ends of the first operational amplifier OTA1 and the third operational amplifier OTA3 are respectively connected with the non-inverting input ends of the second operational amplifier OTA2 and the fourth operational amplifier OTA4; the first operational amplifier OTA1, the second operational amplifier OTA2, the third operational amplifier OTA3 and the fourth operational amplifier OTA4 are all in a negative feedback state;
the variable resistors comprise a variable resistor R1, a variable resistor R2 and a variable resistor R3;
the output end of the first operational amplifier OTA1 is connected with the reverse input end of the first operational amplifier OTA1 through a variable resistor R1, the third operational amplifier OTA3 is connected with the reverse input end of the third operational amplifier OTA3 through a variable resistor R3, and the output end of the first operational amplifier OTA1 is connected with the output end of the third operational amplifier OTA3 through a variable resistor R3.
Optionally, the operational amplifier is a constant transconductance rail-to-rail operational amplifier.
Optionally, the DCOC dc offset cancellation circuit includes: the device comprises a low-pass filter module, a comparator module, a digital logic module and a numerical control current source module;
the output end of the low-pass filter module is connected with the forward input end of the comparator module, the output end of the comparator module is connected with the reverse input end of the digital logic module, the output end of the digital logic module is connected with the control end of the numerical control current source module, and the current output end of the numerical control current source module is connected with the two ends of the first resistor R1 and the two ends of the second resistor R2.
Optionally, the low-pass filter module includes a first low-pass filter and a second low-pass filter; the comparator module comprises a first comparator and a second comparator;
the output port of the first low-pass filter is connected with the positive input end of the first comparator, and the output end of the second low-pass filter is connected with the positive input end of the second comparator.
In order to achieve the above object, the present invention provides a method for implementing a programmable gain amplification circuit with DCOC digital calibration, using a programmable gain amplification circuit with DCOC digital calibration, comprising the steps of:
controlling a variable resistor in a programmable gain operational amplification circuit module, and changing the gain of the programmable operational amplification circuit module;
meanwhile, the DCOC direct current offset cancellation circuit module acquires a direct current signal at the output end of the programmable operational amplification circuit module, and outputs different compensation currents based on the direct current signal;
and the compensation current is input to the input end of the programmable gain operational amplification circuit module, and the direct current offset voltage of the input end of the programmable gain operational amplification circuit module is eliminated.
Preferably, the programmable gain operational amplifier circuit module increases the gain range of the programmable gain operational amplifier circuit module through a constant transconductance rail-to-rail operational amplifier.
Preferably, the DCOC direct current offset cancellation circuit module controls the output of the compensation current through a digital logic module.
The invention has the technical effects that: (1) The invention designs a programmable gain amplifying circuit with DCOC calibration, which comprises a constant transconductance rail-to-rail operational amplifier, a classAB output stage, a programmable gain amplifier and a DCOC anti-maladjustment module, wherein the constant transconductance rail-to-rail operational amplifier is used as a PGA gain device, and a two-stage gain adjustable PGA cascade form is used for realizing the overall 12bits adjustable dynamic gain range with the gain range of 1-4096 times; the design uses a DCOC anti-maladjustment module, and the DCOC anti-maladjustment module is controlled by a compensation coefficient of a digital circuit, and an LPF and a compensation mechanism are introduced into an input end and an output end to eliminate input maladjustment voltage.
(2) The invention provides a method for realizing a programmable gain amplifier with DCOC digital calibration, and designs a method for realizing the DCOC digital calibration, and the current fed back to an input end does not contain alternating current signals due to digital logic, so that the problem of unstable loop is solved.
(3) The programmable gain amplifier with DCOC calibration is provided with the constant-span guide rail-to-rail operational amplifier on the structure of the programmable switch resistor feedback network, so that the programmable gain amplifier can meet the scene application of wide input voltage swing and wide output voltage swing, and the influence of input offset voltage is effectively reduced by adding the DCOC anti-offset module, and is more suitable for being applied to the field of weak signal acquisition and processing when an actual sensor acquisition circuit is used.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application, illustrate and explain the application and are not to be construed as limiting the application. In the drawings:
FIG. 1 is a schematic diagram of a programmable gain amplifier with DCOC calibration according to an embodiment of the present invention;
FIG. 2 is a block diagram of a programmable gain amplifier according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a programmable gain amplifier circuit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a constant transconductance Rail to Rail operational amplifier of a floating class ClassAB output stage according to an embodiment of the present invention;
FIG. 5 is a block diagram of a DCOC circuit based on a digital calibration circuit in accordance with an embodiment of the present invention;
Detailed Description
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, in some cases the steps illustrated or described may be performed in an order other than that illustrated herein.
Example 1
As shown in fig. 1, in this embodiment, a programmable gain amplifying circuit with DCOC calibration is provided, which includes: the input end and the output end of the programmable gain amplifying circuit are connected with the DCOC direct current offset eliminating circuit, a first resistor R1 is arranged between the in-phase input port and the signal positive input end vin+ of the programmable gain amplifying circuit, the reverse phase input port and the signal negative input end Vin-of the programmable gain amplifying circuit are provided with a second resistor R2, the in-phase output end of the programmable gain amplifying circuit is connected with the positive input port of the DCOC direct current offset circuit, the reverse phase output end of the programmable gain amplifying circuit is connected with the negative input port of the DCOC direct current offset circuit, the Q1 output port of the DCOC direct current offset circuit is connected with the in-phase input port of the programmable gain amplifying circuit, the Q2 output port of the DCOC direct current offset circuit is connected with the reverse phase input port vin+ of the signal positive input port, and the Q4 output port of the DCOC direct current offset circuit is connected with the signal negative input port Vin-; wherein the signal positive input terminal Vin+ and the signal negative input terminal Vin-are signals output by the front-stage sensor.
As shown in fig. 2, the two operational amplifiers are identical in structure and are in a negative feedback state. According to the 'virtual short' and 'virtual break' rules of the operational amplifier input end, the following formulas can be deduced:
V op -V on ＝I(R 1 +2R 2 )
V ip -V in ＝IR 1
the gain of the PGA can be expressed as:
the resistance values of the variable resistors R1 and R2 are controlled in a digital code mode, so that the programmable gain amplification function is realized.
As shown in fig. 3, the first gain amplification circuit is composed of four rail-to-rail operational amplifiers and a switched resistor feedback network for amplifying the PGA input signal. The first gain amplifying circuit is adjustable in 6bits, the switches S0-S5 are controlled respectively, the closed loop gain can be changed within the range of 1-64 times, and the relation between the closed loop gain of the first gain amplifying circuit and the switch state is achieved.
When S0 is closed, the remaining switches are all off, gain=1,
when S1 is closed, the remaining switches are all off,
when S2 is closed, the remaining switches are all off,
when S3 is closed, the remaining switches are all off,
when S4 is closed, the remaining switches are all off,
when S5 is closed, the restWhen the switch is turned off,
similarly, the relationship between the closed loop gain and the switch state of the second gain amplifying circuit is the same as that of the first stage. The PGA adjusts the resistance of the equivalent resistor through the input digital code S <11:0>, thereby realizing the gain adjustment of the PGA, and realizing the high gain range of 1-4096 times through a two-stage cascade connection mode.
As shown in fig. 4, a circuit diagram of a constant transconductance Rail to Rail operational amplifier for a floating Class AB output stage, the constant transconductance Rail to Rail operational amplifier comprises: the constant transconductance compensation circuit module, the rail-to-rail operational amplifier circuit module, the folding cascode operational amplifier module and the Class AB output stage circuit module;
the internal differential input end of the constant transconductance compensation circuit module is connected with the input stage of the rail-to-rail operational amplifier circuit module, the input stage of the rail-to-rail operational amplifier circuit module is connected with the folding cascode operational amplifier module, and the output stage of the folding cascode operational amplifier module is connected with the Class AB output stage circuit module.
The amplifier uses a folding common-source common-gate structure, meets the requirement of high gain, and increases chopper switches at the input end and the output end so as to reduce offset voltage brought by the operational amplifier. The operational amplifier input stage uses a constant-span guide rail-to-rail input stage formed by three-time current mirrors, and the output swing rail-to-rail is realized by adopting a floating Class AB output stage at the operational amplifier output stage.
For the rail-to-rail input stage, the rail-to-rail input stage can be realized by adopting NMOS and PMOS complementary differential input geminate transistors, M1 and M2 transistors are NMOS input geminate transistors, M12 and M13 transistors are PMOS input geminate transistors, when the common-mode input voltage is close to the positive power supply voltage, the M1 and M2 transistors are turned on, and the M12 and M13 transistors are turned off; when the common-mode input voltage is close to the negative power supply voltage, the M12 and M13 tube pairs are turned on, and the M1 and M2 tubes are turned off; and when the common-mode input range is in the middle of the power supply range, the M12 and M13 tubes and the M1 and M2 tubes are simultaneously turned on, and the total transconductance is twice that of a single differential pair. Such a change in transconductance not only causes instability in gain and change in unit frequency response, but also reduces the common mode rejection ratio, resulting in large harmonic distortion and change in slew rate. Thus, a constant transconductance input stage is necessary.
Meanwhile, in order to reduce equivalent input noise and operational amplifier input offset voltage, a chopper stabilizing circuit needs to be added. For the rail-to-rail output stage, a Class AB output stage can be adopted, so that the output voltage range is increased, extra power consumption of a circuit is not increased, and the high-frequency characteristic is good.
For NMOS differential pair transistors (M1 and M2), they do not work properly at the low common mode input level. The input common mode level range is:
V SS +V gsn +V sat ＜V cm ＜V DD
wherein V is DD For the supply voltage, V SS Is at ground potential, V cm For common mode input voltage, V gsn Is the gate-source voltage of NMOS tube, V sat Overdrive voltage is applied to two ends of the current source; and for PMOS differential pair transistors (M3, M4) do not work properly with a high common mode input signal. The input common mode level range is:
V SS ＜V cm ＜V DD -V sgp -V sat
wherein V is DD For the supply voltage, V SS Is at ground potential, V cm For common mode input voltage, V sgp Is the gate-source voltage of the PMOS tube, V sat Overdrive voltage is applied to two ends of the current source; therefore, the independent structures of the PMOS and NMOS differential pair tubes cannot meet the common-mode input range, in order to increase the common-mode input voltage range of the operational amplifier and obtain the input voltage of Rail to Rail, a complementary differential pair structure with NMOS and PMOS connected in parallel can be adopted, and the common-mode input range is as follows:
V SS ＜V cm ＜V DD
the Rail to Rail op-amp typically employs a complementary differential pair structure as the input stage, the transconductance of NMOS and PMOS is as follows:
g m，nmos ＝[2μ n C ox (W/L) n I n ] 1/2
g m，pmos ＝[2μ p C ox (W/L) p I p ] 1/2
assume that: k=1/2K n (W/L) n ＝1/2K p (W/L) p Wherein, K n ＝μ n C ox ，K p ＝μ p C ox Transconductance coefficients of the NMOS tube and the PMOS tube are respectively; and the tail currents of the NMOS and PMOS differential pairs are equal, namely: i p ＝I n G is =i n ＝g m，nmas ＝g m，pmos In g m，nmos And g is equal to m，pmos Transconductance of NMOS and PMOS differential pairs, respectively.
According to common mode input voltage V cm Different, the working state can be divided into three areas: region 1: when V is SS ＜V cm ＜V od +V gsn When the NMOS differential pair transistors M1 and M2 are turned off, the transconductance of the input stage is g mpmos The method comprises the steps of carrying out a first treatment on the surface of the Region 2: when V is DD -V sgp -V od ＜V cm ＜V DD When the PMOS differential pair transistors M3 and M4 are turned off, the transconductance of the input stage is g m，nmos The method comprises the steps of carrying out a first treatment on the surface of the Region 3: when V is od +V gs ＜V cm ＜V DD -V sgp -V od When the PMOS and NMOS differential pair transistors M1, M2, M3 and M4 are simultaneously conducted, the transconductance of the input stage is the sum of the transconductance of the NMOS and PMOS differential pair: g m，nmos +g m，pmos ＝2g m 。
When the common mode input level changes from power to ground, the transconductance of the input stage changes doubled. If the amplifier is applied to the operational amplifier with a feedback loop, the loop gain is doubled, and the distortion is increased. When the transconductance changes by one time, the unit gain bandwidth correspondingly changes by one time, so that the phase margin is reduced, and the operational amplifier stability is deteriorated. Thus, it is critical for the input stage design to keep the transconductance constant throughout the common-mode input voltage range.
The constant transconductance of the circuit design adopts a three-time current mirror method to control the complementary differential pair as an input stage to realize constant transconductance. M16 and M17 are two current switches respectively controlling two amplification composed of M14-M15 and M18-M19A current mirror with a multiple of 1:3. From the previous analysis, the common-mode input voltage divides the transconductance into three parts, when V od +V gsn ＜V cm ＜V DD -V sgp -V od At maximum transconductance of V cm At twice that of the other intervals. Because the transconductance of the MOS transistors working in the strong inversion region is proportional to the square root of the leakage current, if the tail currents of two pairs of transistors which are conducted independently are 4 times of the tail currents of the two pairs of transistors which are conducted simultaneously, the transconductance of the input stage is kept constant in the whole common-mode input range. When V is SS ＜V cm ＜V od +V gsn When the PMOS differential pair tube is conducted, the switch M16 is conducted, M3 tail current is led to a current mirror consisting of M18-M19 by the M16, and the tail current is 4 times of the original tail current. Similarly, when V SS ＜V cm ＜V od +V gsn When the NMOS differential pair tube is in conduction, the tail current is 4 times of the original tail current. When V is od +V gsn ＜V cm ＜V DD -V sgp -V od When the switches M17 and M18 are both off, both differential pairs are on, thus achieving a constant input stage transconductance over the common-mode input range of Rail to Rail.
For chopper switches provided in the circuit, M20, M21, M22, M23 are modulation switches of the non-inverting input ports, and M24, M25, M26, M27 are modulation switches of the inverting input ports. The basic principle of the chopper stabilization technology is that 1/f flicker noise with direct loss and low frequency is modulated to high frequency, and then the high frequency component is filtered out by a low-pass filter to eliminate the influence caused by the loss and the 1/f noise.
In the chopper stabilization circuit, the modulation and demodulation positions are also key points of design. The input modulates the input signal, except that they demodulate the recovered input signal differently. The traditional chopper stabilization technology demodulates signals at the output end, and because of the large and small signal output impedance at the output end, the signal is easy to form low-pass filtering with a switching tube, so that the available chopper frequency is limited, and the frequency can only reach within 10 KHz. The chopping technology adopted by the invention demodulates at the low small signal impedance, thus greatly improving the chopping frequency.
The floating class AB output stage consists of output driving pipes MP1 and MN1, a front-stage operational amplifier output stage directly drives MP1 and MN1, MP4 and MN4 to form a floating class AB bias circuit, diode connected MN2 and MN3 provide bias for MN4, diode connected MP2 and MP3 provide bias for MP4, I ref Is the reference current.
Let k=μc ox (W/L)，
I D Is the drain current of each tube, V GS Is the gate-source voltage of each tube, V th Is the threshold voltage of each tube, I Q Is the quiescent current of MN1 and MP 1.
V GSMN1 +V GSMN4 ＝V GSMN2 +V GSMN3
V SGMP1 +V SGMP4 ＝V SGMP2 +V SGMP3
Simplifying the formula to obtain:
I Q ＝MI ref
therefore, output tube I Q Is M times I ref Therefore, the output is limited by the voltage of the power rail only, and the power supply rejection ratio PSRR of the circuit is greatly improved.
In the circuit, the PGA and the front stage sensor AFE are directly connected. The dc level of the pre-stage circuit is directly input to the PGA. When the gain of the PGA is high (for example, 512 times), even if the input end is very small in dc offset (for example, 1 mV), a very large dc offset (about 500 mV) is caused at the output end, and the large dc offset can make the MOS transistor enter the linear region or the cut-off region, so that the PGA and the post-stage circuit are difficult to work normally. In addition to the dc input offset introduced by the previous stage, the non-perfect symmetry of the PGA itself, process variations, parasitics, etc. introduce dc offset, and therefore, in order to ensure the PGA to work properly, a dc offset cancellation (DCOC) circuit must be introduced.
The traditional Direct Current Offset Cancellation (DCOC) circuit extracts a direct current signal in an output signal through a low-pass filter and directly feeds the direct current signal back to an input port, but the loop is unstable due to filtering inaccuracy.
As shown in fig. 5, a digital calibration method is used, the direct current level is extracted by a filter circuit, and the result is transmitted to a digital logic part after comparison by a comparator.
The low-pass filter comprises a first low-pass filter, a second low-pass filter, a first comparator, a second comparator, digital control logic and a numerical control current source module. The in-phase output end of the programmable gain amplifier is connected with the input end of the first low-pass filter, the inverting output end of the programmable gain amplifier is connected with the input end of the second low-pass filter, the output end of the first filter is connected with the input end of the first comparator, the output port of the second filter is connected with the input end of the second comparator, the input end of the first comparator is connected with the positive input end of the digital logic module, the input end of the second comparator is connected with the negative input end of the digital logic module, the output of the digital logic module controls the numerical control current source to generate different currents, and the output of the numerical control current source circuit is connected with the input end resistors R1 and R2 of the programmable gain amplifier.
Example two
The embodiment also provides a programmable gain amplifying circuit implementation method with DCOC calibration, which comprises the following steps:
the input end and the output end of the programmable gain amplifying circuit are connected with a DCOC direct current offset eliminating circuit;
the programmable gain amplifying circuit provides a wide range of variable gain for the signal path;
the programmable gain amplifying circuit comprises a first variable gain operational amplifier and a second variable gain operational amplifier,
the first variable gain operational amplifier comprises a first operational amplifier, a second operational amplifier, a third operational amplifier, a fourth operational amplifier, a variable resistor R1, a variable resistor R2 and a variable resistor R3, and is characterized in that the non-inverting input port of the first operational amplifier is used as the non-inverting input port of the first variable gain operational amplifier, the variable resistor R1 is connected between the inverting input port of the first operational amplifier and the output port of the first operational amplifier, the output port of the first operational amplifier is connected with the non-inverting input port of the second operational amplifier, the inverting input port of the second operational amplifier is connected with the output port of the second operational amplifier, the non-inverting input port of the third operational amplifier is used as the inverting input port of the first variable gain operational amplifier, the non-inverting input port of the third operational amplifier is connected with the non-inverting input port of the third operational amplifier, the variable resistor R3 is connected between the inverting input port of the third operational amplifier and the non-inverting input port of the fourth operational amplifier is connected with the inverting input port of the fourth operational amplifier;
the first variable gain operational amplifier controls the resistance values of the variable resistors R1, R2 and R3 through a multi-way switch, and different gains are obtained by changing the feedback coefficient of the negative feedback circuit;
the first operational amplifier is a constant transconductance rail-to-rail operational amplifier;
the constant transconductance rail-to-rail operational amplifier comprises a rail-to-rail input stage, a folding cascode operational amplifier and a classAB output stage;
the rail-to-rail operational amplifier with constant transconductance is characterized in that an internal differential input end of the rail-to-rail operational amplifier is connected with a rail-to-rail input stage circuit, the rail-to-rail input stage circuit is connected to a folded cascode operational amplifier circuit, and the output of the folded cascode operational amplifier is connected to a classAB output stage circuit;
the rail-to-rail input stage provides a wide input range;
the folded cascode operational amplifier provides gain;
the classAB output stage provides a wide output range.
The DCOC direct current offset cancellation circuit comprises a first low-pass filter, a second low-pass filter, a first comparator C1, a second comparator C2, a digital logic module and a numerical control current source module, and is used for counteracting the influence of larger input offset voltage generated by other factors at an input end on an alternating current signal path signal;
the digital control circuit is characterized in that an input port of the first low-pass filter is connected with an in-phase output port of the second variable gain operational amplifier, an input port of the second low-pass filter is connected with an inverted output port of the second variable gain operational amplifier, an output port of the first low-pass filter is connected with an input port of the first comparator, an output port of the second low-pass filter is connected with an input port of the second comparator, an output port of the first comparator is connected with a positive input port of the digital logic module, an output port of the second comparator is connected with a negative input port of the digital logic module, an output port of the digital logic module is connected with a control port of the digital control current source, and current outputs of the digital control current source module are connected to two ends of an input resistor of the input end to form a current loop;
the output signal output by the in-phase output port of the programmable gain amplifier is extracted by a first filter to obtain a direct current level, the direct current level is compared by a first comparator and then is transmitted to a digital logic module, the direct current level is extracted by a second filter and then is compared by a second comparator and then is transmitted to the digital logic module, the digital logic module judges whether to start compensation or not through the digital signal obtained by comparison, and when the output of the first comparator or the second comparator is 1, after the compensation is started, a switching current source controlled by digital logic can be used for pouring current into an input resistor to generate a certain voltage drop, and the voltage drop generated on the resistor can be offset with the input offset voltage. When compensation is started, only the first path of compensation is performed, whether the output continues to need to be increased by the compensation value is detected in a very short time, if the output needs to be increased or decreased, the digital logic can control to turn on or off more switching current sources until the offset voltage approaches 0.
The digital logic module generates 10-bit output to control the circulation of ten paths of currents, when the input signal is 10, which represents that the compensation current is insufficient, the control switch is used for pouring more currents, the input signal is 01, which represents that the compensation current is overlarge, the control switch is used for pouring less currents, the input signal is 00, which represents that the compensation is completed, and the state of the switch is maintained. The current in the compensation circuit is obtained by using current source mirror images, the sizes of two adjacent current sources are 2 times of weighting relation, for example, when the direct current offset reaches 500mV, the purpose of efficiently compensating input offset can be achieved by outputting only 0.5mV under the condition that 500mV offset voltage is input.
The digital logic module enables the current fed back to the input end not to contain alternating current signals, so that the problem of unstable loop is solved, and the maximum current of the DCOC is related to the feedback resistance of the DCOC, so that the DCOC can be effectively controlled within the range. For example, when the direct current offset reaches 500mV, the switch is closed, ten paths of current flow into the compensation resistor at the same time, the voltage drop reaches 500mV, when the offset is smaller than 500mV, only a few paths of current flow are poured, but if the comparison is started according to the condition of 0000000000 of the total of the simple method, the compensation process can be completed after 1024 times of comparison when the offset voltage is 500mV, so that the building time is too slow, and a binary algorithm is used in the digital logic part, so that each compensation is controlled within 10 times of comparison, and the building time is greatly reduced.
The foregoing is merely a preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A programmable gain amplification circuit with DCOC digital calibration, comprising: the input end of the programmable gain amplifying circuit is connected with the signal input end through a resistor, the in-phase output end of the programmable gain amplifying circuit is connected with the positive input end of the DCOC direct current offset eliminating circuit, the reverse output end of the programmable gain amplifying circuit is connected with the negative input end of the DCOC direct current offset eliminating circuit, and the output end of the DCOC direct current offset eliminating circuit is respectively connected with the input end of the programmable gain amplifying circuit and the signal input end.
2. The programmable gain amplification circuit with DCOC digital calibration of claim 1, wherein the programmable gain amplification circuit comprises a first variable gain operational amplifier module and a second variable gain operational amplifier module;
the non-inverting output end of the first variable gain operational amplifier module is connected with the non-inverting input end of the second variable gain operational amplifier module, and the inverting output end of the first variable gain operational amplifier module is connected with the inverting input end of the second variable gain operational amplifier module.
3. The programmable gain amplification circuit with DCOC digital calibration of claim 1, wherein the programmable gain amplification circuit has an input coupled to the signal input via a resistor comprising:
the non-inverting input end of the programmable gain amplifying circuit is connected with the positive signal input end through a first resistor R1, and the inverting input end of the programmable gain amplifying circuit is connected with the negative signal input through a second resistor R2.
4. The programmable gain amplification circuit with DCOC digital calibration of claim 2, wherein said first variable gain operational amplifier and said second variable gain operational amplifier are identical in structure, each comprised of a plurality of operational amplifiers and a plurality of variable resistors;
the operational amplifiers comprise a first operational amplifier OTA1, a second operational amplifier OTA2, a third operational amplifier OTA3 and a fourth operational amplifier OTA4;
the output ends of the first operational amplifier OTA1 and the third operational amplifier OTA3 are respectively connected with the non-inverting input ends of the second operational amplifier OTA2 and the fourth operational amplifier OTA4; the first operational amplifier OTA1, the second operational amplifier OTA2, the third operational amplifier OTA3 and the fourth operational amplifier OTA4 are all in a negative feedback state;
the variable resistors comprise a variable resistor R1, a variable resistor R2 and a variable resistor R3;
the output end of the first operational amplifier OTA1 is connected with the reverse input end of the first operational amplifier OTA1 through a variable resistor R1, the third operational amplifier OTA3 is connected with the reverse input end of the third operational amplifier OTA3 through a variable resistor R3, and the output end of the first operational amplifier OTA1 is connected with the output end of the third operational amplifier OTA3 through a variable resistor R3.
5. The programmable gain amplifier circuit with DCOC digital calibration of claim 4, wherein the operational amplifier is a constant transconductance rail-to-rail operational amplifier.
6. The programmable gain amplifier circuit with DCOC digital calibration of claim 1, wherein the DCOC dc offset cancellation circuit comprises: the device comprises a low-pass filter module, a comparator module, a digital logic module and a numerical control current source module;
the output end of the low-pass filter module is connected with the forward input end of the comparator module, the output end of the comparator module is connected with the reverse input end of the digital logic module, the output end of the digital logic module is connected with the control end of the numerical control current source module, and the current output end of the numerical control current source module is connected with the two ends of the first resistor R1 and the two ends of the second resistor R2.
7. The programmable gain amplification circuit with DCOC digital calibration of claim 6, wherein the low pass filter module comprises a first low pass filter and a second low pass filter; the comparator module comprises a first comparator and a second comparator;
the output port of the first low-pass filter is connected with the positive input end of the first comparator, and the output end of the second low-pass filter is connected with the positive input end of the second comparator.
8. A method for implementing a programmable gain amplification circuit with DCOC digital calibration, characterized in that a programmable gain amplification circuit with DCOC digital calibration according to any one of claims 1-8 is used, comprising the steps of:
controlling a variable resistor of a programmable gain operational amplifier circuit, and changing the gain of the programmable operational amplifier circuit;
meanwhile, the DCOC direct current offset cancellation circuit acquires a direct current signal at the output end of the programmable operational amplification circuit, and outputs different compensation currents based on the direct current signal;
the compensation current is input to the input end of the programmable gain operational amplifier circuit, and the direct current offset voltage of the input end of the programmable gain operational amplifier circuit is eliminated.
9. The method of claim 8, wherein the programmable gain operational amplifier circuit expands the gain range of the programmable gain operational amplifier circuit by a constant transconductance rail-to-rail operational amplifier.
10. The method of claim 8, wherein the DCOC dc offset cancellation circuit controls the output of the compensation current via a digital logic module.
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| Publication number | Publication date |
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| CN116032283B (en) | 2023-09-22 |
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