WO2010134287A1 - Pll周波数シンセサイザ - Google Patents
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- WO2010134287A1 WO2010134287A1 PCT/JP2010/003197 JP2010003197W WO2010134287A1 WO 2010134287 A1 WO2010134287 A1 WO 2010134287A1 JP 2010003197 W JP2010003197 W JP 2010003197W WO 2010134287 A1 WO2010134287 A1 WO 2010134287A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
- H03L2207/50—All digital phase-locked loop
Definitions
- the present invention relates to a PLL frequency synthesizer used for a wireless communication device, a wireless measuring device, and the like.
- FIG. 1 is a diagram showing a configuration of a conventional ADPLL frequency synthesizer disclosed in Patent Document 1. As shown in FIG.
- a digitally controlled oscillator (DCO) 1 includes an inductor element 2, a negative resistance element 3, a varactor array 4, and a varactor array 5.
- Each of the varactor array 4 and the varactor array 5 has a plurality of varactors. All varactors have the same capacity. The capacity value of each varactor is controlled by a binary control signal. Then, by controlling the capacitance value of the varactor, the oscillation frequency f CKV of the DCO 1 is controlled.
- This oscillation frequency f CKV is expressed by Expression (1) using the total capacitance value C of the varactor array 4 and the varactor array 5 and the inductance value L of the inductor element 2.
- the capacity value of the varactor is controlled as follows. First, the phase comparator 9 compares the phase of the reference signal F REF with the phase of the output CKV of the DCO 1 to generate a phase error signal. Then, the loop filter 11 filters the phase error signal and outputs the filtered phase error signal as the DCO control signal TUNE_T.
- the TUNE_T signal is composed of an integer part and a decimal part. The integer part is input to the tracking varactor control unit 6, and the decimal part is input to the tracking varactor control unit 7.
- the tracking varactor control unit 6 converts the integer part into an OTW (Oscillator ⁇ ⁇ Tuning ⁇ Word) Integrer signal, and outputs the OTW Integrer signal to the varactor array 4 to adjust the capacity of the varactor array 4.
- the tracking varactor control section 7 adjusts the capacity of the varactor array 5 by converting the decimal part into an OTW Fract signal and outputting the OTW Fract signal to the varactor array 5.
- the tracking varactor control unit 7 includes a ⁇ modulator.
- a negative feedback system is configured and a PLL (Phase Locked Loop) operation is performed.
- PLL Phase Locked Loop
- the tracking varactor control unit 6 operates in synchronization with the CKR clock which is a signal obtained by retiming the reference signal F REF with CKV
- the tracking varactor control unit 7 is a signal obtained by dividing the CKV by the frequency divider 8. It operates in synchronization with a certain CKVD clock.
- the CKVD frequency is set sufficiently higher than the CKR frequency.
- the output of the ⁇ modulator (that is, OTW Fract) fluctuates at almost any of 1, 2, and 3 in order to set the average value to 1.02. It changes from the state where it was present to a state that fluctuates at almost any of the values 0, 1, and 2.
- the value of OTW Integrer changes from 250 to 251 after the change timing of OTW Fract.
- Such a phenomenon in which an error between the TUNE_T target value and OTW (Total) temporarily increases can occur even when a “carry” occurs.
- the target value of TUNE_T is 252.06 close to the integer value 252 and the actual value of TUNE_T at a certain rise time of CKR is 252.02.
- the value of OTW Integrer is 251 and the value of OTW Fract is 1.02.
- the output of the ⁇ modulator is almost 0, It fluctuates depending on the value of 1 or 2.
- the error between the target value of TUNE_T and the average value of OTW (Total) which is the sum of OTWOIntegrer and OTW Fract, is approximately zero.
- the output of the ⁇ modulator (that is, OTWcFract) fluctuates almost between 0, 1 and 2 in order to make the average value 1.99. It changes from the state that has been changed to a state that fluctuates at almost any one of values 1, 2, and 3. On the other hand, due to the difference in the frequency of the clock signal, the value of OTW Integrer changes from 251 to 250 after the change timing of OTW Fract.
- the present invention has been made in view of this point, and an object thereof is to provide a PLL frequency synthesizer that improves phase noise characteristics.
- a PLL frequency synthesizer includes an oscillating unit including a first capacitive element group including a plurality of variable capacitive elements and a second capacitive element group including a plurality of variable capacitive elements, and a phase of an output signal of the oscillating unit.
- a phase error signal corresponding to a difference between the phase of the reference signal and a phase error signal, a capacitance value of the first capacitive element group is controlled by an integer part of the phase error signal, and a fractional part of the phase error signal
- An oscillation frequency control means for controlling an output frequency of the oscillating unit by controlling a capacitance value of the two capacitive element groups, wherein the value of the decimal part and the value of the decimal part
- An adjustment signal generating means for generating an adjustment signal based on a comparison result between a difference from an integer value closest to the predetermined value and a predetermined threshold, and the oscillation unit based on the adjustment signal It adopts a configuration comprising a frequency characteristic shifting means for shifting the oscillation frequency characteristics, a.
- a PLL frequency synthesizer that improves phase noise characteristics can be provided.
- the figure which shows the structure of the conventional ADPLL frequency synthesizer 1 is a block diagram showing a schematic configuration of an ADPLL frequency synthesizer according to an embodiment of the present invention.
- Diagram for explaining oscillation frequency characteristic shift Flow diagram showing the operation of the ADPLL frequency synthesizer
- Fig. 5 is an enlarged view of the time zone in which carry or carry occurs.
- Diagram showing the calculation results of phase noise characteristics The figure which shows the modification of the means to shift the basic characteristic of an oscillation frequency
- FIG. 2 is a block diagram showing a schematic configuration of an ADPLL frequency synthesizer according to an embodiment of the present invention.
- an ADPLL frequency synthesizer 100 includes a digitally controlled oscillator (DCO) 110, a frequency divider 120, a flip-flop 130, a phase comparator 140, a loop filter 150, tracking varactor controllers 160 and 170, A frequency characteristic adjusting unit 180.
- DCO digitally controlled oscillator
- the frequency divider 120, the flip-flop 130, the phase comparator 140, the loop filter 150, and the tracking varactor control units 160 and 170 are basically the same as the corresponding function units of the ADPLL frequency synthesizer shown in FIG. It has the same configuration.
- the digitally controlled oscillator 110 includes an inductor element 111, a negative resistance element 112, a varactor array 113, a varactor array 114, and an additional varactor 115.
- the inductor element 111, the negative resistance element 112, the varactor array 113, and the varactor array 114 have basically the same configuration as the corresponding functional unit of the ADPLL frequency synthesizer shown in FIG.
- Each of the varactor array 113 and the varactor array 114 includes a plurality of varactors (variable capacitance elements).
- the capacity value of each varactor is the same value COTW .
- the capacity of the varactor array 113 is controlled by an OTW Integrer signal received from the tracking varactor control unit 160.
- the capacity of the varactor array 114 is controlled by an OTW Fract signal received from the tracking varactor control unit 170.
- the capacity value of the additional varactor 115 changes based on the adjustment signal received from the frequency characteristic adjustment unit 180.
- the oscillation frequency f CKV of the DCO 110 is calculated by using the total capacitance value C of the varactor array 113 and the varactor array 114, the inductance value L of the inductor element 111, and the capacitance value C offset of the additional varactor 115. It is represented by
- the frequency divider 120 divides the oscillation signal CKV of the DCO 110 and outputs the CKVD to the tracking varactor control unit 170.
- the flip-flop 130 retimates the reference signal F REF with CKV, and outputs CKR to the tracking varactor control unit 160.
- the phase comparator 140 compares the phase of the reference signal F REF with the phase of the output signal CKV of the DCO 110 to generate a phase error signal.
- the loop filter 150 filters the phase error signal and outputs the filtered phase error signal as the DCO control signal TUNE_T.
- the tracking varactor control unit 160 adjusts the capacity of the varactor array 113 by converting the integer part of the DCO control signal TUNE_T into an OTW / Integrer signal and outputting the OTW / Integrer signal to the varactor array 113.
- the tracking varactor control unit 170 adjusts the capacity of the varactor array 114 by converting the decimal part of the DCO control signal TUNE_T into an OTW Fract signal and outputting the OTW Fract signal to the varactor array 114.
- the tracking varactor control unit 170 includes a ⁇ modulator.
- the output frequency of the DCO 110 is controlled by controlling the capacitance values of the varactor array 113 and the varactor array 114 by the phase comparator 140, the loop filter 150, and the tracking varactor control units 160 and 170.
- the frequency characteristic adjustment unit 180 receives the decimal part of the PLL lock detection signal and the DCO control signal TUNE_T, compares the difference between the value of the decimal part of the DCO control signal TUNE_T and the nearest integer value, and a predetermined threshold value, and compares them. An adjustment signal is generated based on the result. That is, after detecting lock, the frequency characteristic adjustment unit 180 determines whether the value of the DCO control signal TUNE_T is near an integer value, and controls the capacitance value of the additional varactor 115 when it is determined that the value is near the integer value. A signal OTW offset is generated. This adjustment signal is output to the additional varactor 115 and the additional varactor 115 is turned on or off, so that the basic characteristics of the transmission frequency determined by the capacity of the varactor array 113 and the varactor array 114 are adjusted.
- FIG. 4 is a flowchart showing the operation of the ADPLL frequency synthesizer 100.
- the C offset is turned off (S1), and the tracking operation is performed until the oscillation frequency of the DCO 110 converges (PLL lock) to a desired frequency range (that is, the target range). Is performed (S2, S3).
- the frequency characteristic adjustment unit 180 determines whether or not the value of the decimal part of the DCO control signal TUNE_T is within a predetermined range (S4).
- the ADPLL frequency synthesizer 100 continues tracking while keeping the C offset off state.
- C offset is changed to the ON state (S5), and tracking is continued.
- the predetermined range determined to be near the integer value is 1 ⁇ TUNE_T decimal part ⁇ 1.1 or 1.9 ⁇ TUNE_T decimal part ⁇ 2. That is, the frequency characteristic adjustment unit 180 compares the difference between the decimal part value and the nearest integer value with a predetermined threshold (here, 0.1).
- FIGS. 5A to 5F respectively show TUNE_T Integrer signal, TUNE_T Fract signal, OTW Integrator signal, OTW Fract signal, OTW (Total), and OTW offset time variation waveforms.
- the tracking varactor control unit 170 uses a secondary ⁇ modulator.
- an integer value of 0 to 3 is instantaneously output in synchronization with the rising edge of CKVD, but a value including a decimal is realized when viewed on a time average, and the DCO oscillation frequency resolution Has been improved.
- the capacitance value C offset of the additional varactor 115 is 1.5 C OTW .
- the target value of the DCO control signal TUNE_T is 252.06, and carry and carry are repeated (see FIGS. 5A and 5C). Specifically, before the time 2500 usec, a phenomenon occurs in which the error between the actual value of OTW (Total) and the target value of TUNE_T jumps up to around ⁇ 2 when the carry or carry down occurs. .
- the oscillation frequency characteristic of DCO 1 is changed. That is, after time 2500 usec, the target value of the DCO control signal TUNE_T is 253.56. This eliminates carry and carry, and OTW (Total) reconverges about 100 usec after the OTW offset changes (see FIG. 5E). After time 2600 usec after reconvergence, the absolute value of the error between the value of OTW (Total) and the target value of TUNE_T is stable at about ⁇ 1.5 at the maximum.
- FIG. 6 is an enlarged view of a time zone in which a carry or a carry has occurred in FIG. 5 (that is, a time zone before time 2500 usec).
- OTW OIntegrer FIG. 6C
- OTW Fract FIG. 6D
- the timing of the change is shifted at the time of carry or carry, and as a result, the error between the desired TUNE_T value and OTW (Total)
- FIGS. 6A, B, and E the clock varactor control unit 160 and the tracking varactor control unit 170 have different clock frequencies and clock timings as described above.
- FIG. 7 is a diagram showing the calculation result of the phase noise characteristics.
- FIG. 7A shows the phase noise characteristics calculated in the time zone in which the carry or the carry-down occurs in FIG. 5 (that is, the time zone before time 2500 usec).
- FIG. 7B shows the phase noise characteristics calculated after time 2600 usec after reconvergence in FIG.
- FIG. 7A it can be seen that the phase noise characteristic (Closed-Loop) of the ADPLL at 4 MHz offset or more is particularly deteriorated.
- FIG. 7B the TUNE_T value converges stably as shown in FIG. 5, so that the phase noise characteristic (Closed-Loop) degradation as seen in FIG. 7A is not observed. That is, the ADPLL frequency synthesizer 100 according to the present embodiment adjusts the frequency characteristics when it is determined that the target value carry-up or carry-down of the current DCO control signal TUNE_T is within a high probability range.
- the unit 180 performs control to shift the oscillation frequency characteristic, it is possible to prevent deterioration of the phase noise characteristic.
- the open-loop phase noise characteristics of FIGS. 7A and 7B are exactly the same, and are shown together to make the difference in phase noise characteristics (Closed-Loop) easier to understand.
- the digitally controlled oscillator 110 as the oscillation unit includes the first capacitive element group (varactor array 113) including a plurality of variable capacitive elements and the plurality of variable capacitors.
- a phase comparator 140 serving as an oscillation frequency control means, a loop filter 150, and tracking varactor control units 160 and 170 are included in the output of the digitally controlled oscillator 110.
- a phase error signal corresponding to the difference between the phase of the signal and the phase of the reference signal is generated, the capacitance value of the varactor array 113 is controlled by the integer part of the phase error signal, and the capacitance of the varactor array 114 is controlled by the decimal part of the phase error signal By controlling the value, the output frequency of the digitally controlled oscillator 110 is To your.
- the frequency characteristic adjustment unit 180 as the adjustment signal generation unit compares the difference between the decimal part value of the DCO control signal TUNE_T and the nearest integer value with a predetermined threshold value, and the comparison result is obtained. Based on the adjustment signal received from the frequency characteristic adjustment unit 180, the additional varactor 115 serving as a frequency characteristic shift means shifts the oscillation frequency characteristic.
- the target of the decimal part of the DCO control signal TUNE_T is set in the range in which the carry or carry occurrence probability is high.
- the oscillation frequency characteristic can be shifted. This shift of the oscillation frequency characteristic can shift the target value of the decimal part of the DCO control signal TUNE_T to a range where the probability of occurrence of carry or carry is low, so that the phase noise characteristic of the ADPLL frequency synthesizer deteriorates. Can be prevented.
- the frequency characteristic adjustment unit 180 performs the determination using the instantaneous value of the DCO control signal TUNE_T in a PLL locked state.
- the present invention is not limited to this, and the frequency characteristic adjustment unit 180 may determine using the average value of the DCO control signal TUNE_T. By doing so, even when the value of TUNE_T instantaneously falls within a predetermined range determined to be near the integer value due to noise mixing or the like, it is possible to prevent a control malfunction due to an erroneous output of OTW offset .
- the predetermined range does not need to be fixed, and may be changed depending on the order of the ⁇ modulator provided in the tracking varactor control unit 170 or the CKV frequency.
- the capacitance value C offset of the additional varactor 115 takes a binary value of 1.5 C OTW or 0 by binary control.
- FIG. 8 is a block diagram of the DCO 110A when a plurality of additional varactors are provided.
- the frequency characteristic may be controlled. That is, when the value of the decimal part of the DCO control signal TUNE_T is in the first predetermined range (1 ⁇ TUNE_T decimal part ⁇ 1.1 or 1.9 ⁇ TUNE_T decimal part ⁇ 2), the capacity is 0.5 C OTW. Turn on the additional varactor.
- the oscillation frequency characteristic may be controlled so that the decimal part of the target value of the DCO control signal is close to 0.5. If multi-value control is performed in this manner, the probability of occurrence of carry or carry at the time of convergence of the DCO control signal can be further reduced as compared with the case of binary control.
- FIG. 9 is a block diagram of a DCO 110B having a variable inductance element.
- the oscillation frequency can be changed. In this case, since only the variable inductance element can be controlled to change the oscillation frequency characteristics of the DCO 110B, the chip area is not increased.
- the frequency characteristic adjustment unit 180 receives the lock detection signal from the lock detection unit (not shown) as an input, and determines whether the value of the DCO control signal TUNE_T is within a predetermined range after the lock detection. Judging. Not limited to this, the frequency characteristic adjustment unit 180 recognizes or estimates the target value of the DCO control signal TUNE_T after lock detection before lock detection without using the lock detection signal, and the recognition value or estimated value is predetermined. It may be determined whether it is within the range. In this case, it is possible to converge to the target value of the DCO control signal that is less likely to cause a carry or a carry than when the target value of the DCO control signal is changed by changing the oscillation frequency characteristic of the DCO after lock detection.
- the frequency characteristic adjustment unit 180 is provided with a register that stores the amount of change in the DCO control signal TUNE_T every predetermined time.
- the target value of the DCO control signal TUNE_T can be estimated from the change amount.
- the target value of the DCO control signal TUNE_T with respect to the oscillation frequency of the DCO when the additional varactor is turned on and off is set. It is recorded in the memory table, and the frequency characteristic adjusting unit 180 can recognize the DCO control signal TUNE_T corresponding to the desired oscillation frequency with reference to the memory table.
- the frequency characteristic adjustment unit 180 is provided in the ADPLL frequency synthesizer.
- the frequency characteristic adjustment unit 180 is not limited to this, and may be provided in the communication device on which the ADPLL frequency synthesizer is mounted.
- an adjustment signal input terminal connected to the output terminal of the frequency characteristic adjustment unit 180 when the ADPLL frequency synthesizer is mounted on the communication device is provided on the input side of the additional varactor (or variable inductance element). .
- the PLL frequency synthesizer of the present invention is useful for improving the phase noise characteristics.
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Abstract
Description
110 デジタル制御発振器
111 インダクタ素子
112 負性抵抗素子
113,114 バラクタアレイ
115 付加バラクタ
120 分周器
130 フリップフロップ
140 位相比較器
150 ループフィルタ
160,170 トラッキングバラクタ制御部
180 周波数特性調整部
Claims (6)
- 複数の可変容量素子からなる第1の容量素子群と複数の可変容量素子からなる第2の容量素子群とを含む発振部と、
前記発振部の出力信号の位相と基準信号の位相との差分に対応する位相誤差信号を生成し、前記位相誤差信号の整数部によって前記第1の容量素子群の容量値を制御するとともに前記位相誤差信号の小数部によって前記第2の容量素子群の容量値を制御することにより、前記発振部の出力周波数を制御する発振周波数制御手段と、
を具備するPLL周波数シンセサイザであって、
前記小数部の値と前記小数部の値に最も近い整数値との差分と、所定の閾値との比較結果に基づいて、調整信号を生成する調整信号生成手段と、
前記発振部に設けられ、前記調整信号に基づいて前記発振部の発振周波数特性をシフトする周波数特性シフト手段と、
を具備するPLL周波数シンセサイザ。 - 前記周波数特性シフト手段は、可変容量素子からなり、
前記可変容量素子の容量値は、前記調整信号に基づいて変化する、
請求項1に記載のPLL周波数シンセサイザ。 - 前記可変容量素子の容量値は、前記第1の容量素子群及び前記第2の容量素子群を構成する可変容量素子の容量値の整数倍を除く値に設定される、
請求項2に記載のPLL周波数シンセサイザ。 - 前記周波数特性シフト手段は、複数の容量素子からなり、
前記複数の容量素子の容量値は互いに異なり、
前記複数の容量素子の少なくとも1つが、前記調整信号に基づいてオンする、
請求項1に記載のPLL周波数シンセサイザ。 - 前記調整信号生成手段は、前記発振周波数制御手段に含まれるデルタシグマ変調器の次数、又は前記発振部の出力周波数に基づいて、前記所定の閾値を変更する、
請求項1に記載のPLL周波数シンセサイザ。 - 前記周波数特性シフト手段は、可変インダクタ素子からなり、
前記可変インダクタ素子のインダクタンス値は、前記調整信号に基づいて変化する、
請求項1に記載のPLL周波数シンセサイザ。
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US13/319,221 US8525608B2 (en) | 2009-05-22 | 2010-05-11 | PLL frequency synthesizer |
JP2011514316A JP5367075B2 (ja) | 2009-05-22 | 2010-05-11 | Pll周波数シンセサイザ |
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US9641113B2 (en) | 2014-02-28 | 2017-05-02 | General Electric Company | System and method for controlling a power generation system based on PLL errors |
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US8953730B2 (en) | 2012-04-20 | 2015-02-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Auto frequency calibration for a phase locked loop and method of use |
JP6171522B2 (ja) * | 2013-04-16 | 2017-08-02 | 富士通株式会社 | デジタル制御発振器及び出力周波数制御方法 |
US20150116012A1 (en) * | 2013-10-30 | 2015-04-30 | Hasnain Lakdawala | Digital Voltage Ramp Generator |
US11277096B2 (en) | 2020-02-25 | 2022-03-15 | Stmicroelectronics International N.V. | Digitally controlled LC oscillator |
US11018680B1 (en) * | 2020-07-15 | 2021-05-25 | Keysight Technologies, Inc. | Phase lock loops (PLLS) and methods of initializing PLLS |
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JP2009010599A (ja) * | 2007-06-27 | 2009-01-15 | Panasonic Corp | デジタル制御発振回路、周波数シンセサイザ、それを用いた無線通信機器及びその制御方法 |
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JP2002076886A (ja) * | 2000-06-30 | 2002-03-15 | Texas Instruments Inc | デジタル小位相検出器 |
JP2004015387A (ja) * | 2002-06-06 | 2004-01-15 | Matsushita Electric Ind Co Ltd | 電圧制御型発振器及び周波数シンセサイザ |
JP2009504063A (ja) * | 2005-08-02 | 2009-01-29 | アールエフ マジック インコーポレイテッド | 多重周波数源システム及び動作方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US9641113B2 (en) | 2014-02-28 | 2017-05-02 | General Electric Company | System and method for controlling a power generation system based on PLL errors |
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US8525608B2 (en) | 2013-09-03 |
JP5367075B2 (ja) | 2013-12-11 |
US20120119839A1 (en) | 2012-05-17 |
JPWO2010134287A1 (ja) | 2012-11-08 |
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