WO2010110275A1 - 裏面入射型固体撮像素子 - Google Patents
裏面入射型固体撮像素子 Download PDFInfo
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- WO2010110275A1 WO2010110275A1 PCT/JP2010/055004 JP2010055004W WO2010110275A1 WO 2010110275 A1 WO2010110275 A1 WO 2010110275A1 JP 2010055004 W JP2010055004 W JP 2010055004W WO 2010110275 A1 WO2010110275 A1 WO 2010110275A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
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- H01L27/14831—Area CCD imagers
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- H—ELECTRICITY
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
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Definitions
- the present invention relates to a back-illuminated solid-state imaging device.
- BT (Back-illuminated Thinning) -CCD is known as a back-illuminated solid-state imaging device in which a light incident surface side of a substrate is thinned.
- interference etalon phenomenon
- the thickness of the photosensitive region is increased, and an antireflection film is further provided in the photosensitive region.
- the conventional BT-CCD solution technique sacrifices the inherent advantage of BT-CCD, which is improved detection sensitivity by thinning the film, and has not led to an essential improvement in image quality.
- the present invention has been made in view of such a problem, and an object thereof is to provide a back-illuminated solid-state imaging device capable of suppressing image deterioration due to an etalon phenomenon and improving image quality.
- a back-illuminated solid-state imaging device is provided on a semiconductor substrate having a light incident surface on the back surface side and a light detection surface opposite to the light incident surface of the semiconductor substrate.
- a back-illuminated solid-state imaging device having a plurality of charge transfer electrodes is characterized in that a plurality of light transmission openings are formed between adjacent ones of the charge transfer electrodes.
- the solid-state imaging device of the present invention Although the light incident on the back surface is detected on the light detection surface side, in the solid-state imaging device of the present invention, a part of the light used for light detection is originally transmitted to the outside through the opening. Thereby, since there is no charge transfer electrode in the opening, reflection is suppressed, and interference between incident light and reflected light is suppressed. Therefore, image degradation due to the etalon phenomenon is suppressed, and image quality is improved.
- the openings are preferably arranged in alignment along the charge transfer direction. As described above, when the openings formed between the adjacent charge transfer electrodes are aligned, the reflected light is suppressed although the configuration is simple. However, in this structure, alignment accuracy at the time of manufacturing the charge transfer electrode is required, and when the alignment accuracy is low, the area of the opening in the pixel for each column is different, and the characteristics of each pixel vary. There is room for further improvement.
- the openings are preferably arranged in a staggered manner along the charge transfer direction. That is, the openings are arranged alternately.
- the charge transfer electrodes in the odd-numbered rows p + 1 row and p + 3 row (p is an integer of 0 or more)) are formed at the same time, and the even-numbered rows (p + 2).
- the charge transfer electrodes of the (row) and (p + 4) rows are formed separately at the same time, the charge transfer electrodes of the even-numbered rows are shifted laterally during manufacturing, and an opening between the charge transfer electrodes of the (p + 1) th and p + 2th rows is formed.
- the opening area between the charge transfer electrodes in the p + 3 and p + 4 rows decreases. That is, this structure has a high tolerance of alignment accuracy, and the amount of transmitted light for each pixel becomes equal, and the characteristics become uniform.
- the charge transfer electrode in the (p + 1) th row has the first shape
- the charge transfer electrode in the (p + 2) th row has the second shape
- the charge transfer electrode in the (p + 3) th row has the first shape.
- the charge transfer electrodes in the p + 4th row have a fourth shape, the first to fourth shapes are all different from each other, and the first to fourth charge transfer electrodes are between the p + 1th row and the p + 2th row.
- a pattern opening is formed, and a second pattern opening is formed between the charge transfer electrodes in the p + 3 and p + 4 rows, and the first and second patterns are preferably different from each other.
- the shape of the charge transfer electrode and the pattern of the opening are different, the randomness of the opening is high.
- the charge transfer electrodes in the p + 2 and p + 4 rows are laterally displaced. Even in this case, fluctuations in the opening area can be suppressed.
- a back-illuminated solid-state imaging device includes a semiconductor substrate having a light incident surface on the back surface side, and a plurality of charge transfer electrodes provided on a light detection surface opposite to the light incident surface of the semiconductor substrate.
- a plurality of light transmitting openings are formed in each charge transfer electrode.
- a high-quality image can be acquired.
- FIG. 1 is a perspective view of a back-illuminated solid-state imaging device 100 according to an embodiment.
- FIG. 2 is a bottom view of the back-illuminated solid-state imaging device 100 as viewed from the side opposite to the light incident direction.
- FIG. 3 is a diagram showing the imaging region 10 and the horizontal shift register 20 formed on the front surface side (the side opposite to the light incident surface (back surface)).
- FIG. 4 is a vertical cross-sectional view of a pixel obtained by cutting one pixel along the XZ plane.
- FIG. 5 is a plan view of the imaging region for explaining the structure of the charge transfer electrode 2 (mp + 1 to mp + 17...) Of the comparative example. 6 is a cross-sectional view taken along the line BB in the pixel shown in FIG. FIG.
- FIG. 7 is a plan view of the imaging region for explaining the structure of the charge transfer electrodes 2 (mp + 1 to mp + 17%)
- FIG. 8 is a cross-sectional view taken along the line BB in the pixel shown in FIG.
- FIG. 9 is a plan view of the imaging region for explaining the structure of the charge transfer electrodes 2 (mp + 1 to mp + 17%)
- 10 is a cross-sectional view taken along the line B1-B1 in the pixel shown in FIG.
- FIG. 11 is a cross-sectional view taken along arrow B2-B2 in the pixel shown in FIG.
- FIG. 12 is a plan view of the imaging region for explaining the structure of the charge transfer electrodes 2 (mp + 1 to mp + 17%)
- FIG. 13 is a plan view of the imaging region for explaining the structure of the charge transfer electrode 2 (mp + 1 to mp + 17%) According to the embodiment.
- FIG. 1 is a perspective view of a back-illuminated solid-state imaging device 100 according to an embodiment.
- a three-dimensional orthogonal coordinate system including an X axis, a Y axis, and a Z axis orthogonal to each other is shown.
- the back-illuminated solid-state imaging device 100 is a BT-CCD (charge-coupled device) in which the back side of a semiconductor substrate is thinned by etching with a KOH aqueous solution or the like, and a concave portion TD is formed in the etched central region. There is a thick frame around the TD. Side surfaces 102 a, 102 b, 102 c, 102 d of the recess TD are inclined with an obtuse angle with respect to the bottom surface 101. Note that the frame portion may be removed by etching to form a back-illuminated solid-state imaging device in which the entire region is thinned.
- BT-CCD charge-coupled device
- the thinned central region of the semiconductor substrate is a light sensitive region (imaging region), and a light image L from an object enters the light sensitive region along the negative direction of the Z axis.
- the bottom surface 101 of the recess TD of the semiconductor substrate constitutes a light incident surface.
- an imaging CCD composed of a plurality of vertical shift registers is formed as a pixel.
- FIG. 2 is a bottom view of the back-illuminated solid-state imaging device 100 as viewed from the side opposite to the light incident direction.
- An imaging region 10 is formed in a region corresponding to the bottom surface 101 of the thinned semiconductor substrate.
- the light image incident on the imaging region 10 is converted into a two-dimensional charge image, and this charge is transferred along the negative direction of the Y axis.
- a horizontal shift register 20 is provided at the end of the imaging region 10 in the charge transfer direction, and the charges of each pixel transferred in the vertical direction are sequentially transferred along the X-axis direction.
- a plurality of electrode pads are provided on the frame portion of the back-illuminated solid-state imaging device 100.
- the main electrode pads are electrode pads P1V and P2V for applying a two-phase transfer voltage to the charge transfer electrode, electrode pads P1H and P2H for applying a two-phase transfer voltage to the charge transfer electrode, and the semiconductor substrate to ground.
- the electrode pad SS for connecting to the electrode pad, the electrode pad SG, OG, OD, RG, RD for reading out the charges transferred in the horizontal direction, and the output can be taken out from the electrode pad OS.
- Electrodes may be provided as appropriate according to specifications.
- the electrode pad TG for functioning the charge transfer gate to the horizontal shift register 20 and the electrode pad ISV for inputting a test signal are used.
- ISH and electrode pads 1G1V, 1G2V, 1G1H, 1G2H for functioning the charge transfer gates of these test signals.
- Known CCD charge transfer methods include a frame transfer method, an interline transfer method, and a full frame transfer method. Many such CCD structures are known and are not particularly limited. As an example, a full frame transfer CCD will be described.
- FIG. 3 is a diagram showing the imaging region 10 and the horizontal shift register 20 formed on the front surface side (the side opposite to the light incident surface (back surface)).
- This figure is a schematic diagram, and the shape of each transfer electrode extending in the X-axis direction is a rectangle, and there is a gap between them. A part or all of them are overlapped, and the shape thereof is set so as to have an opening for light transmission as will be described later.
- the imaging area 10 is formed by arranging a plurality of vertical shift registers n 1 to n N (N is an integer of 2 or more), that is, vertical charge transfer CCDs. Note that the actual imaging area is the central area of the imaging area 10, and surrounding pixels are shielded from light as necessary.
- the pixels in the vertical direction are arranged along the Y axis, and each of the charge transfer electrodes m 1 to m M (M is an integer of 2 or more) extends along the X axis.
- Charge transfer electrodes m 1 ⁇ m M, the electrode pads P1V, transfer voltage of two phases is applied from the P2V, charge transfer electrodes m 1 ⁇ m M accumulated in the semiconductor region directly below the vertical charge (Y-axis negative Direction).
- an isolation region having a conductivity type opposite to the charge flowing through the CCD channel is formed.
- the isolation region suppresses mutual mixing of charges from different pixel columns.
- the final position of the vertical charge transfer is provided with the transfer gate electrodes m T, depending on the voltage from the electrode pad TG, horizontal shift register via the potential immediately under the transfer gate electrodes m T from the imaging region 10 Charges will flow into 20.
- horizontal charge transfer CCDs that transfer charges in the horizontal direction (X-axis positive direction) are aligned along the X-axis, and are disposed on the semiconductor charge transfer region HSR extending in the X-axis direction.
- Charge transfer electrodes h 1 to h K (K is an integer of 2 or more) are provided, and these charge transfer electrodes are arranged along the X-axis direction.
- a charge readout circuit is provided at the final position of the X-axis charge transfer.
- the charge readout circuit includes a signal gate region located at the end of a horizontal shift register connected to the electrode pad SG. Next to this signal the gate region, the floating diffusion region FD is provided via a transistor to Q 1 MOS-FET structure. Floating diffusion region FD is connected to the reset drain electrode pads RD via the reset transistor Q 2, also connected to the gate electrode of the output transistor Q 3. One terminal of the output transistor Q 3 are connected to the overflow drain electrode pads OD, other constitutes an output terminal OS.
- a load resistor R is connected to the output terminal OS.
- the gate electrode of the transistor Q 2 is connected to the reset gate electrode pad RG.
- a suitable high level potential is applied to the electrode pads OG, OD, and RD throughout.
- the electrode pad SG and the electrode pad RG are set to high level, the potential of the floating diffusion region FD is set to the reset potential of the reset electrode pad RD, and then the electrode pad RG is set to low level.
- the output signal becomes a floating level.
- the electrode pad SG to a low level, the signal charge temporarily stored in the signal gate region flows into the floating diffusion region FD, and the output signal taken out from the electrode pad OS is stored in the amount of stored charge.
- the signal level according to.
- the remaining configuration is for performing a test operation.
- a test signal is input from the electrode pads ISV and ISH, and an appropriate potential is applied to the electrode pads IG1V, IG2V, IG1H, and IG2H, and the test operation is performed.
- Electrode pads ISV is connected to the electrode m V which is electrically connected to the semiconductor substrate, the electrode pads IG1V, IG2V is connected to the gate electrode m G1, m G2 provided via an insulating film on a CCD channel ing.
- FIG. 4 is a longitudinal sectional view of a pixel obtained by cutting one pixel along the XZ plane.
- Incident light L enters from the back surface (light incident surface) of the semiconductor substrate. That is, the semiconductor substrate has a light incident surface.
- the semiconductor substrate 4 includes a P-type semiconductor substrate 4C, an N-type semiconductor layer 4A formed on the P-type semiconductor substrate 4C, an accumulation layer 4D formed on the back side of the P-type semiconductor substrate 4C, and both sides of the CCD channel. And an isolation region 4B formed on the substrate.
- the P-type semiconductor substrate 4C and the N-type semiconductor layer 4A are in contact with each other to form a PN junction, and a buried channel CCD is configured.
- the N-type semiconductor layer 4A (PN junction) can be omitted, and in this case, the CCD functions as a surface channel CCD.
- the protective film 1 is made of BPSG (Boro-Phospho Silicate Glass)
- the charge transfer electrode 2 is made of polysilicon
- the insulating layer 3 is made of SiO 2
- the isolation region 4B and the accumulation layer 4D are both It is made of Si to which a high concentration P-type impurity is added.
- the high concentration means that the impurity concentration is higher than the impurity concentration of the P-type semiconductor substrate 4C, and is preferably a concentration of 1 ⁇ 19 cm 3 or more.
- a P-type semiconductor substrate 4C is prepared.
- the semiconductor substrate 4C is thinned.
- a mask is formed by patterning in a region corresponding to a pixel, and a P-type impurity is added to the substrate surface using an ion implantation method or a diffusion method to form an isolation region 4B, and then thermal oxidation is performed.
- the insulating layer 3 is formed on the isolation region 4B.
- the insulating layer 3 made of SiO 2 is also formed on the photodetecting surface of silicon.
- N-type impurities are ion-implanted into the semiconductor substrate through the insulating layer 3 to form an N-type semiconductor layer 4A in a region immediately below the insulating layer 3. Since the initial semiconductor substrate is a P-type semiconductor substrate 4C, a PN junction is formed between them. Next, a charge transfer electrode 2 made of a metal such as Al or polysilicon is formed on the insulating layer 3, and a protective film 1 made of BPSG is formed thereon.
- a high concentration P-type impurity is added to the back side of the semiconductor substrate 4 to form an accumulation layer 4D, and subsequently, an antireflection film 5 is formed on the accumulation layer 4D.
- the antireflection film 5 is made of a dielectric multilayer film, and is formed, for example, by laminating Si and Ge oxides.
- SiO 2 is formed after the formation of the lower charge transfer electrode 2.
- An insulating layer serving as a spacer is formed so as to be continuous with the original insulating layer 3, and an upper charge transfer electrode 2 is formed through the spacer. Since these forming processes are different, the alignment accuracy of the mask for forming the lower-layer (odd-numbered row) charge transfer electrode 2 and the mask for forming the upper-layer (even-numbered row) charge transfer electrode 2 is high. Required.
- FIG. 5 is a plan view of the imaging region for explaining the structure of the charge transfer electrode 2 (mp + 1 to mp + 17%) Of the comparative example, and shows a plurality of charge transfer electrodes extending in the X-axis direction and the Y-axis direction.
- An extended CCD channel n N (nk + 1 to nk + 4) is shown (where p and k are integers).
- a region surrounded by a dotted line PIXEL in the figure corresponds to one pixel.
- the cross-sectional view taken along the line AA in this pixel is the same as that shown in FIG.
- a low-concentration N-type semiconductor region 4A ′ is formed immediately below the upper-layer electrodes mp + 6, mp + 8, and mp + 10.
- Low concentration means an impurity concentration lower than that of the N-type semiconductor region 4A.
- the N-type semiconductor layer 4A and the low-concentration N-type semiconductor layer 4A ′ form the surface layer of the P-type semiconductor substrate 4C, and the low-concentration N-type semiconductor layer 4A ′ is between adjacent N-type semiconductor layers 4A. Is located.
- This low-concentration N-type semiconductor region 4A ' is formed so as to have an impurity concentration lower than that of the N-type semiconductor region 4A.
- a method for controlling the impurity concentration there are a method in which the formation time and the amount of impurities added are different, a method in which the thickness of the insulating layer 3 is increased on the low concentration side, and ion implantation is performed through this.
- the structure of this charge transfer electrode is a part of the comparative example that is cut away and constitutes a so-called open gate structure.
- FIG. 7 is a plan view of the imaging region for explaining the structure of the charge transfer electrodes 2 (mp + 1 to mp + 17...) According to the embodiment, and includes a plurality of charge transfer electrodes extending in the X-axis direction, and a Y-axis.
- a CCD channel n N (nk + 1 to nk + 4) extending in the direction is shown (where p and k are integers).
- a region surrounded by a dotted line PIXEL in the figure corresponds to one pixel.
- the cross-sectional view taken along the line AA in this pixel is the same as that shown in FIG.
- a low-concentration N-type semiconductor region 4A ′ is formed immediately below the upper-layer electrodes mp + 6, mp + 8, and mp + 10.
- This low-concentration N-type semiconductor region 4A ' is formed so as to have an impurity concentration lower than that of the N-type semiconductor region 4A.
- the method for controlling the impurity concentration is as described above.
- a part of the adjacent charge transfer electrodes 2 (mp + 1 to mp + 17%) Along the charge transfer direction (Y-axis) is overlapped.
- upper charge transfer electrodes mp + 6, mp + 8, mp + 10... are formed through the insulating layer 3 serving as a spacer.
- a plurality of light transmission openings OP are formed between the charge transfer electrodes 2 (mp + 1 to mp + 17%) Adjacent to each other along the Y-axis direction. Yes.
- the structure of the charge transfer electrode will be described in detail.
- the side not mentioned is a straight line parallel to the X axis.
- One side of the charge transfer electrode mp + 7 has a notch that is periodically recessed in a trapezoidal shape in the positive direction of the Y axis, and one side of the charge transfer electrode mp + 8 adjacent thereto has a period in the negative direction of the Y axis.
- it has a notch that is recessed in a trapezoidal shape, and the opening OP is defined by the two notches facing each other.
- an opening OP is formed between the notch portions of the adjacent charge transfer electrode mp + 9 and charge transfer electrode mp + 10.
- These four charge transfer electrodes mp + 7 to mp + 10 are included in the same pixel PIXEL.
- a high-concentration P-type semiconductor region 4C ′ is formed in a region immediately below the opening OP. Therefore, in such a region, no PN junction is formed and carriers are not accumulated.
- the light L incident on the back surface is detected on the light detection surface side, but in the solid-state imaging device of the present embodiment, a part of the light used for light detection is transmitted to the outside through the opening OP.
- a part of the light used for light detection is transmitted to the outside through the opening OP.
- the plurality of openings OP are arranged in alignment along the charge transfer direction (Y-axis direction).
- the configuration is simple.
- alignment accuracy at the time of manufacturing the lower and upper charge transfer electrodes is required, and when the alignment accuracy is low, the area of the opening OP in the pixel for each column is different.
- further improvement such as variations in characteristics.
- FIG. 9 is a plan view of the imaging region for explaining the structure of the charge transfer electrodes 2 (mp + 1 to mp + 17...)
- a plurality of charge transfer electrodes extending in the X-axis direction, and the Y-axis
- a CCD channel n N (nk + 1 to nk + 4) extending in the direction is shown (where p and k are integers).
- a region surrounded by a dotted line PIXEL in the figure corresponds to one pixel.
- the cross-sectional view taken along the line AA in this pixel is the same as that shown in FIG.
- FIG. 10 a cross-sectional view taken along arrow B1-B1 in this pixel is shown in FIG. 10, and a cross-sectional view taken along arrow B2-B2 is shown in FIG.
- a low-concentration N-type semiconductor region 4A ′ is formed immediately below the upper-layer electrodes mp + 6, mp + 8, and mp + 10.
- This low-concentration N-type semiconductor region 4A ' is formed so as to have an impurity concentration lower than that of the N-type semiconductor region 4A.
- the method for controlling the impurity concentration is as described above.
- a part of the adjacent charge transfer electrodes 2 (mp + 1 to mp + 17%) Along the charge transfer direction (Y-axis) is overlapped.
- upper charge transfer electrodes mp + 6, mp + 8, mp + 10... are formed through the insulating layer 3 serving as a spacer.
- a plurality of light transmission electrodes 2 Adjacent to each other along the Y-axis direction are arranged.
- An opening OP is formed.
- One side of the charge transfer electrode mp + 7 has a notch that is periodically recessed in a trapezoidal shape in the positive direction of the Y axis, and one side of the charge transfer electrode mp + 8 adjacent thereto has a period in the negative direction of the Y axis.
- it has a notch that is recessed in a trapezoidal shape, and the opening OP is defined by the two notches facing each other. The period along the X-axis direction of the formation position of these notches is the same.
- an opening OP is formed between the notch portions of the adjacent charge transfer electrode mp + 9 and charge transfer electrode mp + 10.
- the formation position of the notches of the charge transfer electrodes mp + 7 and mp + 8 is, in other words, the formation position along the X-axis direction.
- the phase is inverted.
- These four charge transfer electrodes mp + 7 to mp + 10 are included in the same pixel PIXEL.
- a high-concentration P-type semiconductor region 4C ′ is formed in the region immediately below the opening OP. Therefore, in such a region, no PN junction is formed and carriers are not accumulated.
- the openings OP are arranged in a staggered manner along the charge transfer direction (Y-axis direction). That is, the openings OP are arranged alternately.
- the odd-numbered charge transfer electrodes mp + 1, mp + 3, mp + 5, mp + 7...) Located in the lower layer are simultaneously formed, and the even-numbered rows (mp + 2, mp + 4, mp + 6, mp + 8,.
- the charge transfer electrode (1) is formed at the same time after the formation of the lower electrode. Therefore, when the staggered opening arrangement as in the present embodiment is adopted, the charge transfer electrodes in the even-numbered rows are shifted in the horizontal direction during manufacturing, for example, an opening between the charge transfer electrode mp + 7 and the charge transfer electrode mp + 8.
- this structure has a high tolerance of alignment accuracy, and the amount of transmitted light for each pixel is equal, and has the advantage of uniform characteristics, and the occurrence of a fixed noise pattern is also suppressed.
- FIG. 12 is a plan view of an imaging region for explaining the structure of the charge transfer electrodes 2 (mp + 1 to mp + 17).
- a plurality of charge transfer electrodes extending in the X-axis direction, and the Y-axis CCD channels n N (nk + 1 to nk + 4) extending in the direction are shown (where p and k are integers).
- a region surrounded by a dotted line PIXEL in the figure corresponds to one pixel.
- the only difference from the above embodiment is the shape and arrangement of the charge transfer electrodes 2 (mp + 1 to mp + 17).
- the other configuration is the same as that described above except that a P-type impurity is added immediately below the opening OP to form a P-type semiconductor region 4C ′ as shown in FIG. 8, FIG. 10, or FIG. This is the same as the embodiment. Further, the cross-sectional structure of the pixel cut along a plane perpendicular to the charge transfer direction (Y axis) and not passing through the opening is the same as that shown in FIG.
- the charge transfer electrode mp + 7 has a first shape
- the charge transfer electrode mp + 8 has a second shape
- the charge transfer electrode mp + 9 has a third shape
- the charge transfer electrode p + 4 has a fourth shape.
- These first to fourth shapes are all different from each other, and these four shapes are repeated along the charge transfer direction for each pixel.
- the first shape of the charge transfer electrode mp + 7 has a cutout portion whose one side is periodically recessed in a trapezoidal shape in the positive direction of the Y axis.
- the second shape of the charge transfer electrode mp + 8 has a cutout portion with one side periodically recessed in a trapezoidal shape in the negative Y-axis direction, but the cycle is the same as that of the charge transfer electrode mp + 7. Thus, the length of the innermost side of the notch is different from that of the charge transfer electrode mp + 7.
- the cutout portions of the charge transfer electrode mp + 7 and the charge transfer electrode mp + 8 face each other to form an opening OP of the first pattern.
- the third shape of the charge transfer electrode mp + 9 has a cutout portion with one side periodically recessed in a trapezoidal shape or a triangular shape in the positive direction of the Y-axis.
- the number of notches per unit length in the X-axis direction is larger than the number of notches in the charge transfer electrodes mp + 7 and mp + 8.
- the trapezoidal cutouts and the triangular cutouts are alternately formed along the X axis.
- the fourth shape of the charge transfer electrode mp + 10 has a cutout portion with one side periodically recessed in a trapezoidal shape in the negative Y-axis direction, but the cycle is the same as that of the charge transfer electrode mp + 9.
- the length of the innermost side of the notch is longer than the length of the innermost side of the trapezoidal notch in the charge transfer electrode mp + 9.
- the cutout portions of the charge transfer electrode mp + 9 and the charge transfer electrode mp + 10 face each other to form the opening OP of the second pattern. Further, the first pattern and the second pattern of the opening OP are different from each other.
- the general shape of the charge transfer electrode is such that when p is an integer greater than or equal to 0, the charge transfer electrode in the (p + 1) th row has the first shape, and the charge transfer electrode in the (p + 2) th row has the second shape. , The charge transfer electrode in the (p + 3) th row has a third shape, and the charge transfer electrode in the (p + 4) th row has a fourth shape.
- FIG. 13 is a plan view of an imaging region for explaining the structure of the charge transfer electrodes 2 (mp + 1 to mp + 17%)
- a CCD channel n N (nk + 1 to nk + 4) extending in the axial direction is shown (where p and k are integers).
- a region surrounded by a dotted line PIXEL in the figure corresponds to one pixel.
- each of the charge transfer electrodes 2 (mp + 1 to mp + 17%) Linearly extending along the X axis has a plurality of openings OP.
- a P-type impurity is added immediately below, and a P-type semiconductor region 4C ′ as shown in FIG. 8, FIG. 10, or FIG. 11 is formed immediately below the opening OP.
- Other configurations are the same as those of the above-described comparative example.
- the cross-sectional structure of the pixel cut along a plane perpendicular to the charge transfer direction (Y axis) and not passing through the opening is the same as that shown in FIG. Note that the number and arrangement of the openings OP in each pixel are the same.
- a plurality of light transmission openings OP are formed in each charge transfer electrode 2 (mp + 1 to mp + 17). The portion is transmitted to the outside through the opening OP.
- the present invention is not limited to the above embodiment, and for example, a compound semiconductor such as GaAs or GaN can be used as the semiconductor material.
- SYMBOLS 100 Back-illuminated solid-state image sensor, L ... Incident light, 1 ... Protective film, 2 ... Charge transfer electrode, 3 ... Insulating layer, 4 ... Semiconductor substrate, 5 ... Antireflection film, 4A ... N-type semiconductor layer, 4B ... Isolation region, 4C... P-type semiconductor substrate, 4D... Accumulation layer.
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Abstract
Description
Claims (5)
- 裏面側に光入射面を有する半導体基板と、
前記半導体基板の前記光入射面とは反対側の光検出面に設けられた複数の電荷転送電極と、を備えた裏面入射型固体撮像素子において、
前記電荷転送電極の隣接するもの同士の間に、光透過用の複数の開口部が形成されていることを特徴とする裏面入射型固体撮像素子。 - 前記開口部は、電荷転送方向に沿って整列して配置されていることを特徴とする請求項1に記載の裏面入射型固体撮像素子。
- 前記開口部は、電荷転送方向に沿って千鳥状に配置されていることを特徴とする請求項1に記載の裏面入射型固体撮像素子。
- pは0以上の整数であり、
p+1行目の前記電荷転送電極は第1形状を有し、
p+2行目の前記電荷転送電極は第2形状を有し、
p+3行目の前記電荷転送電極は第3形状を有し、
p+4行目の前記電荷転送電極は第4形状を有し、
前記第1乃至第4形状は互いに全て異なり、
p+1行目とp+2行目の前記電荷転送電極との間には第1パターンの前記開口部が形成され、
p+3行目とp+4行目の前記電荷転送電極との間には第2パターンの前記開口部が形成され、
前記第1及び第2パターンは互いに異なっている、ことを特徴とする請求項1に記載の裏面入射型固体撮像素子。 - 裏面側に光入射面を有する半導体基板と、
前記半導体基板の前記光入射面とは反対側の光検出面に設けられた複数の電荷転送電極と、を備えた裏面入射型固体撮像素子において、
各電荷転送電極内に、光透過用の複数の開口部が形成されていることを特徴とする裏面入射型固体撮像素子。
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CN201080014116.0A CN102365743B (zh) | 2009-03-27 | 2010-03-23 | 背面入射型固体摄像元件 |
EP10756071.6A EP2413361B1 (en) | 2009-03-27 | 2010-03-23 | Back-illuminated solid-state image pickup device |
US13/258,696 US8624301B2 (en) | 2009-03-27 | 2010-03-23 | Back-illuminated solid-state image pickup device |
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JP2009079563A JP5410808B2 (ja) | 2009-03-27 | 2009-03-27 | 裏面入射型固体撮像素子 |
JP2009-079563 | 2009-03-27 |
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US (1) | US8624301B2 (ja) |
EP (1) | EP2413361B1 (ja) |
JP (1) | JP5410808B2 (ja) |
KR (1) | KR101653435B1 (ja) |
CN (1) | CN102365743B (ja) |
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JP5410808B2 (ja) * | 2009-03-27 | 2014-02-05 | 浜松ホトニクス株式会社 | 裏面入射型固体撮像素子 |
JP6306989B2 (ja) | 2014-09-09 | 2018-04-04 | 浜松ホトニクス株式会社 | 裏面入射型固体撮像装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02168669A (ja) * | 1988-09-14 | 1990-06-28 | Mitsubishi Electric Corp | 固体撮像素子 |
JP2001057418A (ja) * | 1999-08-18 | 2001-02-27 | Fuji Film Microdevices Co Ltd | 固体撮像素子 |
JP2002231925A (ja) * | 2001-01-31 | 2002-08-16 | Hamamatsu Photonics Kk | 半導体エネルギー線検出器 |
JP2003078826A (ja) * | 2001-09-06 | 2003-03-14 | Sony Corp | 固体撮像素子 |
JP2004241653A (ja) * | 2003-02-06 | 2004-08-26 | Hamamatsu Photonics Kk | X線撮像素子 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6125391A (ja) * | 1984-07-13 | 1986-02-04 | Sanyo Electric Co Ltd | カラ−固体撮像装置 |
US5760431A (en) * | 1995-11-29 | 1998-06-02 | Massachusetts Institute Of Technology | Multidirectional transfer charge-coupled device |
DE60045484D1 (de) * | 1999-09-30 | 2011-02-17 | Shimadzu Corp | Ultraschnelles bildaufnahmegerät |
FR2857160B1 (fr) | 2003-07-01 | 2005-09-23 | Atmel Grenoble Sa | Capteur d'image ergonomique |
JP4281613B2 (ja) * | 2004-05-07 | 2009-06-17 | ソニー株式会社 | 固体撮像素子、固体撮像素子の製造方法、及び固体撮像素子の駆動方法 |
JP4710305B2 (ja) * | 2004-11-15 | 2011-06-29 | ソニー株式会社 | 固体撮像素子 |
JP5410808B2 (ja) * | 2009-03-27 | 2014-02-05 | 浜松ホトニクス株式会社 | 裏面入射型固体撮像素子 |
-
2009
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2010
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- 2010-03-23 WO PCT/JP2010/055004 patent/WO2010110275A1/ja active Application Filing
- 2010-03-23 EP EP10756071.6A patent/EP2413361B1/en active Active
- 2010-03-23 US US13/258,696 patent/US8624301B2/en active Active
- 2010-03-23 KR KR1020117024971A patent/KR101653435B1/ko active IP Right Grant
- 2010-03-26 TW TW99109211A patent/TWI470782B/zh active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02168669A (ja) * | 1988-09-14 | 1990-06-28 | Mitsubishi Electric Corp | 固体撮像素子 |
JP2001057418A (ja) * | 1999-08-18 | 2001-02-27 | Fuji Film Microdevices Co Ltd | 固体撮像素子 |
JP2002231925A (ja) * | 2001-01-31 | 2002-08-16 | Hamamatsu Photonics Kk | 半導体エネルギー線検出器 |
JP2003078826A (ja) * | 2001-09-06 | 2003-03-14 | Sony Corp | 固体撮像素子 |
JP2004241653A (ja) * | 2003-02-06 | 2004-08-26 | Hamamatsu Photonics Kk | X線撮像素子 |
Non-Patent Citations (2)
Title |
---|
"Etaloning in Back-Illuminated CCDs", ROPER SCIENTIFIC TECHNICAL NOTE, 2000 |
See also references of EP2413361A4 |
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CN102365743A (zh) | 2012-02-29 |
US20120256287A1 (en) | 2012-10-11 |
JP5410808B2 (ja) | 2014-02-05 |
KR101653435B1 (ko) | 2016-09-01 |
EP2413361B1 (en) | 2021-04-28 |
US8624301B2 (en) | 2014-01-07 |
TW201104858A (en) | 2011-02-01 |
TWI470782B (zh) | 2015-01-21 |
EP2413361A1 (en) | 2012-02-01 |
EP2413361A4 (en) | 2013-04-17 |
JP2010232495A (ja) | 2010-10-14 |
CN102365743B (zh) | 2015-05-13 |
KR20110137376A (ko) | 2011-12-22 |
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