WO2010105445A1

WO2010105445A1 - Channel interleaving method and channel interleaver

Info

Publication number: WO2010105445A1
Application number: PCT/CN2009/070937
Authority: WO
Inventors: 梁生宝; 周华; 田军
Original assignee: 富士通株式会社
Priority date: 2009-03-20
Filing date: 2009-03-20
Publication date: 2010-09-23
Also published as: CN102067640A; CN102067640B

Abstract

A channel interleaving method and channel interleaver, the method comprises: receiving N first check sub-blocks and N second check sub-blocks from an encoder, wherein N is an integer and N≥1; respectively partitioning each one of the first and second check sub-blocks into multiple data units, and each data unit contains M bits with different reliability levels, M≥2 and M is an integer which could divide the integer of the bits number of a modulation symbol; it is supposed that the descending order of different reliability levels is R₀≥R₁≥…R_i≥…R_M-1, i=0, 1, …, M-1, for respective bits within each data unit in every first check sub-blocks, interchanging its position in that data unit such that the position of the bit with reliability level of R_i within the interchanged data unit corresponds to the position of the bit with reliability level of R_M-1-i within the corresponding data unit in the corresponding second check sub-block.

Description

Channel interleaving method and channel interleaver

Technical field

The present invention relates to the field of communications, and in particular to a channel interleaving method and a channel interleaver.

Background technique

The channel interleaver can effectively average bursty channel errors. A channel interleaver that can be used for convolutional Turbo Code (CTC) coding is used in the IEEE 802.16e standard. Fig. 1 shows a schematic diagram of CTC channel interleaving according to the IEEE 802.16e standard. The channel interleaver according to this standard mainly interleaves CTC-encoded data by the following procedure:

1, bit segmentation

Specifically, the bit sequence of the mother code rate is divided into six sub-blocks A, B,

Y ₂ and W ₂ , wherein sub-block A and sub-block B represent information bits, that is, payload data, sub-blocks and sub-blocks represent check bit sequences generated by the first convolutional encoder in the CTC encoder, sub-block Y ₂ and sub-block W ₂ represent a check bit sequence generated by a second convolutional encoder in the CTC encoder.

2, sub-block interleaving

Specifically, the same interleaving algorithm is used to independently interleave in the above six sub-blocks. The IEEE 802.16e standard uses the interleaving algorithm shown in the following equation (1):

T _k = 2 ^m (k mod J) + BRO _m ([k IJ") (1)

Where /W and respectively represent the parameters of the interleaving algorithm in the sub-blocks shown, these parameters can be determined according to the relevant parameter table provided in IEEE 802.16e, and are not described here. T _k represents a temporary output address. If r _A ≥ V, discard the Γ _Α . Here, the information bits in the coding block t/2, A^ OH...^-^ IEEE 802.16e describes specific steps for interleaving in each sub-block using the above-described interleaving algorithm, and details are not described herein again.

3, bit grouping

Specifically, after interleaving in the sub-block, directly mapping the sub-block A and the sub-block B, inter-sub-block interleaving in the sub-block and sub-block Y ₂ , and sub-block and sub-block W ₂ performs inter-subblock interleaving. The specific interleaving process is shown in Figure 1.

Some of the relevant references are listed below, which are hereby incorporated by reference herein in its entirety in its entirety herein.

IEEE P802.16e D12, released in October 2005: "Draft IEEE Standard for Local and Metropolitan area Networks - Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems - Amendment for Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands".

Summary of the invention

The present invention provides a channel interleaving method and a channel interleaver in which the symmetry of the output bits of the channel coder is fully utilized to more effectively discretize burst errors.

According to a first aspect of the present invention, a channel interleaving method is provided. The channel interleaving method may include: receiving N first parity subblocks and N second parity subblocks from an encoder, where N is an integer greater than or equal to 1, and the first parity subblock includes First check data of the payload data, the second check sub-block includes second check data of the payload data; respectively dividing each first check sub-block and the corresponding second check sub-block into a plurality of data units, wherein each data unit includes M bits, the M bits have different reliability levels, M≥2 and M is an integer capable of divising the number of bits in one modulation symbol, and assuming the difference The reliability levels are represented by Ro, R _l5 ..., , ..., RM I from high to low, respectively, Ro≥Ri≥...≥Ri≥...,≥R _M i, i = 0 , l, . . . , M l; and swapping the positions of the bits in each data unit in each of the first parity sub-blocks within the data unit such that the data unit after the interchange The position of the bit with the internal reliability level corresponds to the ratio of the reliability level in the corresponding data unit in the corresponding second parity sub-block to the RMU s position.

According to a second aspect of the present invention, a channel interleaver is provided. The channel interleaver can include a receiving module and a bit position interchange module within the sub-block.

The receiving module is configured to receive N first parity subblocks and N second parity subblocks from an encoder, where N is an integer greater than or equal to 1, and the first parity subblock includes a net The first parity data of the payload data, the second parity subblock includes second parity data of the payload data. The sub-block internal bit position interchange module is configured to divide each first parity sub-block and the corresponding second parity sub-block into a plurality of data units, where each data unit includes M bits, M bits have different reliability levels, M ≥ 2 and M is an integer capable of divising the number of bits in one modulation symbol, and it is assumed that the different reliability, etc. are represented by Ro, R _l5 ..., 3⁄4,..., R _M -i,, Ro≥Ri≥...≥Ri≥...,≥R _M -i, i = 0,1,..., M-1; and for each The positions of each bit in each data unit in a parity sub-block are interchanged in the data unit such that the position of the bit of the reliability level in the data unit after the swap corresponds to the corresponding second The reliability level in the corresponding data unit in the parity sub-block is

The position of the bit.

DRAWINGS

The above and other objects, features and advantages of the present invention will become more <RTIgt; The components in the figures are not drawn to scale, but only to illustrate the principles of the invention. In the drawings, the same or similar technical features or components will be denoted by the same or similar reference numerals.

1 is a schematic diagram showing a channel interleaving method of the prior art;

Figure 2 shows a constellation diagram of 16QAM (Quadrature Amplitude Modulation);

Figure 3 shows a constellation diagram of 64QAM (Quadrature Amplitude Modulation);

4 is a flow chart showing a channel interleaving method according to an embodiment of the present invention; FIGS. 5 through 8 are diagrams showing channel interleaving sequences for 16QAM and 64QAM, according to some embodiments of the present invention;

9 is a flow chart showing a channel interleaving method according to an embodiment of the present invention; FIGS. 10 and 11 are schematic diagrams showing channel interleaving sequences for 16QAM and 64QAM, respectively, according to some embodiments of the present invention;

FIG. 12 is a flow chart showing a channel interleaving method according to an embodiment of the present invention; FIG.

13 and FIG. 14 are diagrams respectively showing channel interleaving sequences for 16QAM and 64QAM according to some embodiments of the present invention, using a convolutional turbo code encoder; and

15 and 16 are diagrams respectively showing a channel interleaver according to some embodiments of the present invention. Schematic block diagram of the structure.

detailed description

Embodiments of the present invention will now be described with reference to the accompanying drawings. The elements and features described in one of the figures or one embodiment of the invention may be combined with elements and features illustrated in one or more other figures or embodiments. It should be noted that, for the sake of clarity, representations and descriptions of components and processes known to those of ordinary skill in the art that are not relevant to the present invention are omitted from the drawings and the description.

In some modulation schemes (eg, bitmap modulation schemes with different reliable protection, including star 8QAM, high order QAM, etc.), the reliability of each bit in each modulation symbol is different. 2 and 3 exemplarily show constellations of two modulation modes, 16QAM and 64QAM. As shown in FIG. 2, in 16QAM, each modulation symbol contains 4 bits: i^i ₂ q ₂ . Under this constellation diagram, 4 bits can be divided into two reliability levels, where _Zl is a high reliability bit; _ζ · ₂ is a low reliability bit. As shown in FIG. 3, in 64QAM, each modulation symbol contains 6 bits: i _iqi i ₂ q ₂ i ₃ q ₃ . Under this constellation diagram, 6 bits can be divided into three reliability levels, wherein the high reliability bits, _ζ · ₂ , are medium reliability bits, _ζ · ₃ , which are low reliability bits.

As mentioned earlier, the channel interleaver is used to more effectively average the burst errors of the channel, thereby obtaining better diversity gain. When considering frequency domain mapping, adjacent bits should be set on non-contiguous subcarriers to make full use of frequency diversity gain. When considering symbol constellation mapping, adjacent bits should be set in different symbols. In the bit position, to make full use of the constellation diversity gain.

The channel interleaving method and channel interleaver according to an embodiment of the present invention make full use of the symmetry of the output bits of the encoder. FIG. 4 is a flow chart exemplarily showing a channel interleaving method according to an embodiment of the present invention. 5 to 8 are diagrams exemplarily showing a channel interleaving sequence for 16QAM or 64QAM according to an embodiment of the present invention. The channel interleaving method will be described below with reference to the drawings.

As shown in FIG. 4, in step 401, a first parity subblock and a second syndrome block from the encoder are received.

In an embodiment of the present invention, the encoder may include one check generator, Ν Is an integer, and N ≥ l. That is, the encoder can output N first syndrome blocks ¥ ₁ ,...,^,...^ and 1^second syndrome blocks\¥ ₁ ,...,\^,. ..,\¥ ₁ ^ , l≤j≤N, where Yj and Wj are the output of the jth check generator. For example, an example of using a general-purpose Turbo code encoder including a check generator that outputs a first syndrome block ₁ and a second syndrome block W ₁ is shown in FIG. 5 or FIG. 6 _> As another example, FIG. 7 or FIG. 8 shows an example of a convolutional Turbo code encoder, convolutional Turbo code encoder comprises two parity generator outputs a first parity sub-block and a second correction ^ The test block and the first parity block Y ₂ and the second syndrome block W ₂ .

These syndrome blocks contain parity data for payload data.

The encoder may be a general-purpose Turbo code encoder, a convolutional turbo code encoder, or other channel encoder with output bits having symmetry. For example, the examples given in Figures 5 and 6 interleave the output sequence of the general turbo code encoder, while the examples given in Figures 7 and 8 interleave the output sequence of the convolutional turbo code encoder. It should be understood that these are merely exemplary and are not to be construed as limiting the invention.

In step 403, each of the first parity subblocks and the corresponding second parity subblocks are respectively divided into a plurality of data units.

Wherein each data unit contains M bits having different reliability levels. Here, the length M of each data unit is an integer that can divide the number of bits in one modulation symbol, and M ≥ 2. For example, in the example for 16QAM shown in Figs. 5 and 7, M is half the modulation symbol length 4, i.e., M=2. As another example, in the example for 64QAM shown in Figs. 6 and 8, M is half of the modulation symbol length 6, i.e., M=3.

Assume that the different reliability levels of the M bits in each data unit are from high to low. Another 'J is represented by Ro, ,···, ,···, R _M -, Ro≥Ri≥...≥Ri ≥..., ≥R _M -i, i = 0,1,..., Ml. For example, in the example for 16QAM shown in FIGS. 5 and 7, each data unit includes two bits, one being a high reliability bit and the other being a low reliability bit. As another example, in the example for 64QAM shown in FIGS. 6 and 8, each data unit includes three bits, one being a high reliability bit, one being a medium reliability bit, and the remaining one being low reliability. Sex bit.

In step 405, the positions of each bit in each data unit in each of the first parity sub-block Yj (or each second parity sub-block Wj) are interchanged in the data unit, so that The changed position of the bit in the data unit with the reliability level is corresponding to the corresponding number in the corresponding second syndrome block (or the corresponding first syndrome block Yj) The position of the bit according to the reliability level within the unit.

For example, in the example for 16QAM shown in Figs. 5 and 7, the high reliability bit of each data unit of sub-block Y1 or sub-block W1 is swapped with the low reliability bit. For another example, in the example for 64QAM shown in FIGS. 6 and 8, the high reliability bit in each data unit of the sub-block Y1 or the sub-block W1 is interchanged with the low-reliability bit, and the medium reliability is The bit position is unchanged.

After the above interleaving process, the distribution of high reliability bits and low reliability bits in the check sequence can be discretized, thereby improving the ability to resist sudden channel errors.

FIG. 9 is a flow chart exemplarily showing a channel interleaving method according to another embodiment of the present invention. 10 and 11 are schematic diagrams exemplarily showing channel interleaving sequences for 16QAM and 64QAM, respectively, according to an embodiment of the present invention.

The difference from the embodiment shown in Fig. 4 is that the embodiment shown in Fig. 9 includes a sub-block interleaving step 902. In step 902, sub-block interleaving is performed independently for each of the received sub-blocks. The intra-sub-block interleaving can be performed using any suitable interleaving algorithm, for example, an interleaving algorithm in IEEE 802.16e or other standards can be employed. I won't go into details here. The other steps 901, 903, and 905 are similar to steps 401, 403, and 405 shown in Fig. 4, and are not described here.

The channel interleaving diagrams shown in Figs. 10 and 11 respectively include sub-block interleaving, and other sequence changes are the same as those shown in Figs. 5 and 6.

In some embodiments, the received payload sub-blocks may also be channel interleaved. The payload sub-block includes payload data. For example, the payload sub-block A of the general-purpose Turbo code encoder output is shown in FIG. 5, FIG. 6, FIG. 10 and FIG. 11, and in the example shown in FIGS. 10 and 11, the payload sub-block A is made. Sub-block interleaving processing (method similar to step 902).

As another example, the two payload sub-blocks and 8 of the convolutional turbo code encoder output are shown in FIG. 7 or FIG. In the illustrated example, position bit swapping within the sub-blocks is also performed for the two payload sub-blocks A and B (methods are similar to steps 903 and 905). The intra-subblock location interchange includes the following steps: dividing the first payload sub-block A and the second payload sub-block B into a plurality of data units, each data unit including M bits (similar to step 403 or 903) Similarly, assume that the different reliability levels of the M bits in each data unit are represented by Ro, Ri, ..., 3⁄4, ..., RM I from high to low, respectively, Ro ≥ Ri ≥ ... ≥ Ri ≥. .., ≥ R _M -i, i = 0, 1, ..., M-1, swapping the positions of the bits in each data unit in the payload sub-block B within the data unit ( Similar to step 405 or 905), so that after the interchange The position of the bit of the reliability level within the data unit corresponds to the position of the bit of the reliability level in the corresponding data unit in the payload sub-block A.

In another example, after the payload sub-blocks A and B are respectively divided into a plurality of data units, the data in each data unit in the payload sub-block A (instead of the sub-block B) is in the data. The positions within the unit are interchanged such that the position of the bit of the reliability level in the data unit after the swap corresponds to the reliability level in the corresponding data unit in the payload sub-block B is

The position of the bit.

In the examples of Figures 4-6 and 9-11, the bit position swapping within the sub-blocks is performed in each of the first parity sub-blocks Yi (i = 1, ..., N). One of ordinary skill in the art will appreciate that the bit position swap within a sub-block can also be performed in each second parity sub-block Wi(i=l,...,N), as shown in Figure 7, Figure 8, Figure 13 and Figure 14.

In the embodiment of Fig. 9, the concept of the data unit is the same as the foregoing embodiments, and the length M of each data unit is an integer capable of divising the number of bits in one modulation symbol, and M ≥ 2. For example, in the example for 16QAM shown in Figs. 5, 7, and 10, M is half the modulation symbol length 4, i.e., M=2. As another example, in the example for 64QAM shown in Figs. 6, 8, and 12, M is half of the modulation symbol length 6, i.e., M=3.

In addition, the number of payload sub-blocks is not limited to 1 or 2, but varies depending on the encoder. For example, according to different structures of the encoder, N first parity subblocks and N second parity subblocks may be output, N being an integer, and 1^≥1.

In some embodiments, only the received payload sub-block may be divided into data units (similar to step 403 or 903) and bit position swapping within sub-blocks (similar to step 405 or 905), without verification The sub-block performs any processing. For example, in the case of N=2, only the received two payload sub-blocks A and B can be divided into data units and the bit positions in the sub-blocks are swapped, instead of the parity sub-blocks Y1, Y2. Wl and W2 do any processing.

FIG. 12 is a flow chart exemplarily showing a channel interleaving method according to another embodiment of the present invention.

The difference from the embodiment shown in FIG. 4 or FIG. 9 is that the embodiment shown in FIG. 12 includes an inter-sub-block interleaving step 1207. In step 1207, sub-block interleaving is sequentially performed between two syndrome sub-blocks and Y ₂ in units of groups of data units, and correspondingly two syndromes are sequentially arranged in units of groups of data units. block \ inter sub-block interleaving between ¥ ₁ and W _2. The group of data units includes X consecutive (or discontinuous) data sheets Yuan, X is an integer and X≥l.

The interleaving manner between the sub-block and W ₂ and the interleaving manner between the sub-block and Y ₂ should have symmetry. For example, in one example, after sub-block interleaving, the check sub-block

Each set of data units of Υ ₂ immediately follows the corresponding data unit group of the check sub-block, and accordingly, each set of data units of the check sub-block W ₂ immediately follows the corresponding data unit group of the check sub-block after that. In another example, after inter-sub-block interleaving, each set of data units of the check sub-block follows the corresponding data unit group of the check sub-block Y ₂ ; and, correspondingly, each group of the check sub-block The data unit follows the corresponding data unit group of the parity sub-block w ₂ . Of course, the manner of interlacing is not limited to the above-listed methods, and those skilled in the art can make modifications and changes in accordance with the teachings of the present invention, and these should be covered by the scope of the present invention.

In another example, the inter-block interleaving between the payload sub-block A and the payload sub-block B may be sequentially performed in the same manner in units of the data units, and details are not described herein again.

In the example shown in FIG. 12, the intra-sub-block interleaving step 1202 is between receiving step 1201 and step 1203. It should be understood that this is merely exemplary, and the present invention is not limited thereto. In another example, the intra-sub-block interleaving step 1202 may also be followed by inter-sub-block interleaving step 1207 (not shown). In another example, the intra-sub-block bit position interchange step 1203 may also be after the inter-sub-block interleaving step 1207 (not shown). In other words, the method flow in the embodiments of the present invention is not limited to the steps and/or sequences shown or described. These steps may be modified, added, deleted, and/or changed in accordance with the teachings of the present invention, and these should be covered by the scope of the present invention.

13 and 14 respectively exemplarily show channel interleaving sequences for 16QAM and 64QAM according to an embodiment of the present invention, in the case of using a convolutional turbo code encoder.

As shown in FIG. 13, in the case of using 16QAM modulation, first, the payload sub-blocks A and B from the encoder, the first parity block and Y _2, and the second syndrome block \^ and \¥ are received. ₂ . Alternatively, sub-block interleaving may be performed independently in each of the sub-blocks Α, Β, Υ ₂ , \¥ ₁ and \¥ ₂ (similar to steps 902 and 1202, and details are not described herein again). Then, each sub-block Α, Β, Υ ₂ , \¥ ₁ and \¥ _{2 is} divided into a plurality of data units. In the example shown in Figure 13, each data unit includes 2 bits. Of course, one of ordinary skill in the art can select data units that include other numbers of bits. Then, sub-blocks, sub-blocks, and sub-blocks W ₂ are inter-sub-block bit-interleaved (similar to steps 405, 905, and 1205, and are not described herein again), such that sub-block A, sub-block, and sub-block W The position of the low reliability bit (high reliability bit) in each data unit of ₂ and the corresponding sub-block B, sub-block

The positions of the high reliability bits (low reliability bits) in the corresponding data units in Y ₂ correspond. In another example, the sub-block intra-bit position swapping may be performed on the sub-block Β, the sub-block, and the sub-block Υ ₂ such that each of the sub-block Β, the sub-block 及, and the sub-block Υ ₂ The position of the low reliability bit (high reliability bit) in the cell is the position of the high reliability bit (low reliability bit) in the corresponding data block, the sub block, and the corresponding data unit in the sub block W ₂ correspond.

Finally, a group of data units in units of sub-blocks are sequentially between A and B, and W ₂ between ^ and inter sub-block interleaving subblocks between ₁ and Y ₂ subblock \. The group of data units includes X data units (X≥l). In the example shown in FIG. 13, X=l.

In the example shown in Fig. 13, after inter-sub-block interleaving, each set of data units of the sub-block 紧 follows the corresponding data unit group of the sub-block Α. In another example, after inter-sub-block interleaving, each set of data units of sub-block A may follow the corresponding data unit group of sub-block B.

In the example shown in FIG. 13, after inter-sub-block interleaving, each set of data units of the check sub-block Y ₂ immediately follows the corresponding data unit group of the check sub-block, and accordingly, the parity sub-block Each set of data units of W ₂ follows the corresponding data unit group of the check sub-block. In another example, after inter-sub-block interleaving, each set of data units of the parity sub-block ¥ ₁ may follow the corresponding data unit group of the verification sub-block Y ₂ ; and correspondingly, the syndrome Each set of data units of the block may follow the corresponding data unit group of the check sub-block W ₂ .

The interleaving manner between the sub-block and W ₂ and the interleaving manner between the sub-block and Y ₂ should have symmetry. In the example shown in FIG. 13, after the inter-sub-block interleaving, if a certain bit is a high-reliability bit at the time of modulation, the bit at the corresponding position is a low-reliability bit at the time of modulation; A certain bit of the bit is a low-reliability bit at the time of modulation, and the bit at the corresponding position is a high-reliability bit at the time of modulation.

Of course, the manner in which the sub-blocks are interleaved is not limited to the above-listed methods, and those skilled in the art can modify and change them according to the teachings of the present invention, and these should be covered by the scope of the present invention.

As shown in Figure 14, in the case of using 64QAM modulation, first, the reception comes from The payload sub-blocks A and 8, the first syndrome block ^ and ¥ _2, and the second syndrome block \^ and \¥ _{2 of the} encoder. Alternatively, sub-block interleaving may be performed independently in each of the sub-blocks A, B, Υ ₂ , \¥ ₁ and \¥ ₂ (similar to steps 902 and 1202, and details are not described herein again). Then, each sub-block Α, Β, Υ ₂ , \¥ ₁ and \¥ _{2 is} divided into a plurality of data units. In the example shown in Figure 14, each data unit includes 3 bits. Of course, one of ordinary skill in the art can select data units that include other numbers of bits.

Then, sub-blocks, sub-blocks, and sub-blocks W ₂ are inter-sub-block bit-interleaved (similar to steps 405, 905, and 1205, and are not described herein again), such that sub-blocks, sub-blocks, and sub-blocks W ₂ Low reliability bit (high reliability bit) in each data unit in the corresponding subblock B, subblock Yt ^ high reliability bit in the corresponding data unit in the subblock Y ₂ (low reliability The position of the sex bit) corresponds. In another example, the sub-block intra-bit position swapping may be performed on the sub-block Β, the sub-block, and the sub-block Υ ₂ such that each of the sub-block Β, the sub-block, and the sub-block Y ₂ The position of the low reliability bit (high reliability bit) within the corresponding subblock Α, the subblock, and the position of the high reliability bit (low reliability bit) in the corresponding data unit in the subblock W ₂ .

Finally, a group of data units in units of sub-blocks are sequentially between A and B, sub-block inter-block interleaving between the sub \ ¥ between ₁ and W ₂ subblock and ¥ ₁ and Y _2. The group of data units includes X data units (X≥l). In the example shown in Fig. 14, X = l.

In the example shown in Fig. 14, after inter-sub-block interleaving, each set of data units of the sub-block 紧 follows the corresponding data unit group of the sub-block Α. In another example, after inter-sub-block interleaving, each set of data units of sub-block A may follow the corresponding data unit group of sub-block B.

In the example shown in FIG. 14, after inter-sub-block interleaving, each set of data units of the check sub-block Y ₂ immediately follows the corresponding data unit group of the check sub-block, and accordingly, the parity sub-block Each set of data units of W ₂ follows the corresponding data unit group of the check sub-block. In another example, after inter-sub-block interleaving, each set of data units of the parity sub-block ¥ ₁ may follow the corresponding data unit group of the verification sub-block Y ₂ ; and correspondingly, the syndrome Each set of data units of the block may follow the corresponding data unit group of the check sub-block W ₂ .

As described above, the interleaving manner between the sub-block and W ₂ and the interleaving manner between the sub-block and Y ₂ should have symmetry. In the example shown in FIG. 14, after inter-sub-block interleaving, if a certain bit in the modulation is a high-reliability bit at the time of modulation, the corresponding position is The bits are low-reliability bits when modulated; if one of the bits is a medium-reliability bit at the time of modulation, the bit at the corresponding position in \^ is a medium-reliability bit at the time of modulation; if one of the bits When the modulation is a low reliability bit, the bit at the corresponding position in \¥ ₁ is a low reliability bit at the time of modulation.

Figure 15 illustrates a channel interleaver 1500 in accordance with one embodiment of the present invention. The channel interleaver 1500 includes a receiving module 1501 and a sub-block bit position interchange module 1502. The receiving module 1501 is configured to receive N first parity subblocks and N second parity subblocks from the encoder, where N is an integer greater than or equal to 1, the first syndrome The block contains first parity data of payload data, and the second parity subblock contains second parity data of payload data.

The intra-sub-block bit position interchange module 1502 is configured to divide each received first parity sub-block and the corresponding second parity sub-block into a plurality of data units, respectively. Wherein each data unit contains M bits having different reliability levels. It is assumed that the different reliability levels of the M bits are represented as Ro, ..., 3⁄4, ..., RM I, Ro ≥ Ri ≥ ... ≥ Ri ≥ ..., ≥ R, respectively. _M -i, i = 0,1,..., Ml. The intra-sub-block bit position interchange module 1502 is further configured to interchange the positions of each bit in each data unit in each of the first parity sub-blocks within the data unit, such that after the interchange The location of the bit in the data unit with a reliability level corresponding to the reliability level in the corresponding data unit in the corresponding second syndrome block is

The position of the bit.

Optionally, the receiving module 1501 is further configured to receive the N payload sub-blocks encoded by the encoder. And when N is equal to 2 (for example, in the case of using a convolutional turbo code encoder), it is assumed that the two received payload sub-blocks are a payload sub-block A and a payload sub-block B, respectively, within the sub-block The bit position interchange module 1502 is further configured to divide the payload sub-blocks A and B into M bits respectively having different reliability levels Ro, R _l5 ..., 3⁄4, ..., R _{M 1} . Multiple data units, and swapping the positions of the bits in each of the data sub-blocks A or B within the data unit such that the reliability level in the data unit after the swap is The position of the bit corresponds to the reliability level in the corresponding data unit in the payload sub-block B or A is

The position of the bit.

Optionally, the channel interleaver 1500 further includes an inter-block interleaving module 1503. When N, etc. In 2 (for example, in the case of using a convolutional turbo code encoder), it is assumed that the two received first parity sub-blocks are respectively represented by Y1 and Y2, and the two received second parity sub-blocks are respectively Expressed by W1 and W2. The inter-sub-block interleaving module 1503 may be configured to sequentially inter-sub-block interleaving between two parity sub-blocks Y1 and Y2 in units of one or more data units, and symmetrically in one or more data units Sub-block interleaving is sequentially performed between the two syndrome sub-blocks W1 and W2 in units. Optionally, the inter-sub-block interleaving module 1503 is further configured to perform inter-sub-block interleaving between the payload sub-blocks A and B sequentially in units of one or more data units.

Figure 16 shows a channel interleaver 1600 in accordance with another embodiment of the present invention. As shown in FIG. 16, the channel interleaver 1600 includes a receiving module 1601, a sub-block bit position swapping module 1602, and an inter-subblock interleaving module 1603. These modules have the same function as the corresponding modules shown in Figure 15. Channel interleaver 1600 also includes an intra-block interleaving module 1604. The intra-block intra-blocking module 1604 is configured to perform sub-block interleaving on each of the received parity sub-blocks and/or the payload sub-blocks.

In FIG. 16, an intra-sub-block interleaving module 1604 is disposed between the receiving module 1601 and the intra-sub-block bit position interchange module 1602. In another example, the intra-sub-block interleaving module 1604 can also be placed at other locations, such as after the inter-sub-block interleaving module 1603 (not shown). In another example, the intra-sub-block bit position interchange module 1602 can be located after the inter-sub-block interleaving module 1603 (not shown). In other words, the devices in the above embodiments are not limited to the structures shown or described. Modifications, additions and/or deletions of these structures may be made by those skilled in the art in light of the teachings of the present invention, and these should be covered by the scope of the invention.

In the embodiments described with reference to FIGS. 15 and 16, parameters such as N, M, Ro, R _l5 ..., R _} , ..., R _M -i and data units, inter-subblock interleaving, sub-blocks The concepts of interleaving, bit position interchange, and the like are the same as the corresponding concepts in the foregoing method embodiments, and are not repeated here.

With the channel interleaving method or channel interleaver according to an embodiment of the present invention, the distribution of high reliability bits and low reliability bits in the check sequence and/or the payload sequence can be discretized, thereby improving the anti-burst channel error. Ability.

The channel interleaving method or channel interleaver according to an embodiment of the present invention can be applied to a bit map modulation scheme having different reliable protection, such as 8-order star-quadrature amplitude modulation or high-order quadrature amplitude modulation. The high-order quadrature amplitude modulation is preferably a modulation scheme such as 2 ^K- order quadrature amplitude modulation, where Κ is preferably an integer greater than or equal to 4. In the field It will be understood by those skilled in the art that the modulation schemes exemplified herein are exemplary, and the present invention is not limited thereto.

A channel interleaving method or channel interleaver according to an embodiment of the present invention can be applied to a channel coder having output symmetry, such as a general turbo code encoder, a convolutional turbo code encoder, or other encoder. Those of ordinary skill in the art will appreciate that the encoders exemplified herein are exemplary and the invention is not limited thereto.

In the present specification, the expressions "first", "second", and "nth" are used to distinguish the features described in the text to clearly describe the present invention. Therefore, it should not be considered to have any limiting meaning. For example, the "first syndrome block" does not specifically refer to the "Y ₂ " sub-block shown in the drawing, and in another expression, it may also represent the "W ₂ " sub-block shown in the drawing. Blocks, etc. The "first payload sub-block" does not specifically refer to the "A" sub-block shown in the drawing, and in another expression, it may also represent the "B" sub-block shown in the drawing.

The various components or modules of the above devices may be configured in software, hardware or a combination thereof. The specific means or manner in which the configuration can be used is well known to those skilled in the art and will not be described herein.

It is to be understood that the device or system incorporating the above-described embodiments of the present invention should also be considered to fall within the scope of the present invention.

The present invention also provides a program product for storing a machine readable instruction code. When the instruction code is read and executed by a machine, the above-described channel interleaving method according to an embodiment of the present invention can be performed.

Accordingly, a storage medium for carrying a program product storing the above-described storage machine readable instruction code is also included in the disclosure of the present invention. The storage medium includes, but is not limited to, a floppy disk, an optical disk, a magneto-optical disk, a memory card, a memory stick, and the like.

In the above description of specific embodiments of the present invention, features described and/or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, and features in other embodiments. Combine, or replace, features in other embodiments.

It should be emphasized that the term "comprising" or "comprising" is used to mean the presence of a feature, element, step or component, but does not exclude the presence or addition of one or more other features, elements, steps or components. Furthermore, the method of the present invention is not limited to being performed in the chronological order described in the specification, and may be performed in other chronological order, in parallel or independently. Therefore, the order of execution of the methods described in the present specification does not limit the technical scope of the present invention.

While the invention has been described by the foregoing embodiments of the present invention, it will be understood by those skilled in the art Things. Such modifications, improvements or equivalents should also be considered to be included within the scope of the invention.

Claims

Claim

A channel interleaving method, comprising:

Receiving N first syndrome sub-blocks Yh from the encoder ^,...^^ and N second syndrome blocks\¥ ₁ ,...,\^,...,\¥ ₁ ^, wherein the encoder includes N check generators, N is an integer greater than or equal to 1, l ≤ j ≤ N, and the first syndrome block Yj and the second syndrome block Wj are the jth Outputs of the check generator, the first check sub block and the second check sub block containing check data of the payload data;

Each first parity sub-block and the corresponding second parity sub-block are respectively divided into a plurality of data units, wherein each data unit includes M bits, and the M bits have different reliability levels, M≥ 2 and M is an integer capable of divising the number of bits in one modulation symbol, and it is assumed that the different reliability levels are represented by Ro, Ri, ..., 3⁄4, ..., R _M -i from high to low, respectively. Ro≥Ri≥...≥3⁄4≥...,≥R _M -i, i = 0,1,..., M l; and

Interchanging the positions of each bit in each data unit in each of the first parity sub-blocks Yj within the data unit, so that the position of the bit with the reliability level in the data unit after the interchange corresponds The reliability level in the corresponding data unit in the corresponding second parity sub-block Wj is

The position of the bit.

2. The channel interleaving method according to claim 1, further comprising:

Receiving N payload sub-blocks from the encoder, the N payload sub-blocks respectively containing the payload data.

3. The channel interleaving method according to claim 2, wherein when N is equal to 2, it is assumed that the received two payload sub-blocks are a first payload sub-block and a second payload sub-block, respectively, the method Also includes:

And dividing the first payload sub-block and the second payload sub-block into a plurality of data units, where each data unit includes M bits, and the M bits have different reliability levels. .. " R^, and

Interchanging positions of each bit in each data unit in the first payload sub-block in the data unit, so that the position of the bit with a reliability level of 3⁄4 in the data unit after the interchange corresponds The reliability level within the corresponding data unit in the second payload sub-block is the location of the bit.

4. The channel interleaving method according to claim 1, wherein when N is equal to 2, The two first parity sub-blocks are respectively represented by ^ and Y ₂ , and the two received second parity sub-blocks are respectively represented by \¥ ₁ and \¥ ₂ , and the method further includes:

Sub-block interleaving is sequentially performed between two first parity sub-blocks and Y ₂ in units of groups of data units, wherein each group includes X data units, and X is an integer greater than or equal to 1;

Sub-block interleaving is sequentially performed between two second syndrome blocks \¥ ₁ and \¥ ₂ in units of groups of data units, wherein each group includes X data units.

5. The channel interleaving method according to claim 3 or 4, further comprising:

Sub-block interleaving is sequentially performed between the first payload sub-block and the second payload sub-block in units of groups of data units, wherein each group includes X data units, and X is greater than or equal to An integer of 1.

The channel interleaving method according to claim 1 or 2 or 3, wherein the encoder is a general-purpose Turbo code encoder or a convolutional turbo code encoder.

The channel interleaving method according to claim 1 or 2 or 3, wherein the channel interleaving method is applied to a bit map modulation scheme having different reliable protection, and the bit map modulation scheme of the different reliable protection includes an 8th order star Quadrature amplitude modulation or 2 ^K- order quadrature amplitude modulation, Κ is a positive integer greater than or equal to 4.

The channel interleaving method according to claim 1 or 2, wherein the first first parity subblock, the second second parity subblock, and/or the one of the payloads are received After the sub-block, it also includes:

Inter-block interleaving is performed in each of the first parity sub-blocks, the second second parity sub-blocks, and/or the one of the plurality of payload sub-blocks.

9. A channel interleaver, comprising:

a receiving module, configured to receive 第一 first parity sub-blocks from the encoder, ¥ ₁ , . . . , . . . and ^^ second parity sub-blocks\¥ ₁ ,...,\^ ,...,\¥ ₁ ^ where the encoder includes one check generator, Ν is an integer greater than or equal to 1, l ≤ j ≤ N, the first syndrome block Yj and the second check The sub-block Wj is an output of the j-th check generator, the first parity sub-block and the second parity sub-block include check data of payload data; and a bit-bit swapping module in the sub-block, Used for:

Dividing each first parity subblock and the corresponding second parity subblock into a plurality of data units, wherein each data unit includes M bits, the M bits have different reliability levels, M≥2 and M is an integer capable of divising the number of bits in one modulation symbol, and assuming the difference The reliability level is expressed from high to low as Ro, Ri,..., 3⁄4,..., R _{M 1} , Ro≥Ri≥...≥Ri≥...,≥R _M -i, i = 0,l" .., M l; and

The position of the bit.

10. The channel interleaver according to claim 9, wherein the receiving module is further configured to receive N payload sub-blocks from the encoder, where the N payload sub-blocks respectively include the payload data.

The channel interleaver according to claim 10, wherein when N is equal to 2, it is assumed that the received two payload sub-blocks are a first payload sub-block and a second payload sub-block, respectively, The intra-block bit position interchange module is also used to:

And dividing the first payload sub-block and the second payload sub-block into a plurality of data units, where each data unit includes M bits, and the M bits have the different reliability levels. , ,.. " R^, and

Interchanging positions of each bit in each data unit in the first payload sub-block in the data unit, so that the position of the bit with a reliability level of 3⁄4 in the data unit after the interchange corresponds The reliability level in the corresponding data unit in the second payload sub-block is the position of the bit.

The channel interleaver according to claim 9, wherein the channel interleaver further comprises an inter-sub-block interleaving module, and when N is equal to 2, the received two first parity sub-blocks are respectively used by ₁ and Y ₂ indicates that the received two second parity sub-blocks are respectively represented by \¥ ₁ and W ₂ , and the inter-sub-block interleaving module is used for:

The channel interleaver according to claim 11 or 12, wherein the inter-block interleaving module is further configured to:

The channel interleaver according to claim 9 or 10, further comprising an intra-block inter-interleaving module, wherein the sub-block inner interleaving module is configured to:: the received the first N parity sub-blocks And performing, by the N second parity sub-blocks and/or each of the N payload sub-blocks, intra-sub-block interleaving.

The channel interleaver according to claim 9 or 10 or 11, wherein the encoder is a general-purpose turbo code encoder or a convolutional turbo code encoder.

16. The channel interleaver according to claim 9 or 10 or 11, wherein the channel interleaver is applied to a bit map modulation scheme having different reliable protection, and the bit map modulation scheme of the different reliable protection includes an 8th order star Quadrature amplitude modulation or 2 ^K- order quadrature amplitude modulation, where Κ is an integer greater than or equal to 4.