CN104811266B - Bit Interleave, de-interweaving method and corresponding emitter, receiver - Google Patents

Bit Interleave, de-interweaving method and corresponding emitter, receiver Download PDF

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CN104811266B
CN104811266B CN201410043830.2A CN201410043830A CN104811266B CN 104811266 B CN104811266 B CN 104811266B CN 201410043830 A CN201410043830 A CN 201410043830A CN 104811266 B CN104811266 B CN 104811266B
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sub
check
code
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CN104811266A (en
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张文军
徐胤
管云峰
何大治
史毅俊
郭序峰
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Shanghai National Engineering Research Center of Digital Television Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H04L1/0063—Single parity check
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

Present invention is disclosed a kind of Bit Interleave, de-interweaving method and corresponding emitter, receiver.The deinterleaving method that emitter emitter uses for：LDPC code word to be interweaved is divided into message part and check part, and check part is divided into the first sub- check bit and the second sub- check bit, the first sub- check bit and the second sub- check bit are done into first time Bit Interleave respectively, obtain the first bit stream.Treat that interleaved bitstream is divided into multiple sub-blocks by certain length by first, and second of Bit Interleave is carried out in units of sub-block, obtain the second bit stream.Second bit stream is divided into Part I and Part II, and Part I and Part II are done into third time Bit Interleave, obtains the 3rd bit stream.Receiver and de-interweaving method are corresponding with the deinterleaving method of emitter.The present invention can to 4 LDPC code words and QPSK by set in emitter, receiver targetedly interweave, de-interweaving method makes systematic function preferably be lifted.

Description

Bit Interleave, de-interweaving method and corresponding emitter, receiver
Technical field
The present invention relates to one kind intertexture, de-interweaving method and corresponding device, handed over more specifically to a kind of bit Knit, de-interweaving method and corresponding emitter, receiver
Background technology
In existing broadcast communication standard, LDPC codings, Bit Interleave and constellation mapping are that most commonly seen coding is adjusted Mode processed.In different emission systems, LDPC codings, Bit Interleave and constellation mapping are required for individually designed, and combine Debugging, to obtain best channel performance.Therefore, how for specific LDPC code word and constellation mapping mode formation specific aim Bit Interleave, be this area a technical barrier.
The content of the invention
The purpose of the present invention aims to provide a kind of Bit Interleave, de-interweaving method and corresponding emitter, receiver, to solve Certainly in the prior art under with specific LDPC code word and QPSK mappings, above-mentioned condition collocation bit felt properties do not reach The problem of optimal.
According to above-mentioned purpose, implement a kind of Bit Interleave method for LDPC code of the present invention, comprise the following steps：Will LDPC code word to be interweaved is divided into message part and check part, and check part is divided into the first sub- check bit and Two sub- check bits, the first sub- check bit and the second sub- check bit are done into first time Bit Interleave respectively, obtain the first ratio Spy's stream.Treat that interleaved bitstream is divided into multiple sub-blocks by certain length by first, and second of bit is carried out in units of sub-block Interweave, obtain the second bit stream.Second bit stream is divided into Part I and Part II, and by Part I and second Divide and do third time Bit Interleave, obtain the 3rd bit stream.
According to above-mentioned purpose, a kind of emitter for the present invention that has a try, including LDPC encoder, interleaving block and mapping mould Block.Wherein, interleaving block by LDPC code word to be interweaved to be divided into message part and check part, and check part is drawn It is divided into the first sub- check bit and the second sub- check bit, the first sub- check bit and the second sub- check bit is done first respectively Secondary Bit Interleave, obtain the first bit stream.Treat that interleaved bitstream is divided into multiple sub-blocks by certain length by first, and with sub-block Second of Bit Interleave is carried out for unit, obtains the second bit stream.Second bit stream is divided into Part I and Part II, And Part I and Part II are done into third time Bit Interleave, obtain the 3rd bit stream.
Preferably, the first sub- check bit is the bit that LDPC code table moderate is not 1, and the second sub- check bit is LDPC code Table moderate is 1 bit.
Preferably, the first sub- check bit and the second sub- check bit are written in column first time Bit Interleave, are read by row Go out；The exchange pattern of second Bit Interleave setting sub-block, according to exchanging pattern by sub-block order change；Third time Bit Interleave Part I and Part II are written as two equal row by row respectively, then read by row.
Preferably, the code length and code check that LDPC encoder uses share four kinds of selections, are code check 5/15 respectively, code length 16200；Code check 5/15, code length 64800；Code check 6/15, code length 64800；Code check 7/15, code length 64800.
Preferably, mapping block is mapped using QPSK, and each complex symbol in QPSK mappings corresponds to third time bit The bit that the every a line to interweave is read.
Preferably, interleaving block is built-in exchanges pattern, for code check 5/15, the LDPC code of code length 16200, first ratio Special stream is divided into 45 sub-blocks, and the exchange pattern is：
21 27 44 8 19 11 38 43 4 16 28 24 1 37 9 42 41 212 30 26 17 18 39 31 13 32 20 15 3 23 10 35 40 7 22 45 625 34 5 29 14 36 33；
For code check 5/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange Pattern is：
123 99 174 32 40 22 175 34 152 92 170 91 146 119112 127 165 35 6 121 160 55 148 396 166 136 68 16 140135 69 115 11 101 54 105 176 30 133 149 45 77 60 113171 147 150 163 74 78 72 62 70 129 107 134 51 33 7 86 103 38100 157 58 76 143 81 172 159 89 42 162 28 128 145164 151 17 131 41 120 47 111 180 98 80 14 156 46 15556 63 144 104 93 117 8 67 84 139 90 97 169 138 8359 106 79 142 5 48 179 177 108 53 29 21 25 52 109 37 6431 49 178 27 110 61 88 50 87 26 43 124 94 161 19 102 44130 15 73 1 125 173 36 116 82 71 23 141 126 137 65 158153 2 132 114 4 18 85 75 24 95 167 154 39 168 13 966 20 57 122 10 12 118；
For code check 6/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange Pattern is：
55 130 114 22 75 156 150 158 47 120 6 64 111 10616 31 3 25 103 125 19 98 33 79 148 173 167 53 135119 176 168 73 4 149 58 40 86 62 9 32 52 49 61 29127 30 8 57 138 134 107 84 91 94 38 128 109 151 178180 21 81 69 96 70 139 56 132 43 131 59 88 175 71 108105 65 77 104 124 15 50 68 116 92 97 2 115 45 78 166 121153 136 67 147 117 11 12 20 36 90 154 24 123 159141 60 28 172 87 63 137 170 74 51 89 164 1 93 1742 5 37 85 144 27 35 46 126 157 18 66 163 155 95113 39 142 152 118 100 102 82 129 44 161 41 80122 110 83 133 140 14 76 171 7 101 146 72 34 143145 23 112 162 179 165 10 160 177 13 26 99 169 48174 54；
For code check 7/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange Pattern is：
147 76 92 113 150 27 82 101 94 118 59 37 12079 84 17 12 100 83 45 22 89 91 135 13 5 52 72 145109 103 164 133 3 105 39 126 102 166 151161 50 24 23 56 111 70 136 156 177 142 40 14 7 4410 33 68 81 112 29 87 69 167 4 2 159 148 88 11 74 171123 1 58 18 155 90 32 25 170 143 146 20 10473 116 152 95 131 162 173 179 175 127 63169 41 130 108 26 144 129 139 137 96 30 98 140115 165 43 47 34 163 160 53 153 67 65 168 158 60 68 77 119 121 42 54 64 62 36 122 132 106 17297 35 9 80 114 124 57 99 21 46 55 176 125 14938 71 85 19 51 110 48 141 28 107 75 49 180 93174 117 154 86 128 16 138 66 178 157 15 31 61134 78。
According to above-mentioned purpose, implement a kind of bit de-interweaving method suitable for LDPC code of the invention, including following step Suddenly：3rd bit stream is done into third time than deinterleave, obtains being divided into the second bit stream of Part I and Part II.Will Second bit stream carries out second than deinterleave in units of sub-block, obtains being divided into the first bit stream of multiple sub-blocks.Look for Go out the message part and check part of the first bit stream, and the first sub- check bit of check part and the second son verification ratio Spy, the first sub- check bit and the second sub- check bit are done for the first time than deinterleave respectively, obtained than after deinterleave LDPC code word.
According to above-mentioned purpose, implement a kind of receiver of the invention, including De-mapping module, de-interleaving block and LDPC are translated Code device.Wherein, de-interleaving block is by the 3rd bit stream doing third time than deinterleave, obtains being divided into Part I and the Second bit stream of two parts.Second bit stream is carried out in units of sub-block to second than deinterleave, obtains being divided into more First bit stream of individual sub-block.Find out the message part and check part of the first bit stream, and the first sub- school of check part Bit and the second sub- check bit are tested, the first sub- check bit and the second sub- check bit are done respectively and handed over for the first time than particular solution Knit, the LDPC code word after obtaining than deinterleave.
Preferably, the first sub- check bit is the bit that LDPC code table moderate is not 1, and the second sub- check bit is LDPC code Table moderate is 1 bit.
Preferably, first time Bit Interleave is read in the first sub- check bit and the second sub- check bit by row, is write by row Go out；Second of Bit Interleave according to sub-block exchange pattern by sub-block inverse transformation order；Third time Bit Interleave is by Part I Read respectively by row with Part II, then two equal row are written as by row.
Preferably, the code length and code check that ldpc decoder uses share four kinds of selections, are code check 5/15 respectively, code length 16200；Code check 5/15, code length 64800；Code check 6/15, code length 64800；Code check 7/15, code length 64800.
Preferably, de-interleaving block is built-in exchanges pattern, for code check 5/15, the LDPC code of code length 16200, and described first Bit stream is divided into 45 sub-blocks, and the exchange pattern is：
21 27 44 8 19 11 38 43 4 16 28 24 1 37 9 42 41 212 30 26 17 18 39 31 13 32 20 15 3 23 10 35 40 7 22 45 625 34 5 29 14 36 33；
For code check 5/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange Pattern is：
123 99 174 32 40 22 175 34 152 92 170 91 146 119112 127 165 35 6 121 160 55 148 3 96 166 136 68 16 140135 69 115 11 101 54 105 176 30 133 149 45 77 60 113171 147 150 163 74 78 72 62 70 129 107 134 51 33 7 86 103 38100 157 58 76 143 81 172 159 89 42 162 28 128 145164 151 17 131 41 120 47 111 180 98 80 14 156 46 15556 63 144 104 93 117 8 67 84 139 90 97 169 138 8359 106 79 142 5 48 179 177 108 53 29 21 25 52 109 37 6431 49 178 27 110 61 88 50 87 26 43 124 94 161 19 102 44130 15 73 1 125 173 36 116 82 71 23 141 126 137 65 158153 2 132 114 4 18 85 75 24 95 167 154 39 168 13 966 20 57 122 10 12 118；
For code check 6/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange Pattern is：
55 130 114 22 75 156 150 158 47 120 6 64 111 10616 31 3 25 103 125 19 98 33 79 148 173 167 53 135119 176 168 73 4 149 58 40 86 62 9 32 52 49 61 29127 30 8 57 138 134 107 84 91 94 38 128 109 151 178180 21 81 69 96 70 139 56 132 43 131 59 88 175 71 108105 65 77 104 124 15 50 68 116 92 97 2 115 45 78 166 121153 136 67 147 117 11 12 20 36 90 154 24 123 159141 60 28 172 87 63 137 170 74 51 89 164 1 93 1742 5 37 85 144 27 35 46 126 157 18 66 163 155 95113 39 142 152 118 100 102 82 129 44 161 41 80122 110 83 133 140 14 76 171 7 101 146 72 34 143145 23 112 162 179 165 10 160 177 13 26 99 169 48174 54；
For code check 7/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange Pattern is：
147 76 92 113 150 27 82 101 94 118 59 37 12079 84 17 12 100 83 45 22 89 91 135 13 5 52 72 145109 103 164 133 3 105 39 126 102 166 151161 50 24 23 56 111 70 136 156 177 142 40 14 7 4410 33 68 81 112 29 87 69 167 4 2 159 148 88 11 74 171123 1 58 18 155 90 32 25 170 143 146 20 10473 116 152 95 131 162 173 179 175 127 63169 41 130 108 26 144 129 139 137 96 30 98 140115 165 43 47 34 163 160 53 153 67 65 168 158 60 68 77 119 121 42 54 64 62 36 122 132 106 17297 35 9 80 114 124 57 99 21 46 55 176 125 14938 71 85 19 51 110 48 141 28 107 75 49 180 93174 117 154 86 128 16 138 66 178 157 15 31 61134 78。
Technical scheme is employed, can be led on the premise of specific 4 LDPC code words and QPSK map Cross in emitter, receiver set targetedly interweave, de-interweaving method makes systematic function preferably be lifted.
Brief description of the drawings
In the present invention, identical reference represents identical feature all the time, wherein：
Fig. 1 is emitter of the present invention, the functional block diagram of receiver；
Fig. 2 is the schematic diagram of first time Bit Interleave；
Fig. 3 is the schematic diagram of second of Bit Interleave；
Fig. 4 is the schematic diagram of the third time Bit Interleave of 64800 code lengths；
Fig. 5 is the schematic diagram of the third time Bit Interleave of 16200 code lengths；
Fig. 6 is the planisphere of QPSK mappings.
Embodiment
Technical scheme is further illustrated with reference to the accompanying drawings and examples.
In any one individual DTTB transmitting, reception system, coding, interweave, mapping（Demapping, solution are handed over Knit, decode）It is the processing step of core.Emitter disclosed by the invention, receiver employ specific LDPC coding/decodings And QPSK constellation mappings/demapping, therefore devised to adapt to above-mentioned specific LDPC codings and QPSK mappings, the present invention Targetedly Bit Interleave, de-interweaving method, and the transmitting using specific LDPC codings, Bit Interleave and QPSK mappings Machine, receiver.
As shown in figure 1, the emitter of the present invention includes LDPC encoder, interleaving block and mapping block, and receiver is then Accordingly include De-mapping module, de-interleaving block and ldpc decoder.Emitter first inputs bit stream after message sink coding The coding of specific LDPC code word is carried out to LDPC encoder.Input bit interleaving block afterwards, according to bit disclosed by the invention Deinterleaving method is interleaved processing, and the data after then Bit Interleave is handled carry out QPSK constellation mappings, be finally modulated, Transmitting, undergo channel.On the other hand, the data after channel are demodulated by receiver, the data input after then demodulating De-mapping module, carry out QPSK demappings.The bit soft value information that De-mapping module exports is input to de-interleaving block afterwards It is deinterleaved, is output to ldpc decoder afterwards, the decoding based on specific LDPC code word is carried out to it, finally decoding output Bit stream.
It is to be directed to all LDPC code words that Bit Interleave, the de-interweaving method used in emitter, receiver, which is not, but For specific LDPC code word, and suitable for QPSK constellation mapping/demapping.Specifically, emitter of the invention is adopted It is specific LDPC code word, coordinates the interleaving block of the Bit Interleave method using the present invention, and corresponding to use QPSK maps, and the receiver of the present invention coordinates the bit de-interweaving method using the present invention using QPSK demapping De-interleaving block, and use specific LDPC code word.
Therefore, the LDPC encoder in emitter of the present invention, used LDPC code in the ldpc decoder in receiver Word, i.e., totally 4 kinds of above-mentioned " specific LDPC code ", respectively as shown in 1~table of table 4：
The code check 5/15 of table 1, the code table of code length 16200
The code table of the code length 64800 of 2 code check of table 5/15
The code table of the code length 64800 of 3 code check of table 6/15
The code table of the code length 64800 of 4 code check of table 7/15
Above-mentioned specific LDPC code word is obtained by following coding method：
Step S1：Bit stream after message sink coding is split as block of information one by one, each block of information is by K information bit Composition, i.e., each block of information can be expressed as S=(s0,s1,...,sK-1)。
Step S2：According to multiple block of information S=(s obtained above0,s1,...,sK-1), generate M1+M2Individual check bitObtain code word Λ=(λ of N number of bit0,λ1,...,λN-1), wherein N=K+M1+M2.This Outside, Λ can be expressed as again,Wherein, M1It is the first sub- check bit, table Show LDPC code table moderate be 1 bit, M2It is the second sub- check bit, represents the bit that LDPC code table moderate is 1, it is above-mentioned Each LDPC code word corresponds to one group of M1And M2。
Step S3：Initialize λi=si, i=0,1 ..., K-1.pj=0, j=0,1 ..., M1+M2-1。
Step S4：To information bit λ0, to being added up using check bit of the first row numeral as address in code table.
Step S5：For remaining L-1 information bit λm, m=1,2 ..., L-1,（Wherein L represents information bit Length, usual L=360）, by each information bit respectively with being added up according to the check bit that following y is address：
Wherein, x refers to and λ0Related verification bit address, and
Step S6：For l-th information bit λL, check bit is tired out according to the second line number word address in code table Add.Likewise, for ensuing L-1 information bit, continue to add up to check bit according to the formula in step S5, At this time the x of the formula in step S5 is the numeral of the second row in code table.
Step S7：Similarly, for the individual information bits of 2L, 3L, 4L ... iL ..., according to distinguish the 3rd in code table, 4,5 ..., (i+1) address capable L ... is added up to check bit, and L-1 information bit after its information bit then respectively according to Formula in step S5 adds up to check bit.Now, it is current i-th L letter corresponding to the x for waiting the formula in step S5 Cease the row in the code table corresponding to bit, such as L-1 bit after i-th L information bit, the public affairs in its applying step S5 When formula corresponding x address be code table in (i+1) OK.
Step S8：Finally, after step S7 is completed, proceed as follows：Wherein i=1,2 ..., M1-1。
Accordingly, the decoder in inventive receiver uses the interpretation method corresponding with above-mentioned coding method, therefore It is not repeated to illustrate.
Using the code check of table 1 as 5/15, exemplified by code length is 16200 LDPC code code table, step S4 accumulation method is：
In x be first in code table Capable numeral：69 244 706 5,145 5,994 6,066 6,763 6,815 8509, and Then have：
LDPC code word by above-mentioned coding method generation is sent to interleaving block, interleaving block and received by LDPC encoder LDPC code word include message part and check part, and check part can be divided into the first sub- check bit M1With the second son Check bit M2.It is as shown in Figure 2 that interleaving block adopts the method being interleaved to 4 kinds of above-mentioned LDPC codes.
Step S9：First time Bit Interleave is carried out to the check part of LDPC code word, obtains the first bit stream.
Specifically, the common M of the check part of code word1+M2Individual bit, the first sub- check bit M1Individual bit, one is write by row In individual memory space, each column Q1Individual bit, common q row, that is to say, that M1=Q1× q, then sequentially read by row.Second son verification Bit M2Individual bit, write by row in a memory space, Q2 bit of each column, common q row, that is to say, that M2=Q2× q, then Sequentially read by row.By check part after first time Bit Interleave, the whole code word of reading（Message part+check part） As the first bit stream.
Step S10：Continuous sub-block will be divided into by 360 bit lengths by the code word of first time Bit Interleave, then pressed According to a certain specific sequence, second of Bit Interleave is carried out, obtains the second bit stream.
As shown in figure 3, interlacing device and de-interlacing device is built-in to exchange pattern.Second of Bit Interleave converts each 360 length ratio The order of special sub-block, form new code word bits.For example, (the m shown in Fig. 31,m2,...,mN/360) it is each 360 length The exchange pattern of sub-blocks of bits, it indicates shifting one's position for each sub-block to identify each sub-block.
For code check 5/15, the LDPC code of code length 16200, the first bit stream is divided into 45 sub-blocks, exchanges pattern and is：
21 27 44 8 19 11 38 43 4 16 28 24 1 37 9 42 41 212 30 26 17 18 39 31 13 32 20 15 3 23 10 35 40 7 22 45 625 34 5 29 14 36 33；
For code check 5/15, the LDPC code of code length 64800, the first bit stream is divided into 180 sub-blocks, exchanges pattern and is：
123 99 174 32 40 22 175 34 152 92 170 91 146 119112 127 165 35 6 121 160 55 148 3 96 166 136 68 16 140135 69 115 11 101 54 105 176 30 133 149 45 77 60 113171 147 15016374 78 72 62 70 129107134 51 33 7 86 103 38100 157 58 76 143 81 172 159 89 42 162 28 128 145164 151 17 131 41 120 47 111 180 98 80 14 156 46 15556 63 144 104 93 117 8 67 84 139 90 97 169 138 8359 106 79 142 5 48 179 177 108 53 29 21 25 52 109 37 6431 49 178 27 110 61 88 50 87 26 43 124 94 161 19 102 44130 15 73 1 125 173 36 116 82 71 23 141 126 137 65 158153 2 132 114 4 18 85 75 24 95 167 154 39 168 13 966 20 57 122 10 12 118；
For code check 6/15, the LDPC code of code length 64800, the first bit stream is divided into 180 sub-blocks, exchanges pattern and is：
55 130 114 22 75 156 150 158 47 120 6 64 111 10616 31 3 25 103 125 19 98 33 79 148 173 167 53 135119 176 168 73 4 149 58 40 86 62 9 32 52 49 61 29127 30 8 57 138 134 107 84 91 94 38 128 109 151 178180 21 81 69 96 70 139 56 132 43 131 59 88 175 71 108105 65 77 104 124 15 50 68 116 92 97 2 115 45 78 166 121153 136 67 147 117 11 12 20 36 90 154 24 123 159141 60 28 172 87 63 137 170 74 51 89 164 1 93 1742 5 37 85 144 27 35 46 126 157 18 66 163 155 95113 39 142 152 118 100 102 82 129 44 161 41 80122 110 83 133 140 14 76 171 7 101 146 72 34 143145 23 112 162 179 165 10 160 177 13 26 99 169 48174 54；
For code check 7/15, the LDPC code of code length 64800, the first bit stream is divided into 180 sub-blocks, exchanges pattern and is：
147 76 92 113 150 27 82 101 94 118 59 37 12079 84 17 12 100 83 45 22 89 91 135 13 5 52 72 145109 103 164 133 3 105 39 126 102 166 151161 50 24 23 56 111 70 136 156 177 142 40 14 7 441 0 33 68 81 112 29 87 69 167 4 2 159 148 88 11 74 171123 1 58 18 155 90 32 25 170 143 146 20 10473 116 152 95 131 162 173 179 175 127 63169 41 130 108 26 144 129 139 137 96 30 98 140115 165 43 47 34 163 160 53 153 67 65 168 158 60 68 77 119 121 42 54 64 62 36 122 132 106 17297 35 9 80 114 124 57 99 21 46 55 176 125 14938 71 85 19 51 110 48 141 28 107 75 49 180 93174 117 154 86 128 16 138 66 178 157 15 31 61134 78。
With above-mentioned code check 5/15, exemplified by code length 16200, it is length according to 360 bits to exchange pattern by the first bit stream Divide sub-block, mark off 45 sub-blocks altogether, each sub-block is numbered as 1,2 ..., 45.After order change, the sequence of sub-block For 21,27 ..., 33, i.e., numbering is 21 sub-block is after exchanging, on the position of the 1st sub-block, i.e., the first ratio 21st sub-block of spy's stream becomes the 1st sub-block of the second bit stream, by that analogy, what all sub-blocks were formed after exchange Complete code is the second bit stream.De-mapping device exchange pattern exchange method it is corresponding with mapper, behind be not repeated Explanation.
Step S11：The step S10 code words generated are divided into Part I and Part II, and according to the difference of code length, entered Row third time Bit Interleave, obtains the 3rd bit stream.
Specifically, because the code length of above-mentioned LDPC code word has 2 kinds of selections, i.e., 16200 and 64800, then interleaving block There is the dividing mode of different Part I and Part II for this 2 kinds of different code lengths.Interleaving block presses Part I Row are write as two equal row, are then read by row, using remaining bit as Part II, and are write as two equal row by row, Then read by row, it is the 3rd bit stream to read result.
Specifically, if the code word size of Part I is 64800 bits, division Part I is 64800 bits, this Part II is 0 in the case of kind, and each in Part I shows 32400 bits.And if the code word size of Part I is 16200 bits, then it is 15840 bits to divide Part I, and Part II is 360 bits.Now, each of Part I shows 7920 bits, each of Part II show 180 bits.
Interleaving block will be streamed to mapping by bit data for the first time, for the second time and after third time Bit Interleave Module, carries out constellation mapping, and the present invention uses QPSK constellation mappings.As shown in table 5：
Table 5, QPSK mapped modes
Afterwards, mapping block is to the bitstream data (b after above-mentioned Bit Interleave0,b1,...,bN-1), according to Fig. 4 QPSK planisphere, bit map to some constellation point, obtains symbol stream two-by-two, wherein the corresponding star of each complex symbol Seat point, and low level（LSB）Formerly, i.e. each complex symbol in QPSK mappings corresponds to every a line reading of third time Bit Interleave The bit gone out, bit is exported for two of the first row, low level is arranged to b0, a high position is arranged to b1, the output of other rows is with such Push away.And it is corresponding with mapping method for the De-mapping module of receiver, its de-mapping method, therefore be not repeated to illustrate.
Finally, OFDM operations are carried out to symbol stream in modulation module, adds carrier wave and launched.On the other hand, receive The carrier wave received is first transferred to base band by prow, does FFT operations, is obtained QPSK symbol stream soft value data, is sent to demapping Module, demapping operation is carried out according to QPSK soft de-mapped method, bit soft value data flow is obtained, is sent to de-interleaving block, Inverse operation according to above-mentioned Bit Interleave method to bit soft value data flow obtain after deinterleaving than deinterleave Bit soft value data flow, ldpc decoder is sent into, based on the specific code table given, LDPC decoding behaviour is carried out to bit data flow Make, finally give decoded bitstream data.
Particularly, de-interweaving method is corresponding with above-mentioned deinterleaving method used by the de-interleaving block in receiver, It may be summarized to be following steps：
1st step：3rd bit stream is done into third time than deinterleave, obtains being divided into the of Part I and Part II Two bit streams.
2nd step：Second bit stream is carried out second than deinterleave in units of sub-block, obtains being divided into multiple sub-blocks The first bit stream.
3rd step：Find out the message part and check part of the first bit stream, and the first sub- check bit of check part With the second sub- check bit, the first sub- check bit and the second sub- check bit are done for the first time than deinterleave respectively, obtained Than the LDPC code word after deinterleave.
In above-mentioned 3 steps, first time Bit Interleave is read the first sub- check bit and the second sub- check bit by row Enter, write out by row, second of Bit Interleave will by sub-block inverse transformation order, third time Bit Interleave according to the exchange pattern of sub-block Part I and Part II are read by row respectively, then are written as two equal row by row.Due to the side of above-mentioned 3 steps and intertexture Method is corresponding, therefore explanation is not repeated herein in its further detail operation.
It will be understood to one skilled in the art that the specification of the above is only one kind in the numerous embodiments of the present invention Or several embodiments, and not use limitation of the invention.Any equivalent change for embodiment described above, modification with And the technical scheme such as equivalent substitute, as long as meeting the spirit of the present invention, will all fall in claims of the present invention In the range of protecting.

Claims (22)

  1. A kind of 1. Bit Interleave method for LDPC code, it is characterised in that comprise the following steps：
    LDPC code word to be interweaved is divided into message part and check part, and check part is divided into the first son verification ratio Special and the second sub- check bit, does first time Bit Interleave by the first sub- check bit and the second sub- check bit, obtains respectively First bit stream；
    Treat that interleaved bitstream is divided into multiple sub-blocks by certain length by first, and carry out second in units of the sub-block and compare Spy interweaves, and obtains the second bit stream；
    Second bit stream is divided into Part I and Part II, and the Part I and Part II are done the 3rd Secondary Bit Interleave, obtain the 3rd bit stream.
  2. 2. it is used for the Bit Interleave method of LDPC code as claimed in claim 1, it is characterised in that the first sub- check bit It is not 1 bit for LDPC code table moderate, the second sub- check bit is the bit that LDPC code table moderate is 1.
  3. 3. it is used for the Bit Interleave method of LDPC code as claimed in claim 1, it is characterised in that the first time Bit Interleave First sub- check bit and the second sub- check bit are written in column, read by row；Second of Bit Interleave sets sub-block Exchange pattern, according to the exchange pattern by the sub-block order change；The third time Bit Interleave by Part I and Part II is written as two equal row by row respectively, then is read by row.
  4. 4. it is used for the Bit Interleave method of LDPC code as claimed in claim 1, it is characterised in that the Bit Interleave method is fitted The code length and code check of LDPC codings share four kinds of selections, are code check 5/15 respectively, code length 16200；Code check 5/15, code length 64800；Code check 6/15, code length 64800；Code check 7/15, code length 64800.
  5. 5. it is used for the Bit Interleave method of LDPC code as claimed in claim 3, it is characterised in that hand over the third time bit The every a line bit for knitting reading carries out QPSK mappings.
  6. 6. it is used for the Bit Interleave method of LDPC code as claimed in claim 4, it is characterised in that：
    For code check 5/15, the LDPC code of code length 16200, first bit stream is divided into 45 sub-blocks, the interchange graph of sub-block Case is：
    For code check 5/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the interchange graph of sub-block Case is：
    For code check 6/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the interchange graph of sub-block Case is：
    For code check 7/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the interchange graph of sub-block Case is：
  7. 7. a kind of bit de-interweaving method suitable for LDPC code, it is characterised in that comprise the following steps：
    3rd bit stream is done into third time than deinterleave, obtains being divided into the second bit stream of Part I and Part II；
    Second bit stream is carried out second than deinterleave in units of sub-block, obtains being divided into the first of multiple sub-blocks Bit stream；
    Find out the message part and check part of first bit stream, and the first sub- check bit of check part and second Sub- check bit, the first sub- check bit and the second sub- check bit are done for the first time than deinterleave respectively, obtain comparing particular solution LDPC code word after intertexture.
  8. 8. it is applied to the bit de-interweaving method of LDPC code as claimed in claim 7, it is characterised in that the first son verification Bit is the bit that LDPC code table moderate is not 1, and the second sub- check bit is the bit that LDPC code table moderate is 1.
  9. 9. it is applied to the bit de-interweaving method of LDPC code as claimed in claim 7, it is characterised in that the first time bit Interweave and read in the first sub- check bit and the second sub- check bit by row, write out by row；Second of Bit Interleave according to The exchange pattern of sub-block by the sub-block inverse transformation order；The third time Bit Interleave distinguishes Part I and Part II Read by row, then two equal row are written as by row.
  10. 10. it is applied to the bit de-interweaving method of LDPC code as claimed in claim 7, it is characterised in that described to be handed over than particular solution The code length and code check of the applicable LDPC decodings of organization method share four kinds of selections, are code check 5/15 respectively, code length 16200；Code check 5/ 15, code length 64800；Code check 6/15, code length 64800；Code check 7/15, code length 64800.
  11. 11. it is applied to the bit de-interweaving method of LDPC code as claimed in claim 9, it is characterised in that：
    For code check 5/15, the LDPC code of code length 16200, first bit stream is divided into 45 sub-blocks, the exchange pattern For：
    For code check 5/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange pattern For：
    For code check 6/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange pattern For：
    For code check 7/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange pattern For：
  12. 12. a kind of emitter, including LDPC encoder, interleaving block and mapping block, it is characterised in that：
    The interleaving block draws check part LDPC code word to be interweaved is divided into message part and check part It is divided into the first sub- check bit and the second sub- check bit, the first sub- check bit and the second sub- check bit is done first respectively Secondary Bit Interleave, obtain the first bit stream；
    Treat that interleaved bitstream is divided into multiple sub-blocks by certain length by first, and carry out second in units of the sub-block and compare Spy interweaves, and obtains the second bit stream；
    Second bit stream is divided into Part I and Part II, and the Part I and Part II are done the 3rd Secondary Bit Interleave, obtain the 3rd bit stream.
  13. 13. emitter as claimed in claim 12, it is characterised in that the first sub- check bit be LDPC code table moderate not For 1 bit, the second sub- check bit is the bit that LDPC code table moderate is 1.
  14. 14. emitter as claimed in claim 12, it is characterised in that the first time Bit Interleave is by the first sub- check bit It is written in column with the second sub- check bit, is read by row；The exchange pattern of second of Bit Interleave setting sub-block, according to institute State and exchange pattern by the sub-block order change；The third time Bit Interleave is write Part I and Part II by row respectively For two equal row, then read by row.
  15. 15. emitter as claimed in claim 12, it is characterised in that the code length and code check that the LDPC encoder uses share Four kinds of selections, are code check 5/15 respectively, code length 16200；Code check 5/15, code length 64800；Code check 6/15, code length 64800；Code check 7/15, code length 64800.
  16. 16. emitter as claimed in claim 14, it is characterised in that the mapping block is mapped using QPSK, QPSK mappings In each complex symbol correspond to the third time Bit Interleave every a line read bit.
  17. 17. emitter as claimed in claim 14, it is characterised in that the interleaving block is built-in to exchange pattern：
    For code check 5/15, the LDPC code of code length 16200, first bit stream is divided into 45 sub-blocks, the exchange pattern For：
    For code check 5/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange pattern For：
    For code check 6/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange pattern For：
    For code check 7/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange pattern For：
  18. 18. a kind of receiver, including De-mapping module, de-interleaving block and ldpc decoder, it is characterised in that：
    The de-interleaving block obtains being divided into Part I and second the 3rd bit stream is done into third time than deinterleave The second partial bit stream；
    Second bit stream is carried out second than deinterleave in units of sub-block, obtains being divided into the first of multiple sub-blocks Bit stream；
    Find out the message part and check part of first bit stream, and the first sub- check bit of check part and second Sub- check bit, the first sub- check bit and the second sub- check bit are done for the first time than deinterleave respectively, obtain comparing particular solution LDPC code word after intertexture.
  19. 19. receiver as claimed in claim 18, it is characterised in that the first sub- check bit be LDPC code table moderate not For 1 bit, the second sub- check bit is the bit that LDPC code table moderate is 1.
  20. 20. receiver as claimed in claim 18, it is characterised in that the first time Bit Interleave is by the first sub- check bit Read in by row with the second sub- check bit, write out by row；Second of Bit Interleave is according to the exchange pattern of sub-block by described in Sub-block inverse transformation order；The third time Bit Interleave is read Part I and Part II by row respectively, then is written as by row Two equal row.
  21. 21. receiver as claimed in claim 18, it is characterised in that the code length and code check that the ldpc decoder uses share Four kinds of selections, are code check 5/15 respectively, code length 16200；Code check 5/15, code length 64800；Code check 6/15, code length 64800；Code check 7/15, code length 64800.
  22. 22. receiver as claimed in claim 20, it is characterised in that the de-interleaving block is built-in to exchange pattern：
    For code check 5/15, the LDPC code of code length 16200, first bit stream is divided into 45 sub-blocks, the exchange pattern For：
    For code check 5/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange pattern For：
    For code check 6/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange pattern For：
    For code check 7/15, the LDPC code of code length 64800, first bit stream is divided into 180 sub-blocks, the exchange pattern For：
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