JP2007329592A - Interleaving device and communications device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform efficient interleave processing according to the size of transfer data, while taking into consideration the conformity, in an interleaver system between radio devices. <P>SOLUTION: The interleaving device rearranges input data according to a prescribed rule for output. The interleaving device comprises a storage means that stores the input data to be rearranged temporarily and allows the size of a region for storing the input data to be variable; a region size determination means for determining the region size of the storage means, according to the data size of at least the input data; and an interleave control means for changing the region size of the storage means to size determined by the region size determination means, for rearranging the input data stored in the storage means according a prescribed rule, and for outputting the rearranged data. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an interleaver device and a communication device, for example, an OFDM (Orthogonal Frequency Multiplexing) modulation method and a CSMA / CA (Carrier Sense Multiple Access With Collision Avoidance) method. The present invention can be applied to a wireless device in the adopted wireless system.

  Conventionally, there is a wireless LAN system constructed based on the IEEE 802.11 or IEEE 802.11a standard. In such a wireless LAN system, an OFDM modulation method is adopted as a modulation method, and a CSMA / CA method is adopted as access control.

  By the way, in the wireless LAN system, in order to avoid an error due to a burst error that may occur due to the influence of fading or the like in the wireless LAN system, interleaving is adopted in which burst errors are dispersed and reliable information is restored ( For example, see Patent Document 1).

  FIG. 2 shows a main configuration of a transceiver in a radio apparatus adopting the OFDM modulation scheme. Hereinafter, processing in a conventional transceiver will be briefly described.

  First, when input data is input to the convolutional encoding circuit unit 11 on the transmission side, the input data is convolutionally encoded and provided to the interleave circuit unit 12. The interleave circuit unit 12 rearranges the encoded data for each symbol (information constituent unit), and the rearranged data is given to the subcarrier modulation circuit unit 13 to perform a predetermined modulation process. Further, the modulated data that has been modulated is given to the transmitter 14, and is subjected to quadrature modulation and transferred.

  On the receiving side, when quadrature modulation data arrives at the receiver 15, the receiver 15 performs quadrature detection and receives it. The detected detection data is subjected to predetermined demodulation processing by the subcarrier demodulation circuit unit 16 and is given to the deinterleave circuit unit 17. The deinterleave circuit unit 17 rearranges the demodulated data so that the original data is arranged, and the rearranged data is supplied to the Viterbi decoding circuit unit 18 for decoding.

  3 and 4 are configuration diagrams showing main internal configurations of the interleave circuit unit 12 and the deinterleave circuit unit 17.

  As shown in FIGS. 3 and 4, the interleave circuit unit 12 and the deinterleave circuit unit 17 have a width of n bits (that is, columns are n bits: n is a positive integer) and a depth m (that is, rows are m stages: m Is a positive integer) m × n interleaver buffer 121 and m × n deinterleaver buffer 171.

In FIG. 3, for example, if the encoded data is composed of D ₁ , D ₂ ,..., D _mn , the encoded data is divided every n bits, and a data sequence II ₁ (= D ₁ , D ₂ , _{..., D n), II 2} (= D n + 1, D n + 2, ..., D 2n), ..., II m (= D (m-1) n + 1, D (m-1) n + 2, ..., D mn) and To do.

Then, each data of II ₁ , II ₂ ,..., II _m is written in order from the top side of the first row of the interleaver buffer 121, and when reading data, it is sequentially from the top side of the first column. Data is read, and data series IO ₁ (= D ₁ , D _{n + 1} , D _{2n + 1} ,..., D _{(m−1) n + 1} ), IO ₂ (= D ₂ , D _{n + 2} , D _{2n + 2} ,..., D _{(m−1) ) N + 2} ),..., IO _n (= D _n , D _2n , D _3n ,..., D _mn ) are obtained and combined to obtain rearranged data.

On the other hand, in FIG. 4, when demodulated data is input, the demodulated data is divided every n bits, and data series DI ₁ (= D ₁ , D _{n + 1} , D _{2n + 1} ,..., D _{(m−1) n + 1} ), DI ₂ (= D ₂ , D _{n + 2} , D _{2n + 2} ,..., D _{(m−1) n + 2} ),..., DI _n (= D _n , D _2n , D _3n ,..., D _mn ).

Then, each data of DI ₁ , DI ₂ ,..., DI _n is written in order from the top of the first column of the deinterleaver buffer 171, and when reading the data, the data is read from the top of the first row. To the data series DO ₁ (= D ₁ , D ₂ ,..., D _n ), DO ₂ (= D _{n + 1} , D _{n + 2} ,..., D _2n ), ..., DO _m (= D _{(m−1) ) N + 1} , D _{(m−1) n + 2} ,..., D _mn ) are obtained and combined to restore.

  Conventionally, the interleave size (referring to the sizes of the interleaver buffer 121 and the deinterleaver buffer 171) is determined by the subcarrier modulation method.

  That is, m (row) × n (column) of the interleave size is determined by (number of subcarriers) × (modulation scheme constant), and the number of subcarriers is generally 48 in OFDM modulation (52 if pilot subcarriers are included). This is determined by the modulation system constant. The modulation scheme constant is “1” for BPSK, “2” for QPSK, “4” for 16 QAM, and “6” for 64 QAM.

  In addition, the sub-modulation method recognition method between wireless devices is to send and receive a control signal in which the data size of the transmission data and the sub-carrier modulation method are added to the Physical Layer Convergence Protocol header between the wireless devices before data transmission. Thus, the data size and the subcarrier modulation scheme are recognized.

JP 2005-210708 A

  However, when performing narrowband wireless communication in a wireless system employing the OFDM modulation scheme, the conventional interleave circuit unit and deinterleave circuit unit have the following problems.

  For example, in the CSMA / CA system, every time large data is sent once, the communication partner returns an ACK frame, and this is alternately and continuously repeated. Therefore, if the same interleaving process is performed on a small ACK frame as in the case of a frame having a large data size, a data transfer delay associated with the interleaving process may occur, resulting in a decrease in communication speed of the entire system. .

  For this reason, there is a need for an interleaving device and a communication device that can perform efficient interleaving processing according to the data size of transfer data while considering the consistency of the interleaver method between the communication devices.

  In order to solve this problem, an interleaving apparatus according to a first aspect of the present invention is an interleaving apparatus that rearranges the order of input data according to a predetermined rule and outputs the rearranged data. Storage means for temporarily storing certain input data, and the area size for storing the input data is variable; and (2) determining the area size of the storage means according to at least the data size of the input data. (3) The area size of the storage means is changed to the size determined by the area size determination means, the input data stored in the storage means is rearranged according to a predetermined rule, and the rearranged data is output. And interleaving control means.

  A communication apparatus according to a second aspect of the present invention provides an interleaving apparatus that rearranges the order of data to be transmitted according to a predetermined rule and transmits the data, or rearranges the order of received data according to a predetermined rule to the order of the original data. In the communication device provided, the interleave device is the interleave device according to the first aspect of the present invention.

  According to the wireless device including the interleave device of the present invention, efficient interleaving processing can be performed in accordance with the data size of the transfer data while considering the consistency of the interleaver method between the communication devices.

(A) First Embodiment Hereinafter, a first embodiment of an interleave device and a wireless device of the present invention will be described with reference to the drawings.

  In the present embodiment, an example in which the interleaving apparatus of the present invention is applied to a wireless apparatus in a wireless system that employs an OFDM modulation system as a modulation system and a CSMA / CA system as an access control system will be described.

(A-1) Configuration of First Embodiment FIG. 1 is a block diagram illustrating a main internal configuration of a transceiver of a wireless device according to the present embodiment.

  As shown in FIG. 1, the transceiver 10 of this embodiment includes a frame generation circuit unit 1, a convolutional coding circuit unit 2, an interleaving circuit unit 3, a subcarrier modulation circuit unit 4, a subcarrier demodulation circuit unit 5, and a deinterleaving unit. The circuit unit 6, the Viterbi decoding circuit unit 7, the control circuit unit 8, and the interleave size setting unit 9 are configured at least.

  When transmitting data, the frame generation circuit unit 1 captures data to be transmitted, forms a predetermined transmission frame based on the data, and supplies the transmission frame to the convolutional coding circuit unit 2.

  At this time, the frame generation circuit unit 1 captures the data size of the data to be transmitted, calculates the delay amount due to the interleaving process of the interleave circuit unit 3 based on the data size, and sets the Duration (medium reservation time) in the frame ) A transmission frame is formed by reflecting the value calculation.

  The convolutional coding circuit unit 2 performs convolutional coding on the transmission frame data received from the frame generation circuit unit 1 and supplies the convolutional coded data to the interleave circuit unit 3.

  When the interleaving circuit unit 3 receives the convolutional encoded data from the convolutional encoding circuit unit 2, the interleaving circuit unit 3 performs interleaving processing on the convolutional encoded data, and gives the rearranged data in which the data order is rearranged to the subcarrier modulation circuit unit 4. Is.

  In addition, the interleave circuit unit 3 forms size information for determining the size of the interleaver buffer from the interleave size setting unit 9 in order to form an interleaver buffer having a size corresponding to the data size (also referred to as the number of symbols in this embodiment). ) And an interleaver buffer is formed based on the number of symbols.

  It should be noted that after the interleaver buffer is formed, it is desirable to perform interleaving processing of the convolutionally encoded data.

  The subcarrier modulation circuit unit 4 modulates the rearranged data given from the interleave circuit unit 3 with a plurality of subcarriers. The subcarrier modulation scheme by the subcarrier modulation circuit unit 4 includes, for example, BPSK, QPSK, 16QAM, and 64QAM.

  When receiving the received detection data, the subcarrier demodulation circuit unit 5 performs a predetermined demodulation process on the detected data and gives the demodulated data to the deinterleave circuit unit 6.

  Here, the demodulation processing by the subcarrier demodulation circuit unit 5 corresponds to the modulation processing by the subcarrier modulation circuit 4, and recognizes the subcarrier modulation scheme based on the PLCP header transmitted from the transmission side before data transmission. can do.

  The deinterleaving circuit unit 6 receives the demodulated data from the subcarrier demodulation circuit unit 5 and performs deinterleaving processing on the demodulated data, thereby rearranging and restoring the order of the data. This is given to the decoding circuit unit 7.

  Further, the deinterleave circuit unit 6 receives the number of symbols from the interleave size setting unit 9 in order to form a deinterleave buffer corresponding to the interleave size on the transmission side, and forms a deinterleaver buffer based on the number of symbols. To do.

  It is desirable to perform deinterleaving processing of demodulated data after the deinterleaver buffer is formed.

  The Viterbi decoding circuit unit 7 receives the rearranged data from the deinterleave circuit unit 6 and performs Viterbi decoding on the rearranged data.

  The control circuit unit 8 gives a transmission / reception switching signal to the interleave size setting unit 9 based on the determination of the transmission status and the reception status by a conveyance path status determination unit (not shown).

  When the interleave size setting unit 9 receives the transmission / reception switching signal from the control circuit unit 8, the interleaving size setting unit 9 recognizes whether the wireless device is in a transmission state or a reception state based on the transmission / reception switching signal. In this case, the interleave size of the interleave circuit unit 3 is set, and in the reception state, the interleave size of the deinterleave circuit unit 6 is set.

  Further, the interleave size setting unit 9 receives the transmission data size or the reception data size, determines an interleave size according to the transmission data size or the reception data size with reference to the interleave size setting table 9a, and determines the determined size information. This is given to the interleave circuit unit 3 or the deinterleave circuit unit 6.

  FIG. 5 is an explanatory diagram illustrating a configuration example of the interleave size setting table 9a. In FIG. 5, the interleave size setting table 9a is configured by associating the data size of the transmission frame or the reception frame with the interleave size.

  The interleave size in FIG. 5 is information for determining the number of stages (number in the row direction) of the m × n interleaver buffer 31 or the m × n deinterleaver buffer 61. In this embodiment, subcarrier modulation of transmission data or reception data is performed. The number of information symbols that can be transferred with one carrier in the system.

  For example, in FIG. 5, when the data size is “0 to 255 bytes”, the interleave size is “1 symbol”, and when the data size is “256 to 512 bytes”, the interleave size is “4 symbols”. In the case of “513 to 1024 bytes”, the interleave size is “16 symbols”, and in the case of the data size “1025 bytes or more”, the interleave size is “64 symbols”.

  Next, configurations of the interleave circuit unit 3 and the deinterleave circuit unit 6 will be described with reference to the drawings.

  6, 7, and 10 show configuration examples of the interleave circuit unit 3, and FIGS. 8, 9, and 11 show configuration examples of the deinterleave circuit unit 6.

  As shown in FIG. 10, the interleave circuit unit 3 of this embodiment includes an interleaver configuration control unit 32 that configures the size of the interleaver buffer 31 based on the number of symbols from the interleaver buffer 31 and the interleave size setting unit 9, encoded data At least an input rearrangement unit 33 that writes data to the interleaver buffer 31 and an output rearrangement unit 34 that reads rearrangement data from the interleaver buffer 31.

  As shown in FIG. 6, the interleave circuit unit 31 of this embodiment includes an interleaver buffer 31 that takes in encoded data, temporarily holds the data, and rearranges the data. The interleaver buffer 31 is a matrix buffer memory of m (m: positive integer) × n (n: positive integer).

  The interleaver buffer 31 according to the present embodiment can change the number of stages in the row direction (that is, the depth direction) based on the size information (also referred to as the number of symbols in the present embodiment) given from the interleave size setting unit 9. It is.

  That is, the interleaver configuration control unit 32 configures a basic interleave size based on the subcarrier modulation scheme of transmission data during data transmission. This interleave size is determined by m × n = (number of subcarriers) × (modulation scheme constant), as in the conventional interleave size.

  Thereafter, the interleaver configuration control unit 32 expands the number of stages in the row direction of the interleaver buffer 31 to m × s based on the size information (number of symbols) s from the interleave size setting unit 9 and changes the interleave size.

  In this way, by changing the interleave size depending on the size of the transmission data, a large interleaver can be applied to large data, and a small interleaver can be applied to small data. Can be applied.

  As a result, it is possible to reduce interleaving processing for small data, reduce data transfer delay, and improve the communication speed of the entire system.

  Further, as shown in FIG. 11, the deinterleave circuit unit 6 of the present embodiment performs deinterleaver configuration control that configures the size of the deinterleaver buffer 61 based on the number of symbols from the deinterleaver buffer 61 and the interleave size setting unit 9. Unit 62, input reordering unit 63 that writes detection data to deinterleaver buffer 61, and output reordering unit 64 that reads reordered data from deinterleaver buffer 61.

  As shown in FIG. 8, the deinterleave circuit unit 7 of this embodiment has an interleaver buffer 71 that takes in demodulated data and temporarily holds the data for rearrangement for restoration.

  The deinterleaver buffer 61 according to the present embodiment can change the number of stages in the row direction (that is, the depth direction) based on the number of symbols s given from the interleave size setting unit 9, similarly to the interleaver buffer 31 described above. Is.

(A-2) Operation of the First Embodiment Next, the operation of the interleave size setting process in the transceiver 10 of the present embodiment will be described.

  First, a conveyance path state determination unit (not shown in FIG. 1) determines whether the transceiver 10 is in a transmission state or a reception state by a predetermined determination method, and based on the determination result, a control circuit unit 8 gives a transmission / reception switching signal to the interleave size setting unit 9. Thereby, it is possible to determine whether to set the interleave size to the transmission data size or the reception data size.

  The control circuit unit 8 of the present embodiment notifies the transmission / reception switching signal notifying only when the transmission / reception status is switched, but is not particularly limited as long as it can notify the switching of the transmission / reception status.

  When the interleave size setting unit 9 receives a transmission / reception switching signal from the control circuit unit 8, it can recognize whether the current state is a transmission state or a reception state based on reception of the transmission / reception switching signal. .

  In the case of the transmission status, first, a PLCP header having information on the transmission data size and subcarrier modulation scheme is created and transmitted to the opposite radio apparatus.

  Next, when the transmission data is given to the frame generation circuit unit 1, the frame generation circuit unit 1 calculates the delay amount due to the interleaving processing of the interleave circuit unit 3 based on the transmission data size, and generates a Duration in the generated frame. A frame reflected in the (medium reservation time) value calculation is generated, and the generated transmission frame is given to the convolutional coding circuit unit 2.

  When the transmission frame from the frame generation circuit unit 1 is given to the convolutional coding circuit unit 2, the transmission frame is convolutionally coded and given to the interleaving circuit unit 3.

  When the encoded data is supplied to the interleave circuit unit 3, the interleave circuit unit 3 rearranges the data by an interleaver adjusted to a size corresponding to the data size of the encoded data, and the rearranged data is converted into a subcarrier. The signal is supplied to the modulation circuit unit 4.

  At this time, the interleave circuit 3 sets a basic interleaver having a size corresponding to one symbol based on the subcarrier modulation scheme. The basic interleaver size m × n can be obtained by m × n = number of subcarriers × modulation system constant. The modulation scheme constant is “1” for BPSK, “2” for QPSK, “4” for 16 QAM, and “6” for 64 QAM.

  The interleave circuit unit 3 receives the number of symbols indicating the interleave size corresponding to the transmission data size from the interleave size setting unit 9, and sets an interleaver whose depth is changed according to the number of symbols.

  For example, when the number of symbols given from the interleave size setting unit 9 is s, as shown in FIG. 6, the depth direction (row direction) of the basic interleaver with width (column) n bits and depth (row) m. S m × n interleavers are set, and an interleaver buffer 31 having a width (column) of n bits and a depth (row) of m × s is formed.

  When the interleave circuit unit 3 sets an interleaver buffer 31 having an interleave size corresponding to the transmission data size, the encoded data is divided every n bits, and the data is interleaved buffer 31 in order from the beginning of the first row. Is written to.

For example, in FIG. 6, it is assumed that the encoded data are D ₁ , D ₂ ,... D _mn , D _{m (n + 1) ,.}

When it is divided for each n bits, the data series _{II 1 (= D 1, D} 2, ..., D n), II 2 (= D n + 1, D n + 2, ..., D 2n), ... II m (= D _{(m-1) (n + 1)} , D _{(m-1) (n + 2)} , ..., _Dmn ), _{IIm + 1} (= _{Dm (n + 1)} , _{Dm (n + 2)} , ..., D _{(m + 1) n} ) II _sm (= D _{(s-1) m (n + 1)} , D _{(s-1) m (n + 2)} ,..., _Dsmn ), and these data are written in the interleave buffer 31 as shown in FIG. .

When reading data, data series IO ₁ (= D ₁ , D _{n + 1} , D _{2n + 1} ,..., D _{(s−1) m (n + 1)} ), IO ₂ (= D ₂ , D _{n + 2} , D _{2n + 2} , _{..., D (s-1)} m (n + 2)), ..., IO n (= D n, D 2n, D 3n, ..., read as _{D smn),} these _{IO 1, IO 2, ...,} in order to IO _n Line up and output as rearranged data.

  When the rearranged data from the interleave circuit unit 3 is given to the subcarrier modulation circuit unit 4, a plurality of subcarriers are modulated according to a predetermined modulation method based on the rearranged data, and transmitted from a transmitter (not shown in FIG. 1). Transmission data is transferred.

  On the other hand, in the case of reception status, the received data size and subcarrier modulation scheme are recognized based on the PLCP header of the received frame received by the receiver (not shown in FIG. 1).

  When the detection data detected by the receiver is supplied to the subcarrier demodulation circuit 5, the detection data is demodulated in accordance with a predetermined demodulation method in the subcarrier demodulation circuit 5 and is supplied to the deinterleave circuit unit 6.

  At this time, the deinterleave circuit unit 6 sets a basic interleaver having a size corresponding to one symbol based on the recognized subcarrier modulation scheme.

  Further, the deinterleave circuit unit 6 receives the number of symbols indicating the interleave size corresponding to the received data size from the interleave size setting unit 9, and sets the interleaver whose depth is changed according to the number of symbols.

  For example, when the number of symbols given from the interleave size setting unit 9 is s, as shown in FIG. 8, the depth direction (row direction) of the basic interleaver with width (column) n bits and depth (row) m. S m × n deinterleavers are set to form a deinterleaver buffer 61 having a width (column) of n bits and a depth (row) of m × s.

  When the deinterleave circuit unit 6 sets the deinterleaver buffer 61 having an interleave size corresponding to the received data size, the demodulated data is written to the deinterleave buffer 61 in order from the top of the first column.

For example, in FIG. 8, the demodulated data includes data series DI ₁ (= D ₁ , D _{n + 1} , D _{2n + 1} ,..., D _{(s−1) m (n + 1)} ), DI ₂ (= D ₂ , D _{n + 2} , D _{2n + 2, ..., D (} s-1) m (n + 2)), ... DI n (= D n, D 2n, ..., D smn) next, these data are written into the de-interleave buffer 61, as shown in FIG. 8 .

Also, when reading data, the data sequence _{DO 1 (= D 1, D} 2, D 3, ..., D n), DO 2 (= D n + 1, D n + 2, ..., D 2n), ..., DO m ( = D _{(m-1) (n + 1)} , D _{(m-1) (n + 2)} , ..., _Dmn ), DOm _{+ 1} (= _{Dm (n + 1)} , _{Dm (n + 2)} , ..., D _{(m + 1) n ), ..., DO sm (=} D (s-1) m (n + 1), D (s-1) m (n + 2), ..., read as _{D Smn),} they _{DO 1, DO 2, ...,} DO m, DO _{m + 1} ,..., DO _sm are arranged in order and output as rearranged data.

  When the rearranged data from the deinterleave circuit unit 6 is given to the Viterbi decoding circuit unit 7, the rearranged data is Viterbi decoded.

(A-3) Effect of First Embodiment As described above, according to the present embodiment, the interleave size is changed according to the data size of transmission data or reception data by providing the interleave size setting unit 9. It is possible to reduce the interleaving process for a small data size, reduce the data transfer delay, and improve the communication speed of the entire system.

  Further, according to the present embodiment, since it is possible to apply a large interleave size to a large size data frame, it is possible to further improve the transfer quality.

(B) Other Embodiments In the above-described embodiments, the case where the present invention is applied to a wireless device has been described. However, the present invention is not limited to a wireless device, and can be applied to a device that uses an OFDM modulation scheme in a wired data communication device. It is.

  In the above-described embodiment, as a method for matching the interleaving method, each wireless device is provided with the interleave size setting table 9a and the interleave size is set in each wireless device. However, the present invention is not limited to this. For example, the PLCP header may be extended, and an interleave size determined on the transmission side may be added to the PLCP header to be recognized between wireless devices.

  In the above-described embodiment, the case where the number of stages in the row direction (depth direction) of the interleaver buffer 31 and the deinterleaver buffer 61 is changed has been described. However, if possible, the column direction (width direction) may be changed. Further, both the row direction and the column direction may be changed.

  In the above-described embodiment, the function of determining the interleave size of the interleave buffer 31 and the deinterleave buffer and configuring the interleaver can be realized in software or hardware.

  FIG. 5 shows a configuration example of the interleave size setting table, and other configurations may be used as long as the interleave size can be determined according to the data size. In the above-described embodiment, the data frame encoding method and decoding method are not particularly limited.

It is a block diagram which shows the internal structure of the transmitter / receiver of 1st Embodiment. It is a block diagram which shows the internal structure of the conventional transmitter / receiver. It is a block diagram which shows the structure of the conventional interleave circuit. It is a figure explaining the structure and process of the conventional deinterleave circuit. It is explanatory drawing explaining the structural example of the interleave size setting table of 1st Embodiment. It is a block diagram which shows the structure of the interleave circuit part of 1st Embodiment (1). It is a block diagram which shows the structure of the interleave circuit part of 1st Embodiment (2). It is a block diagram which shows the structure of the deinterleave circuit part of 1st Embodiment (1). It is a block diagram which shows the structure of the deinterleave circuit part of 1st Embodiment (2). It is a functional block diagram which shows the internal structure of the interleave circuit part of 1st Embodiment. It is a functional block diagram which shows the internal structure of the interleave circuit part of 1st Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Frame generation circuit part, 2 ... Convolution coding circuit part, 3 ... Interleaving circuit part, 4 ... Subcarrier modulation circuit part, 5 ... Subcarrier demodulation circuit part, 6 ... Deinterleaving circuit part, 7 ... Viterbi decoding circuit part , 8 ... Control circuit unit, 9 ... Interleave size setting unit, 9a ... Interleave size setting table, 10 ... Transceiver, 31 ... Inleaver buffer, 32 ... Interleaver configuration control unit, 33 ... Input reordering unit, 34 ... Output parallel Replacement unit, 61 ... deinterleaver buffer, 62 ... deinterleaver configuration control unit, 63 ... input rearrangement unit, 64 ... output rearrangement unit.

Claims (5)

In an interleaving device that rearranges the order of input data according to a predetermined rule and outputs the rearranged data,
Storage means for temporarily storing the input data to be rearranged, and having a variable area size for storing the input data;
Area size determining means for determining the area size of the storage means according to at least the data size of the input data;
Interleaving control means for changing the area size of the storage means to the size determined by the area size determination means, rearranging the input data stored in the storage means according to a predetermined rule, and outputting rearranged data. An interleaving device characterized by.   The region size determining means refers to a predetermined region size setting table in which the region size is determined according to the input data size to be rearranged, and determines the region size based on the data size of the input data. The interleaving apparatus according to claim 1.   3. The interleaving apparatus according to claim 1, wherein the size of the area for storing the input data is a storage area indicated by an m × n matrix, and at least the row direction is variable. In a communication device including an interleave device that rearranges the order of data to be transmitted according to a predetermined rule and transmits the received data or rearranges the order of received data according to a predetermined rule in the order of the original data.
A communication apparatus, wherein the interleave apparatus is the interleave apparatus according to any one of claims 1 to 3. Comprising a communication means for exchanging a control signal including information regarding the region size of the interleave device with an opposing communication device;
The region size determining means of the interleave device determines the region size of the interleave device of its own device based on the information regarding the region size of the interleave device on the opposite communication device side included in the control signal. A communication device characterized by:

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