JP5937194B2 - Apparatus and method for signal mapping / demapping in a system using a low density parity check code - Google Patents

Description

  The present invention relates to an apparatus and method for signal mapping / demapping in a system using a low density parity check (hereinafter referred to as 'LDPC') code.

  In communication systems, link performance may be significantly degraded due to channel noise, fading phenomena, and inter-symbol interference (ISI). Therefore, in the next generation communication system, consideration is given to actively using an LDPC code as an error-correcting code.

FIG. 1 is a diagram schematically illustrating a general LDPC encoding process.
Referring to FIG. 1, the LDPC encoder 110 is an information word vector _having a length of K _ldpc.
LDPC codeword vector
Is generated. Here, the information word vector includes a total of K _ldpc information bits. That is, the information word vector
Each of the elements is an information bit.

The LDPC encoder 110 uses a parity check matrix in which the number of columns is N _ldpc and N _ldpc −K _ldpc parity vectors.
An LDPC code using the information word vector and the parity vector, that is, an LDPC codeword vector
Is generated.

On the other hand, the next generation communication system actively considers the use of QAM (Quadrature Amplitude Modulation) modulation method with high frequency efficiency due to the demand for high-speed data transmission and the development of hardware. In this case, each modulation bit included in one QAM symbol has a different error probability.
Also, the error correction capability of each LDPC codeword bit included in the LDPC codeword vector is determined to correspond to the degree of the variable node corresponding to each LDPC codeword bit. The

  Therefore, even when the same LDPC code is used, the error probability of the corresponding QAM modulation symbol varies depending on which modulation bit in the QAM modulation symbol is used to map the LDPC codeword bit. Therefore, there is a need for a method of mapping LDPC codeword bits to modulation bits included in the QAM modulation symbol so that the error probability of the QAM modulation symbol can be minimized.

The present invention proposes a signal mapping / demapping apparatus and method in a system using an LDPC code.
In addition, the present invention proposes a mapping / demapping apparatus and method between an LDPC codeword and a QAM modulation symbol in a system using an LDPC code.

  According to one aspect of the present invention, a signal transmission apparatus in a system using a low density parity check (LDPC) code is provided. The signal transmission apparatus writes an LDPC codeword bit in a column direction, reads an LDPC codeword bit written in a row direction, and de-multiplexing the read bit. ) Method to generate a sub-stream by demultiplexing, and the bits included in each of the sub-streams as symbols in a signal constellation The demultiplexing scheme is determined to correspond to the modulation scheme used in the signal transmission apparatus, the length of the LDPC codeword, and the number of substreams. It is characterized by that.

  According to another aspect of the present invention, a signal receiving apparatus of a system using a low density parity check (LDPC) code is provided. The signal receiving apparatus includes a multiplexer that multiplexes sub-streams using a multiplexing scheme, a deinterleaver that deinterleaves the multiplexed bits, and the deinterleaver. An LDPC decoder that generates LDPC codeword bits by LDPC decoding of the leaved bits, and the multiplexing scheme is determined to correspond to the demultiplexing scheme used in the signal transmission apparatus, The demultiplexing scheme is determined so as to correspond to a modulation scheme used in the signal transmission apparatus, a length of an LDPC codeword, and the number of substreams.

  According to still another aspect of the present invention, a signal mapping method in a signal transmission apparatus of a system using a low density parity check (LDPC) code is provided. The method includes writing LDPC codeword bits in a column direction, reading the written LDPC codeword bits in a row direction, and de-multiplexing the read bits. ) A step of generating a sub-stream by demultiplexing using a method, and a step of mapping bits included in each of the sub-streams in a signal constellation with symbols And the demultiplexing scheme is determined to correspond to the modulation scheme used in the signal transmission apparatus, the length of the LDPC codeword, and the number of substreams. To do.

  According to another aspect of the present invention, a signal mapping method in a signal receiving apparatus of a system using a low density parity check (LDPC) code is provided. The method includes multiplexing a sub-stream using a multiplexing scheme, deinterleaving the multiplexed bits, and deinterleaving the deinterleaved bits. And LDPC decoding to generate LDPC codeword bits, wherein the multiplexing scheme is determined to correspond to the demultiplexing scheme used in the signal transmission apparatus, and the demultiplexing scheme is It is determined to correspond to the modulation scheme used in the signal transmission apparatus, the length of the LDPC codeword, and the number of substreams.

The present invention minimizes the error probability of a system using an LDPC code by allowing LDPC codeword bits to be mapped to modulation symbols to correspond to the modulation scheme used, and thus the overall It has the effect of improving system performance.
The above and other aspects, features and advantages of the present invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings.
In the drawings, it should be understood that the same reference numerals denote the same components, characteristics, and structures.

FIG. 10 is a diagram schematically illustrating a general LDPC encoding process. FIG. 3 is a diagram illustrating an internal structure of a signal transmission device of a system using an LDPC code according to an embodiment of the present invention. FIG. 6 illustrates a 16-QAM signal constellation according to an embodiment of the present invention. FIG. 6 illustrates a 64-QAM signal constellation according to an embodiment of the present invention. FIG. 6 illustrates a 256-QAM signal constellation according to one embodiment of the present invention. FIG. 6 illustrates a 256-QAM signal constellation according to one embodiment of the present invention. FIG. 6 illustrates a 256-QAM signal constellation according to one embodiment of the present invention. FIG. 6 illustrates a 256-QAM signal constellation according to one embodiment of the present invention. FIG. 3 is a diagram schematically illustrating an operation process of the interleaver of FIG. 2 according to an embodiment of the present invention. FIG. 3 schematically illustrates an operation process of the demultiplexer of FIG. 2 according to an embodiment of the present invention. FIG. 6 is a diagram schematically illustrating an example of an operation process of a demultiplexer when N _ldpc = 16200 and a 16-QAM modulation scheme is used according to an exemplary embodiment of the present invention. FIG. 6 is a diagram schematically illustrating another example of an operation process of a demultiplexer when N _ldpc = 16200 and a 64-QAM modulation scheme is used according to an embodiment of the present invention; FIG. 10 is a diagram schematically illustrating still another example of an operation process of a demultiplexer when N _ldpc = 16200 and a 16-QAM modulation scheme is used according to an embodiment of the present invention; FIG. 10 is a diagram schematically illustrating still another example of an operation process of a demultiplexer when N _ldpc = 16200 and a 16-QAM modulation scheme is used according to an embodiment of the present invention; FIG. 7 is a diagram schematically illustrating still another example of an operation process of a demultiplexer when N _ldpc = 16200 and a 64-QAM modulation scheme is used according to an embodiment of the present invention; FIG. 7 is a diagram schematically illustrating still another example of an operation process of a demultiplexer when N _ldpc = 16200 and a 64-QAM modulation scheme is used according to an embodiment of the present invention; FIG. 10 is a diagram schematically illustrating still another example of an operation process of a demultiplexer when N _ldpc = 16200 and a 16-QAM modulation scheme is used according to an embodiment of the present invention; FIG. 10 is a diagram schematically illustrating still another example of an operation process of a demultiplexer when N _ldpc = 16200 and a 256-QAM modulation scheme is used according to an embodiment of the present invention; FIG. 10 is a diagram schematically illustrating still another example of an operation process of a demultiplexer when N _ldpc = 16200 and a 256-QAM modulation scheme is used according to an embodiment of the present invention; FIG. 3 is a diagram illustrating an internal structure of a signal reception device of a system using an LDPC code according to an embodiment of the present invention. FIG. 3 is a diagram illustrating an internal structure of the demultiplexer of FIG. 2 according to an embodiment of the present invention. FIG. 18 is a diagram illustrating an internal structure of the multiplexer of FIG. 17 according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
In the following description, specific details such as specific configurations and components are provided only to assist in a general understanding of embodiments of the present invention. Accordingly, it will be apparent to those skilled in the art that various modifications and variations of the present invention described below can be made without departing from the scope and spirit of the invention. Note that specific descriptions of known functions or configurations are omitted for clarity and conciseness.

According to an embodiment of the present invention, a signal mapping / demapping apparatus and method in a system using a low density parity check (hereinafter referred to as 'LDPC') code is proposed. .
According to another embodiment of the present invention, an apparatus and method for mapping / demapping between an LDPC codeword and a QAM (Quadrature Amplitude Modulation) modulation symbol is proposed.

  Hereinafter, in the description of the present invention, a system using an LDPC code can take various forms. System, MMT (MPEG (Moving Picture Experts Group) Media Transport) system, evolved packet system (hereinafter referred to as “EPS”), LTE (Long-Term Evolution) mobile communication system, and IEEE (Institute of Electrical and Electronics Engineers) Of course, it can be a communication system such as an 802.16m communication system.

  Further, although the present invention will be described using an LDPC code as an example, it goes without saying that not only an LDPC code but also other codes can be applied to the apparatus and method proposed in the present invention. Although the present invention will be described by taking the QAM scheme as an example, it is needless to say that not only the QAM scheme but also other modulation schemes can be applied to the apparatus and method proposed in the present invention.

FIG. 2 is a diagram illustrating an internal structure of a signal transmission apparatus in a system using an LDPC code.
Referring to FIG. 2, the signal transmission apparatus includes an LDPC encoder 210, a preprocessor 220, an interleaver 230, a de-multiplexer (DEMUX) 240, a symbol mapper (symbol). mapping unit) 250.

The LDPC encoder 210 is an information vector.
A parity vector including N _ldpc −K _ldpc parity bits
_And an LDPC codeword vector having a length of N _ldpc is generated and output to the preprocessor 220. The pre-processor 220 uses an LDPC codeword vector
Is pre-processed using a pre-set pre-processing method
Is output to the interleaver 230. Here, the preprocessor 220 may be omitted, or the function thereof may be integrated and implemented in the interleaver 230, and the specific description of the preprocessing method itself is omitted.

The interleaver 230 writes the vector U in Nc columns in the column-wise direction and writes it in the row-wise direction.
Is output to the demultiplexer 240. The demultiplexer 240 demultiplexes the vector V in units of Nc and performs N _{substreams substreams.}
Is output to the symbol mapper 250. The symbol mapper 250 uses a bit corresponding to each of the N _{substreams substreams} as an input and has a length.
Is a cell word
Are mapped to signal points in the signal constellation to generate a symbol Z. At this time,
Is a divisor of N _substreams .

  On the other hand, FIG. 3, FIG. 4, FIG. 5A, FIG. 5B, FIG. 5C and FIG. It is the figure which showed schematically the mapping relationship between signal constellations.

FIG. 6 is a diagram schematically illustrating an operation process of the interleaver 230 of FIG. 2 according to an embodiment of the present invention.
In FIG. 6, it is assumed that the interleaver 230 is implemented with Nc columns and N _ldpc / Nc rows.
First, assuming that N _ldpc = 16200, the number of rows Nr and the number of columns Nc according to the 16-QAM modulation method and the 64-QAM modulation method are implemented as shown in Table 1 below.

First, the interleaver 230 sequentially writes the received vector U to Nc columns in the column direction and reads in the row direction. Note that at this time, the first storage position in each row can be moved by the twist parameter tc. When N _ldpc = 16200, the twist parameter tc can be expressed as shown in Table 2 below using 16-QAM and 64-QAM modulation schemes.

FIG. 7 is a diagram schematically illustrating an operation process of the demultiplexer 240 of FIG. 2 according to an embodiment of the present invention.
Referring to FIG. 7, the demultiplexer 240 operates as follows: Vi (i = 0, 1,..., N _ldpc −1) and bj (j = 0, 1,..., N _substreams −1). In the case where N _ldpc is a multiple of N _substreams , the same rule can be applied and extended.

FIG. 8 is a diagram schematically illustrating an example of an operation process of the demultiplexer 240 when N _ldpc = 16200 and the 16-QAM modulation scheme is used.
In FIG. 8, assuming that N _substreams = 8, the demultiplexer 240 maps the input bits v0 to v7 to the output bits b0 to b7.
That is, the demultiplexer 240 sets bit v0 to bit b2, bit v1 to bit b4, bit v2 to bit b5, bit v3 to bit b0, bit v4 to bit b7, and bit v5 to bit b1. , Bit v6 is mapped to bit b3, and bit v7 is mapped to bit b6.

FIG. 9 is a diagram schematically illustrating another example of the operation process of the demultiplexer 240 when N _ldpc = 16200 and the 64-QAM modulation scheme is used.
In FIG. 9, assuming that N _substreams = 12, the demultiplexer 240 maps the input bits v0 to v11 to the output bits b0 to b11.
That is, the demultiplexer 240 sets bit v0 to bit b4, bit v1 to bit b0, bit v2 to bit b1, bit v3 to bit b6, bit v4 to bit b2, and bit v5 to bit b3. , Bit v6 is mapped to bit b8, bit v7 is mapped to bit b9, bit v8 is mapped to bit b7, bit v9 is mapped to bit b5, bit v10 is mapped to bit b10, and bit v11 is mapped to bit b11.

FIG. 10 is a diagram schematically illustrating still another example of the operation process of the demultiplexer 240 when N _ldpc = 16200 and the 16-QAM modulation scheme is used.
In FIG. 10, assuming that N _substreams = 8, the demultiplexer 240 maps the input bits v0 to v7 to the output bits b0 to b7.
That is, the demultiplexer 240 sets bit v0 to bit b2, bit v1 to bit b4, bit v2 to bit b5, bit v3 to bit b1, bit v4 to bit b6, and bit v5 to bit b0. , Bit v6 is mapped to bit b7, and bit v7 is mapped to bit b3.

FIG. 11 is a diagram schematically illustrating still another example of the operation process of the demultiplexer 240 when N _ldpc = 16200 and the 16-QAM modulation scheme is used.
In FIG. 11, assuming that N _substreams = 8, the demultiplexer 240 maps the input bits v0 to v7 to the output bits b0 to b7. That is, the demultiplexer 240 sets bit v0 to bit b2, bit v1 to bit b0, bit v2 to bit b1, bit v3 to bit b3, bit v4 to bit b6, and bit v5 to bit b4. , Bit v6 is mapped to bit b7, and bit v7 is mapped to bit b5.

FIG. 12 is a diagram schematically illustrating still another example of the operation process of the demultiplexer 240 when N _ldpc = 16200 and the 64-QAM modulation scheme is used.
In FIG. 12, assuming that N _substreams = 12, the demultiplexer 240 maps the input bits v0 to v11 to the output bits b0 to b11.
That is, the demultiplexer 240 sets bit v0 to bit b4, bit v1 to bit b2, bit v2 to bit b0, bit v3 to bit b5, bit v4 to bit b6, and bit v5 to bit b1. , Bit v6 to bit b3, bit v7 to bit b7, bit v8 to bit b8, bit v9 to bit b9, bit v10 to bit b10, and bit v11 to bit b11.

FIG. 13 is a diagram schematically illustrating still another example of the operation process of the demultiplexer 240 when N _ldpc = 16200 and the 64-QAM modulation scheme is used.
In FIG. 13, assuming that N _substreams = 12, the demultiplexer 240 maps the input bits v0 to v11 to the output bits b0 to b11.
That is, the demultiplexer 240 sets bit v0 to bit b4, bit v1 to bit b0, bit v2 to bit b1, bit v3 to bit b6, bit v4 to bit b2, and bit v5 to bit b3. , Bit v6 to bit b5, bit v7 to bit b8, bit v8 to bit b7, bit v9 to bit b10, bit v10 to bit b9 and bit v11 to bit b11.

FIG. 14 is a diagram schematically illustrating still another example of the operation process of the demultiplexer 240 when N _ldpc = 16200 and the 16-QAM modulation scheme is used.
In FIG. 14, assuming that N _substreams = 8, the demultiplexer 240 maps the input bits v0 to v7 to the output bits b0 to b7.
That is, the demultiplexer 240 sets bit v0 to bit b2, bit v1 to bit b0, bit v2 to bit b4, bit v3 to bit b1, bit v4 to bit b6, and bit v5 to bit b5. , Bit v6 is mapped to bit b7, and bit v7 is mapped to bit b3.

FIG. 15 is a diagram schematically illustrating still another example of the operation process of the demultiplexer 240 when N _ldpc = 16200 and the 256-QAM modulation scheme is used.
In FIG. 15, assuming that N _substreams = 8, the demultiplexer 240 maps the input bits v0 to v7 to the output bits b0 to b7.
That is, the demultiplexer 240 sets bit v0 to bit b4, bit v1 to bit b0, bit v2 to bit b1, bit v3 to bit b2, bit v4 to bit b5, and bit v5 to bit b3. , Bit v6 is mapped to bit b6 and bit v7 is mapped to bit b7.

FIG. 16 is a diagram schematically showing still another example of the operation process of the demultiplexer 240 when N _ldpc = 16200 and the 256-QAM modulation scheme is used.
In FIG. 16, assuming that N _substreams = 8, the demultiplexer 240 maps the input bits v0 to v7 to the output bits b0 to b7.
That is, the demultiplexer 240 sets bit v0 to bit b4, bit v1 to bit b0, bit v2 to bit b5, bit v3 to bit b1, bit v4 to bit b2, and bit v5 to bit b3. , Bit v6 is mapped to bit b6 and bit v7 is mapped to bit b7.

  As described above, in the embodiment of the present invention, the demultiplexer provides LDPC codeword bits to the symbol mapper according to a preset mapping rule. Thus, when LDPC codeword bits are mapped to symbols (eg, symbols in a QAM signal constellation), the signals have different performance due to different mapping rules.

FIG. 17 is a diagram illustrating an internal structure of a signal receiving device in a system using an LDPC code.
Referring to FIG. 17, the signal receiving apparatus includes a bit metric calculator 1710, a multiplexer 1720, a deinterleaver 1730, a post processor 1740, and an LDPC decoder 1750.

First, the length
Is a received symbol vector
Is input to the bit metric calculator 1710, the bit metric calculator 1710 receives N _{substreams substreams.}
Bit metric estimate for
Is output to the multiplexer 1720. At this time, for the bit metric, for example, a log likelihood ratio (LLR) is used as a value for decoding the LDPC code.

Multiplexer 1720 received from bit metric calculator 1710
Bit metric vector estimate of length N _ldpc
Is output to the deinterleaver 1730.

Deinterleaver 1730 is a bit metric vector
Is deinterleaved using a deinterleaving scheme corresponding to the interleaving scheme used in the signal transmission device, and as a result
Bit metric vector estimate for
Is output to the post-processor 1740.

The post-processor 1740 uses a post-processing method corresponding to the pre-processing method used in the signal transmission device, that is, the pre-processor 220 in FIG.
The transmitted LDPC codeword by processing
Bit metric estimate for
Is generated. The LDPC decoder 1740 is a bit metric vector
Is decoded by LDPC decoding to obtain an information word vector
Estimated value for
Is generated.

FIG. 18 is a diagram showing an internal structure of the demultiplexer 240 of FIG.
Referring to FIG. 18, the demultiplexer 240 includes a demultiplexing unit 1811 and a selection signal generation unit 1813.
The demultiplexing unit 1811 generates N _{substreams substreams} using the selection signal output from the selection signal generation unit 1813 from the vector V output from the interleaver 230. The selection signal generation unit 1813 determines to which substream each bit included in the vector V is assigned. The selection signal generation unit 1813 reads a value stored in a storage unit, for example, a memory, or generates a signal having a preset rule and outputs a selection signal. At this time, the selection signal output from the selection signal generation unit 1813 is determined by the type of error correction code (error correction code) used in the system, the codeword length, the code rate, the modulation method, etc., and the error correction capability of the system. It is an important factor that affects

FIG. 19 shows the internal structure of multiplexer 1720 of FIG.
Referring to FIG. 19, the multiplexer 1720 includes a multiplexing unit 1911 and a selection signal generation unit 1913.
Multiplexing unit 1911 outputs an estimate of codewords interleaved using the selection signal output from selection signal generation unit 1913 for N _{substreams substreams} . The selection signal generation unit 1913 determines which substream to acquire each bit value of the estimated values of the interleaved codewords. The selection signal generation unit 1913 reads a value stored in the memory or generates a signal having a preset rule and outputs a selection signal. The selection signal generation unit 1913 includes a demultiplexer included in the signal transmission apparatus, that is, FIG. The demultiplexer 240 is designed to perform a multiplexing operation corresponding to the demultiplexing operation.

  Although the present invention has been described in detail with reference to specific embodiments, it will be apparent to those skilled in the art that various modifications can be made without departing from the scope and spirit of the invention. The scope of the present invention should not be limited to the above-described embodiments, but should be defined within the scope of the appended claims and their equivalents.

210 LDPC encoder 220 Pre-processor 230 Interleaver 240, 440 Demultiplexer 250 Symbol mapper 1710 Bit metric calculator 1720 Multiplexer 1730 Deinterleaver 1740 Post processor 1750 LDPC decoder 1811 Demultiplexer unit 1813 Selection signal generation Unit 1911 Multiplexing unit 1913 Selection signal generation unit

Claims (10)

A sub-stream generation method of signal transmission apparatus,
Storing low density parity check ( LDPC ) codeword bits in the column direction;
Outputting the stored LDPC codeword bits in a row direction;
Comprises the steps of generating a sub-stream by demultiplexing the output bits,
The step of generating the substream includes:
The modulation scheme is a 64-QAM modulation scheme, the length of the LDPC codeword N _ldpc is 16200 (N _ldpc = 16200), and the number of _substreams N _substreams is 12 (N _substreams = 12). And when the output bits v0 to v11 are assigned to the 12 substreams b0 to b11, the bit v0 is the bit b4, the bit v1 is the bit b2, the bit v2 is the bit b0, Bit v3 to bit b5, bit v4 to bit b6, bit v5 to bit b1, bit v6 to bit b3, bit v7 to bit b7, bit v8 to bit b8, bit v9 to bit b9, bit the v10 bits b10, sub signal transmission apparatus characterized by comprising a step of allocating bits v11 to bit b11 Stream generation method. A method for generating a substream of a signal transmission device, comprising:
Storing low density parity check (LDPC) codeword bits in a column direction;
Outputting the stored LDPC codeword bits in a row direction;
Generating a substream by demultiplexing the output bits, and
The step of generating the substream includes:
Modulation scheme is the 64-QAM modulation scheme, the length of N _{[iota] dpc} the LDPC codeword is 16200 (N _ldpc = 16200), the N _Substreams 12 is the number of sub-streams _(N substreams = 12 ), And when the output bits v0 to v11 are assigned to the 12 substreams b0 to b11, bit v0 is set to bit b4, bit v1 is set to bit b0, and bit v2 is set to bit b1. , Bit v3 to bit b6, bit v4 to bit b2, bit v5 to bit b3, bit v6 to bit b5, bit v7 to bit b8, bit v8 to bit b7, bit v9 to bit b10, bit v10 bit b9, sub signal transmitting apparatus you comprising the step of allocating bits v11 to bit b11 Stream generation method. A method for generating a substream of a signal transmission device, comprising:
Storing low density parity check (LDPC) codeword bits in a column direction;
Outputting the stored LDPC codeword bits in a row direction;
Generating a substream by demultiplexing the output bits, and
The step of generating the substream includes:
Modulation scheme is the 256-QAM modulation scheme, said the length of the LDPC codeword N _{[iota] dpc} is the 16200 (N _ldpc = 16200), the a number of sub-streams N _Substreams is 8 _(N substreams = 8 ), And when the output bits v0 to v7 are assigned to the eight substreams b0 to b7, bit v0 is assigned to bit b4, bit v1 is assigned to bit b0, and bit v2 is assigned to bit b1. the bit v3 bit b2, bit v4 bit b5, bit v5 bit b3, bit v6 bits b6, the signal transmission apparatus you comprising the step of allocating bits v7 to bit b7 Substream generation method. A method for generating a substream of a signal transmission device, comprising:
Storing low density parity check (LDPC) codeword bits in a column direction;
Outputting the stored LDPC codeword bits in a row direction;
Generating a substream by demultiplexing the output bits, and
The step of generating the substream includes:
Modulation scheme is the 256-QA M modulation scheme, wherein a length of N _{[iota] dpc} the LDPC codeword is 16200 (N _ldpc = 16200), the a number of sub-streams N _Substreams is 8 _(N substreams = 8), and assigning the output bits v0 to v7 to the eight substreams b0 to b7, bit v0 is bit b4, bit v1 is bit b0, and bit v2 is bit to b5, bit v3 bit b1, bit v4 bit b2, bit v5 bit b3, bit v6 bit b6, signal transmission you comprising the step of allocating bits v7 to bit b7 Device substream generation method. 5. A signal transmission apparatus for performing the method according to any one of claims 1 to 4 in a system using a low density parity check (LDPC) code. A method of operating a signal receiving apparatus,
Includes steps of generating a bit that is processed by processing the sub-stream generated based on the low density parity check (LDPC) codeword bits,
Processing the substream includes:
The modulation scheme used in the signal transmission apparatus is a 64-QAM modulation scheme, the length of the LDPC codeword N _ldpc is 16200 (N _ldpc = 16200), and the number of _substreams N _substreams is 12. (N _substreams = 12), and when assigning the 12 _substreams b0 to b11 to the processed bits v0 to v11, the bit b0 is the bit v2, the bit b1 is the bit v5, the bit b2 to bit v1, bit b3 to bit v6, bit b4 to bit v0, bit b5 to bit v3, bit b6 to bit v4, bit b7 to bit v7, bit b8 to bit v8, bit b9 Assigning bit b9 to bit v10, bit b10 to bit v10 and bit b11 to bit v11. A method for operating a signal receiving apparatus. A method of operating a signal receiving device, comprising:
Processing a substream generated based on low density parity check (LDPC) codeword bits to generate processed bits;
Processing the substream includes:
The modulation scheme used in the signal transmission apparatus is a 64-QAM modulation scheme, N _ldpc which is the length of the LDPC codeword is 16200 (N _ldpc = 16200), and N _substreams which is the number of _substreams is 12 (N _substreams = 12), and when the 12 _substreams b0 to b11 are assigned to the processed bits v0 to v11, the bit b0 is the bit v1, the bit b1 is the bit v2, Bit b2 to bit v4, bit b3 to bit v5, bit b4 to bit v0, bit b5 to bit v6, bit b6 to bit v3, bit b7 to bit v8, bit b8 to bit v7, bit allocating b9 to bit v10, bit b10 to bit v9, and bit b11 to bit v11. Operation method of the signal receiving apparatus said. A method of operating a signal receiving device, comprising:
Processing a substream generated based on low density parity check (LDPC) codeword bits to generate processed bits;
Processing the substream includes:
The modulation scheme used in the signal transmission apparatus is a 256-QAM modulation scheme, N _ldpc which is the length of the LDPC codeword is 16200 (N _ldpc = 16200), and N _substreams which is the number of _substreams is 8 (N _substreams = 8), and when assigning the eight _substreams b0 to b7 to the processed bits v0 to v7, bit b0 is bit v1, bit b1 is bit v2, Allocating bit b2 to bit v3, bit b3 to bit v5, bit b4 to bit v0, bit b5 to bit v4, bit b6 to bit v6, bit b7 to bit v7 method of operating that signal receiving apparatus. A method of operating a signal receiving device, comprising:
Processing a substream generated based on low density parity check (LDPC) codeword bits to generate processed bits;
Processing the substream includes:
The modulation scheme used in the signal transmitting apparatus is a 256-QAM modulation scheme, the length of the LDPC codeword N _ldpc is 16200 ( N _ldpc = 16200 ) , and the number of _substreams N _substreams is 8 (N _substreams = 8), and when assigning the eight _substreams b0 to b7 to the processed bits v0 to v7, bit b0 is bit v1, bit b1 is bit v3, Allocating bit b2 to bit v4, bit b3 to bit v5, bit b4 to bit v0, bit b5 to bit v2, bit b6 to bit v6, bit b7 to bit v7 method of operating that signal receiving apparatus. A signal receiving apparatus for executing the method according to any one of claims 6 to 9 in a system using a low density parity check (LDPC) code.