AU2012237118B2

AU2012237118B2 - Apparatus and method for mapping and demapping signals in a communication system using a low density parity check code

Info

Publication number: AU2012237118B2
Application number: AU2012237118A
Authority: AU
Inventors: Hong-Sil Jeong; Hyun-Koo Yang; Sung-Ryul Yun
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2011-03-30
Filing date: 2012-03-28
Publication date: 2016-02-25
Anticipated expiration: 2032-03-28
Also published as: TWI528731B; RU2701085C2; JP5937194B2; RU2016106337A; KR101865068B1; TW201246801A; KR20120111903A; JP2014513889A; RU2580085C2; RU2013148102A; AU2012237118A1; RU2016106337A3; CN103460607A; CN103460607B

Abstract

An apparatus and method for mapping and demapping signals in a system using a Low Density Parity Check (LDPC) code are provided. In the method, LDPC codeword bits are written column-wise and read row-wise, substreams are generated by demultiplexing the read bits using a demultiplexing scheme, and bits included in each of the substreams are mapped to symbols on a signal constellation, wherein the demultiplexing scheme is determined corresponding to a modulation scheme used in the signal transmitter, a length of the LDPC codeword, and a number of the substreams.

Description

APPARATUS AND METHOD FOR MAPPING AND DEMAPPING SIGNALS IN A COMMUNICATION SYSTEM USING A LOW DENSITY PARITY CHECK CODE 5 Field of the Invention The present invention relates to an apparatus and method for mapping and demapping signals in a system using a Low Density Parity Check (LDPC) code. Background Art 10 In a communication system, link performance may be significantly degraded by noise, fading, and Inter-Symbol Interference (ISI) of a channel. Therefore, a future-generation communication system is actively considering using LDPC codes as error correction codes. 15 FIG. 1 illustrates a conventional LDPC encoding operation. Referring to FIG. 1, an LDPC encoder 110 encodes an information word vector of length Kldpc, I = if,''iK,,,-1 to an LDPC codeword vectorA = ",il,---,iK 1 c- 1 ,p 0

,P

1 ,'''*'N*c-K*,,,-1 . The information word vector includes Kidpc information bits. That is, each element of the information word vector 20 I = 0,i,*-,iK 1 1 i is an informaiton bit. The LDPC encoder 110 generates a parity vector of length Nldpc-Kldpc, o, 1,- PN,dpII-Kl, c~1 using a paricy check matrix having Nidpc columns, and generates the LDPC code, i.e., the LDPC codeword vector 25 A = fo,il,...,iK 1 ,p,'Po 1 ',''''PN, -K,,c-I , using the information word vector and the parity vector. Along with growing demands for high-rate data transmission and hardware development, the future-generation communication system is actively considering 30 using Quadrature Amplitude Modulation (QAM), which is excellent in terms of frequency efficiency. In QAM, different modulation bits included in one QAM symbol have different error probabilities. The error correction ability of each LDPC codeword bit included in the LDPC codeword vector is determined according to the degree of a variable node 35 corresponding to the LDPC codeword bit. Consequently, even though the same LDPC code is used, the error 1 probability of a QAM symbol varies depending on modulation bits of the QAM symbol, to which LDPC codeword bits are mapped. Accordingly, a need exists for a technique for mapping LDPC codeword bits to modulation bits of a QAM symbol, which minimizes the error probability of the QAM symbol. 5 SUMMARY OF THE INVENTION Accordingly, an embodiment of the present invention provide an apparatus and method for mapping and demapping signals in a system using an LDPC code. 10 Another embodiment of the present invention provides an apparatus and method for mapping and demapping between LDPC codewords and QAM symbols in a system using an LDPC code. 15 In accordance with an aspect of the present invention, there is provided a substream generating method of a signal transmitter, the substream generating method comprising: writing low density parity check (LDPC) codeword bits column-wise; reading the written LDPC codeword bits row-wise; and 20 generating substreams by demultiplexing the read bits, wherein if 64-ary quadrature amplitude modulation (64-QAM) is used as a modulation scheme, a length of an LDPC codeword Nidpc is 16200 (Niadc=1 6 2 00), a number of the substreams Nsubstreams is 12 (Nsubstreams=12), and the read bits vO to vII are allocated to the 12 substreams bO to b 11, generating the substreams comprises 25 allocating bit vO to bit b4, bit vi to b2, bit v2 to bit bO, bit v3 to bit b5, bit v4 to bit b6, bit v5 to bit bI, bit v6 to b3, bit v7 to bit b7, bit v8 to bit b8, bit v9 to bit b9, bit v10 to bit bi0, and bit vI1 to bit bl1. In accordance with another aspect of the present invention, there is provided 30 a substream generating method of a signal transmitter, the substream generating method comprising: writing low density parity check (LDPC) codeword bits column-wise; reading the written LDPC codeword bits row-wise; and generating substreams by demultiplexing the read bits, 2 wherein if 64-ary quadrature amplitude modulation (64-QAM) is used as a modulation scheme, a length of an LDPC codeword N1dpc is 16200 (N1dpc=16 2 00), a number of the substreams Nsubstreams is 12 (Nsubstreams=12), and the read bits v0 to vII are allocated to the 12 substreams bO to b 11, generating the substreams comprises 5 allocating bit v0 to bit b4, bit vi to bO, bit v2 to bit bi, bit v3 to bit b6, bit v4 to bit b2, bit v5 to bit b3, bit v6 to b5, bit v7 to bit b8, bit v8 to bit b7, bit v9 to bit b10, bit v10 to bit b9, and bit v1I to bit bl1. In accordance with another aspect of the present invention, there is provided 10 a substream generating method of a signal transmitter, the substream generating method comprising: writing low density parity check (LDPC) codeword bits column-wise; reading the written LDPC codeword bits row-wise; and generating substreams by demultiplexing the read bits using a demultiplexing 15 scheme, wherein if 256-ary quadrature amplitude modulation (256-QAM) is used as a modulation scheme, a length of an LDPC codeword N1dpc is 16200 (N1dpc=16 2 00), a number of the substreams Nsubstreams is 8 (Nsubstreams= 8 ), and the read bits v0 to v7 are allocated to the 8 substreams bO to b7, generating the substreams comprises 20 allocating bit v0 to bit b4, bit vi to bO, bit v2 to bit bi, bit v3 to bit b2, bit v4 to bit b5, bit v5 to bit b3, bit v6 to b6, and bit v7 to bit b7. In accordance with another aspect of the present invention, there is provided a substream generating method of a signal transmitter, the substream generating 25 method comprising: writing low density parity check (LDPC) codeword bits column-wise; reading the written LDPC codeword bits row-wise; and generating substreams by demultiplexing the read bits using a demultiplexing scheme, 30 wherein if 256-ary quadrature amplitude modulation (256-QAM) is used as a modulation scheme, a length of an LDPC codeword N1dpc is 16200 (N1dpc=16 2 00), a number of the substreams Nsubstreams is 8 (Nsubstreams= 8 ), and the read bits v0 to v7 are 3 allocated to the 8 substreams bO to b7, generating the substreams comprises allocating bit v0 to bit b4, bit vi to bO, bit v2 to bit b5, bit v3 to bit bI, bit v4 to bit b2, bit v5 to bit b3, bit v6 to b6, and bit v7 to bit b7. 5 In accordance with another aspect of the present invention, there is provided multiplexed bit generating method of a signal receiver, the multiplexed bit generating method comprising: generating multiplexed bits by multiplexing substreams which are generated 10 based on low density parity check (LDPC) codeword bits, wherein if 64-ary quadrature amplitude modulation (64-QAM) is used as a modulation scheme in a signal transmitter, a length of an LDPC codeword Nidpc is 16200 (Nldpc=16200), a number of the substreams Nsubstreams is 12 (Nsubstreams=12), and the 12 substreams bO to b 11 are allocated to the multiplexed bits v0 to vil, 15 multiplexing the substreams comprises allocating bit bO to bit v2, bit bI to bit v5, bit b2 to bit vI, bit b3 to bit v6, bit b4 to bit vO, bit b5 to bit v3, bit b6 to bit v4, bit b7 to bit v7, bit b8 to bit v8, bit b9 to bit v9, bit b10 to bit v10, and bit bI1 to bit vi1. In accordance with another aspect of the present invention, there is provided 20 multiplexed bit generating method of a signal receiver, the multiplexed bit generating method comprising: generating multiplexed bits by multiplexing substreams which are generated based on low density parity check (LDPC) codeword bits, wherein if 64-ary quadrature amplitude modulation (64-QAM) is used as a 25 modulation scheme in a signal transmitter, a length of an LDPC codeword N1dpc is 16200 (Nldpc=16200), a number of the substreams Nsubstreams is 12 (Nsubstreams=12), and the 12 substreams bO to bi1 are allocated to the multiplexed bits v0 to vll, multiplexing the substreams comprises allocating bit bO to bit vi, bit bI to bit v2, bit b2 to bit v4, bit b3 to bit v5, bit b4 to bit vO, bit b5 to bit v6, bit b6 to bit v3, bit b7 30 to bit v8, bit b8 to bit v7, bit b9 to bit v10, bit blO to bit v9, and bit bl to bit vl1. In accordance with another aspect of the present invention, there is provided 4 multiplexed bit generating method of a signal receiver, the multiplexed bit generating method comprising: generating multiplexed bits by multiplexing substreams which are generated based on low density parity check (LDPC) codeword bits, 5 wherein if 256-ary quadrature amplitude modulation (256-QAM) is used as a modulation scheme in a transmitter, a length of an LDPC codeword Nidpc is 16200 (Nldpc=16200), a number of the substreams, Nsubstreams is 8 (Nsubstreams= 8 ), and the 8 substreams bO to b7 are allocated to the multiplexed bits vO to v7, multiplexing the substreams comprises allocating bit bO to bit vl, bit bI to bit v2, bit b2 to bit v3, bit 10 b3 to bit v5, bit b4 to bit vO, bit b5 to bit v4, bit b6 to bit v6, and bit b7 to bit v7. In accordance with another aspect of the present invention, there is provided multiplexed bit generating method of a signal receiver, the multiplexed bit generating method comprising: 15 generating multiplexed bits by multiplexing substreams which are generated based on low density parity check (LDPC) codeword bits, wherein if 256-ary quadrature amplitude modulation (256-QAM) is used as a modulation scheme in a signal transmitter, a length of an LDPC codeword Nidpc is 16200 (Nldpc=16200), a number of the substreams Nsubstreams is 8 (Nsubstreams= 8 ), and 20 the 8 substreams bO to b7 are allocated to the multiplexed bits vO to v7, multiplexing the substreams comprises allocating bit bO to bit vi, bit bI to bit v3, bit b2 to bit v4, bit b3 to bit v5, bit b4 to bit vO, bit b5 to bit v2, bit b6 to bit v6, and bit b7 to bit v7. BRIEF DESCRIPTION OF THE DRAWINGS 25 The above and other aspects, features, and advantages of certain embodiments of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: 30 FIG. 1 illustrates a conventional LDPC encoding operation; FIG. 2 is a block diagram illustrating a signal transmitter in a system using an LDPC code according to an embodiment of the present invention; FIG. 3 illustrates a 16-ary QAM (16-QAM) signal constellation according to 5 an embodiment of the present invention; FIG 4 illustrates a 64-ary QAM (64-QAM) signal constellation according to an embodiment of the present invention; FIG 5 illustrates a 256-ary QAM (256-QAM) signal constellation according 5 to an embodiment of the present invention; FIG 6 illustrates an operation of an interleaver illustrated in FIG. 2 according to an embodiment of the present invention; FIG 7 illustrates an operation of a Demultiplexer (DEMUX) unit illustrated in FIG 2 according to an embodiment of the present invention; 10 FIG. 8 illustrates an operation of the DEMUX unit, when Nidac=16200 and 16-QAM is used, according to an embodiment of the present invention; FIG. 9 illustrates an operation of the DEMUX unit, when Nidpc=16200 and 64-QAM is used, according to an embodiment of the present invention; FIG. 10 illustrates another operation of the DEMUX unit, when Nidpc= 16200 15 and 16-QAM is used, according to an embodiment of the present invention; FIG. 11 illustrates another operation of the DEMUX unit, when Nidac= 16200 and 16-QAM is used, according to an embodiment of the present invention; FIG. 12 illustrates another operation of the DEMUX unit, when Nidpc=1 6 2 00 and 64-QAM is used, according to an embodiment of the present invention; 20 FIG. 13 illustrates another operation of the DEMUX unit, when Nidpc= 16200 and 64-QAM is used, according to an embodiment of the present invention; FIG. 14 illustrates a further operation of the DEMUX unit, when N1dpc=16 2 00 and 16-QAM is used, according to an embodiment of the present invention; 25 FIG. 15 illustrates an operation of the DEMUX unit, when Nidpc=16200 and 256-QAM is used, according to an embodiment of the present invention; FIG. 16 illustrates an operation of the DEMUX unit, when Nidac=16200 and 256-QAM is used, according to an embodiment of the present invention; FIG. 17 is a block diagram illustrating a signal receiver in a system using an 30 LDPC code, according to an embodiment of the present invention; FIG. 18 is a block diagram illustrating the DEMUX unit illustrated in FIG. 2, according to an embodiment of the present invention; and FIG. 19 is a block diagram illustrating a Multiplexer (MUX) unit illustrated in FIG. 17, according to an embodiment of the present invention. 35 Throughout the drawings, the same drawing reference numerals will be understood to refer to the same elements, features, and structures. 6 DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION Various embodiments of the present invention will now be described in 5 detail with reference to the accompanying drawings. In the following description, specific details such as detailed configuration and components are merely provided to assist the overall understanding of these embodiments of the present invention. Therefore, it should be apparent to those skilled in the art that various changes and modifications of the embodiments described herein can be made without departing 10 from the scope and spirit of the present invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness. In accordance with an embodiment of the present invention, an apparatus and method are provided for mapping and demapping signals in a system using an 15 LDPC code. In accordance with another embodiment of the present invention, an apparatus and method are provided for mapping and demapping between LDPC codewords and QAM symbols. 20 The following description of the present invention is provided for a system using LDPC codes, , for example, a broadcasting system such as Digital Video Broadcasting (DVB)-Next Generation Handheld (NGH) or a communication system such as Moving Picture Experts Group (MPEG) Media Transport (MMT), Evolved 25 Packet System (EPS), Long-Term Evolution (LTE), and Institute of Electrical and Electronics Engineers (IEEE) 802.16m. While the present invention is described in the context of an LDPC code and QAM modulation schemes, it is to be clearly understood that the apparatus and method of the present invention are also applicable to other codes and other 30 modulation schemes. FIG. 2 is a block diagram illustrating a signal transmitter in a system using an LDPC code according to an embodiment of the present invention. 35 Referring to FIG. 2, the signal transmitter includes an LDPC encoder 210, a pre-processor 220, an interleaver 230, a DEMUX unit 240, and a symbol mapper 250. 7 The LDPC encoder 210 generates a parity vector ke'PJ,---,PN ,-K g-1 including Nldpc-Kldpc parity bits and then an LDPC codeword vector of length Nidc by encoding an information word vector I= *'i,iKg.-1 . The pre-processor 5 220 generates a vector U = ..p.,--,pN.,- 1 by pre-processing the LDPC codeword vector A received from the LDPC encoder 210 using a predetermined pre processing scheme. Alternatively, the pre-processor 220 may be omitted or its function may be incorporated into the interleaver 230. A detailed description of the pre-processing scheme is not provided herein. 10 The interleaver 230 writes the vector U received from the pre-processor 220 column-wise in Nc columns and reads the vector U row-wise, thus outputting a vector V = jIQV1,--,VNp 1 to the DEMUX UNIT 240. The DEMUX UNIT 240 demultiplexes the vector V into Nsubstreams substreams 15 B = , ,b,,,- --,N Nsa - (i = 0,1,- , Nbstre,s - 1) each having Nc bits. For the input of the bits of each of the Nsubstreams substreams, the symbol mapper 250 generates a cell word of length qMOD, |-yo,y .,--y... yMOD-1 and maps the cell word to signal points on a signal constellation, thereby producing a symbol Z. Herein qMOD is a divisor of Nsubstreams. 20 FIGs. 3, 4 and 5 illustrate mapping relationships between cell words and signal constellations in 16-QAM, 64-QAM, and 256-QAM, respectively, according to embodiments of the present invention. FIG. 6 illustrates an operation of the interleaver 230 illustrated in FIG. 2 25 according to an embodiment of the present invention. Specifically, in FIG. 6, it is assumed that the interleaver 230 has Nc rows x Nidpc/Nc columns. If Nidpc=1 6 2 00, the number of rows Nr and the number of columns Nc are given for 16-QAM and 64-QAM as shown in Table 1. 30 Table 1 Modulation Nr Nc scheme 16-QAM 8100 8 64-QAM 5400 12 The interleaver 230 sequentially writes the received vector U column-wise in 8 Nc columns and reads the written vector row-wise. Herein, the first storing position of each column may be shifted by a twisting parameter tc. The twisting parameter tc may have the values shown in Table 2 for 16-QAM and 64-QAM, when Nidac= 16200, for example. 5 Table 2 Mo tc dulation c C scheme olumn 0 1 0 16- 0 QAM 0 0 1 64- 0 QAM 2 FIG. 7 illustrates an operation of a DEMUX unit illustrated in FIG. 2 according to an embodiment of the present invention. 10 Referring to FIG. 7, the operation of the DEMUX UNIT 240 may be expressed as the relationship between Vi(i=0,1,... , Nlipc_1) and bj(j=0,1, Nsubstreams-1), which may be extended in the same rule, if Nidpc is a multiple of Nsubstreams. 15 FIG. 8 illustrates an operation of the DEMUX UNIT 240, when Nidpc= 16200 and 16-QAM is used, according to an embodiment of the present invention. Referring to FIG. 8, assuming Nsubstreams=8, the DEMUX UNIT 240 maps 20 input bits v0 to v7 to output bits bO to b7. Specifically, the DEMUX UNIT 240 maps bit v0 to bit b2, bit vi to b4, bit v2 to bit b5, bit v3 to bit bO, bit v4 to bit b7, bit v5 to bit bi, bit v6 to b3, and bit v7 to bit b6. 25 FIG. 9 illustrates an operation of the DEMUX UNIT 240, when Nidac= 16200 and 64-QAM is used, according to an embodiment of the present invention. Referring to FIG. 9, assuming Nsubstreams=12, the DEMUX UNIT 240 maps input bits v0 to vII to output bits bO to b 11. Specifically, the DEMUX UNIT 240 9 maps bit v0 to bit b4, bit vi to bO, bit v2 to bit bi, bit v3 to bit b6, bit v4 to bit b2, bit v5 to bit b3, bit v6 to b8, bit v7 to bit b9, bit v8 to bit b7, bit v9 to bit b5, bit v10 to bit bl0, and bit vl1 to bit bl1. 5 FIG. 10 illustrates another operation of the DEMUX UNIT 240, when N1dpc=1 6 2 00 and 16-QAM is used, according to an embodiment of the present invention. Referring to FIG. 10, assuming Nsubstreams=8, the DEMUX UNIT 240 maps 10 input bits v0 to v7 to output bits bO to b7. Specifically, the DEMUX UNIT 240 maps bit v0 to bit b2, bit vi to b4, bit v2 to bit b5, bit v3 to bit bl, bit v4 to bit b6, bit v5 to bit bO, bit v6 to b7, and bit v7 to bit b3. FIG. 11 illustrates another operation of the DEMUX UNIT 240, when 15 Nidac=16 2 00 and 16-QAM is used, according to an embodiment of the present invention. Referring to FIG. 11, assuming Nsubstreams=8, the DEMUX UNIT 240 maps input bits v0 to v7 to output bits bO to b7. Specifically, the DEMUX UNIT 240 maps bit v0 to bit b2, bit vi to bO, bit v2 to bit bl, bit v3 to bit b3, bit v4 to bit b6, 20 bit v5 to bit b4, bit v6 to b7, and bit v7 to bit b5. FIG. 12 illustrates another operation of the DEMUX UNIT 240, when N1dpc=16 2 00 and 64-QAM is used, according to an embodiment of the present invention. 25 Referring to FIG. 12, assuming Nsubstreams=1 2 , the DEMUX UNIT 240 maps input bits v0 to vII to output bits bO to b 11. Specifically, the DEMUX UNIT 240 maps bit v0 to bit b4, bit vi to b2, bit v2 to bit bO, bit v3 to bit b5, bit v4 to bit b6, bit v5 to bit bI, bit v6 to b3, bit v7 to bit b7, bit v8 to bit b8, bit v9 to bit b9, bit v10 30 to bit bi0, and bit v1I to bit bl1. FIG. 13 illustrates another operation of the DEMUX UNIT 240, when N1dpc=16 2 00 and 64-QAM is used, according to an embodiment of the present invention. 35 Referring to FIG. 13, assuming Nsubstreams=1 2 , the DEMUX UNIT 240 maps input bits v0 to vII to output bits bO to b 11. Specifically, the DEMUX UNIT 240 10 maps bit vO to bit b4, bit vi to bO, bit v2 to bit bi, bit v3 to bit b6, bit v4 to bit b2, bit v5 to bit b3, bit v6 to b5, bit v7 to bit b8, bit v8 to bit b7, bit v9 to bit b10, bit v10 to bit b9, and bit v11 to bit bIl. 5 FIG. 14 illustrates another operation of the DEMUX UNIT 240, when N1dpc=1 6 2 00 and 64-QAM is used, according to an embodiment of the present invention. Referring to FIG. 14, assuming Nsubstreams=8, the DEMUX UNIT 240 maps 10 input bits vO to v7 to output bits bO to b7. Specifically, the DEMUX UNIT 240 maps bit vO to bit b2, bit vi to bO, bit v2 to bit b4, bit v3 to bit bl, bit v4 to bit b6, bit v5 to bit b5, bit v6 to b7, and bit v7 to bit b3. FIG. 15 illustrates an operation of the DEMUX UNIT 240, when Nidpc 15 =16200 and 256-QAM is used, according to an embodiment of the present invention. Referring to FIG. 15, assuming Nsubstreams=8, the DEMUX UNIT 240 maps input bits vO to v7 to output bits bO to b7. Specifically, the DEMUX UNIT 240 maps bit vO to bit b4, bit vi to bO, bit v2 to bit bl, bit v3 to bit b2, bit v4 to bit b5, 20 bit v5 to bit b3, bit v6 to b6, and bit v7 to bit b7. FIG. 16 illustrates another operation of the DEMUX UNIT 240, when N1dpc=16 2 00 and 256-QAM is used, according to an embodiment of the present invention. 25 Referring to FIG. 16, assuming Nsubstreams= 8 , the DEMUX UNIT 240 maps input bits vO to v7 to output bits bO to b7. Specifically, the DEMUX UNIT 240 maps bit vO to bit b4, bit vi to bO, bit v2 to bit b5, bit v3 to bit bl, bit v4 to bit b2, bit v5 to bit b3, bit v6 to b6, and bit v7 to bit b7. 30 As described above, in accordance with the embodiments of the present invention, the DEMUX unit provides LDPC codeword bits to the symbol mapper according to a predetermined mapping rule. Therefore, when the LDPC codeword bits are mapped to symbols (e.g., symbols on a QAM signal constellation), the 35 symbols have different performances according to different mapping rules. FIG. 17 is a block diagram illustrating a signal receiver in the system using 11 the LDPC code, according to an embodiment of the present invention. Referring to FIG. 17, the signal receiver includes a bit metric calculator 1710, a MUX unit 1720, a deinterleaver 1730, a post-processor 1740, and an LDPC 5 decoder 1750. Upon receipt of a symbol vector of length Nd,, /qMOD R = 0r,-, -,r, /MOD -1j, the bit metric calculator 1710 calculates bit metric estimates h, = ,O'*,-,N,, |N,,/,,,/,, -1 ( i = 0,1,-.-, N,,bs,,s -1 ) of Nsuhstrears 10 substreams B, = g O,b 1 ,---,bi,N,I /N,,',,rea, - 1 ( i = 0,1, -, N,,b',,,e,, -1 ). The bit metrics are used for decoding an LDPC code. For example, Log-Likelihood Ratios (LLRs) may be used as the bit metrics. The MUX UNIT 1720 generates a bit metric vector estimate of length Nd, 15 Y = *, -,. .. ,N, ,- by multiplexing the bit metric estimates BE i= 0,1,... NAms,,,a, -1 received from the bit metric calcualtor 1710. The deinterleaver 1730 deinterleaves the bit metric vector estimate V using a deinterleaving scheme corresponding to the interleaving scheme used in the signal transmitter, thereby producing a bit metric vector estimate U = j^,Ai,...,'N,-, -1 of 20 U = Op,,,N,-1 The post-processor 1740 generates a bit metric vector estimate A= {,Il,--,K, 1 o 1 ,' 1N, 1 "-_K,,1 } of the transmitted LDPC codeword A = ,j,---. , iKp p-1'' 1 N, ,-K,1," -1 by processing the bit metric vector estimate 25 0 = iO, '...,AN,-1 using a post-processing scheme corresponding to the pre processing scheme used in the pre-processor of the signal transmitter, i.e., the pre processor 220, as illustrated in FIG. 2. The LDPC decoder 1740 decodes the bit metric vector A by LDPC decoding, thereby generating an estimate Z = O, -,K, 1

,

1 -1 1 of the information word vector I = O'i,. -,iK,-1 30 FIG. 18 is a block diagram illustrating the DEMUX unit 240 illustrated in FIG. 2, according to an embodiment of the present invention. Referring to FIG. 18, the DEMUX unit 240 includes a DEMUX 1811 and a 35 selection signal generator 1813. 12 The DEMUX 1811 generates Nuhs,,,a,, substreams from the vector V received from the interleaver 230 using selection signals received from the selection signal generator 1813. The selection signal generator 1813 determines a substream to which each bit of the vector V is to be allocated, and then outputs a selection 5 signal by reading a value stored in a storage, for example, a memory, or generating a signal using a predetermined rule. The selection signal output from the selection signal generator 1813 is determined according to the type, codeword length, code rate, and modulation scheme of an error correction code used in the system. The selection signal is an important factor that affects the error correction capability of 10 the system. FIG. 19 is a block diagram illustrating the MUX unit 1720 illustrated in FIG. 17, according to an embodiment of the present invention. 15 Referring to FIG. 19, the MUX unit 1720 includes a MUX 1911 and a selection signal generator 1913. The MUX 1911 outputs an estimate of an interleaved codeword from Nuhs,,,a,, substreams using selection signals received from the selection signal generator 1913. The selection signal generator 1913 determines a substream from which each bit of an estimated interleaved codeword is 20 obtained. The selection signal generator 1913 outputs a selection signal by reading a value stored in a memory or generating a signal using a predetermined rule. The MUX unit 1720 performs multiplexing using a manner corresponding to demultiplexing of the DEMUX unit 240 as illustrated in FIG. 2. 25 As is apparent from the description above, various embodiments of the present invention can minimize the error probability of a system using an LDPC code, and thus, improve overall system performance by enabling mapping of LDPC codeword bits to modulation symbols according to a used modulation scheme. 30 While the present invention has been particularly shown and described with reference to certain embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. 35 In the claims which follow and in the preceding description of the invention, except where the context requires otherwise due to express language or necessary 13 implication, the word "comprise" or variations such as "comprises" or "comprising" is used in an inclusive sense, i.e. to specify the presence of the stated features but not to preclude the presence or addition of further features in various embodiments of the invention. 5 It is to be understood that, if any prior art publication is referred to herein, such reference does not constitute an admission that the publication forms a part of the common general knowledge in the art, in Australia or any other country. 10 14

Claims

1. A substream generating method of a signal transmitter, the substream 5 generating method comprising: writing low density parity check (LDPC) codeword bits column-wise; reading the written LDPC codeword bits row-wise; and generating substreams by demultiplexing the read bits, wherein if 64-ary quadrature amplitude modulation (64-QAM) is used as a 10 modulation scheme, a length of an LDPC codeword Nidpc is 16200 (Nidpc=1 6 2 00), a number of the substreams Nsubstreams is 12 (Nsubstreams=12), and the read bits vO to vII are allocated to the 12 substreams bO to b 11, generating the substreams comprises allocating bit vO to bit b4, bit vi to b2, bit v2 to bit bO, bit v3 to bit b5, bit v4 to bit b6, bit v5 to bit bI, bit v6 to b3, bit v7 to bit b7, bit v8 to bit b8, bit v9 to bit b9, bit 15 vI0 to bit bI0, and bit vI Ito bit bl1.

2. A substream generating method of a signal transmitter, the substream generating method comprising: writing low density parity check (LDPC) codeword bits column-wise; 20 reading the written LDPC codeword bits row-wise; and generating substreams by demultiplexing the read bits, wherein if 64-ary quadrature amplitude modulation (64-QAM) is used as a modulation scheme, a length of an LDPC codeword N1dpc is 16200 (N1dpc=16 2 00), a number of the substreams Nsubstreams is 12 (Nsubstreams= 12), and the read bits vO to vi1 25 are allocated to the 12 substreams bO to b 11, generating the substreams comprises allocating bit vO to bit b4, bit vi to bO, bit v2 to bit bi, bit v3 to bit b6, bit v4 to bit b2, bit v5 to bit b3, bit v6 to b5, bit v7 to bit b8, bit v8 to bit b7, bit v9 to bit b10, bit vI0 to bit b9, and bit v11 to bit bIl. 30

3. A substream generating method of a signal transmitter, the substream generating method comprising: writing low density parity check (LDPC) codeword bits column-wise; 15 reading the written LDPC codeword bits row-wise; and generating substreams by demultiplexing the read bits using a demultiplexing scheme, wherein if 256-ary quadrature amplitude modulation (256-QAM) is used as a 5 modulation scheme, a length of an LDPC codeword N1dpc is 16200 (N1dpc=16 2 00), a number of the substreams Nsubstreams is 8 (Nsubstreams= 8 ), and the read bits v0 to v7 are allocated to the 8 substreams bO to b7, generating the substreams comprises allocating bit v0 to bit b4, bit vi to bO, bit v2 to bit bi, bit v3 to bit b2, bit v4 to bit b5, bit v5 to bit b3, bit v6 to b6, and bit v7 to bit b7. 10

4. A substream generating method of a signal transmitter, the substream generating method comprising: writing low density parity check (LDPC) codeword bits column-wise; reading the written LDPC codeword bits row-wise; and 15 generating substreams by demultiplexing the read bits using a demultiplexing scheme, wherein if 256-ary quadrature amplitude modulation (256-QAM) is used as a modulation scheme, a length of an LDPC codeword Nidpc is 16200 (Niadc=1 6 2 00), a number of the substreams Nsubstreams is 8 (Nsubstreams= 8 ), and the read bits v0 to v7 are 20 allocated to the 8 substreams bO to b7, generating the substreams comprises allocating bit v0 to bit b4, bit vi to bO, bit v2 to bit b5, bit v3 to bit bI, bit v4 to bit b2, bit v5 to bit b3, bit v6 to b6, and bit v7 to bit b7.

5. The substream generating method of any one of claims 1 to 4, further 25 comprising: mapping bits included in each of the substreams to at least one symbol on a signal constellation.

6. A signal transmitter adapted to perform the method of any one of 30 claims 1 to 5.

7. A multiplexed bit generating method of a signal receiver, the 16 multiplexed bit generating method comprising: generating multiplexed bits by multiplexing substreams which are generated based on low density parity check (LDPC) codeword bits, wherein if 64-ary quadrature amplitude modulation (64-QAM) is used as a 5 modulation scheme in a signal transmitter, a length of an LDPC codeword N1dpc is 16200 (Nldpc=16200), a number of the substreams Nsubstreams is 12 (Nsubstreams=12), and the 12 substreams bO to bi1 are allocated to the multiplexed bits v0 to vll, multiplexing the substreams comprises allocating bit bO to bit v2, bit bI to bit v5, bit b2 to bit vI, bit b3 to bit v6, bit b4 to bit vO, bit b5 to bit v3, bit b6 to bit v4, bit b7 10 to bit v7, bit b8 to bit v8, bit b9 to bit v9, bit b10 to bit v10, and bit bI1 to bit vi1.

8. A multiplexed bit generating method of a signal receiver, the multiplexed bit generating method comprising: generating multiplexed bits by multiplexing substreams which are generated 15 based on low density parity check (LDPC) codeword bits, wherein if 64-ary quadrature amplitude modulation (64-QAM) is used as a modulation scheme in a signal transmitter, a length of an LDPC codeword N1dpc is 16200 (Nldpc=16200), a number of the substreams Nsubstreams is 12 (Nsubstreams=12), and the 12 substreams bO to bi1 are allocated to the multiplexed bits v0 to vll, 20 multiplexing the substreams comprises allocating bit bO to bit vi, bit bI to bit v2, bit b2 to bit v4, bit b3 to bit v5, bit b4 to bit vO, bit b5 to bit v6, bit b6 to bit v3, bit b7 to bit v8, bit b8 to bit v7, bit b9 to bit v10, bit b10 to bit v9, and bit bI1 to bit vi1.

9. A multiplexed bit generating method of a signal receiver, the 25 multiplexed bit generating method comprising: generating multiplexed bits by multiplexing substreams which are generated based on low density parity check (LDPC) codeword bits, wherein if 256-ary quadrature amplitude modulation (256-QAM) is used as a modulation scheme in a transmitter, a length of an LDPC codeword Nidpc is 16200 30 (Nldpc=16200), a number of the substreams, Nsubstreams is 8 (Nsubstreams= 8 ), and the 8 substreams bO to b7 are allocated to the multiplexed bits v0 to v7, multiplexing the substreams comprises allocating bit bO to bit vi, bit bI to bit v2, bit b2 to bit v3, bit 17 b3 to bit v5, bit b4 to bit vO, bit b5 to bit v4, bit b6 to bit v6, and bit b7 to bit v7.

10. A multiplexed bit generating method of a signal receiver, the multiplexed bit generating method comprising: 5 generating multiplexed bits by multiplexing substreams which are generated based on low density parity check (LDPC) codeword bits, wherein if 256-ary quadrature amplitude modulation (256-QAM) is used as a modulation scheme in a signal transmitter, a length of an LDPC codeword N1dpc is 16200 (Nldpc=16200), a number of the substreams Nsubstreams is 8 (Nsubstreams= 8 ), and 10 the 8 substreams bO to b7 are allocated to the multiplexed bits v0 to v7, multiplexing the substreams comprises allocating bit bO to bit vl, bit bI to bit v3, bit b2 to bit v4, bit b3 to bit v5, bit b4 to bit vO, bit b5 to bit v2, bit b6 to bit v6, and bit b7 to bit v7.

11. The multiplexed bit generating method of any one of claims 7 to 10, 15 further comprising: deinterleaving the multiplexed bits; and generating the LDPC codeword bits by LDPC-decoding the deinterleaved bits. 20

12. A signal receiver adapted to perform the method of any one of claims 7 to 11. 18