WO2011048997A1 - Soft output decoder - Google Patents

Abstract

Provided is a soft output decoder by which a decoding process can be performed with a simple circuit structure at high speed. A soft output decoding means (110) of a soft output decoder (10) comprises a branch metric memory (150) which temporarily stores a branch metric, a backward processing unit (120) which performs an estimation process of a path metric from the end of the code trellis of the branch metric, a forward processing unit (130) which performs an estimation process of a path metric from the head, a path metric memory (160) which stores a result of the estimation process, and a soft output generation processing unit (130) which calculates a posterior probability ratio of an information symbol at each time point from the result of the estimation process and outputs the calculated result as the soft output code, wherein the backward processing unit is provided with a plurality of backward processors (121 and 122) corresponding to each time point of the estimation process, and the path metric memory is provided with a plurality of storage regions (161 and 162) which respectively correspond to the backward processors.

Description

Soft output decoder

The present invention relates to soft output decoding, and more particularly, to reduction of load due to processing related to error correction processing at the time of decoding.

The error correction coding technique is a technique for protecting data from errors such as bit inversion occurring on a communication path during data transmission through operations such as data coding and decoding. Encoding is an operation of converting information to be transmitted into a codeword with redundancy added. Decoding is an operation of estimating the original codeword (information) from the codeword (received word) in which an error is mixed using the redundancy. This technology has already been widely used in communications and storage media, especially in speeding up wired communications such as wireless communications or ADSL (Asymmetric Digital Subscriber Line), or increasing the capacity of storage media such as optical disks. It is an indispensable technology.

As described above, decoding is a process of estimating an original codeword, and a plurality of methods can be considered even if the same code is used. Usually, the decoding result is given as a code word or an information bit string for generating it, but a decoding method for estimating each information bit with a weight with respect to a received sequence is also known. This is called a soft output decoding method. Optimal soft-output decoding is decoding that outputs a conditional probability of the information bit or symbol based on the received sequence for the code word under the constraint that the bit string constitutes the code word for each information symbol. . This is called posterior probability decoding.

In the case of binary values, it is sufficient for the posterior probability decoding to generate the log likelihood ratio L (t) expressed by the following equation (1). Here, u (t) is an information bit at time t, Y is a sequence of received values for a codeword, and P (u (t) = b | Y) (b = 0, 1) is u under the received sequence Y. It is a conditional probability that (t) = b.

A posterior probability decoding method with a relatively small amount of calculation is known in decoding processing, particularly in decoding of a code that can be represented by a code trellis with a small number of states. This method can be logically realized as a process on a code trellis, similarly to Viterbi decoding known as a maximum likelihood decoding method of a convolutional code. This method is called BCJR (Bahl, Cocke, Jelinek, Raviv) algorithm or MAP (Maximum A Posteriori probability) algorithm described in Non-Patent Document 1.

In the MAP algorithm, the input received word Y is not a hard decision result in which each bit is determined to be 0 or 1, but a value obtained by adding reliability to the determination of each bit, that is, a soft decision result (soft input value). It can be a decoding method. For this reason, this method is also called a soft input / soft output decoding method. This technique is an important element in the decoding of the turbo code described in Non-Patent Document 2. Hereinafter, for ease of explanation, a case where a symbol is a binary code will be described. However, the present invention can be extended to a case where a symbol is composed of multi-level symbols.

FIG. 22 is an explanatory diagram showing the structure of a general turbo encoder 900 and decoder 1000. A turbo encoder 900 shown in FIG. 22A is configured by connecting two systematic convolutional encoders 901 and 902 having feedback via an interleaver 903 in parallel. This convolutional code is called an element code of a turbo code, and a code having 4 or less memories is usually used. FIG. 22 shows an example in the case of 2 memories.

The convolutional encoder 901 includes two memories 901a and 901b and three adders 901c and 901e. The convolutional encoder 902 is composed of two memories 902a-b and three adders 902c-e. The convolutional encoder 901 is referred to as element code 1 and 902 as element code 2, and the parity sequences generated by them are referred to as parity 1 and parity 2, respectively. Interleaver 903 rearranges the output bits from convolutional encoders 901 and 902. The size and design of the interleaver 903 greatly affects the encoding performance.

On the other hand, a turbo decoder 1000 shown in (b) of FIG. 22 corresponds to soft input / soft output decoding means 1001 corresponding to the element code output from the turbo encoder 900, and corresponds to the information sequence, parity 1, and parity 2, respectively. And memories 1012, 1013, and 1014 that hold received values. The turbo code decoding method is to use a soft output value obtained by soft output decoding of one element code as a soft input value (preliminary information) of the other element code and repeat this. The soft output value exchanged in the process of this repetition is not the value L (t) of Equation 1 but a value Le (t) called external information represented by Equation 2 calculated from L (t). .

Here, y (t) is a received value for information bit u (t), La (t) is a soft output value obtained by soft output decoding of the other element code used as prior information of u (t), and C is It is a constant determined according to the SN ratio of the communication path. The processing of the interleaver 1003 and the deinterleaver 1016 is realized as memory address generation processing.

The above MAP algorithm (BCJR algorithm) will be described in detail. The MAP algorithm is an algorithm using a code trellis as in the Viterbi algorithm well known as the maximum likelihood decoding method. In the convolutional code, the code word for the input information changes according to the value of the memory in the encoder. This memory value in the encoder is called the “state” of the encoder. Coding using a convolutional code is performed while changing the state according to the information sequence.

The code trellis is a graph representing a combination of transitions of this state, and is configured by assigning an edge to a pair of states where a transition exists, with each state of the encoder at each point as a node. The edge is determined by input information in each state, and the code word at that time is assigned as a label. The connection of edges is called a path, and a codeword sequence corresponds to the path.

That is, the state of all transmitted data is related to the state before and after that. For this reason, if a code trellis is used, an error occurring in the transmission path can be corrected with higher accuracy. In particular, a time-invariant convolutional code has a feature that has a trellis structure that is invariant with respect to a point in time. Therefore, if the number of states is small, it is easy to execute an algorithm using a code trellis.

FIG. 23 is an explanatory diagram showing a more detailed configuration of the turbo encoder 900 shown in FIG. FIG. 23A shows a convolutional code (number of memories 2) of the element code shown in FIG. 22, and FIG. 23B shows a corresponding code trellis. Assume that the initial state is that all the values of the memories 1012 to 1014 are 0, and the encoder state is expressed by a series of memory bits. The convolutional encoder 901 shown in FIG. 23A is composed of the two memories 901a and 901b and the three adders 901c and 901e as described above.

In the convolutional code shown in FIG. 23B, if the first information bit is 0, the code word “00” is output, and the state becomes “00” at time 1. On the other hand, if the information bit is 1, the code word “11” is output, and the state at time 1 becomes “10”. At time 2, for each of the states “00” and “11” at time 1, an output of a code word corresponding to 0 or 1 of the information bit and state transition to time 2 are performed.

The MAP algorithm is roughly divided into a forward process for calculating a path metric that reaches each node from the head of the code trellis, a backward process for calculating a path metric that reaches each node from the end of the code trellis, and the results of both. The soft output generation process for calculating the soft output (posterior probability ratio) of the information symbol at each point of time, and the above three types of processes.

The path metric in forward processing relatively represents the logarithmic value of the probability of reaching each node from the top of the trellis under the received sequence and prior information. The path metric in backward processing relatively represents the logarithmic value of the probability of reaching each node from the end of the trellis.

Hereinafter, a set of convolutional code states is represented by S = {0, 1,..., | S | −1}, and path metrics calculated by forward processing and backward processing at nodes at time t and state s are represented by α ( t, s) and β (t, s). In addition, the transition at the time t from the state s to the state s ′, calculated from the received value and prior information (soft output of the other element code in the case of a turbo code) by γ (t, s, s ′) Represents a branch metric corresponding to a probability.

This can be calculated as the likelihood between the codeword corresponding to the transition from s to s ′ and the received value, and γ (t, s, s ′) is the transition from s to s ′ in the white Gaussian channel. It can be easily calculated using the Euclidean distance between the modulation value and the reception value of the output codeword and the prior information on the information bits.

At this time, the forward processing, backward processing, and soft output generation processing are expressed as shown in the following equations 3 to 5, using values before or after one time point. Equation 3 represents forward processing, Equation 4 represents backward processing, and Equation 5 represents soft output generation processing.

Thereafter, in the lines other than the mathematical expressions in the present specification, for example, Σ designated as “s ′: τ (s ′, b) = s, b = 0,1” as a suffix is replaced with Σ_ {s, s ′: τ. (S, b) = s ′}. τ (s ′, b) = s represents a transition from state s ′ to s with information bit b, and Σ_ {s ′: τ (s ′, b) = s, b = 0, 1} It represents that the sum is taken over all the states s that become s ′ at the time. Also, Σ_ {s, s ′: τ (s, b) = s ′} is summed with respect to the pair of states {s, s ′} in which the information bit in the state transition from s to s ′ is b. Represents.

An algorithm that improves the MAP algorithm and performs the processing shown in Equations 3 to 5 by changing the calculation of the sum by an operation that takes the maximum value is referred to as a Max-Log-MAP algorithm. This eliminates the need for conversion to exp and log, enables calculation processing by the same processing as the ACS (Add-Compare-Select) processing in the Viterbi algorithm, and greatly simplifies the calculation. For example, Equation 3 is simplified as shown in Equation 6 in the Max-Log-MAP algorithm.

As an algorithm for increasing the accuracy of approximation from the Max-Log-MAP algorithm to improving the decoding characteristics efficiently, a correction value for the result of Expression 6 is obtained by referring to the table from the path metric difference value compared in Expression 6. An algorithm to be calculated is described in Non-Patent Document 3, and this is called a Log-MAP algorithm.

FIG. 24 is an explanatory diagram showing the order of forward processing, backward processing, and soft output generation processing performed by the MAP algorithm (or Max-Log-MAP algorithm). If the forward processing α and the backward processing β are not prepared at each time point, the soft output generation processing is impossible. In FIG. 24A, backward processing is performed from the end of the code trellis to generate β at each time point (time T1), and then forward processing and soft output generation processing are performed from the beginning of the trellis (time T2). ) Shows an example of a simple scheduling process.

However, in the example shown in FIG. 24A, a delay corresponding to the trellis length, that is, the information length occurs due to this processing, so that it is not suitable for speeding up. Further, since it is necessary to hold β for the information length, a memory having a capacity corresponding to the information length is required.

FIG. 24 (b) shows an example of a scheduling process for improving this defect, dividing the trellis into blocks at the time point of size W, and performing backward processing, forward processing, and soft output generation processing for each block. . At time T1, backward processing is performed on the block W1. At time T2, backward processing is performed on the block W2 while performing forward processing and soft output generation processing on the block W1. At time T3, the backward process is performed on the block W3 while the forward process and the soft output generation process are performed on the block W2. Thereafter, the processing is continued in the same manner.

In the process illustrated in FIG. 24B, the occurrence of delay and the memory capacity can be reduced to some extent. However, the number of processing cycles corresponding to at least the information length is necessary. Non-Patent Document 3 describes a technique called radix-2 ^ n that improves this drawback. radix-2 ^ n is a technique of reducing the number of cycles and increasing the speed by performing forward processing, backward processing, and soft output generation processing for n time points in one cycle. n is an integer of 2 or more.

Radix-2 ^ n has not only the effect of speeding up, but also the effect of reducing the power consumption of the decoding device because the clock frequency can be lowered by reducing the number of cycles if the throughput is the same. Non-Patent Document 4 describes an example in which processing for radix-4, that is, n = 2 time points, is performed in one cycle. Equation 7 represents forward processing, Equation 8 represents backward processing, and Equation 9 represents soft output generation processing.

Non-Patent Document 3 describes simplification by approximation processing based on the Log-MAP algorithm using table references in equations 7-8. FIG. 25 is an explanatory diagram showing a trellis representing transitions for two time points of time points 2t and 2 (t + 1) in the convolutional encoder with two memories shown in FIG. Time point 2t and time point 2 (t + 1) are indicated by ●, and the time point (2t + 1) in between is indicated by ○.

FIG. 26 is an explanatory diagram showing the backward processing unit 1100 in soft output decoding by radix-4 shown in equations 7-9. The backward processing unit 1100 performs scheduling for storing the backward processing path metric as shown in FIG. As many path metrics as the number of states are generated for even time points.

The backward processing unit 1100 includes a two-time backward processor 1102 that executes the processing shown in Equation 8 and a register 1103 that temporarily stores β every two time points. At the same time, a branch metric memory 1101 for storing the branch metric γ and a path metric memory 1104 are provided.

The branch metric memory 1101 uses the branch metrics γ for two time points in one cycle of processing. Β every two points stored in the register 1103 is also held in the path metric memory 1104 until the generation of the soft output is completed. The register 1103 holds the number of path metrics corresponding to the number of states.

FIG. 27 is an explanatory diagram showing a forward processing / soft output generation unit 1200 in soft output decoding by radix-4 shown in equations 7 to 9. The forward processing / soft output generation unit 1200 performs forward processing / soft output generation processing as shown in FIG. 24A in radix-4, and simultaneously executes forward processing and soft output generation processing. Is.

The forward processing / soft output generation unit 1200 executes a two-time forward processor 1202 that executes the processing shown in Expression 7, a register 1203 that temporarily stores α every two time points, and a processing shown in Expression 9. And a two-time soft output generation processor 1204. The branch metric memory 1101 for storing the branch metric γ and the path metric memory 1104 are the same as those shown in FIG.

The branch metric memory 1101 uses the branch metrics γ for two time points in one cycle of processing. The 2-time soft output generation processor 1204 generates a soft output from α and β at time t and from γ at time t and t + 1.

In addition to the aforementioned non-patent documents 1 to 4, there are the following patent documents as technical documents related to this. Patent Document 1 describes a soft output decoding device that reduces the amount of calculation by performing in parallel the processing within the truncation length and processing that goes back beyond the truncation length. Patent Document 2 describes a Viterbi decoding apparatus that reads out surviving path information from only the bank corresponding to the state having the maximum likelihood metric, performs traceback, and does not read out other unnecessary surviving path information. ing.

Patent Document 3 describes a soft output decoding apparatus that can reduce the number of repetitions of decoding processing by including local soft input / soft output decoding means capable of local input / output of element codes. Patent Document 4 describes a soft output decoding device in which a circuit scale is reduced by providing a memory capable of simultaneously writing and reading data.

Re-specialized WO99 / 62183 JP 2001-186025 A JP 2007-006541 A JP 2008-182442 A

However, since the decoding process related to soft output decoding by radix-4 shown in Equations 7 to 9 based on the code trellis involves processing for two time points, the circuit configuration of the soft output generation processing of Equation 9 in particular It becomes difficult to speed up the decoding process. It is more difficult to increase the speed by setting radix-2 ^ n to a value of 3 or more.

The technologies described as Non-Patent Documents 1 to 4 and Patent Documents 1 to 4 cannot be said to be sufficient in this respect, and the above-described problems cannot be solved.

An object of the present invention is to provide a soft output decoder capable of performing soft output generation processing in soft output decoding by radix-2 ^ n at high speed with a simple circuit configuration.

In order to achieve the above object, a soft output decoder according to the present invention is a soft output decoder that receives an encoded and transmitted bit stream, decodes the bit stream, and outputs the decoded bit stream to the outside. Received value memory for storing, branch metric generating means for generating a branch metric for each time point in the trellis diagram based on the contents stored in the received value memory, and soft output including the posterior probability ratio by decoding the branch metric A soft output decoding means for outputting a code; and a hard output determining means for converting the soft output code into a hard output code not including a posteriori probability ratio and outputting the hard output code to an upper layer. From the branch metric memory to be stored and the end of the branch metric code trellis stored in the branch metric memory, A backward processing unit that estimates a path metric that reaches the node, a forward processing unit that estimates a path metric that reaches each node from the top of the branch metric code trellis stored in the branch metric memory, and a backward processing A path metric memory for storing the estimation processing results by the processing unit, and calculating the posterior probability ratio of the information symbols at each time point from the estimation processing results by the backward processing unit and the forward processing unit, and outputting this as a soft output code And a soft output generation processing unit. The backward processing unit includes a plurality of backward processors connected to each other and corresponding to the estimation processing for each time point of the code trellis. A path metric memory is provided in each backward processor. Featuring multiple corresponding storage areas .

In the present invention, as described above, the path metric for each time point is stored in the path metric memory, and the decoding process is performed on the basis of the path metric memory. Therefore, the decoding device does not require a complicated circuit configuration, and speeding up is easy. Thus, it is possible to provide a soft output decoder having an excellent feature that a decoding process based on a code trellis can be performed at high speed with a simple circuit configuration.

It is explanatory drawing which shows the structure of the soft output decoder (turbo code decoder) which concerns on the 1st Embodiment of this invention. It is explanatory drawing which shows the structure of the transmission system containing the turbo code decoder which concerns on the 1st Embodiment of this invention. 2A shows a transmission system using wireless communication, and FIG. 2B shows a transmission system using a storage medium such as an optical disk. It is explanatory drawing which shows the further detailed structure of the soft output decoding means demonstrated in FIG. It is explanatory drawing which shows the more detailed structure of the backward process part shown in FIG. It is explanatory drawing which shows the more detailed structure of the forward process part and soft output production | generation part which were shown in FIG. FIG. 5 is an explanatory diagram showing a configuration of a backward processing unit in which the configuration of the backward processing unit shown in FIG. 4 is expanded for a general radix-2 ^ n (n is an integer of 2 or more). The configurations of the forward processing unit and the soft output generation processing unit shown in FIG. 5 are expanded for the general radix-2 ^ n (n is an integer of 2 or more). It is explanatory drawing shown. It is explanatory drawing which shows the structure of the turbo code decoder based on the 2nd Embodiment of this invention. It is explanatory drawing which shows the more detailed structure of the soft output decoding means shown in FIG. It is explanatory drawing which shows the more detailed structure of the backward process part shown in FIG. It is explanatory drawing which shows the more detailed structure of the 1st and 2nd 1 time backward processor shown in FIG. It is explanatory drawing which shows in more detail the structure with respect to the state "00" of the 1st 1 time backward processor shown in FIG. It is explanatory drawing which shows the more detailed structure of the forward process part shown in FIG. It is explanatory drawing which shows the more detailed structure of the 1st and 2nd 1 time point forward processor shown in FIG. 10 is a table showing information stored in a register at each time point, data read from a memory, and generated soft output in the forward processing unit and the soft output generating unit in the present embodiment shown in FIG. 9. It is explanatory drawing which shows the structure of the turbo code decoder based on the 3rd Embodiment of this invention. It is explanatory drawing which shows the more detailed structure of the soft output decoding means shown in FIG. FIG. 18 is an explanatory diagram showing a more detailed configuration of the backward processing unit shown in FIG. FIG. 19 is an explanatory diagram showing in more detail the configuration for the state “00” of the configuration of the first one-time backward processor shown in FIG. 18; FIG. 20 is an explanatory diagram showing a more detailed configuration of the forward processing unit and the soft output generation unit shown in FIG. FIG. 20 is an explanatory diagram showing the configuration of the first soft output generation processor shown in FIG. 19 in more detail. It is explanatory drawing which shows the structure of a general turbo encoder and decoder. FIG. 22A shows a turbo encoder, and FIG. 22B shows a turbo decoder. It is explanatory drawing which shows the more detailed structure of the turbo encoder shown in FIG. FIG. 23A shows a convolutional encoder (number of memories 2) of the element code of FIG. 22, and FIG. 23B shows a corresponding code trellis. It is explanatory drawing which shows the order of the forward process performed by a MAP algorithm (or Max-Log-MAP algorithm), a backward process, and a soft output production | generation process. FIG. 24 (a) shows an example of a simple scheduling process, and FIG. 24 (b) shows an example of a scheduling process in which the drawbacks are improved. FIG. 25 is an explanatory diagram showing a trellis representing transitions for two time points of time points 2t and 2 (t + 1) in the convolutional encoder with two memories shown in FIG. FIG. 10 is an explanatory diagram showing a backward processing unit in soft output decoding by radix-4 shown in equations 7-9. FIG. 10 is a block diagram of a forward processing / soft output generation unit in soft output decoding by radix-4 shown in equations 7-9.

(First embodiment)
The configuration of the first embodiment of the present invention will be described below with reference to FIGS.
First, the basic content of the present embodiment will be described, and then more specific content will be described.
The soft output decoder 10 according to the present embodiment is a soft output decoder that decodes a bit stream and outputs the decoded bit stream to the outside. This soft output decoder 10 includes received value memories 101 to 103 for storing a bit stream and branch metric generating means 105 for generating a branch metric for each time point in the trellis diagram based on the contents stored in the received value memory. A soft output decoding unit 110 that decodes the branch metric and outputs a soft output code including the posterior probability ratio; and a hard output determination that converts the soft output code into a hard output code that does not include the posterior probability ratio and outputs the same to the outside Means 106. The soft output decoding means stores a branch metric memory 150 that temporarily stores a branch metric, a backward processing unit 120 that estimates a path metric that reaches each node from the end of a code trellis of the stored branch metric, and A forward processing unit 130 for estimating a path metric reaching each node from the head of the code trellis of the branch metric, a path metric memory 160 for storing a result of estimation processing by the backward processing unit, a backward processing unit and a forward A soft output generation processing unit 140 that calculates a posteriori probability ratio of the information symbols at each time point from the estimation processing result by the processing unit and outputs the information symbol as a soft output code. The backward processing unit is connected to each other and includes a plurality of backward processors 121 to 122 corresponding to the estimation processing for each time point of the code trellis, and the path metric memory 160 includes a plurality of backward processors corresponding to each of the backward processors. Storage areas 161 to 162 are provided.

Also, this backward processing unit and forward processing unit perform path metric estimation processing for a plurality of time points for one cycle. The forward processing unit includes a plurality of forward processors 131 to 132 that are connected to each other and correspond to estimation processing for each time point of the code trellis. Further, the path metric memory 160 includes a plurality of storage areas 161 to 162 corresponding to each of the forward processors, and the soft output generation processing unit is based on the estimation processing result by the backward processing unit and the forward processing unit stored in the path metric memory. A posteriori probability ratio of information symbols at each time point is calculated.

With the above configuration, the soft output decoder 10 can perform the decoding process based on the code trellis at high speed with a simple circuit configuration.
Hereinafter, this will be described in more detail.

FIG. 2 is an explanatory diagram showing a configuration of a transmission system 1 including a turbo code decoder 10 which is a soft output decoder according to the first embodiment of the present invention. The transmission system 1 shown in FIG. 2A includes an antenna 20 that receives radio signals by wireless communication, a demodulator 30 that extracts a bit stream from the radio signals received by the antenna 20, and an extracted bit stream. The turbo code decoder 10 performs error correction and decoding.

Further, the antenna 20 shown in FIG. 2A may be replaced with a wired transmission system such as ADSL. Further, as shown in FIG. 2B, the antenna 20 may be replaced with an optical pickup 20a that reads recorded data from a storage medium such as an optical disk. That is, the turbo code decoder 10 can be widely applied to all uses for decoding a bitstream. The bit stream output from the demodulator 30 to the turbo code decoder 10 includes an information reception value and first and second parity reception values.

FIG. 1 is an explanatory diagram showing the configuration of the turbo code decoder 10 according to the present embodiment shown in FIG. The turbo code decoder 10 includes an information reception value memory 101 for storing the reception value from the demodulator 30, first and second parity reception value memories 102 and 103, and an interleaver 104 for generating an interleave output from the information reception value. A branch metric generation unit 105 that generates a branch metric from the information reception value and its interleaved output, the first and second parity reception values, and a soft output decoding unit 110 that decodes the branch metric and outputs a soft output code With.

The turbo code decoder 10 also converts the soft output code output from the soft output decoding unit 110 into a hard output code and outputs the hard output code to an upper layer, and generates a deinterleaved output from the soft output code. A deinterleaver 107, an external information memory 108 that stores the soft output code and its deinterleave output as external information, and an interleaver 109 that further generates an interleave output from the external information. The branch metric generation means 105 also uses this external information and its interleaved output to generate branch metrics.

FIG. 3 is an explanatory diagram showing a more detailed configuration of the soft output decoding unit 110 described in FIG. The soft output decoding unit 110 includes a backward processing unit 120, a forward processing unit 130, a soft output generation processing unit 140, a branch metric memory 150, and a path metric memory 160.

The branch metric output from the branch metric generation unit 105 is stored in the branch metric memory 150 and then input to each of the backward processing unit 120, the forward processing unit 130, and the soft output generation processing unit 140. The processing contents of these units will be described later. The content processed by the backward processing unit 120 is stored in the path metric memory 160 and then input to the soft output generation processing unit 140. The soft output generation processing unit 140 generates content that is finally output by the soft output decoding unit 110.

The soft output decoding unit 110 is configured to perform processing in the order of backward processing, forward processing, and soft output generation processing as described with reference to FIG. 24. The backward processing unit 120, the forward processing unit 130, The path metric α may be generated by first performing forward processing and stored in the path metric memory 160, and then backward processing and soft output generation processing may be performed.

As will be described later, the path metric memory 160 has a plurality of storage areas according to the processing stage of the backward processing.

Hereinafter, α (t) represents a set of α (t, s) for all states s at time t. The same applies to β (t). Γ (t) represents a set of all branch metrics at time t.

FIG. 4 is an explanatory diagram showing a more detailed configuration of the backward processing unit 120 shown in FIG. The backward processing unit 120 performs two-time backward processing when the present embodiment is applied to radix-4, and includes first and second one-time backward processors 121 and 122, and β every second time. Is stored temporarily. The path metric memory 160 has first and second path metric storage areas 161 and 162 that hold path metrics generated by the respective one-time backward processors 121 and 122.

Each one-time backward processor and 122 may perform the same processing or different processing. The branch metric memory 150 uses the branch metrics γ for two time points in one cycle of processing. When the register 123 holds β (2 (t + 1)), the backward processing unit 120 completes the next processing in one cycle.

The first one-time backward processor 121 uses the equation shown in the above equation 4 using β (2 (t + 1)) stored in the register 123 and γ (2t + 1) stored in the branch metric memory 150. A metric β (2t + 1) is generated and stored in the first path metric storage area 161.

The second one-time backward processor 122 uses the intermediate path metric β (2t + 1) generated by the first one-time backward processor 121 and γ (2t) stored in the branch metric memory 150 to Β (2t) is generated by the processing shown, and the register 123 is updated and stored in the second path metric storage area 162.

FIG. 5 is an explanatory diagram showing a more detailed configuration of the forward processing unit 130 and the soft output generation processing unit 140 shown in FIG. The forward processing unit 130 performs two-time point forward processing when the present embodiment is applied to radix-4, and includes first and second one-time point forward processors 131 and 132, and these one-time point forward processors 131. And 132 have first and second registers 133 and 134 for temporarily storing intermediate path metrics generated.

The soft output generation processing unit 140 performs soft output generation processing when the present embodiment is applied to radix-4, and includes a register 141 that temporarily stores the branch metric memory output from the branch metric memory 150, a path First and second soft output generation processing is performed from the contents stored in the first and second path metric storage areas 161 and 162 of the metric memory 160 and the contents stored in the respective registers 133, 134 and 141. Soft output generation processing processors 142 and 143.

The operation when the register 133 holds α (2t) will be described. First, the first one-time forward processing means 131 uses the intermediate path metric by α 10 (2t) held by the register 133 and γ (2t) input from the branch metric memory 150 by the processing shown in the above-described Expression 10. α (2t + 1) is generated and stored in the register 134.

The second one-time-point forward processing means 132 is based on the intermediate path metric α (2t + 1) stored in the first path metric storage area 161 in FIG. 4 and γ (2t + 1) input from the branch metric memory 150. Α (2 (t + 1)) is generated by the processing shown in Equation 10 above, and the register 133 is updated.

The first and second soft output generation processing processors 142 and 143 each generate a soft output at each of the time points 2t and 2t + 1. The first soft output generation processor 142 calculates the following equation 11 from α (2t) of the register 133, β (2t + 1) of the path metric memory 161, and γ (2t) input from the branch metric memory 150. The soft output at time 2t is generated by the processing shown in FIG.

The second soft output generation processor 143 calculates the above-described value from α (2t−1) of the register 134, β (2t) of the path metric memory 161, and γ (2t−1) stored in the register 141. The soft output at the time point 2t-1 is generated by the processing shown in equation (11). The register 141 is updated to γ (2t + 1).

(Overall operation of the first embodiment)
Next, the overall operation of the above embodiment will be described. The security policy creation method according to the present embodiment is a turbo code decoding method that decodes a bitstream encoded by a turbo code and outputs it to the outside. First, a bit stream is stored in a reception value memory provided in advance, a branch metric for each time point in the trellis diagram is generated based on the contents stored in the reception value memory, and a code trellis is generated from the end of the branch metric code trellis. The path metric reaching each node is estimated at each point of time, the result of the estimation process from the end of the code trellis is stored in a path metric memory prepared for each point in time, and the head of the branch metric code trellis Is used to estimate the path metric reaching each node at each point in time of the code trellis from the end of the code trellis and calculate the posterior probability ratio of the information symbols at each point of time from the results of the estimation process from the end and beginning of the code trellis. Is a soft output code that includes the posterior probability ratio, and the soft output code is changed to a hard output code that does not include the posterior probability ratio. To output to the outside.
With this configuration and operation, the present embodiment has the following effects.

This embodiment can realize the soft output decoding algorithm on the code trellis based on radix-2 ^ n without increasing the complexity of the soft output generation process. Therefore, it is possible to increase the speed of the operation of the decoder and improve the device scale.

For example, in the case of soft output decoding based on the normal Max-Log-MAP algorithm for each point in time in the convolutional code of FIG. 2, the logical depth of the soft output generation processing shown in Equation 5 is two stages of arithmetic additions, There are a total of four stages of max circuits (select one from four metrics each of which is information bits 0 and 1), and the radix-4 soft output generation processing shown in Equation 9 is three stages of arithmetic additions, max circuits There are three stages.

On the other hand, if this embodiment is used, the radix-4 soft output generation process remains the two stages of arithmetic addition and the two stages of the max circuit, and the forward process and the backward process also include the two stages of arithmetic addition and the max circuit 2. It becomes a step. That is, according to the present embodiment, the maximum latency can be suppressed to about 2/3 as compared with the normal radix-4, and accordingly, the maximum clock frequency is increased and the operation speed can be increased. it can.

(Extension of the first embodiment)
In the first embodiment described above, only the case of radix-4 has been described. However, this can be easily extended to the case of radix-2 ^ n (n is an integer of 2 or more).

FIG. 6 is an explanatory diagram showing a configuration of the backward processing unit 120n obtained by extending the configuration of the backward processing unit 120 shown in FIG. 4 in the case of a general radix-2 ^ n (n is an integer of 2 or more). is there. The backward processing unit 120n includes an n-time backward processing unit configured by connecting n one-time backward processors 121a, 121b,... 121n, and a register 123n for temporarily storing β every n time points. Have. The path metric memory 160 has n path metric storage areas 161a, 161b,... 161n that hold path metrics generated by the respective one-time backward processors 121a to 121n.

When the register 123n stores β (nt), in the next step, each processor generates β (nt + 1),..., Β (nt + n−1), β (n (t + 1)) and corresponds to each. Stored in the path metric storage areas 161a to 161n. The register 123n is updated by β (n (t + 1)).

FIG. 7 shows a configuration of the forward processing unit 130n and the soft output generation processing unit 140 shown in FIG. 5 in the case of a general radix-2 ^ n (n is an integer of 2 or more) and a forward processing unit 130n and a soft processing unit 130n. It is explanatory drawing which shows the structure of the output generation process part 140n. The forward processing unit 130n includes n one-time forward processors 131a, 131b,... 131n and n-1 registers 134a, 134b corresponding to the one-time forward processors 131a to 131n. ... 134 (n-1).

When α (nt) is stored in the register 133, α (nt-1), α (nt-2), ..., α (nt-n + 1) are stored in the registers 134a to (n-1). Has been. The soft output generation processing unit 140n includes n one-time soft output generation processors 142a to 142n that execute the processing shown in Equation 11 above.

With the above configuration, a turbo code decoder having the same effect as that of the first embodiment can be obtained even in the case of general radix-2 ^ n (n is an integer of 2 or more).

(Second Embodiment)
In the second embodiment of the present invention, compared to the first embodiment described above, a correction processing unit 400 is provided between the backward processor and the path metric memory, and the output data of the backward processing is transferred to the non-patent document described above. 3 is corrected based on the Log-MAP algorithm described in No. 3, and then stored in the path metric memory. As a result, the calculation amount and the memory capacity can be reduced while improving the accuracy of the soft output generation process.

FIG. 8 is an explanatory diagram showing the configuration of the turbo code decoder 210 according to the second embodiment of the present invention. The configuration of the turbo code decoder 210 is different from the configuration of the turbo code decoder 10 according to the first embodiment described in FIG. 1 only in the internal configuration of the soft output decoding means 110. This is called decryption means 310. All other components are referred to by the same name and reference number. The turbo code decoder 210 performs a decoding process on the turbo code using the Max-Log-MAP algorithm described above.

FIG. 9 is an explanatory diagram showing a more detailed configuration of the soft output decoding means 310 shown in FIG. The configuration of the soft output decoding unit 310 differs from the configuration of the soft output decoding unit 110 according to the first embodiment described in FIG. 3 only in the internal configurations of the backward processing unit 120 and the forward processing unit 130. These are referred to as a backward processing unit 320 and a forward processing unit 330. All other components are referred to by the same name and reference number.

FIG. 10 is an explanatory diagram showing a more detailed configuration of the backward processing unit 320 shown in FIG. The configuration of the backward processing unit 320 is different from the configuration of the backward processing unit 120 according to the first embodiment described in FIG. 4 only in the first and second one-time backward processors 121 and 122. These are referred to as first and second one-time backward processors 321 and 322, respectively. All other components are referred to by the same name and reference number.

FIG. 11 is an explanatory diagram showing a more detailed configuration of the first and second one-time backward processors 121 and 122 shown in FIG. The register 123 holds path metrics for the respective states β (2t, 00), β (2t, 10), β (2t, 01), β (2t, 11).

The first one-time backward processor 321 includes eight arithmetic addition circuits 321a to 321h that add the corresponding values of β and γ, and max circuits 321i to 321 that compare the numerical values and output the larger numerical value. Composed. Similarly, the second one-time backward processor 322 also includes eight arithmetic addition circuits 322a to 322h that add the corresponding β and γ values, and max circuits 322i to 322 that compare the numerical values and output the larger numerical value. It consists of.

The first one-time backward processor 321 uses the aforementioned Max-Log-MAP algorithm to store γ (2t−1,00), γ (2t−1,10), γ held in the branch metric memory 150. For each of (2t−1,01), γ (2t−1,11) and each numerical value held in the register 123, the processing shown in the following Expression 12 is performed.

Here, γ (t, xy) represents a branch metric of the codeword bit string “xy” at time t, and is collectively referred to as γ (t). Similarly, β (t, xy) represents the path metric of the codeword bit string “xy” at time t, and is collectively referred to as β (t).

The second one-time backward processor 322 uses the aforementioned Max-Log-MAP algorithm to store γ (2t−2,00), γ (2t−2,10), γ held in the branch metric memory 150. For each of (2t−2,01) and γ (2t−2,11) and each numerical value output from the first one-time backward processor 321, the process shown in the above equation 12 is also performed.

The path metric storage area 161 generates β (2t−1) by the first one-time backward processor 321, and the path metric storage area 162 generates β (2t−2) by the second one-time backward processor 322. Hold. Register 123 is also updated with β (2t−2).

FIG. 12 is an explanatory diagram showing in more detail the configuration for the state “00” of the first one-time backward processor 321 shown in FIG. The first one-time backward processor 321 includes a simple backward processor 410 that performs the process shown in the above-described equation 12 and a correction processing unit 400 described later.

The simple backward processor 410 includes the max circuit 322i and adders 322a and 322b shown in FIG. The same applies to states other than “00”. The correction processing unit 400 includes a difference unit 401 that takes a difference value | xy− between the input values x and y with respect to the max circuit 321i expressed by Equation 13, and a table reference that corrects the difference value based on a previously prepared table. Means 402, and an adder 403 for adding the output of the max circuit 321i and the output of the table reference means 402.

The Log-MAP algorithm realizes the second term on the right side of Equation 14 by referring to the table based on Equation 14 shown below.

The table reference unit 402 refers to the table 420 stored in advance, and | x−y for the path metric β ′ (2t−1,00): = max (x, y) selected by the max circuit 321i. Based on |, the correction value shown in Formula 15 is output. Here, LUT () is a table reference function. The table 420 may be stored in the first one-time backward processor 321 or may be stored in an external storage device. An output between the table reference unit 402 and the adder 403 is stored in the path metric memory 161.

FIG. 13 is an explanatory diagram showing a more detailed configuration of the forward processing unit 330 shown in FIG. The configuration of the forward processing unit 330 is different from the configuration of the forward processing unit 130 according to the first embodiment described in FIG. 4 only in the first and second one- time forward processors 131 and 132. Are referred to as first and second one- time forward processors 331 and 332. All other components are referred to by the same name and reference number.

FIG. 14 is an explanatory diagram showing a more detailed configuration of the first and second one- time forward processors 131 and 132 shown in FIG. The register 133 holds path metrics for the respective states β (2t, 00), β (2t, 10), β (2t, 01), and β (2t, 11).

The first one-time forward processor 331 includes eight arithmetic addition circuits 331a to 331h that add corresponding values of β and γ, and max circuits 331i to 331 that compare the numerical values and output a larger numerical value. Composed. Similarly, the second one-time forward processor 332 adds eight arithmetic addition circuits 332a to 332h that add the corresponding β and γ values, and max circuits 332i to 332 that compare the numerical values and output the larger numerical value. It consists of.

The first one-time forward processor 331 uses the aforementioned Max-Log-MAP algorithm to store γ (2t, 00), γ (2t, 10), γ (2t, 01) held in the branch metric memory 150. ), Γ (2t, 11) and each numerical value held in the register 133.

The path metric memory 161 holds α (2t + 1) generated by the one-time forward processor 331. The register 133 storing α at time 2t is updated to α (2t + 2) in the next cycle. The register 141 stores α (2t + 1) generated in the process.

FIG. 15 is a table showing the forward processing means and soft output generation means shown in FIG. 9, the information stored in each register, the data read from the memory, and the generated soft output at each time point. It is. The branch metric γ (1) at time 0 is used to generate α (1) and is held in the register 141. At time 1, L (1) is calculated using γ (1) of register 141 and α (1) and β (2) of register 134.

Since the operation by the correction processing unit 400 described above can be operated in parallel with the second one-time backward processor 322, the overall processing time is not affected, and the processing speed is not deteriorated. Does not occur. The same applies to the second one-time forward processor 332.

Thus, in this embodiment, the accuracy of the path metric value can be further improved, and at the same time, the output characteristics can be improved.

(Third embodiment)
Compared with the second embodiment described above, the third embodiment of the present invention further adds a path memory 670 to the first one-time forward processor, and stores an index of a state corresponding to the selected path metric. It is configured to memorize. As a result, the max circuit used in the second embodiment can be replaced with a selector, so that the circuit configuration can be further simplified.

FIG. 16 is an explanatory diagram showing a configuration of a turbo code decoder 510 according to the third embodiment of the present invention. The configuration of the turbo code decoder 510 differs from the configuration of the turbo code decoder 10 according to the first embodiment described in FIG. 1 only in the internal configuration of the soft output decoding means 110. This is called decoding means 610. All other components are referred to by the same name and reference number. The turbo code decoder 510 performs a decoding process on the turbo code using the Max-Log-MAP algorithm described above.

FIG. 17 is an explanatory diagram showing a more detailed configuration of the soft output decoding means 610 shown in FIG. The configuration of the soft output decoding unit 610 differs from the configuration of the soft output decoding unit 110 according to the first embodiment described in FIG. 3 in the internal configurations of the backward processing unit 120 and the soft output generation unit 140. These are referred to as a backward processing unit 620 and a soft output generation unit 640. The forward processing unit 330 is the same as that of the second embodiment described with reference to FIG. Furthermore, a path memory 670 described later is added. All other components are referred to by the same name and reference number.

FIG. 18 is an explanatory diagram showing a more detailed configuration of the backward processing unit 620 shown in FIG. The configuration of the backward processing unit 620 is different from the configuration of the backward processing unit 320 according to the second embodiment described above with reference to FIG. 10 only in the first one-time backward processor 321. The one-time backward processor 621. All other components are referred to by the same name and reference number.

The first one-time backward processor 621 uses the information stored in the path memory 670 to perform backward processing using β (2 (t + 1)) to γ (2t + 1) of the path metric memory 161 at the time t. An intermediate metric β (2t + 1) is generated, and α (2t) and γ (2t) in the register 133 are combined to generate L (2t). The first one-time backward processor 621 stores, in the path memory 670, an index in a state corresponding to the selected path metric generated in this generation process together with the path metric of the previous time.

FIG. 19 is an explanatory diagram showing in more detail the configuration for the state “00” of the configuration of the first one-time backward processor 621 shown in FIG. For the state “00”, the first soft output generation processor 621 performs an arithmetic addition circuit 621a that arithmetically adds β (2t, 00) and γ (2t, 00), and β (2t, 10). An arithmetic addition circuit 621b that arithmetically adds γ (2t, 11), a comparator 624i that compares outputs from these arithmetic addition circuits 621a and 621b, and a selector that switches an output according to the output from the comparator 624i 621i. The first one-time backward processor 621 has the same configuration except for “00”.

In the forward processing of the Max-Log-MAP algorithm, if there is information on which path metric of the state s at time t is determined from the path metric of which state (t + 1), the max circuit shown in FIG. It is possible to replace with ~ r. Therefore, the first one-time backward processor 621 stores this in the path memory 670.

FIG. 20 is an explanatory diagram showing a more detailed configuration of the forward processing unit 330 and the soft output generation unit 640 shown in FIG. The forward processing unit 330 is the same as that of the second embodiment already described in FIG. The configuration of the soft output generation unit 640 is different from the configuration of the soft output generation unit 340 according to the second embodiment described above with reference to FIG. This is referred to as a soft output generation processor 642. Further, a register 645 described later is included. All other components are referred to by the same name and reference number.

For a rate 1 / n convolutional code, one bit per index is sufficient for this index. Since the path metric memory typically requires 5 to 8 bits to store one state, the path memory 670 requires a much smaller storage capacity than the path metric memory 161.

FIG. 21 is an explanatory diagram showing the configuration of the first soft output generation processor 642 shown in FIG. 19 in more detail. The first soft output generation processor 642 passes eight arithmetic addition circuits 642a to 642h for adding the corresponding β and γ values, and a path metric obtained by arithmetic addition of β (2t) and γ (2t−1). It is composed of selectors 642i to 642l that switch outputs in accordance with the stored contents of the memory 670. By combining the path memory 670 and the selectors 642i to l, the max circuits 322i to l in the second embodiment described in FIG. 11 are substituted. The register 645 temporarily stores β (2 (t + 1)).

The first soft output generation processor 642 uses the information stored in the path memory 670 to perform backward processing using β (2 (t + 1)) to γ (2t + 1) stored in the register 645 at time t. An intermediate metric β (2t + 1) is generated, and L (2t) is generated using α (2t) and γ (2t) stored in the register 123.

In the present embodiment described above, since the path memory 670 is added, it is necessary to slightly increase the capacity of the memory as compared with the first and second embodiments described above, but instead, a soft output generation circuit is provided. It can be configured more simply.

The present invention has been described with reference to the specific embodiments shown in the drawings. However, the present invention is not limited to the embodiments shown in the drawings, and any known hitherto provided that the effects of the present invention are achieved. Even if it is a structure, it is employable.

For each of the embodiments described above, the main points of the new technical contents are summarized as follows. In addition, although part or all of the said embodiment is summarized as follows as a novel technique, this invention is not necessarily limited to this.

(Supplementary Note 1) A soft output decoder that receives a coded and transmitted bitstream, decodes it, and outputs it to the outside.
A reception value memory for storing the received bitstream; branch metric generation means for generating a branch metric for each time point in the trellis diagram based on the contents stored in the reception value memory; and decoding the branch metric Soft output decoding means for outputting a soft output code including a posterior probability ratio, and hard output determining means for converting the soft output code into a hard output code not including a posterior probability ratio and outputting the same to the outside,
A branch metric memory that temporarily stores the branch metric, and a backward processing unit that estimates a path metric that reaches each node from the end of a code metric of the branch metric stored in the branch metric memory. A forward processing unit that estimates a path metric that reaches each node from the top of the branch metric code trellis stored in the branch metric memory, and a path metric memory that stores a result of estimation processing by the backward processing unit And a soft output generation processing unit that calculates a posteriori probability ratio of the information symbols at each time point from the estimation processing results by the backward processing unit and the forward processing unit and outputs the information symbol as the soft output code. ,
The backward processing unit includes a plurality of backward processors connected to each other and corresponding to the estimation processing for each time point of the code trellis,
The soft output decoder, wherein the path metric memory comprises a plurality of storage areas corresponding to each of the backward processors.

(Supplementary note 2) The soft output decoder according to supplementary note 1, wherein the backward processing unit and the forward processing unit perform estimation processing of the path metrics for a plurality of time points for one cycle.

(Supplementary Note 3) The forward processing unit includes a plurality of forward processors connected to each other and corresponding to the estimation processing for each time point of the code trellis,
The path metric memory comprises a plurality of storage areas corresponding to each of the forward processors;
The soft output generation processing unit calculates an a posteriori probability ratio of information symbols at each time point from a result of estimation processing by the backward processing unit and the forward processing unit stored in the path metric memory. The soft output decoder according to appendix 1.

(Supplementary Note 4) The backward processing unit performs correction processing based on the Log-MAP algorithm for the path metric stored in the path metric memory by the backward processor that is not the last stage among the plurality of backward processors. The soft output decoder according to claim 1, further comprising a correction processing unit.

(Supplementary Note 5) The soft output decoding unit includes a path memory in which the backward processor that is not the last stage among the plurality of backward processors stores an index indicating selection information of the path metric,
The soft output decoder according to appendix 4, wherein the soft output generation processing unit calculates an a posteriori probability ratio of the information symbol based on the path metric and the index.

As mentioned above, although this invention was demonstrated with reference to embodiment (and an Example), this invention is not limited to the said embodiment (and Example). Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

This application claims priority based on Japanese Patent Application No. 2009-242911 filed on October 22, 2009, the entire disclosure of which is incorporated herein.

The present invention can be widely applied to all uses for decoding a bit stream, such as wireless and wired communication, or an optical disc.

1 Transmission system 10, 210, 510 Turbo code decoder 20 Antenna 20a Optical pickup 30 Demodulator 101 Information reception value memory 102, 103 Parity reception value memory 104, 109 Interleaver 105 Branch metric generation means 106 Hard output determination means 107 Deinterlacing Lever 108 External information memory 110, 310, 610 Soft output decoding means 120, 120n, 320, 620 Backward processing units 121, 122, 121a, 121b, 121n, 321, 322, 621 Backward processors 123, 133, 134, 141, 123n, 134a, 134b, 134 (n-1), 645 registers 130, 130n, 330 Forward processing units 131, 132, 131a, 131b, 131n, 331, 3 2 Forward processor 140, 640 Soft output generation processing unit 142, 143, 142a, 142b, 142n, 642 Soft output generation processor 150 Branch metric memory 160 Path metric memory 161, 162, 161a, 161b, 161n Path metric storage area 321a, 321h 322a, 322h, 331a, 331h, 332a, 332h, 621a, 621b Arithmetic addition circuit 321i, 321l, 322i, 322l, 331i, 331l, 332i, 332l max circuit 400 Correction processing unit 401 Difference means 402 Table reference means 403 Adder 410 Simple backward processor 420 Table 621i, 621o, 621r Selector 624i Comparator 670 Path memory

Claims (5)

1. A soft output decoder that receives a coded and transmitted bitstream, decodes it, and outputs it to the outside.
   A reception value memory for storing the received bitstream; branch metric generation means for generating a branch metric for each time point in the trellis diagram based on the contents stored in the reception value memory; and decoding the branch metric Soft output decoding means for outputting a soft output code including a posterior probability ratio, and hard output determining means for converting the soft output code into a hard output code not including a posterior probability ratio and outputting the same to the outside,
   A branch metric memory that temporarily stores the branch metric, and a backward processing unit that estimates a path metric that reaches each node from the end of a code metric of the branch metric stored in the branch metric memory. A forward processing unit that estimates a path metric that reaches each node from the top of the branch metric code trellis stored in the branch metric memory, and a path metric memory that stores a result of estimation processing by the backward processing unit And a soft output generation processing unit that calculates a posteriori probability ratio of information symbols at each time point from the estimation processing results by the backward processing unit and the forward processing unit and outputs the information symbol as the soft output code. ,
   The backward processing unit includes a plurality of backward processors connected to each other and corresponding to the estimation processing for each time point of the code trellis,
   A soft output decoder, wherein the path metric memory comprises a plurality of storage areas corresponding to each of the backward processors.
2. The soft output decoder according to claim 1, wherein the backward processing unit and the forward processing unit perform the estimation processing of the path metrics for a plurality of time points for one cycle.
3. The forward processing unit includes a plurality of forward processors connected to each other and corresponding to the estimation processing for each time point of the code trellis;
   The path metric memory comprises a plurality of storage areas corresponding to each of the forward processors;
   The soft output generation processing unit calculates a posteriori probability ratio of information symbols at each time point from a result of estimation processing by the backward processing unit and the forward processing unit stored in the path metric memory. The soft-output decoder according to claim 1.
4. The backward processing unit includes a correction processing unit that performs a correction process based on a Log-MAP algorithm for a path metric stored in the path metric memory by the backward processor that is not the last stage among the plurality of backward processors. The soft output decoder according to claim 1, comprising:
5. The soft output decoding means includes a path memory for storing an index indicating selection information of the path metric by the backward processor that is not the last stage among the plurality of backward processors,
   The soft output decoder according to claim 4, wherein the soft output generation processing unit calculates a posterior probability ratio of the information symbol based on the path metric and the index.

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