JP7144621B2 - Communication system and communication method - Google Patents

Description

The present invention relates to a communication system that performs error correction coding in wireless communication, and in particular, a communication system and communication that can greatly reduce the implementation scale and delay time when performing tail-biting convolutional coding with a large coding size. Regarding the method.

[Conventional technology]
Data communication such as wireless communication generally incorporates error correction coding processing and error correction decoding processing.
In the field of wireless communication, convolutional coding is used as one of the techniques.
There are two types of convolutional encoding: zero-tail encoding and tail-biting encoding.

In zero-tail coding, when the initial value of the register in the convolutional encoder is 0 (zero) and the constraint length of the convolutional encoder is K, the last K-1 bits of the bit sequence to be encoded are set to 0. Thus, the beginning and end of the internal state of the convolutional encoder are set to 0, and error correction processing is performed on the decoder side based on this.
However, since K-1 bits of redundant bits are sent, a rate loss occurs.

Tail-biting coding solves the problem of zero-tail coding by setting the initial value of the register in the convolutional encoder to the last bit of the bit sequence, thereby aligning the internal state of the convolutional encoder with the first bit. The end is the same (the initial state and the end state of the encoder are the same state) and no rate loss occurs.

That is, the starting state is not all zeros, but depends on the values of the input bits. Zero-tail encoding requires redundant zero-tail bits to return to the all-zero state, whereas tail-biting encoding can utilize the initial state of the input bits.

[Conventional tail-biting convolutional coding processing image: FIG. 13]
Here, an image of conventional tail-biting convolutional encoding processing will be described with reference to FIG. FIG. 13 is a schematic diagram showing a conventional tail-biting convolutional encoding processing image.
As shown in FIG. 13, the conventional tail-biting convolutional encoding process uses the end of the bit sequence as an initial value. Therefore, the convolutional encoding process does not start until the end of the bit sequence is input.

In general, tail-biting coding delays the bit sequence by L cycles, where L is the length of the original bit sequence. The convolutionally encoded bit sequence for the resulting bit sequence is set as the beginning of the next bit sequence.

In other words, by delaying the original bit sequence and adding (K-1) bits from the end of the original bit sequence to the beginning of the next original bit sequence, the internal state of the convolutional encoder is the same at the beginning and end. It is realized so that it becomes

Specifically, if the bit sequence length is L, a shift register of L length or a memory of L depth is required, resulting in a delay of L clock cycles. As a result, when L is hundreds of thousands or millions long, the implementation scale and delay time increase.

[Related technology]
In addition, as related prior art, JP-A-2014-068158 "Decoding device, decoding method, program and receiving device" (Patent Document 1), JP-A-2018-014760 "Encoding method, decoding method, encoding and Decoder” (Patent Document 2), and Japanese Patent Laid-Open No. 2011-146899 “Encoder, Decoder and Encoding Method, Decoding Method” (Patent Document 3).
Patent Literature 1 discloses that a bit sequence encoded by the tail-biting convolutional coding scheme can be easily decoded while reducing the amount of calculation. Patent Document 2 describes that the use of LDPC-CC using the tail-biting method is adapted to a wireless communication device. There is a description that applies to communication devices.

JP 2014-068158 A JP 2018-014760 A JP 2011-146899 A

However, in the conventional tail-biting convolutional encoding process, the end of the bit sequence is used as an initial value, and the convolutional encoding process is started after delaying until the end of the bit sequence is input. As the number of information bits increases, the number of bits to be delayed to wait for the tail end of the bit sequence increases, and there is a problem that the scale of implementation and the delay time increase in order to realize this.

Note that Patent Document 1 does not describe suppressing an increase in implementation scale and delay time in tail-biting convolutional coding processing.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and provides a communication system and communication method that can greatly reduce the implementation scale and delay time when performing tail-biting convolutional coding with a large coding size. With the goal.

The present invention for solving the problems of the conventional example is a communication system in which data communication is performed between a transmitting side communication device and a receiving side communication device using tail-biting convolutional coding, wherein the transmitting side When the communication device is provided with a convolutional encoder, and the transmission bit sequence length is L, and the constraint length of the convolutional encoder is K, K−1 from the beginning of the bit sequence to be encoded in the preceding stage of the convolutional encoder. input bit sequence generating means for adding a bit to the end of the bit sequence to generate an input bit sequence to be input to a convolutional encoder of length L+K−1; , when the output from the convolutional encoder is n bits, n×(K−1) data is deleted from the head of the error-correction-encoded bit sequence, and tail-biting convolutional-encoding is added to the end. transmission data sequence generating means for generating the remaining n×L bit sequence including the original head portion as a transmission data sequence, and the receiving side communication device has error correction means for error correction of the received data. It is characterized by

In the communication system according to the present invention, the receiving side communication device has rearrangement means for rearranging the original head portion at the end of the received data sequence to the head in the process of the error correction means.

In the communication system of the present invention, the transmitting side communication device has interleaving means for rearranging the transmission data sequence in a predetermined order, and the receiving side communication device restores the data sequence rearranged by the interleaving means to the original order. Deinterleaving means is provided, and the deinterleaving means is provided with rearrangement means for first outputting the original head portion at the end of the received data sequence and rearranging it to the head.

In the communication system of the present invention, the transmitting side communication device has interleaving means for rearranging the transmission data sequence in a predetermined order, and the receiving side communication device restores the data sequence rearranged by the interleaving means to the original order. The interleaving means adds an address from the original head to the write address for the original head part at the end of the transmission data sequence, and arranges the original head part at the head in the interleaved output. It is characterized by comprising rearrangement means for rearranging.

The present invention is a communication method for performing data communication between a transmitting side communication device and a receiving side communication device using tail-biting convolutional coding, wherein the transmitting side communication device sets the transmission bit sequence length to L, Assuming that the constraint length of the convolutional encoder is K, K−1 bits from the beginning of the bit sequence to be encoded in the preceding stage of the convolutional encoder are added to the end of the bit sequence to obtain a convolution of length L+K−1. When an input bit sequence to be input to a convolutional encoder is generated, the input bit sequence is error-correction coded by a convolutional encoder, and the output from the convolutional encoder is n bits, the beginning of the error-correction-encoded bit sequence n × (K−1) data is deleted from, and the remaining n × L bit sequence with the original head part of tail-biting convolutional coding at the end is generated as a transmission data sequence, and received The side communication device is characterized by performing error correction of received data.

According to the present invention, the transmission side communication device is equipped with a convolutional encoder, and when the transmission bit sequence length is L and the constraint length of the convolutional encoder is K, bits to be encoded before the convolutional encoder are: input bit sequence generating means for generating an input bit sequence to be input to a convolutional encoder of L+K−1 length by adding K−1 bits from the beginning of the sequence to the end of the bit sequence; When error correction coding is performed by a convolutional encoder and the output from the convolutional encoder is n bits, n×(K−1) data is deleted from the head of the error correction coded bit sequence, and transmission data sequence generating means for generating a remaining n×L bit sequence including the original leading portion of tail-biting convolutional coding as a transmission data sequence, wherein the receiving side communication device detects an error in the received data; Since the communication system has an error correcting means for correcting errors, when performing tail-biting convolutional coding with a large coding size, the implementation scale and delay time can be greatly reduced compared to the conventional system.

1 is a schematic configuration diagram of a first system; FIG. FIG. 4 is a configuration block diagram of a tail-biting preprocessing unit; 1 is a configuration block diagram of a convolutional encoder; FIG. 1 is a schematic diagram of a tail-biting convolutional encoding process; FIG. FIG. 4 is a schematic diagram illustrating operation of a decoding unit in the first embodiment; FIG. 4 is a schematic diagram of the configuration of a second system; FIG. 11 is a schematic diagram of interleaved write control processing in the second embodiment; FIG. 10 is a schematic diagram of deinterleaving read control processing in the second embodiment; It is a schematic diagram explaining operation|movement of the decoding part in 2nd Embodiment. FIG. 11 is a schematic diagram of the configuration of a third system; FIG. 11 is a schematic diagram of interleaved write control processing in the third embodiment; FIG. 11 is a schematic diagram of deinterleaving read control processing in the third embodiment; It is a schematic diagram showing a conventional tail-biting convolutional encoding process image.

An embodiment of the present invention will be described with reference to the drawings.
[Outline of Embodiment]
In a communication system (this system) according to an embodiment of the present invention, a tail-biting preprocessing unit adds a leading portion of a bit sequence to be encoded to the tail end of the bit sequence to generate an input bit sequence, A convolutional encoder performs error correction encoding on an input bit sequence using a convolutional encoder, deletes the leading portion of the bit sequence subjected to error correction encoding, and replaces the original leading portion of the tail-biting convolutional encoding with the trailing end. Since a transmission data sequence with a portion is generated and the receiving side communication device performs error correction on the received data, when performing tail-biting convolutional encoding with a large encoding size, the implementation scale and delay The time can be greatly reduced as compared with the conventional method.

Also, in the first embodiment of this system, the decoding section of the receiving side communication device rearranges the original leading portion at the end of the received data sequence to the leading portion in the process of error correction means.

In a second embodiment of the present system, the transmitting side communication device includes an interleaving section that rearranges the transmission data sequence in a predetermined order, and the receiving side communication device converts the interleaved and rearranged data sequence into the original data sequence. A deinterleaving unit for restoring the order is provided, and the deinterleaving unit first outputs the original head portion at the end of the received data sequence and rearranges it to the head.

In a third embodiment of the present system, the transmission side communication device includes an interleaving section that rearranges the transmission data sequence in a predetermined order, and the reception side communication device converts the interleaved and rearranged data sequence into the original data sequence. A de-interleaving unit for restoring order is provided, and the interleaving unit adds an address from the original head to the write address for the original head part at the end of the transmission data sequence, and interleaves the original head part to the head in the interleaved output. is rearranged into

[First Embodiment: FIG. 1]
A first embodiment (first system) having transmission and reception communication devices in this system will be described with reference to FIG. FIG. 1 is a schematic diagram of the configuration of the first system.
The first system, as shown in FIG. 1, comprises a transmitting side communication device 100a and a receiving side communication device 100b.
The transmission side communication device 100 a includes a tail-biting preprocessing section 101 , a convolutional coding section 102 and a modulation section 103 .
The receiving side communication device 100b includes a demodulator 104 and a decoder 105 .

[Transmitting side communication device]
Each unit of the transmission-side communication device 100a will be specifically described.
[Tail-biting preprocessing unit 101]
Tail-biting preprocessing section 101 holds K−1 bits from the beginning of the bit sequence, where K is the constraint length of convolutional encoding, and adds them to the end of the original bit sequence.
It should be noted that the input bit generation means in the claims is means realized by the tail-biting preprocessing unit 101 .

[Details of tail-biting preprocessing unit 101: FIG. 2]
Details of the tail-biting preprocessor 101 will be described with reference to FIG. FIG. 2 is a configuration block diagram of the tail-biting preprocessing unit. This configuration is for a constraint length of 7 for convolutional coding.
As shown in FIG. 2, the tail-biting preprocessing unit 101 includes a bit counter 201, a register (Reg0) 202, a register (Reg1) 203, a register (Reg2) 204, a register (Reg3) 205, and a register (Reg4) 206. , a register (Reg5) 207 and a selector 208 .

The bit counter 201 counts the bit numbers from the top and outputs them to the selector 208 .
Registers 202 - 207 receive the first bit (u ₀ -u ₅ ) to be encoded and temporarily copy and store successive input bits, which are read out by selection with selector 208 .

A register (Reg0) 202 stores the 0th bit (u ₀ ).
A register (Reg1) 203 stores the first bit (u ₁ ).
Register (Reg2) 204 stores the second bit (u ₂ ).
Register (Reg3) 205 stores the third bit (u ₃ ).
Register (Reg4) 206 stores the fourth bit (u ₄ ).
Register (Reg5) 207 stores the fifth bit (u ₅ ).

A selector 208 selects whether to output a bit (u') of the original bit sequence length or output a register value (stored bit) of one of the registers 202 to 207 according to the count value of the bit counter 201. .
Specifically, after selecting to output the bits of the original bit sequence length, the registers 202 to 207 are sequentially read. That is, after the bits of the original bit sequence length are output, the first bit (u ₀ to u ₅ ) portion is copied and added.

[Convolutional encoder: Fig. 3]
Next, the convolutional encoder in convolutional encoding section 102 will be described with reference to FIG. FIG. 3 is a configuration block diagram of a convolutional encoder.
The convolutional encoding unit 102 includes the convolutional encoder of FIG. 3 and further performs tail-biting convolutional encoding processing, which will be described later.
The convolutional encoder in the claims corresponds to the convolutional encoder in FIG. It is the means to be realized.

The convolutional encoder performs convolutional encoding processing on the input bit sequence (u _x ) and outputs a convolutionally encoded bit sequence (v _2x , v _2x-1 ).
FIG. 3 shows a convolutional encoder of a generator polynomial (133, 171) with a constraint length of 7, which is often used in the wireless communication field. "133" in the generator polynomial is the binary number "1011011", which represents the bit sequence input to the upper exclusive OR, and "171" is the binary number "1111001", which is the lower exclusive OR. represents the bit sequence input to .

Specifically, the convolutional encoder consists of six registers ( _Reg ) and two exclusive ORs (XOR). and the lower stage XOR, the output of the 1st stage register is output to the 2nd stage register and the lower stage XOR, the output of the 2nd stage register is output to the 3rd stage register and the upper and lower stage XOR , the output of the 3rd stage register is output to the 4th stage register and the XOR of the upper and lower stages, the output of the 4th stage register is output to the 5th stage register, and the output of the 5th stage register is It is output to the 6th stage register and the upper stage XOR, and the output of the 6th stage register is output to the upper stage and lower stage XOR.

Then, the XOR in the upper stage inputs the input bit and the register outputs of the 2nd, 3rd, 5th and 6th stages, performs an exclusive OR operation, and outputs a convolutionally coded bit (v _2x ).
The XOR in the lower stage inputs the input bits and the 1st, 2nd, 3rd and 6th stage register outputs, performs an exclusive OR operation, and outputs a convolutionally coded bit (v _2x-1 ).

[Tail-biting convolutional encoding process: FIG. 4]
Next, an outline of the tail-biting convolutional encoding process will be described with reference to FIG. FIG. 4 is a schematic diagram of the tail-biting convolutional encoding process.
FIG. 4 shows an image of a case in which processing by the tail-biting preprocessing unit 101 and processing by the convolutional coding unit 102 are performed in the transmission-side communication device 100a.

By adding the (K-1) bits of the original information bit sequence to the end, the coded bit sequence, which is originally at the beginning, is output at the end after encoding. The beginning of this encoded bit sequence is discarded.
Specifically, in FIG. 4, the tail-biting preprocessing unit 101 copies the information bit sequence (u ₀ to u ₅ ) and adds it to the end, and the convolutional coding unit 102 performs convolutional coding. and discards the coded bit (first coded bit) of the information bit sequence of the copy source.
Therefore, at the end of the encoded bit sequence (v _2x , v _2x-1 ), there is an encoded bit sequence (v ₀ to v ₁₁ ) corresponding to the copied information bit sequence (u ₀ to u ₅ ). .

Advantageously, embodiments of the present invention require only (K-1) registers and introduce no delay.
The purpose of tail-biting is to create the same internal state (same information bit sequence) at the beginning (head) and end (end) of a data frame, and to make the internal state look like a ring. has been achieved. However, since the output order is different from normal tail-biting convolutional coding, it is necessary to compensate for this order in the decoding unit 105 of the receiving communication device 100b.

[Receiving side communication device 100b]
Each unit of the receiving communication device 100b will be described.
[Demodulation section 104, decoding section 105]
The demodulator 104 of the receiving communication device 100b performs demodulation processing on the received signal.
Decoding section 105 performs soft decision or hard decision, and performs error correction decoding.
For soft decision, soft decision information such as bit LLR (Log Likelihood Ratio) is obtained, and for hard decision, a hard decision result is obtained.

Decoding section 105 performs error correction decoding using soft decision information or hard decision results. Error correction decoding is performed by, for example, Viterbi algorithm or BCJR (Bahl, Cocke, Jelinek, Raviv) algorithm.
Error correcting means and rearranging means in the claims are means realized by the decoding section 105 .

[Operation of Decoding Unit in First Embodiment: FIG. 5]
Next, the operation of the decoding section in the first embodiment will be described with reference to FIG. FIG. 5 is a schematic diagram explaining the operation of the decoding unit in the first embodiment.
In the decoding unit 105, for example, decoding by the BCJR algorithm is performed through a training period.

Utilizing the characteristic that the beginning and end are the same internal state, the same data frame or part thereof is connected to generate a training interval. In FIG. 5, three frames of the same data frame are connected in order to simplify the explanation. If the decoding section is set so as to be in the original order, the decoding results can be output in the correct order even if the original leading group is at the end of the data frame on the transmitting side.

Specifically, as shown in the third stage of FIG. 5, for the pre-decoding data, the training period is up to the last group (last bit string) of the original sequence of the first frame, and the copied data of the first frame is set as the training period. The decoding period is set from the first group of the original sequence to the last group of the original sequence of the second frame, and the training period is set after the first group of the copied original sequence of the second frame, as shown in the fourth row of FIG. Thus, the correct order of the decoded data is obtained.
According to the first embodiment described above, it is possible to realize tail-biting convolutional encoding and its decoding with a simple configuration and a reduced implementation scale and reduced delay time.

[Second Embodiment: FIGS. 6 to 9]
Next, a communication system (second system) according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a schematic diagram of the configuration of the second system, FIG. 7 is a schematic diagram of interleaved write control processing in the embodiment, and FIG. 8 is a schematic diagram of deinterleaved read control processing in the second embodiment. FIG. 9 is a schematic diagram, and FIG. 9 is a schematic diagram for explaining the operation of the decoding unit in the second embodiment;
The second system, as shown in FIG. 6, comprises a transmitting side communication device 100c and a receiving side communication device 100d.

[Transmitting side communication device 100c, receiving side communication device 100d]
The transmission side communication device 100 c includes a tail-biting preprocessing section 101 , a convolutional coding section 102 , an interleaving section 301 and a modulation section 103 .
The receiving communication device 100 d also includes a demodulator 104 , a deinterleaver 302 and a decoder 303 .
Note that the tail-biting preprocessing unit 101, the convolutional coding unit 102, the modulation unit 103, and the demodulation unit 104 have the same configurations as those in the first system, so description thereof will be omitted.

[Interleave section 301]
The interleaving section 301 of the transmission-end communication device 100c rearranges the coded bit sequences (v _2x , v _2x-1 ) that have been convolutionally coded in a predetermined order.
Interleave processing is generally performed using memory. The rearrangement is realized by controlling the write address and read address to the memory. This operation will be described with reference to FIG.

[Interleave write processing: FIG. 7]
The interleaving operation in the second embodiment will be described with reference to FIG.
In interleaving by the interleaving unit 301, write addresses are assigned in ascending order of input. Sort by the read address of the sender.

Specifically, the encoded bit sequence (v ₁₂ to v _2L-1 ) is written in ascending order to addresses 0 to 2L-13 of the memory, and the encoded bit sequence (v ₀ to v ₁₁ ) is written to the last address of the memory. It is written in addresses 2L-12 to 2L-1 in the tail.

In this case, the write address in the deinterleaving unit 302 of the receiving communication device 100d is the same as the read address in the interleaving unit 301 of the transmitting communication device 100c, and the deinterleaving unit 302 of the receiving communication device 100d uses the same read address. By leading in ascending order with , it returns to the original.

[Deinterleaving unit 302]
The deinterleaving unit 302 of the receiving communication device 100d rearranges the demodulated soft-decision information series or hard-decision bit series in a predetermined order, and rearranges them in the order of the transmission source.
However, since the original leading bit sequence is at the end due to the processing by the tail-biting preprocessing unit 101 and the convolutional encoding unit 102, the order is corrected at the time of this deinterleaved reading to restore the original order. This operation will be described with reference to FIG.
The deinterleaving means and the rearrangement means in the claims are means realized by the deinterleaving section 302 .

[Deinterleaving readout process: FIG. 8]
The deinterleaving operation in the second embodiment will be described with reference to FIG.
As shown in FIG. 8, it is possible to correct the reading order in the deinterleaving unit 302 to the original order by starting reading from the original head group at the end.

[Decryption unit 303]
Decoding section 303 performs error correction decoding processing in the same manner as decoding section 105 , but since the data frames are restored to their original order by deinterleaving section 302 , the training period and the decoding period are different from decoding section 105 . The operation of decoding section 303 will be described with reference to FIG.

[Operation of Decoding Unit in Second Embodiment: FIG. 9]
Next, the operation of the decoding section in the second embodiment will be described with reference to FIG.
Since the data frames are read out in the correct order by the deinterleaving unit 302 of the second embodiment, the first data frame is set as the training period and the second data frame is decoded as shown in the third row of FIG. With the third data frame set as a training period, the decoding unit 303 decodes and outputs pre-decoding data in the decoding period.

According to the second embodiment, only by changing the read control of tail-biting convolutional coding and deinterleaving with reduced implementation scale and delay time, the decoding unit 303 can Decryption processing can be realized.

[Third Embodiment: FIGS. 10 to 12]
Next, a communication system (third system) according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 10 is a schematic configuration diagram of the third system, FIG. 11 is a schematic diagram of interleaved write control processing in the third embodiment, and FIG. 12 is a deinterleaved readout process in the third embodiment. 4 is a schematic diagram of control processing; FIG.
The third system, as shown in FIG. 10, comprises a transmitting side communication device 100e and a receiving side communication device 100f.

[Transmitting side communication device 100e, receiving side communication device 100f]
The transmission side communication device 100 e includes a tail-biting preprocessing section 101 , a convolutional coding section 102 , an interleaving section 401 and a modulation section 103 .
Further, the receiving side communication device 100f includes a demodulation section 104, a deinterleaving section 402, and a decoding section 303.
The tail-biting preprocessing unit 101, the convolutional coding unit 102, the modulation unit 103, and the demodulation unit 104 have the same configuration as in the first system, and the decoding unit 303 has the same configuration as in the second system. Therefore, the description is omitted.

[Interleave unit 401]
Interleaving section 401 rearranges the convolutionally coded coded bit sequence (v _2x , v _2x-1 ) in a predetermined order. However, since the original leading bit sequence (v ₀ to v ₁₁ ) is at the end due to the processing by the tail-biting preprocessing unit 101 and the convolutional coding unit 102, the order is corrected at the time of writing, and the original order is back to This operation will be described with reference to FIG.
Note that the interleaving means and the rearrangement means in the claims are means realized by the interleaving section 401 .

[Interleave write processing: FIG. 11]
Interleave operation in the third embodiment will be described with reference to FIG.
As shown in FIG. ₁₁ , the interleaving unit 401 provides interleaving write addresses ₀ , 1, 2, . It is possible to correct to the original order at the time of interleaved output.

[Deinterleaving unit 402: FIG. 12]
Deinterleaving section 402 rearranges the demodulated soft-decision information series or hard-decision bit series in a predetermined order, and rearranges them in the order of the transmission sources.
The difference from the deinterleaving section 302 of the second embodiment is that the transmission data is corrected to the original order in the interleaving section 401, so as shown in FIG. If the write and read addresses are read in ascending order, the encoded bit sequence (v ₀ to v _2L-1 ) is output to the decoding unit 303 in the original order.

According to the third embodiment, only by changing the write address of tail-biting convolutional coding and interleaving with reduced implementation scale and delay time, the receiving side can perform decoding processing without considering the order of the bit sequence. can be realized.
The third embodiment is suitable for implementation in a system in which transmission signals are defined by common standards/specifications.

[Effects of Embodiment]
According to this system, the tail-biting preprocessing unit 101 of the transmission-side communication device 100a generates an input bit sequence by adding the leading portion of the bit sequence to be encoded to the tail end of the bit sequence, and The encoding unit 102 error-correction-encodes the input bit sequence with a convolutional encoder, deletes the leading portion of the error-correction-encoded bit sequence, and replaces the original leading portion of the tail-biting convolutional encoding at the end. The transmission data sequence provided is generated, and the receiving side communication device 100b performs error correction on the received data. There is an effect that it can be reduced significantly compared with the conventional one.

INDUSTRIAL APPLICABILITY The present invention is suitable for a communication system and communication method that can significantly reduce the implementation scale and delay time when performing tail-biting convolutional coding with a large coding size. This application claims the benefit of priority based on Japanese Patent Application No. 2019-161369 filed on September 4, 2019, the entire disclosure of which is incorporated herein by reference.

100a, 100c, 100e... transmitting side communication device, 100b, 100d, 100f... receiving side communication device, 101... tail-biting preprocessing section, 102... convolutional coding section,
DESCRIPTION OF SYMBOLS 103... Modulation part 104... Demodulation part 105, 303... Decoding part 201... Bit counter 202-207... Register 208... Selector 301, 401... Interleaving part 302, 402... Deinterleaving part

Claims (5)

A communication system for performing data communication between a transmitting communication device and a receiving communication device using tail-biting convolutional coding,
the transmitting communication device comprising a convolutional encoder;
When the transmission bit sequence length is L and the constraint length of the convolutional encoder is K, K−1 bits from the beginning of the bit sequence encoded in the preceding stage of the convolutional encoder are added to the end of the bit sequence. input bit sequence generation means for generating an input bit sequence to be added and input to the L+K−1 length convolutional encoder;
When the input bit sequence is error-correction coded by the convolutional encoder and the output from the convolutional coder is n bits, n×(K−1) from the head of the error-correction-encoded bit sequence. a transmission data sequence generation means for deleting data and generating a remaining n×L bit sequence with the original head portion of tail-biting convolutional coding at the end as a transmission data sequence;
A communication system, wherein the receiving side communication device has error correcting means for error correction of received data. 2. The communication system according to claim 1, wherein the receiving side communication device has rearrangement means for rearranging the original head portion at the end of the received data sequence to the head in the process of the error correction means. The transmission side communication device comprises interleaving means for rearranging the transmission data sequence in a predetermined order,
The receiving side communication device comprises deinterleaving means for restoring the data sequence rearranged by the interleaving means to its original order,
2. The communication system according to claim 1, wherein said deinterleaving means comprises rearrangement means for first outputting the original head portion at the end of the received data sequence and rearranging it to the head. The transmission side communication device comprises interleaving means for rearranging the transmission data sequence in a predetermined order,
The receiving side communication device comprises deinterleaving means for restoring the data sequence rearranged by the interleaving means to its original order,
the interleaving means assigns an address from the original head to the write address for the original head part at the end of the transmission data sequence, and rearranges the original head part to the head in the interleaved output; 2. The communication system of claim 1, comprising: A communication method for performing data communication between a transmitting communication device and a receiving communication device using tail-biting convolutional coding,
When the transmission bit sequence length is L and the constraint length of the convolutional encoder is K, the transmission side communication device selects K−1 bits from the beginning of the bit sequence to be encoded in the preceding stage of the convolutional encoder. generating an input bit sequence to be added to the end of the bit sequence and input to the convolutional encoder having a length of L+K−1, error correction encoding the input bit sequence by the convolutional encoder, and When the output from is n bits, n×(K−1) data is deleted from the head of the error correction encoded bit sequence, and the original head part of the tail-biting convolutional coding is added to the end. as the transmission data sequence, the remaining n×L bit sequence with
A communication method, wherein the receiving side communication device performs error correction of received data.

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