CN117240401A

CN117240401A - Coding transmission method, decoding method and communication device

Info

Publication number: CN117240401A
Application number: CN202210631665.7A
Authority: CN
Inventors: 王中风; 刘璐; 陈洋洋; 宋苏文; 李苏; 徐自有; 周小军
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-06-06
Filing date: 2022-06-06
Publication date: 2023-12-15
Also published as: WO2023236838A1

Abstract

The embodiment of the application discloses an encoding transmission method, a decoding method and a communication device. The application can be applied to a high-speed wired communication system. The code transmission method comprises the following steps: according to information bits to be encoded, encoding to obtain a first bit stream, wherein the first bit stream comprises first information bits and first redundant bits, the first bit stream is used for decoding to obtain the information bits, and the first redundant bits are used for correcting a plurality of discontinuous first bits in the first information bits; and transmitting the first bit stream. The code transmission method adopts an interleaving scheme of cascade error correction codes. In the embodiment of the application, the first redundant bit is used for correcting a plurality of discontinuous first bits in the first information bit, so that burst continuous error codes can be dispersed into different code words, and the effects of reducing the number of error codes in each code word and improving the error correction success probability can be achieved.

Description

Coding transmission method, decoding method and communication device

Technical Field

The present application relates to the field of encoding, and in particular, to an encoding transmission method, a decoding method, and a communication device.

Background

In order to ensure extremely low bit error rate, the current wired digital communication system based on the high-speed Ethernet protocol adopts a forward error correction coding technology, namely redundant bits are added in the data bit stream before the data bit stream is modulated into signals to be transmitted by a transmitting end. Correspondingly, after the signal processing and demodulation are carried out on the received signal by the transmitting end, the limited transmission errors can be corrected back through calculation by adopting the corresponding forward error correction code decoding technology.

In a high-speed wired communication system, reed-Solomon (RS) codes of various code lengths are widely adopted for their excellent performance and suitability. For example, a forward error correction (forwarderror correction, FEC) scheme RS (544,514) is specified in the ethernet protocol in ieee802.3ck for 100G data rate links.

However, as the transmission rate of the wired communication system increases, the channel condition deteriorates and the transmission error probability increases, and at this time, the RS (544,514) having a limited coding gain has failed to meet the performance requirements. In order to meet the requirements of the bit error rate of the system, a coding scheme with stronger error correction capability needs to be used. The simplest way is to increase the code length to improve the performance of a single coding mode on the premise of determining the code rate. However, as the code length increases, the corresponding complexity increases, resulting in more hardware resource consumption. Therefore, among the numerous FEC schemes, consideration needs to be given in aspects of performance, complexity, delay, etc. in order to select a suitable candidate scheme.

Cascade coding with stronger error correction capability becomes an alternative FEC scheme of the next generation high-speed wired communication system due to the advantages of both performance and complexity. Therefore, it is necessary to study a concatenated coding scheme having a greater error correction capability.

Disclosure of Invention

The embodiment of the application discloses a coding transmission method, a decoding method and a communication device, which can reduce the number of error codes in each codeword by dispersing burst continuous error codes into different codewords, thereby improving the error correction success probability.

In a first aspect, an embodiment of the present application provides a coding transmission method, including: according to information bits to be encoded, encoding to obtain a first bit stream, wherein the first bit stream comprises first information bits and first redundant bits, the first bit stream is used for decoding to obtain the information bits, and the first redundant bits are used for correcting a plurality of discontinuous first bits in the first information bits; and transmitting the first bit stream.

In the embodiment of the application, the first redundant bit is used for correcting a plurality of discontinuous first bits in the first information bit, so that burst continuous error codes can be dispersed into different code words, and the effects of reducing the number of error codes in each code word and improving the error correction success probability can be achieved.

In one possible implementation, the first information bit includes a first symbol block, the first symbol block includes an mth encoded symbol in a first codeword and an mth encoded symbol in a second codeword, the plurality of first bits includes all or part of bits in the mth encoded symbol in the first codeword, and no encoded symbol in the second codeword, the first codeword and the second codeword are obtained by encoding the information bit, and m is an integer greater than 0. The code symbols not included in the second codeword may be any bits in the code symbols not included in the second codeword. Or, any bits in the second codeword are not included.

In this implementation, the plurality of first bits includes all or part of the bits in the mth encoded symbol in the first codeword and does not include the encoded symbol in the second codeword; thus, the continuous error codes of the burst can be dispersed into different code words, and the effect of reducing the number of the error codes in each code word and improving the error correction success probability can be achieved.

In one possible implementation, the plurality of first bits includes one bit or a non-contiguous plurality of bits in an mth encoded symbol of the first codeword.

In this implementation, the plurality of first bits includes one bit or a non-contiguous plurality of bits in an mth encoded symbol of the first codeword, but not all bits in the first codeword; the continuous error codes of the burst can be dispersed into different code words, so that the number of the error codes in each code word can be reduced.

In one possible implementation, the plurality of first bits does not include consecutive bits in any codeword encoded by the information bits.

In this implementation, consecutive errors of a burst may be dispersed among different codewords, so as to reduce the number of errors in each codeword.

In one possible implementation manner, the first information bit further includes a second symbol block, where the second symbol block includes an nth encoded symbol in the first codeword and an nth encoded symbol in the second codeword, the encoded symbols in the second symbol block are sequentially an nth encoded symbol in a K-th codeword to an nth encoded symbol in the first codeword, the encoded symbols in the first symbol block are sequentially an mth encoded symbol in the first codeword to an mth encoded symbol in the K-th codeword, and n is an integer greater than 0 and not equal to m, and the K-th codeword to the first codeword are obtained by encoding the information bit, and K is an integer greater than 1.

In this implementation, the ordering of the encoded symbols in the second symbol block is different from the ordering of the encoded symbols in the first codeword, which may increase the probability of dispersing burst errors into different codewords.

In one possible implementation manner, the first information bit includes a plurality of symbol blocks, the plurality of symbol blocks includes a first symbol block and a second symbol block, the first symbol block includes an mth encoded symbol in a first codeword and an mth encoded symbol in a second codeword, the second symbol block includes an nth encoded symbol in the first codeword and an nth encoded symbol in the second codeword, the first redundancy bit is used for correcting any one of a plurality of bit sequences obtained by arranging the plurality of symbol blocks in a matrix, the first codeword and the second codeword are obtained by encoding the information bit, and m and n are integers greater than 0, and are different from each other.

In this implementation manner, the first redundancy bits are used to correct any one of a plurality of bit sequences obtained by arranging a plurality of symbol blocks in a matrix manner, so that burst continuous error codes can be dispersed into different code words, and the number of error codes in each code word can be reduced.

In one possible implementation manner, the encoding to obtain the first bit stream according to the information bits to be encoded includes: performing outer code coding on the information bits to obtain a plurality of outer code words; interleaving the plurality of outer code words by taking coding symbols as units to obtain a plurality of symbol blocks, wherein the plurality of symbol blocks comprise a first symbol block and a second symbol block, the first symbol block comprises an mth coding symbol in a first code word and an mth coding symbol in a second code word, the second symbol block comprises an nth coding symbol in the first code word and an nth coding symbol in the second code word, the m and the n are integers larger than 0, and the m is different from the n; arranging the plurality of symbol blocks into a matrix in columns; performing inner code coding on each row in the matrix to obtain a plurality of groups of redundant bits, wherein the plurality of groups of redundant bits comprise the first redundant bits; and processing the first bit stream according to the plurality of symbol blocks and the plurality of groups of redundant bits.

In this implementation, a plurality of symbol blocks are arranged in columns into a matrix; and performing inner code coding on each row in the matrix to obtain a plurality of groups of redundant bits. When burst error occurs in the first bit stream in the transmission process, the error correction probability of the code word can be improved.

In one possible implementation, the arranging the plurality of symbol blocks in columns into a matrix includes: arranging the plurality of symbol blocks into the matrix with P bits in each row according to columns, wherein P is equal to the product of an inner code length to be adopted for inner code coding and an inner code symbol length, m bits in each coding symbol in the first symbol block are arranged into t columns, t is divided by m, and m, P and t are integers larger than 0.

In this implementation, a plurality of symbol blocks are arranged in columns into a matrix comprising P bits per row, so that each row of the matrix is inner coded.

In one possible implementation, each encoded symbol in the symbol blocks of the odd columns in the matrix is arranged normally, and each encoded symbol in the symbol blocks of the even columns in the matrix is arranged inversely; alternatively, each code symbol in the symbol blocks of even columns in the matrix is normally arranged, and each code symbol in the symbol blocks of odd columns in the matrix is inversely arranged.

In this implementation, the continuity of the information bits for each row may be made weaker in order to maximize the dispersion of the information bits into different inner codes.

In one possible implementation manner, the encoding to obtain the first bit stream according to the information bits to be encoded includes: performing outer code encoding on the first bit stream to obtain a plurality of outer code words; interleaving the plurality of outer code words by taking coding symbols as units to obtain a plurality of symbol blocks, wherein the plurality of symbol blocks comprise a first symbol block and a second symbol block, the first symbol block comprises an mth coding symbol in a first code word and an mth coding symbol in a second code word, the second symbol block comprises an nth coding symbol in the first code word and an nth coding symbol in the second code word, the m and the n are integers larger than 0, and the m is different from the n; arranging the plurality of symbol blocks into a matrix in rows; performing inner code coding on each column in the matrix to obtain a plurality of groups of redundant bits, wherein the plurality of groups of redundant bits comprise the first redundant bits; and processing the first bit stream according to the plurality of symbol blocks and the plurality of groups of redundant bits.

In this implementation, a plurality of symbol blocks are arranged in rows into a matrix; and performing inner code coding on each column in the matrix to obtain a plurality of groups of redundant bits. When burst error occurs in the first bit stream in the transmission process, the error correction probability of the code word can be improved.

In one possible implementation, the arranging the plurality of symbol blocks in rows into a matrix includes: arranging the plurality of symbol blocks into the matrix with P bits in each column according to rows, wherein P is equal to the product of an inner code length to be adopted for inner code coding and an inner code symbol length, m bits in each coding symbol in the first symbol block are arranged into t rows, t is divided by m, and m, P and t are integers larger than 0.

In this implementation, a plurality of symbol blocks are arranged in rows into a matrix comprising P bits per column, so that each column of the matrix is inner coded.

In one possible implementation, each encoded symbol in the symbol blocks of the odd rows in the matrix is arranged normally, and each encoded symbol in the symbol blocks of the even rows in the matrix is arranged in reverse; alternatively, each of the encoded symbols in the symbol blocks of the even rows in the matrix is normally arranged, and each of the encoded symbols in the symbol blocks of the odd rows in the matrix is inversely arranged.

In this implementation, the continuity of the information bits per column may be made weaker.

In a second aspect, the present application provides a method for decoding and transmitting, the method comprising: a receiving end receives a second bit stream, wherein the second bit stream is a bit stream which is received by the receiving end through channel transmission of a first bit stream sent by a sending end, and comprises second information bits and second redundant bits, and the second redundant bits are used for correcting a plurality of discontinuous second bits in the second information bits; and decoding to obtain information bits according to the second bit stream.

In the embodiment of the application, the second redundant bit is used for correcting a plurality of discontinuous second bits in the second information bits, so that burst continuous error codes can be dispersed into different code words, and the effects of reducing the number of error codes in each code word and improving the error correction success probability can be achieved.

In one possible implementation, the second information bits include a first symbol block including an mth encoded symbol in a first codeword and an mth encoded symbol in a second codeword, the plurality of second bits including all or part of the bits in the mth encoded symbol in the first codeword and not including the encoded symbols in the second codeword, the m being an integer greater than 0. The code symbols not included in the second codeword may be any bits in the code symbols not included in the second codeword. Or, any bits in the second codeword are not included.

In this implementation, the plurality of second bits includes all or part of the bits in the mth encoded symbol in the first codeword and does not include the encoded symbol in the second codeword; therefore, the burst continuous error codes can be dispersed into different code words, and the effects of reducing the number of error codes in each code word and improving the error correction success probability can be achieved.

In one possible implementation, the plurality of second bits includes one bit or a discontinuous plurality of bits in an mth encoded symbol of the first codeword.

In this implementation, the plurality of second bits includes one bit or a non-contiguous plurality of bits in an mth encoded symbol of the first codeword, but not all bits in the first codeword; the continuous error codes of the burst can be dispersed into different code words, so that the number of the error codes in each code word can be reduced.

In one possible implementation, the plurality of second bits does not include consecutive bits in any codeword encoded by the information bits.

In this implementation, consecutive errors of a burst may be dispersed among different codewords, enabling a reduction in the number of errors in each codeword.

In one possible implementation manner, the second information bit further includes a second symbol block, where the second symbol block includes an nth encoded symbol in the first codeword and an nth encoded symbol in the second codeword, the encoded symbols in the second symbol block are sequentially an nth encoded symbol in a K-th codeword to an nth encoded symbol in the first codeword, the encoded symbols in the first symbol block are sequentially an mth encoded symbol in the first codeword to an mth encoded symbol in the K-th codeword, and n is an integer greater than 0 and not equal to m, and the kth codeword to the first codeword are used for decoding to obtain the information bit, and K is an integer greater than 1.

In one possible implementation manner, the second information bits include a plurality of symbol blocks, the plurality of symbol blocks include a first symbol block and a second symbol block, the first symbol block includes an mth encoded symbol in a first codeword and an mth encoded symbol in a second codeword, the second symbol block includes an nth encoded symbol in the first codeword and an nth encoded symbol in the second codeword, the second redundancy bits are used for correcting any one of a plurality of bit sequences obtained by arranging the plurality of symbol blocks in a matrix, and the m and the n are integers greater than 0, and are different from the n.

In this implementation manner, the second redundancy bits are used to correct any one of the plurality of bit sequences obtained by arranging the plurality of symbol blocks in a matrix manner, so that the continuous error codes of the burst can be dispersed into different code words, and the number of error codes in each code word can be reduced.

In one possible implementation manner, the decoding, according to the second bit stream, to obtain information bits includes: the receiving end arranges the second bit stream into a matrix according to columns; the receiving end decodes the inner code of each row of the matrix and reserves the information bit of each row; the receiving end obtains the information bits according to the information bits of each row of the matrix.

In the implementation mode, the receiving end arranges the second bit stream into a matrix according to columns; each row of the matrix is inner code decoded and the information bits of each row are retained. When burst error occurs in the first bit stream in the transmission process, the error correction probability of the code word can be improved.

In one possible implementation manner, the decoding, according to the second bit stream, to obtain information bits includes: the receiving end arranges the second bit stream into a matrix according to rows; the receiving end decodes the inner code of each column of the matrix and reserves the information bit of each column; the receiving end obtains the information bits according to the information bits of each column of the matrix.

In the implementation manner, the receiving end arranges the second bit stream into a matrix according to rows; each column of the matrix is inner code decoded and the information bits of each column are retained. When burst error occurs in the first bit stream in the transmission process, the error correction probability of the code word can be improved.

In one possible implementation manner, the receiving end obtains the information bits according to the information bits of each column of the matrix, where the obtaining includes: de-interleaving the information bit matrix to obtain a plurality of outer code words; performing outer code decoding on each outer code word, and reserving outer code information bits of each outer code word; and outputting the outer code information bits of each outer code word according to the sequence of the words to obtain the information bits. The information bit matrix includes information bits for each column of the matrix. Alternatively, the information bit matrix comprises information bits for each row of the matrix.

In this implementation, the information bits may be decoded quickly.

In a third aspect, an embodiment of the present application provides a communication device having a function of implementing the behavior in the method embodiment of the first aspect described above. The communication device may be a communication apparatus, a component of a communication apparatus (e.g., a processor, a chip, or a system-on-a-chip), or a logic module or software that can implement all or part of the functions of the communication apparatus. The functions of the communication device may be implemented by hardware, or may be implemented by executing corresponding software by hardware, where the hardware or software includes one or more modules or units corresponding to the functions described above. In one possible implementation, the communication device includes an interface module and a processing module, where: the processing module is configured to encode according to information bits to be encoded to obtain a first bit stream, where the first bit stream includes first information bits and first redundancy bits, the first bit stream is used for decoding to obtain the information bits, and the first redundancy bits are used for correcting a plurality of discontinuous first bits in the first information bits; the interface module is configured to send the first bit stream.

In one possible implementation, the first information bit includes a first symbol block, the first symbol block includes an mth encoded symbol in a first codeword and an mth encoded symbol in a second codeword, the plurality of first bits includes all or part of bits in the mth encoded symbol in the first codeword, and no encoded symbol in the second codeword, the first codeword and the second codeword are obtained by encoding the information bit, and m is an integer greater than 0.

In a possible implementation manner, the processing module is specifically configured to perform outer code encoding on the information bits to obtain a plurality of outer code codewords; interleaving the plurality of outer code words by taking coding symbols as units to obtain a plurality of symbol blocks, wherein the plurality of symbol blocks comprise a first symbol block and a second symbol block, the first symbol block comprises an mth coding symbol in a first code word and an mth coding symbol in a second code word, the second symbol block comprises an nth coding symbol in the first code word and an nth coding symbol in the second code word, the m and the n are integers larger than 0, and the m is different from the n; arranging the plurality of symbol blocks into a matrix in columns; performing inner code coding on each row in the matrix to obtain a plurality of groups of redundant bits, wherein the plurality of groups of redundant bits comprise the first redundant bits; and processing the first bit stream according to the plurality of symbol blocks and the plurality of groups of redundant bits.

In a possible implementation manner, the processing module is specifically configured to arrange the plurality of symbol blocks into the matrix including P bits in each row according to a column, where P is equal to a product of an inner code length to be adopted for inner code encoding and an inner code symbol length, m bits in each encoded symbol in the first symbol block are arranged into t columns, t is divided by m, and m, P, and t are integers greater than 0.

In a possible implementation manner, the processing module is specifically configured to perform outer code encoding on the first bit stream to obtain a plurality of outer code codewords; interleaving the plurality of outer code words by taking coding symbols as units to obtain a plurality of symbol blocks, wherein the plurality of symbol blocks comprise a first symbol block and a second symbol block, the first symbol block comprises an mth coding symbol in a first code word and an mth coding symbol in a second code word, the second symbol block comprises an nth coding symbol in the first code word and an nth coding symbol in the second code word, the m and the n are integers larger than 0, and the m is different from the n; arranging the plurality of symbol blocks into a matrix in rows; performing inner code coding on each column in the matrix to obtain a plurality of groups of redundant bits, wherein the plurality of groups of redundant bits comprise the first redundant bits; and processing the first bit stream according to the plurality of symbol blocks and the plurality of groups of redundant bits.

In a possible implementation manner, the processing module is specifically configured to arrange the plurality of symbol blocks in rows into the matrix including P bits in each column, where P is equal to a product of an inner code length to be adopted for inner code encoding and an inner code symbol length, m bits in each encoded symbol in the first symbol block are arranged into t rows, t is divided by m, and m, P, and t are integers greater than 0.

Regarding the technical effects brought about by the various possible embodiments of the third aspect, reference may be made to the description of the technical effects of the first aspect or of the various possible embodiments of the first aspect.

In a fourth aspect, an embodiment of the present application provides a communication device having a function of implementing the behavior in the method embodiment of the second aspect described above. The communication device may be a communication apparatus, a component of a communication apparatus (e.g., a processor, a chip, or a system-on-a-chip), or a logic module or software that can implement all or part of the functions of the communication apparatus. The functions of the communication device may be implemented by hardware, or may be implemented by executing corresponding software by hardware, where the hardware or software includes one or more modules or units corresponding to the functions described above. In one possible implementation, the communication device includes an interface module and a processing module, where: the interface module is configured to receive a second bit stream, where the second bit stream is a bit stream that is received by a receiving end through a channel transmission by a first bit stream sent by a sending end, and the second bit stream includes second information bits and second redundancy bits, where the second redundancy bits are used to correct a discontinuous plurality of second bits in the second information bits; and the processing module is used for decoding to obtain information bits according to the second bit stream.

In one possible implementation, the second information bits include a first symbol block including an mth encoded symbol in a first codeword and an mth encoded symbol in a second codeword, the plurality of second bits including all or part of the bits in the mth encoded symbol in the first codeword and not including the encoded symbols in the second codeword, the m being an integer greater than 0.

In a possible implementation manner, the processing module is specifically configured to arrange the second bit streams into a matrix by columns; performing inner code decoding on each row of the matrix, and reserving information bits of each row; and obtaining the information bits according to the information bits of each row of the matrix.

In one possible implementation, the second bit streams are arranged in rows into a matrix; performing inner code decoding on each column of the matrix, and reserving information bits of each column; and obtaining the information bits according to the information bits of each column of the matrix.

Regarding the technical effects brought about by the various possible embodiments of the fourth aspect, reference may be made to the description of the technical effects of the second aspect or of the various possible embodiments of the second aspect.

In a fifth aspect, embodiments of the present application provide another communications apparatus comprising a processor coupled to a memory for storing a program or instructions that when executed by the processor cause the communications apparatus to perform the method shown in any possible implementation of the first aspect or the first aspect described above, or that when executed by the processor cause the communications apparatus to perform the method shown in any possible implementation of the second aspect or the second aspect described above.

In the embodiment of the present application, in the process of executing the above method, the process of sending information (or signals) in the above method may be understood as a process of outputting information based on instructions of a processor. In outputting the information, the processor outputs the information to the transceiver for transmission by the transceiver. This information, after being output by the processor, may also need to be subjected to other processing before reaching the transceiver. Similarly, when the processor receives input information, the transceiver receives the information and inputs it to the processor. Further, after the transceiver receives the information, the information may need to be further processed before being input to the processor.

Operations such as sending and/or receiving, etc., referred to by a processor, may be generally understood as processor-based instruction output if not specifically stated or if not contradicted by actual or inherent logic in the relevant description.

In implementation, the processor may be a processor dedicated to performing the methods, or may be a processor that executes computer instructions in a memory to perform the methods, such as a general-purpose processor. For example, the processor may also be configured to execute a program stored in the memory, which when executed, causes the communication device to perform the method as described above in the first aspect or any possible implementation of the first aspect.

In one possible implementation, the memory is located outside the communication device. In one possible implementation, the memory is located within the communication device.

In one possible implementation, the processor and the memory may also be integrated in one device, i.e. the processor and the memory may also be integrated together.

In one possible implementation, the communication device further comprises a transceiver for receiving signals or transmitting signals, etc.

In a sixth aspect, the present application provides another communication device comprising processing circuitry and interface circuitry for acquiring data or outputting data; the processing circuitry is to perform the corresponding method as shown in the first aspect or any of the possible implementations of the first aspect or to perform the corresponding method as shown in the second aspect or any of the possible implementations of the second aspect.

In a seventh aspect, the present application provides a computer readable storage medium having stored therein a computer program comprising program instructions which when executed cause a computer to perform a method as shown in the first aspect or any possible implementation of the first aspect, or which when executed cause a computer to perform a method as shown in the second aspect or any possible implementation of the second aspect.

In an eighth aspect, the application provides a computer program product comprising a computer program comprising program instructions which when executed cause a computer to perform a method as shown in the first aspect or any possible implementation of the first aspect, or which when executed cause a computer to perform a method as shown in the second aspect or any possible implementation of the second aspect.

In a ninth aspect, the present application provides a communication system comprising a communication device according to any possible implementation of the third aspect or any possible implementation of the fourth aspect.

Drawings

In order to more clearly describe the embodiments of the present application or the technical solutions in the background art, the following description will describe the drawings that are required to be used in the embodiments of the present application or the background art.

Fig. 1 shows an example of a concatenated FEC encoding flow;

fig. 2 shows an example of a concatenated FEC decoding flow;

FIG. 3 is a schematic diagram of an inner interleaving scheme according to an embodiment of the present application;

FIG. 4 is an example of a high-speed wired communication system provided by the present application;

fig. 5 is an example of a high-speed connection application scenario provided by the present application;

fig. 6 is a flowchart of a coding transmission method according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of an outer code word according to an embodiment of the present application;

fig. 8 is a schematic diagram of an outer code symbol interleaving process according to the present application;

FIG. 9 is an example of a matrix of symbol blocks arranged in columns provided by an embodiment of the present application;

FIG. 10 is a schematic diagram showing a comparison of a normally arranged symbol block and an inverted symbol block according to the present application;

FIG. 11 is an example of another matrix of symbol blocks arranged in columns provided by an embodiment of the present application;

FIG. 12 is an example of a matrix of symbol blocks arranged in columns provided by an embodiment of the present application;

FIG. 13 is a schematic diagram of inner code encoding for each row of a matrix according to an embodiment of the present application;

FIG. 14 is an example of a bit stream provided by the present application;

fig. 15 is a flowchart of another code transmission method according to an embodiment of the present application;

fig. 16 is a flowchart of another code transmission method according to an embodiment of the present application;

fig. 17 is a codeword structure of RS (544,514) according to an embodiment of the present application;

fig. 18 is an example of coding symbol interleaving for two RS (544,514) codewords according to an embodiment of the present application;

FIG. 19 is an example of another matrix of symbol blocks arranged in columns provided by the present application;

FIG. 20 is a codeword structure of a BCH (144,136) provided by the present application;

fig. 21 is an example of a matrix after inner code encoding according to an embodiment of the present application;

FIG. 22 is an example of a first bit stream provided by an embodiment of the present application;

FIG. 23 is a flowchart of a decoding method according to an embodiment of the present application;

FIG. 24 is a flowchart of another decoding method according to an embodiment of the present application;

fig. 25 is a schematic structural diagram of a communication device 2500 according to an embodiment of the present application;

fig. 26 is a schematic structural diagram of another communication device 260 according to an embodiment of the present application;

fig. 27 is a schematic structural diagram of another communication device 270 according to an embodiment of the present application.

Detailed Description

The terms first and second and the like in the description, the claims and the drawings of the present application are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprising," "including," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion. Such as a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to the list of steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In the present application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary," "by way of example," or "such as" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "by way of example," or "such as" is intended to present related concepts in a concrete fashion.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

The terminology used in the following embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates to the contrary. It should also be understood that the term "and/or" as used in this disclosure refers to and encompasses any or all possible combinations of one or more of the listed items. For example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The term "plurality" as used in the present application means two or more.

To facilitate understanding of the aspects of the present application, concepts or terms related to codec in the present application will be first described.

1. Forward error correction (forwarderror correction, FEC) codes

Forward error correction codes: forward error correction codes are a technique for controlling transmission errors in unidirectional communication systems. In a unidirectional communication system, one of the two communication parties is fixed as a transmitting end, the other party is fixed as a receiving end, and information can only be transmitted in one direction, namely, the transmitting end transmits to the receiving end. By adding extra redundant information with the characteristics of the information itself into the data information and decoding the data information according to a corresponding algorithm at a receiving end, the purpose of correcting a certain amount of information transmission errors can be achieved, and the bit error rate is reduced. Or, the code word of the forward error correction code (FEC) is a code pattern with a certain error correction capability, and after decoding at the receiving end, it can not only find errors, but also determine the position of the error code element, and automatically correct errors.

In describing a forward error correction code, the following terminology will generally be used:

1) Coded symbol (symbol) and symbol length (m): the code symbols are the smallest units of an error correction code, and for different error correction codes each code symbol may consist of one or more bits, the number of bits being referred to as the symbol length.

2) Codeword (codewiord) and code length (n): a codeword refers to a complete error correction code, a codeword consisting of a number of encoded symbols, the number of encoded symbols being referred to as the code length of the error correction code.

3) Information bits (information) and information bit length (k): information bits refer to the code symbols carrying data in one codeword, the number of which is referred to as the information bit length.

4) Redundancy bit (or parity bit): the redundant bit refers to an additionally added code symbol in one code word, and the number of the code symbol of the redundant bit is the length of the code word minus the length of the information bit, namely n-k. In the present application, the redundancy bits and the check bits can be replaced with each other.

5) Error correction capability (t): i.e. the upper limit of the number of erroneous code symbols in one codeword that can be corrected.

RS (n, k, t): representing Reed-Solomon (RS) codes (or RS codes) with a code length of n, an information bit length of k, and an error correction capability of t. The RS code is a forward error correction code. For the RS (544,514,15) error correction code, each encoded symbol is 10 bits, its code length is 544 symbols (i.e., 5440 bits), the information bits are 514 symbols (i.e., 5140 bits), and the redundancy bits are 30 symbols (i.e., 300 bits). When errors occur in the transmission of 15 or less symbols, the errors can be corrected according to the corresponding decoding method.

BCH (n, k, t): represents a BCH code (or BCH code) with a code length n, an information bit length k, and an error correction capability t. The BCH code (BCH code) is known as Bose-Chaudhuri-Hocquenghem codes. The BCH code is a cyclic code capable of correcting multi-bit errors. For such error correction codes of BCH (144,136,1), each code symbol is 1 bit, its code length is 144 bits, the information bits are 136 bits, and the redundant bits are 8 bits. When 1 bit error occurs in one codeword, the error can be corrected according to the corresponding decoding method.

Burst error code: when the wired communication system performs data transmission, a plurality of continuous error codes are generated, namely when the current modulated symbol has errors, the next symbol also has errors.

2. Inner code, outer code, concatenated code

In the application, the whole of coding, channel and decoding is regarded as a generalized channel. This channel also has errors and can therefore be further error-corrected coded. For systems with multiple encodings, each level of encoding is considered an overall encoding, known as a concatenated code.

When two codes are concatenated to form a concatenated code, the code in the generalized channel is referred to as an inner code, and the channel code using the generalized channel as a channel is referred to as an outer code. Since the decoding result of the inner code inevitably generates burst errors, an interleaver is generally arranged between the inner code and the outer code. Typically, when constructing concatenated codes, the inner and outer codes select complementary patterns.

Fig. 1 shows an example of a concatenated FEC encoding flow. As shown in fig. 1, the concatenated FEC encoding flow includes: outer code encoding, inner interleaving, inner code encoding, outer interleaving. Arrows in fig. 1 indicate data flow. For example, the cascade encoder at the transmitting end selects the encoding modes of the outer code and the inner code; the information bit stream (or called data bit stream) is encoded by an external code, the encoded information bit stream is subjected to internal interleaving, then the data bit stream after internal interleaving is subjected to internal code encoding, and after the internal code encoding is finished, external interleaving can be performed again. Fig. 2 shows an example of a concatenated FEC decoding flow. As shown in fig. 2, the concatenated FEC decoding flow includes: outer interleaving is removed, inner code is decoded, inner interleaving is removed, and outer code is decoded. Arrows in fig. 2 indicate data flow. For example, a cascade encoder at the receiving end performs de-interleaving on the received bit stream; performing inner code decoding on the bit stream after the outer interleaving; performing de-inner interleaving on the bit stream after the decoding of the inner code; and after the inner interleaving is completed, outer code decoding is performed.

3. Interleaving

Interleaving is in fact a technique employed for data processing in a communication system. An interleaver is essentially a device that achieves the maximum change of the information structure without changing the information content. Conventionally, it is the maximum dispersion of errors in the burst generation set during channel transmission.

On a variable parameter channel such as terrestrial mobile communication, bit errors often occur in strings. This is because a deep fade dip that is long in duration affects a successive series of bits. However, channel coding is only effective in detecting and correcting single errors and error strings that are not too long. To solve this problem, it is desirable to find a way to spread out consecutive bits in a message, i.e. consecutive bits in a message are sent in a non-consecutive manner. Thus, even if a string error occurs during transmission, the error becomes single (or short in length) when the message is recovered as a continuous bit string, and the error is corrected by the channel coding error correction function to recover the original message. This method is an interleaving technique.

An inner interleaving scheme for concatenated coding is a multi-frame interleaving scheme based on outer code symbols. Fig. 3 is a schematic diagram of an inner interleaving scheme according to an embodiment of the present application. As shown in fig. 3, codeword a and codeword B are two codewords of the outer code, A1 to A5 represent the first 5 encoded symbols of codeword a, B1 to B5 represent the first 5 encoded symbols of codeword B, and all the encoded symbols of codeword a and codeword B are alternately arranged in the interleaving process to obtain A1B1A2B2A3B3 …. After the inner interleaving is completed, the interleaved bit stream (A1B 1A2B2A3B3 …) may be inner-code encoded as an information bit stream.

Referring to the inner code interleaving scheme shown in fig. 3, when burst errors are generated, that is, a plurality of continuous errors occur in the same inner code codeword, the number of errors in the same inner code codeword is very probable to exceed the error correction capability of the inner code, resulting in error correction failure of the inner code. In extreme cases, even the inner code is caused to error-correct, more errors are generated, and the error correction effect of the outer code and the whole cascade code is further affected. For the problem that the error correction performance of the existing cascade coding scheme is poor under the condition that the burst error code exceeds the error correction capability of the internal code, the application provides a coding and decoding scheme with stronger error correction capability of the internal code.

The coding and decoding scheme provided by the application can be applied to a high-speed wired communication system and any transmission system (or scene) needing coding and decoding, and the application is not limited.

The embodiments of the present application will be mainly described by way of example in the deployment of high-speed wired communication systems, such as those employing the ieee802.3ck standard. Those skilled in the art will readily appreciate that the various aspects of the present application are amenable to extension to other networks employing a variety of standards or protocols. Fig. 4 is an example of a high-speed wired communication system provided by the present application. As shown in fig. 4, the flow executed by the transmitting end includes: FEC coding, modulation and signal processing. For example, the flow executed by the sender is as follows: FEC encoding the data bit stream to obtain an encoded data bit stream; modulating and signal processing are carried out on the coded data bit stream to obtain a signal to be transmitted; and transmitting the signal to be transmitted through a channel. Referring to fig. 4, a transmitting end adopts a forward error correction coding technique to add redundancy bits to a data bit stream before modulating the data bit stream into a signal for transmission. As shown in fig. 4, the process executed by the receiving end includes: signal processing, demodulation and FEC decoding. For example, the flow executed by the receiving end is as follows: signal processing and demodulation are carried out on the received signals, and a data bit stream to be decoded is obtained; and performing FEC decoding on the data bit stream to be decoded to obtain the data bit stream. Referring to fig. 4, after signal processing and demodulation are performed on the received signal, the transmitting end adopts a forward error correction code decoding technology to correct limited transmission errors through calculation.

The coding and decoding scheme provided by the application can be applied to all high-speed serial interfaces in the field of information communication technology (information and communications technology, ICT), including network equipment interfaces and computer high-speed interfaces. In the present application, the network device interface refers to various interfaces of the network device. The network device interface may be an ethernet interface, conforming to the IEEE802.3 standard. In the application, the computer high-speed interface mainly refers to a serial high-speed interface, and comprises an interface for communication between chips, an interface between the chips and an optical module, and the like. Fig. 5 is an example of a high-speed connection application scenario provided by the present application. In fig. 5, a black rectangle indicates a backplane interface, a rectangle filled with oblique lines and a rectangle filled with vertical lines indicates a panel interface, other rectangles (except chips) indicate interfaces in a board, serial-to-serial converters (SerDes) chips are disposed in interface 1 indicated by 501, serDes chips are disposed in interface 2 indicated by 502, and the SerDes chips in interface 1 and the chips in interface 2 can adopt the coding and decoding scheme provided by the present application. It can be understood that any interface with a SerDes chip can adopt the codec scheme provided by the present application, and not only interface 1 and interface 2 in fig. 5 are limited. The SerDes technology is a mainstream serial communication technology of time division multiplexing (time division multiplexing, TDM), point-to-point (P2P). Specifically, at the transmitting end, the multiple low-speed parallel signals are converted into high-speed serial signals, and finally, at the receiving end, the high-speed serial signals are converted into low-speed parallel signals again through a transmission medium (such as an optical cable or a copper wire). In the high-speed connection application scene, the transmitting end can modulate and encode the signals and then transmit the signals to the receiving end through a wired channel, and the receiving end can perform corresponding channel equalization, demodulation and decoding to obtain data information and/or control information. The coding and decoding scheme provided by the application can be applied to data transmission between two interfaces of the same equipment and can also be applied to data transmission between different equipment.

In the case where burst errors exceed the error correction capability of the inner code, the error correction performance of the existing concatenated coding scheme is poor. The reason why the error correction performance of the existing cascade coding scheme is poor is found by research that when the cascade coding is used for dealing with burst errors, the errors after decoding the inner codes are not random. The technical problems solved by the coding and decoding scheme provided by the application are as follows: when the cascade coding is used for dealing with burst error codes, the error codes after decoding the internal codes are not random. The coding and decoding scheme provided by the application is mainly characterized in that the maximized scattered burst error codes are transmitted to different inner code words in a matrix interleaving mode; secondly, the non-random error codes after the internal code error correction are dispersed into a plurality of external code words in a symbol interleaving mode through the plurality of external code words. The technical effects achieved by the coding and decoding scheme provided by the application are as follows: the burst error code and the non-random error code are successfully dispersed into different internal and external codes and internal code words, so that the error correction success probability of a single code word is improved, and the error rate of the whole system is reduced.

The coding and decoding scheme provided by the application adopts a two-dimensional matrix interleaving mode. In the encoding and decoding scheme, the two-dimensional matrix interleaving mode provided by the application is adopted, and the operation executed by the transmitting end comprises the following steps: 1) After the outer code is coded, interleaving a plurality of outer code words by taking outer code coding symbols as units, and arranging the interleaved symbol sequences into a matrix according to columns; 2) Performing inner code coding on each row in the matrix, and adding redundant bits generated by the inner code coding into new columns of the matrix, namely, the redundant bits are parallel to information bits; 3) The bits are read column by column for subsequent processing. Correspondingly, by adopting the two-dimensional matrix interleaving mode provided by the application in the encoding and decoding scheme, the operation executed by the receiving end comprises the following steps: 1) The bit streams subjected to signal processing and demodulation are arranged in a matrix form in a sequence, which means the order of the demodulated bits according to the received signal. 2) Performing inner code decoding on each row; after the decoding of the inner code is finished, the redundant bit of the inner code is removed, and only the interleaved outer code word is reserved; 3) And de-interleaving the interleaved code words by taking the outer code symbols as units to obtain a plurality of corresponding outer code words, and respectively performing outer code decoding. Or, in the encoding and decoding scheme, the two-dimensional matrix interleaving mode provided by the application is adopted, and the operation executed by the transmitting end comprises the following steps: 1) After the outer code is coded, interleaving a plurality of outer code words by taking outer code coding symbols as units, and arranging the interleaved symbol sequences into a matrix according to rows; 2) Performing inner code coding on each column in the matrix, and adding redundant bits generated by the inner code coding as new rows of the matrix, namely, being parallel to information bits; 3) The bits are read row by row for subsequent processing. Correspondingly, by adopting the two-dimensional matrix interleaving mode provided by the application in the encoding and decoding scheme, the operation executed by the receiving end comprises the following steps: 1) The bit streams subjected to signal processing and demodulation are arranged in a matrix form in a row in order, which means the order of the demodulated bits of the received signal. 2) Performing inner code decoding on each column; after the decoding of the inner code is finished, the redundant bit of the inner code is removed, and only the interleaved outer code word is reserved; 3) And de-interleaving the interleaved code words by taking the outer code symbols as units to obtain a plurality of corresponding outer code words, and respectively performing outer code decoding.

The following describes the codec scheme provided by the present application with reference to the accompanying drawings.

Fig. 6 is a flowchart of a coding transmission method according to an embodiment of the present application. As shown in fig. 6, the method includes:

601. and the transmitting end performs outer code encoding on the information bits to be encoded to obtain a plurality of outer code words.

The transmitting end can be any device needing coding transmission, such as network device, computer device, terminal device, etc., especially the device adopting FEC technology for coding. For example, the transmitting end is a computer, a desktop computer, a notebook computer, a modem, a router, a bridge, a transmission receiving point (transmission reception point, TRP), or the like. In the present application, operations or processes performed by the transmitting end (for example, operations or processes performed by the transmitting end in the method flow in fig. 6) may be performed by the transmitting end, or may be performed by a chip or a circuit system provided in the transmitting end. The circuitry may be, for example, an integrated circuit, a logic circuit. The chip may be, for example, a system on a chip (SoC) chip, a baseband modem (modem) chip, a SerDes chip, etc., and is not limited herein. The transmitting end will be described below as an example.

Exemplary, each code symbol of the outer code employed by the transmitting end includes m bits, and the code length is n ₁ A symbol, an information bit length of k ₁ And code symbols. m is an integer greater than 0, n ₁ K is an integer greater than 1 ₁ Is an integer greater than 0. Transmitting end pair k ₁ Each code symbol (i.e., information symbol) is calculated as the corresponding (n ₁ -k ₁ ) Multiple redundancy symbol additionTo the k ₁ After encoding the symbols, the codeword structure is shown in fig. 7. Fig. 7 is a schematic structural diagram of an outer code codeword according to an embodiment of the present application. As shown in fig. 7, an outer code codeword (codeword) includes an information (information) bit portion and a redundancy (redundancy) bit portion, S ₁ 、S ₂ 、…、S _k1 Represents k ₁ Code symbols S _(k1+1) 、S _(k1+2) 、…、S _n1 Representing according to the k ₁ Calculated from the code symbols (n ₁ -k ₁ ) Redundant symbols S _k1 Includes b ₁ 、b ₂ 、…、b _m And a total of m bits. FIG. 7 shows only S _k1 Including m bits. It should be appreciated that each encoded symbol in the outer code comprises m bits. The application does not limit the external code adopted by the transmitting end, namely m and n ₁ 、k ₁ Is calculated by calculating k ₁ And the mode of redundant symbols corresponding to the coded symbols. Alternatively, the transmitting end may perform outer code encoding on the information bits to be encoded in any manner, so as to obtain a plurality of outer code codewords.

602. The transmitting end interweaves the plurality of outer code words according to the outer code coding symbols to obtain a plurality of symbol blocks.

In the present application, the outer code coding symbol refers to a coding symbol of an outer code codeword, that is, a coding symbol included in the outer code codeword. The plurality of symbol blocks obtained by interleaving the plurality of outer code words by the transmitting end according to the outer code symbols can be called as interleaved outer code symbols. One possible implementation of step 602 is described below using the example of interleaving x outer code words. Fig. 8 is a schematic diagram of an outer code symbol interleaving process according to the present application. Referring to fig. 8, the transmitting end transmits codeword 1 (codeword ₁ ) Codeword 2 (codeword) ₂ ) …, codeword x (codeword) _x ) Interleaving is performed on the outer code encoded symbols to obtain a symbol block 1 (part ₁ ) To symbol block n1 (part) _n1 ). As shown in fig. 8, x outer code words (i.e., codeword 1 to codeword x) are interleaved to obtain n1 symbol blocks, i.e., part ₁ To part _n1 Each outer code word comprises n1 code symbols, each symbol block (part) comprises x code symbols and the x code symbols are located in xThe same position in the outer code codeword; the outer code codeword 1 comprises the encoded symbols S _1,1 To S _1,n1 The outer code word 2 comprises encoded symbols S _2,1 To S _2,n1 The outer code codeword x comprises the encoded symbols S _x,1 To S _x,n1 Symbol block 1 (i.e. part ₁ ) Comprising a first encoded symbol of each of the x outer code words, S _1,1 For the first code symbol in outer code word 1, S _2,1 For the first code symbol in outer code word 2, S _x,1 For the first encoded symbol in outer code codeword x, symbol block n1 (i.e., part _n1 ) N1 st code symbol comprising each of x outer code words, S _1,n1 For the n1 st code symbol in outer code word 1, S _2,n1 For the n1 st code symbol in outer code word 2, S _x,n1 The n1 st code symbol in the outer code word x. In the present application, a symbol block may comprise coded symbols at the same position in a plurality of outer code words. The symbol blocks in the application are interleaved by a plurality of outer code words. Fig. 8 is merely an example of one type of outer code symbol interleaving and not all examples. It should be understood that the transmitting end may interleave the plurality of outer code words according to the outer code symbols in any manner, which is not limited by the present application. The interleaving by outer code symbols means that the interleaving is performed in units of code symbols. Or, when the transmitting end interleaves the plurality of outer code words according to the outer code symbols, each code symbol in each outer code word is taken as a whole.

603. The transmitting end arranges a plurality of symbol blocks into a matrix by columns.

When the transmitting end arranges a plurality of symbol blocks into a matrix according to columns, the number of columns occupied by each coding symbol in the symbol blocks can be flexibly set. That is, when the transmitting end arranges a plurality of symbol blocks into a matrix according to columns, the number of columns occupied by each code symbol in the symbol block can be set according to actual requirements.

Fig. 9 is an example of a matrix formed by a plurality of symbol blocks arranged in columns, according to an embodiment of the present application. In fig. 9, each part represents a symbol block, symbol block 1 (i.e., part ₁ ) Comprising a first encoded symbol of each of a plurality of outer code words, i.eS _1,1 、S _2,1 、…、S _x,1 Code symbol S _1,1 Arranged in t columns (t bits), i.e. code symbols S _1,1 Arranged in t columnsA matrix of rows. The matrix shown in FIG. 9 includes two symbol blocks, one of which is a normally arranged symbol block, e.g., part ₁ Representing a normally arranged symbol block 1, the other being an inversely arranged symbol block, e.g. part ^T _n1 Representing the block of inverted symbols n1. Fig. 10 is a schematic diagram showing a comparison of a normally arranged symbol block and an inverted symbol block according to the present application. Referring to fig. 10, a forward arranged symbol block j (i.e., part _j ) The code symbols in the code sequence are S in sequence according to the column order _1,j 、S _2,j 、…、S _x,j The inversely arranged symbol blocks j (i.e. part _j ) The code symbols in the code sequence are S in sequence according to the column order _x,j 、S _x-1,j 、…、S _1,j . In the present application, a normally arranged symbol block means that each encoded symbol in the symbol block is normally arranged, and a reversely arranged symbol block means that each encoded symbol in the symbol block is reversely arranged. It will be appreciated that the meaning and part of each part in the matrix shown in FIG. 9 ₁ Or part ^T n1 has a similar meaning and will not be described in detail herein. Fig. 9 shows only symbol block 1 (i.e., part ₁ ) S of (3) _1,1 The arrangement of bits involved. It will be appreciated that each encoded symbol of the above plurality of symbol blocks is arranged in a t column +.>A matrix of rows.

m needs to be divisible by t (e.g., t may take 1,2,5 when m=10), i.e., m divides t by t. the value of t (i.e. the number of columns of each code symbol arrangement) can be flexibly configured according to the signal modulation method and the passive link characteristics. the smaller the value of t, the more consecutive burst errors will be dispersed among more inner code words, and the smaller the number of errors per inner code word will be on average, which will be easier to decode successfully. But taking into account the modulation scheme, e.g. fourth order pulse amplitude modulation (pulse amplitude modulation, PAM-4) is modulated into a pulse amplitude modulation (pulse amplitude modulation, PAM) symbol for every two bits, and the PAM modulation mode is characterized in that two bits in a PAM symbol have a high probability of error of only one bit, so that the value of t can be selected to be 2 at this time, and the decoding performance of the inner code is not affected. If the modulation scheme uses non-return-to-zero (NRZ) (also called PAM-2), each bit is modulated into one PAM symbol, then the optimal value of t is 1. In the application, the code length of the internal code adopted by the transmitting end for internal code coding is k ₂ Symbol length m ₂ . Usually the inner code length k ₂ (i.e., code length of inner code) and inner code symbol length m ₂ The product of (i.e., the symbol length of the inner code) may also be divided by t (for k) ₂ m ₂ Not divisible by t, as will be described separately below). In the present application, k ₂ m ₂ Representation (k) ₂ *m ₂ ). Fig. 9 shows the inner code length k ₂ And inner code symbol length m ₂ A matrix in which a plurality of symbol blocks are arranged in columns when the product of (a) is divisible by t. The transmitting end needs to perform inner code encoding on each row of the matrix, so each row of the matrix needs to have k ₂ m ₂ And a number of bits. Because each row needs to have k ₂ m ₂ T bits per row of a symbol block, so that one row needs to have k ₂ m ₂ T symbol blocks. Together with n ₁ A block of symbols, so that one column in the matrix hasA block of symbols. It will be appreciated that the transmitting end can determine from the number of bits per row that a column of the matrix has +.>A block of symbols. That is, the transmitting end is based on k ₂ 、m ₂ N1, t, it can be determined that each row of the matrix needs to have k ₂ m ₂ T symbol blocks, each column is required to have +.>A block of symbols. The transmitting end can arrange a plurality of symbol blocks into a matrix according to the number of the symbol blocks required by each column of the matrix, so that the transmitting end can arrange a plurality of symbol blocks into each row according to the column and k ₂ m ₂ A matrix of bits.

In one possible implementation, the sender performs the following operations before performing step 603: inner code length k ₂ And inner code symbol length m ₂ Where the product of (2) is divisible by t, it is determined that each column of the matrix needs to haveA block of symbols. One possible implementation of step 603 is as follows: arranging the symbol blocks in columns with +.>A matrix of blocks of symbols, wherein each row of the matrix has k ₂ m ₂ And a number of bits.

In one possible implementation, each encoded symbol in the symbol blocks of the odd columns in the matrix is arranged normally, and each encoded symbol in the symbol blocks of the even columns in the matrix is arranged inversely; alternatively, the code symbols in the symbol blocks of even columns in the matrix are arranged normally, and the code symbols in the symbol blocks of odd columns in the matrix are arranged in reverse. In the application, the symbol blocks of each column in the matrix can be arranged normally; the symbol blocks of each column in the matrix can be arranged in reverse; the symbol blocks of the odd columns in the matrix can be normally arranged, and the symbol blocks of the even columns are reversely arranged; the symbol blocks of the odd columns in the matrix may be arranged in reverse, and the symbol blocks of the even columns may be arranged normally, which is not limited by the present application. In this implementation, the continuity of the information bits per row may be made weaker.

When k is ₂ m ₂ And when the matrix cannot be divided by t, the transmitting end needs to adjust the last column of the matrix. The last column here refers to the columns to which the symbol blocks correspond, rather than one column in the matrix. Let k be ₂ m ₂ =αt+β, where α and β are bothThe first (α×t) column of the matrix corresponds to the symbol blocks of the α column, i.e. each t columns corresponds to one column of symbol blocks, and the last β columns can be formed by splitting the remaining L symbol blocks. It should be noted that β does not necessarily have to be divisible by m. Fig. 11 is an example of another matrix provided by an embodiment of the present application, in which a plurality of symbol blocks are arranged in columns. The meaning of each parameter in the matrix shown in fig. 11 can be referred to as meaning of each parameter in the matrix shown in fig. 9. Referring to fig. 11, each row of the matrix has (k ₂ m ₂ ) The first (α×t) columns of the matrix correspond to the symbol blocks of the α columns, i.e. each t columns corresponds to one column of symbol blocks, and the last β columns are formed by splitting the remaining L symbol blocks (i.e. one column of symbol blocks). Assuming that a part (i.e., symbol block) has 20 bits, t=5, each part may be arranged in a matrix of 4 rows and 5 columns. Again assume k ₂ *m ₂ If β=3, the part of the last column has no way to arrange into 5 columns of bits, but only into 3 columns of bits. In this case the last few parts can only be arranged in 3 columns of bits, since 20 is not divisible by 3, so there will be 6 rows of complete 3 columns, with row 7 being only 2 bits. The remaining bit of the seventh line needs to be padded with the first bit of the next part. Fig. 12 is an example of a matrix in which symbol blocks are arranged in columns according to an embodiment of the present application. Referring to fig. 11 and 12, part ₁ Arranged in a matrix of 4 rows and 5 columns, part ^T _n1-1+1 The matrix arranged has 6 rows and 3 columns, the 7 th row has 2 bits only, and part ^T _n1-1+2 (i.e. part) ^T _n1-1+1 Part of (c) is filled with the first bit of the next part) ^T _n1-1+1 Line 7 of (2). The above assumption is that the last β column is formed by splitting the remaining L symbol blocks (less than one column of symbol blocks), and the transmitting end may be formed by splitting the remaining L symbol blocks in a similar manner to form the last β column (corresponding to one column of symbol blocks). The present application does not limit the manner in which the transmitting end forms the last β columns from the remaining L symbol blocks.

In one possible implementation, the sender performs the following operations before performing step 603: inner code length k ₂ And inner code symbol length m ₂ When the product of (2) is not divisible by t, determining that the matrix is divisible mostColumns other than the latter column are required to haveA block of symbols. One possible implementation of step 603 is as follows: the symbol blocks are arranged in each column +.>The symbol blocks are arranged, and the remaining L symbol blocks are split to form the last β columns (corresponding to one column of symbol blocks). L is less than->The manner in which the transmitting end splits the remaining L symbol blocks to form the last β columns can be seen in fig. 11 and fig. 12.

The transmitting end can flexibly configure the number of rows and columns of each outer code symbol arranged into a matrix according to different modulation modes, and the interleaving depth is maximized under the condition of not reducing the error correction capability of the inner code, so that the overall error rate of the system is reduced.

604. The transmitting end carries out internal code coding on each row of the matrix and arranges the redundant bits of the internal code beside the matrix.

Because the number of bits per row of the matrix is exactly the number of bits of the information bits of the inner code (k ₂ *m ₂ ) The transmitting end can encode each row of the matrix into an inner code word, and the redundancy bit corresponding to each inner code word is used as a new column of the matrix to be arranged beside the matrix. Fig. 13 is a schematic diagram of inner code encoding for each row of a matrix according to an embodiment of the present application. As shown in fig. 13, redundant (redundancy) bits added to each inner code word are arranged beside the matrix as newly added columns of the matrix, and each inner code has a redundancy bit of g=n ₂ -k ₂ )*m ₂ The matrix has i rows, each row corresponding to one inner code word, i.e. inner code word 1 (inner code word) ₁ ) Inner code word 2 (inner code word ₂ ) …, inner code codeword i (inner code word) _i ) Inner code codeword 1 is r _1,1 、r _1,2 、…、r _1,g Inner code word 2 is r _2,1 、r _2,2 、…、r _2,g The inner code codeword i is r _i,1 、r _i,2 、…、r _i,g . The meaning of each parameter in the matrix shown in fig. 13 can be referred to as meaning of each parameter in the matrix shown in fig. 9.

605. The transmitting end reads out the bits in the matrix according to the columns to obtain a first bit stream to be transmitted.

One possible implementation of step 605 is as follows: the transmitting end reads out the inner code information part in the matrix from top to bottom and from left to right according to the sequence of the inner code information part in the matrix by taking the symbol block as a unit according to the column, and restores the inner code information part into a bit stream; and for the inner code redundant part, directly reading out according to columns to obtain a first bit stream to be output. Referring to fig. 13, the inner code information part refers to a symbol block, i.e., part, in the matrix ₁ To part ^T _n1 The inner code redundant part refers to the redundant bit corresponding to the inner code word, namely the last g columns. Referring to fig. 13, for the inner code information part, the sending end reads out the inner code information part sequentially from top to bottom and from left to right according to columns and in the unit of symbol blocks, and may read out the inner code information part sequentially: part of the first column ₁ 、part ₂ 、…、part _j Part of the second column ^T _j+1 、part ^T _j+2 、…、part ^T _2j … …, part of last column ^T _n1-j+1 、part ^T _n1-j+2 、…、part ^T _n1 . Fig. 14 is an example of a bitstream provided by the present application. The bit stream shown in fig. 14 may be regarded as the first bit stream to be output obtained by the transmitting end performing step 605, and the meaning of each parameter in fig. 14 may refer to fig. 13 and fig. 9. Referring to fig. 14, the bitstream to be output includes two parts, the former part being information bits (hereinafter, first information bits) of an inner code (after interleaving a plurality of inner code codewords), and the latter part being redundancy bits added at the time of inner code encoding, including hereinafter, first redundancy bits.

In one possible implementation, steps 604 and 605 may be replaced with: performing inner code coding on each row in the matrix to obtain a plurality of groups of redundant bits, wherein any group of the plurality of groups of redundant bits is a first redundant bit; and processing the plurality of symbol blocks and the plurality of groups of redundant bits to obtain the first bit stream. It should be understood that, after obtaining the multiple sets of redundancy bits, the transmitting end may obtain the first bit stream shown in fig. 14 according to the multiple symbol blocks and the multiple sets of redundancy bits in multiple manners, which is not limited by the present application.

Steps 601 to 605 are steps for the transmitting end to encode according to the information bits to be encoded to obtain a first bit stream. The transmitting end may also encode the first bit stream according to the information bits to be encoded in other manners, which is not limited by the present application.

606. The transmitting end transmits a first bit stream.

The sending end sends the first bit stream may be: after modulating and signal processing the first bit stream, a signal obtained from the first bit stream is transmitted. In the present application, transmitting the first bit stream is actually transmitting a signal that modulates and signal-processes the first bit stream. Since modulation, signal processing of the bit stream to be transmitted is a common technical means in the art, it is not stated here. One possible implementation of step 606 is as follows: the transmitting end transmits the first bit stream to the receiving end through a wired channel. Correspondingly, the receiving end receives a second bit stream, and the second bit stream is a bit stream which is received by the receiving end through channel transmission of the first bit stream sent by the sending end. The second bit stream includes second information bits (corresponding to the first information bits) and second redundancy bits (corresponding to the first redundancy bits) for correcting a non-consecutive plurality of second bits of the second information bits. And the receiving end decodes the second bit stream to obtain information bits. The implementation manner of decoding the information bits by the receiving end according to the second bit stream is described in detail later. The receiving end receives the second bit stream, which is actually a signal transmitted by the receiving end after being transmitted by the channel.

The first bit stream includes first information bits and first redundancy bits. The first bit stream is used for decoding to obtain the information bits. The first redundancy bit is used for correcting a plurality of discontinuous first bits among the first information bits.

The first information bit may be the former part shown in fig. 14, the first redundancy bitWhich may be the latter part shown in fig. 14. As can be seen from a combination of fig. 13 and fig. 14, the former part shown in fig. 14 corresponds to the inner code information part (i.e., inner code codeword information bits) in fig. 13, the latter part shown in fig. 14 corresponds to the inner code redundancy part (i.e., redundancy) in fig. 13, and the redundancy bits corresponding to each row in the matrix shown in fig. 13 can be used for error correction of the information bits of this row. Each row in the matrix shown in fig. 13 includes bits that are non-contiguous (or discontinuous) in fig. 14. For example, the first row in FIG. 13 includes part ₁ T bits, part in the first encoded symbol of (a) ^T _j+1 T bits, …, part in the first encoded symbol of (a) ^T _n1-j+1 T bits in the first encoded symbol of (c). The information bits that the redundancy bits corresponding to each row in the matrix shown in fig. 13 can be used to correct this row can be understood as: the redundancy bits corresponding to each row in the matrix shown in fig. 13 may be used to correct a non-contiguous plurality of first bits of the first information bits. The first redundancy bits may comprise one or more sets of redundancy bits, each set of redundancy bits being inner code redundancy bits obtained by inner code encoding a row of the matrix. Alternatively, the first redundancy bit is used for obtaining one or more groups of redundancy bits at the receiving end. Let the first redundant bit be r as shown in FIG. 14 _1,1 、r _2,1 、…、r _i,1 、r _1,2 、r _2,2 、…、r _i,2 、r _1,g 、r _i,g For example, multiple sets of redundancy bits, e.g., r, can be derived from the first redundancy bit _1,1 、r _1,2 、…、r _1,g ，r _1,1 、r _1,2 、…、r _1,g Multiple bits available for the first row in the error correction matrix, i.e. part ₁ T bits, part in the first encoded symbol of (a) ^T _j+1 T bits, …, part in the first encoded symbol of (a) ^T _n1-j+1 T bits in the first encoded symbol of (c). It will be appreciated that each set of redundancy bits derived from the first redundancy bits may be used to correct a non-contiguous plurality of bits in the first information bits, by dispersing consecutive bit errors of a burst to different inner code words, it may be avoided that the number of error bits in the inner code word may exceed the correction of the inner codeError capability.

In one possible implementation manner, the first information bits include a first symbol block, the first symbol block includes an mth encoded symbol in a first codeword and an mth encoded symbol in a second codeword, the plurality of first bits includes all bits or part bits in the mth encoded symbol in the first codeword, and no encoded symbol in the second codeword, the first codeword and the second codeword are obtained by encoding the information bits, and the m is an integer greater than 0. Referring to fig. 9 and 14, part ₁ As an example of the first symbol block, the mth code symbol in the first codeword is S _1,1 The mth code symbol in the second code word is S _2,1 ，part ₁ S of (3) _1,1 B of (2) ₁ 、b ₂ 、…、b _t Located in the first row of the matrix, part ₁ S of (3) _2,1 Including bits not located in the first row of the matrix, the plurality of first bits (corresponding to the first row of the matrix) including S _1,1 B of (b) ₁ 、b ₂ 、…、b _t And does not include S _2,1 . Optionally, the plurality of first bits includes one bit or a discontinuous plurality of bits in an mth encoded symbol of the first codeword. In this implementation, consecutive errors of a burst may be dispersed among different codewords, so as to reduce the number of errors in each codeword.

In one possible implementation manner, the first information bit further includes a second symbol block, where the second symbol block includes an nth encoded symbol in the first codeword and an nth encoded symbol in the second codeword, the encoded symbols in the second symbol block are sequentially an nth encoded symbol in a K-th codeword to an nth encoded symbol in the first codeword, the encoded symbols in the first symbol block are sequentially an mth encoded symbol in the first codeword to an mth encoded symbol in the K-th codeword, and n is an integer greater than 0 and not equal to m, and the K-th codeword to the first codeword is obtained by encoding the information bit, and K is an integer greater than 1. Referring to fig. 9 and 14, part ^T _j+1 As an example of the second symbol block, part ₁ As an example of the first symbol block, part ₁ The code symbols in (a) are sequentially from the mth code symbol in the first code word to the mth code symbol in the K code word, namely S _1,1 、S _2,1 、…、S _x,1 ，part ^T _j+1 The code symbols in (a) are sequentially from the nth code symbol in the Kth code word to the nth code symbol in the first code word, namely S _x,j+1 、S _x-1,j+1 、…、S _1,j+1 . In this implementation, the ordering of the encoded symbols in the second symbol block is different from the ordering of the encoded symbols in the first codeword, which may increase the probability of dispersing burst errors into different codewords.

In one possible implementation manner, the first information bit includes a plurality of symbol blocks, the plurality of symbol blocks includes a first symbol block and a second symbol block, the first symbol block includes an mth encoded symbol in a first codeword and an mth encoded symbol in a second codeword, the second symbol block includes an nth encoded symbol in the first codeword and an nth encoded symbol in the second codeword, the first redundancy bit is used for correcting any one of a plurality of bit sequences obtained by arranging the plurality of symbol blocks in a matrix, the first codeword and the second codeword are obtained by encoding the information bit, the m and the n are integers greater than 0, and the m is different from the n. Referring to fig. 13 and 14, it can be seen that the symbol blocks in the previous part of fig. 14 are arranged in columns to obtain the matrix shown in fig. 13, and the first redundancy bits can be used to correct the bits in any row of the matrix, that is, any one of a plurality of bit sequences obtained by arranging the plurality of symbol blocks in a matrix manner. In this implementation manner, the first redundancy bits are used to correct any one of a plurality of bit sequences obtained by arranging a plurality of symbol blocks in a matrix manner, so that burst continuous error codes can be dispersed into different code words, and the number of error codes in each code word can be reduced.

In the embodiment of the application, a plurality of symbol blocks are arranged into a matrix by columns by a transmitting end, the matrix is coded by a row internal code, and bits are read by rows by taking a part as a unit and then sent to a subsequent signal processing flow; the burst continuous error codes can be dispersed into different inner code words, so as to reduce the number of error codes in each code word, thereby achieving the effect of improving the error correction success probability of the inner code.

Fig. 15 is a flowchart of another code transmission method according to an embodiment of the present application. The main difference between the method flow in fig. 15 and the method flow in fig. 6 is that the symbol blocks are arranged in a matrix. The method flow in fig. 15 and the method flow in fig. 6 are two parallel coding transmission schemes. As shown in fig. 15, the method includes:

1501. and the transmitting end performs outer code encoding on the information bits to be encoded to obtain a plurality of outer code words.

Step 1501 can be implemented as described in step 601.

1502. The transmitting end interweaves the plurality of outer code words according to the outer code coding symbols to obtain a plurality of symbol blocks.

Step 1502 is implemented as described in step 602.

1503. The transmitting end arranges a plurality of symbol blocks into a matrix by rows.

The implementation of step 1503 may refer to step 603. The implementation of the transmitting end in which the plurality of symbol blocks are arranged in a matrix by rows is similar to the implementation of the transmitting end in which the plurality of symbol blocks are arranged in a matrix by columns. It is not essential for those skilled in the art that the transmitting end arranges a plurality of symbol blocks into a matrix by rows and a plurality of symbol blocks into a matrix by columns, and they will not be described in detail herein. Since the code length of the internal code adopted by the transmitting end for internal code coding is k ₂ Symbol length m ₂ Therefore, when the transmitting end arranges a plurality of symbol blocks into a matrix by rows, the transmitting end needs to ensure that each column of the matrix has k ₂ m ₂ And a number of bits.

1504. The transmitting end carries out internal code coding on each column of the matrix and arranges the redundant bits of the internal code beside the matrix.

Step 1504 is implemented as described in step 604. The implementation of the transmitting end for inner code encoding each column of the matrix is similar to the implementation of inner code encoding each row of the matrix. For those skilled in the art, the transmitting end performs inner code encoding on each column of the matrix and inner code encoding on each row of the matrix, which are not described herein. Here, the inner code redundant bits may be arranged beside the matrix by arranging the inner code redundant bits of each column as a new added row of the column under the matrix.

1505. The transmitting end reads out the bits in the matrix according to the rows to obtain a first bit stream to be transmitted.

One possible implementation of step 1505 is as follows: the transmitting end reads out the inner code information part in the matrix from left to right and from top to bottom according to the row by taking the symbol block as a unit and restores the inner code information part into a bit stream; and for the inner code redundant part, reading out the inner code redundant part directly according to the row to obtain a first bit stream to be output. The implementation of step 1505 may refer to step 605.

1506. The transmitting end transmits a first bit stream.

In the embodiment of the application, a plurality of symbol blocks are arranged into a matrix by rows by a transmitting end, after the matrix is subjected to internal code coding by columns, bits are read by rows by taking a part as a unit and are sent to a subsequent signal processing flow; the burst continuous error codes can be dispersed into different inner code words, so as to reduce the number of error codes in each code word, thereby achieving the effect of improving the error correction success probability of the inner code.

The method flow in fig. 15 and the method flow in fig. 6 are two parallel coding transmission schemes, and the possible implementation of the method described in fig. 6 is mainly described below. It should be understood that the possible implementation manner of the method described in fig. 6 may be simply transformed or modified to obtain the possible implementation manner of the method described in fig. 15, which is not described herein.

Fig. 16 is a flowchart of another code transmission method according to an embodiment of the present application. The method flow in fig. 15 is one possible implementation of the method described in fig. 6. In the implementation mode, after the encoding symbols of the outer codes RS (544,514) are arranged in a matrix by columns at the transmitting end, the encoding is carried out according to the row inner codes BCH (144,136); the maximum scattered burst error codes can be transmitted to different BCH code words, and the probability of successful BCH error correction is improved. As shown in fig. 16, the method includes:

1601. The transmitting end performs RS coding on information bits to be coded to obtain a plurality of RS (544,514) code words.

In the embodiment of the application, the transmitting end adopts RS (544,514) as an outer code, adopts BCH (144,136) as an inner code, adopts two-frame outer code interleaving, and realizes cascade coding by a matrix interleaving method. Each code symbol of the outer code RS (544,514) consists of 10 bits and each code symbol of the inner code BCH (144,136) consists of 1 bit. The RS encoding of the information bits to be encoded by the transmitting end may be: for every 514 RS encoded symbols (5140 bits) in the bit stream to be encoded, 30 redundancy symbols (300 bits) are calculated and added. Fig. 17 is a codeword structure of RS (544,514) according to an embodiment of the present application. As shown in fig. 17, each code symbol of the outer code RS (544,514) includes 10 bits, and the information bits of the outer code RS (544,514) include 514 code symbols, i.e., S ₁ 、S ₂ 、…、S ₅₁₄ The redundancy bits of the outer code RS (544,514) comprise 30 code symbols, S ₅₁₅ 、S ₅₁₆ 、…、S ₅₄₄ . In other words, the information bit length of the outer code RS (544,514) is 514 and the code length is 544.

1602. The transmitting end carries out coding symbol interleaving on two RS (544,514) code words in the plurality of RS (544,514) code words to obtain a plurality of symbol blocks.

Optionally, the transmitting end selects two RS (544,514) codewords from the plurality of RS (544,514) codewords according to a preset rule to perform coding symbol interleaving, that is, interleaving is performed by taking the coding symbols as units. Fig. 18 is an example of coding symbol interleaving for two RS (544,514) codewords according to an embodiment of the present application. As shown in fig. 18, codeword 1 (codeword ₁ ) Includes S _1,1 、S _1,2 、…、S _1,544 Codeword 2 (codeword ₂ ) Includes S _2,1 、S _2,2 、…、S _2,544 Codeword 1 and codeword 2 are two RS (544,514) codewords, and codeword 1 and codeword 2 are encoded and symbol interleaved to obtain 544 symbol blocks (parts), i.e., part ₁ 、part ₂ 、…、part ₅₄₃ 、part ₅₄₄ Each part includes two encoded symbols. part ₁ Includes S _1,1 And S is _2,1 ，part ₂ Includes S _1,2 And S is _2,2 ，part ₅₄₂ Includes S _1,543 And S is _2,543 ，part ₅₄₄ Includes S _1,544 And S is _2,544 . It can be appreciated that each part includes the same position of the encoded symbols in two RS (544,514) codewords, e.g., part ₁ The first code comprising codeword 1 corresponds to the first code symbol of codeword 2.

1603. The transmitting end arranges a plurality of symbol blocks into a matrix by columns.

Step 1603 may refer to step 603. Illustratively, t=2, i.e., two bits of each encoded symbol are aligned in a column, 5 rows total, and the symbol blocks of even columns may be arranged in reverse. Alternatively, the transmitting end arranges the above-mentioned symbol blocks in columns in symbol block units, the odd columns arrange 8 forward arranged symbol blocks, the even columns arrange 8 reverse arranged symbol blocks, and the matrix thus arranged has 136 bits per row. Fig. 19 is an example of another matrix provided by the present application, with a plurality of symbol blocks arranged in columns. Referring to FIG. 19, S _1,1 、S _2,1 、S _1,2 、S _2,2 、…、S _1,544 、S _2,544 Arranged in a matrix by columns, i.e. the above-mentioned multiple symbol blocks are arranged in a matrix by columns, the symbol blocks of even columns are inversely arranged, each column corresponds to 16 code symbols, i.e. 8 symbol blocks, S _1,1 Is arranged in a column. Fig. 19 shows only S _1,1 In the case of a column of two bits. It will be appreciated that when the transmitting end arranges a plurality of symbol blocks in a matrix in columns, two bits of each encoded symbol in each symbol block are arranged in a column. As can be seen from FIG. 19, S is arranged first in the first column _1,1 Rearrangement S _2,1 First arrange S in second row _2,9 Rearrangement S _1,9 Indicating that the symbol blocks in the odd columns are normally arranged and the symbol blocks in the even columns are inversely arranged.

When the transmitting end arranges a plurality of symbol blocks into a matrix according to columns, the value of t can take any positive integer which can be divided by the coding symbol length m of the outer code. For example, for NRZ modulated systems, one modulation symbol is 1 bit, so t can be chosen to be 1, maximizing the spreading of burst errors among different inner code codewords. For another example, t may be equal to m.

1604. The transmitting end encodes each row of the matrix with an inner code BCH (144,136) to obtain redundant bits of a plurality of BCH (144,136) codewords.

The transmitting end encodes 136 bits of each row of the matrix by an inner code BCH (144,136), and redundant bits (8 bits) are needed to be calculated and added. Fig. 20 is a codeword structure of a BCH (144,136) provided by the present application. As shown in FIG. 20, the information bits of the BCH (144,136) include 136 bits, i.e., b ₁ 、b ₂ 、…、b ₁₃₆ The redundant bits of the BCH (144,136) comprise 8 bits, i.e. b ₁₃₇ 、…、b ₁₄₄ 。

1605. The transmitting end adds the redundant bit of each BCH (144,136) codeword into the matrix to obtain the matrix after the internal code encoding.

Fig. 21 is an example of a matrix after inner code encoding according to an embodiment of the present application. Referring to FIG. 21, the last 8 columns of the inner code encoded matrix are redundant bits of the BCH (144,136) codeword, e.g., r _1,1 、r _1,2 、…、r _1,8 Is a BCH (144,136) codeword (i.e. BCH (144,136) ₁ ) The inner coded matrix comprises 80 rows, one BCH (144,136) codeword per row, the first row BCH (144,136) ₁ Second behavior BCH (144,136) ₂ 。

1606. And the transmitting end reads out the bits in the matrix after the internal code encoding according to the columns to obtain a first bit stream to be transmitted.

Step 1606 can refer to step 605. For example, the transmitting end reads the inner code information part in the matrix after the inner code encoding according to the sequence from top to bottom and from left to right according to the part unit and restores the inner code information part into a bit stream according to the column; while the inner code redundant part is directly read out by column. Fig. 22 is an example of a first bit stream provided in an embodiment of the present application. As shown in fig. 22, the first bit stream includes two parts, the former part being information bits of an inner code (after interleaving a plurality of inner code words), i.e., part ₁ 、part ₂ 、…、part ₈ 、part ^T ₉ 、part ^T ₁₀ 、…、part ^T ₁₆ 、…、part ^T ₅₄₄ The latter part is the redundancy bits added in inner code encoding, i.e. r _1,1 、r _2,1 、…、r _80,1 、r _1,2 、r _2,2 、…、r _80,2 、r _1,8 、…、r _80,8 ，part ₁ Includes S _1,1 And S is _2,1 ，S _1,1 Includes b ₁ 、b ₂ 、…、b ₁₀ . FIG. 22 shows only part ₁ Comprising coded symbols (i.e. S _1,1 And S is _2,1 ) And S _1,1 Comprising 10 bits, i.e. b ₂ 、…、b ₁₀ . It is understood that each part includes two encoded symbols, each of which includes 10 bits.

In one possible implementation, step 1603 may be replaced by: arranging a plurality of symbol blocks into a matrix in rows; step 1604 may be replaced with: the transmitting end encodes each column of the matrix by an inner code BCH (144,136) to obtain redundant bits of a plurality of BCH (144,136) code words; step 1606 may be replaced by: the transmitting end reads out the bits in the matrix after the internal code coding according to the rows to obtain a first bit stream to be transmitted. It should be understood that, for the sender, this implementation is not substantially different from the method flow in fig. 16, and will not be described in detail here.

1607. The transmitting end transmits a first bit stream.

In the embodiment of the application, two RS (544,514) are interleaved according to the code symbols, so that burst continuous error codes and non-random error codes after internal code error correction can be dispersed into two code words, and the probability of successful error correction of each RS code word is improved. After the matrix is coded according to the row BCH (144,136), the bits are read according to the columns by taking part as a unit and sent to the subsequent signal processing flow, and the burst continuous error codes can be dispersed into different BCH code words, so that the number of error codes in each code word is reduced, and the effect of improving the error correction success probability of the internal code BCH is achieved. When PAM-4 modulation and Gray coding are considered, each PAM symbol consists of two bits, and the two bits in one PAM symbol have high probability of only one error.

The foregoing describes the method of transmitting the code performed by the transmitting end, and the following describes the method of decoding performed by the receiving end with reference to the accompanying drawings.

Fig. 23 is a flowchart of a decoding method according to an embodiment of the present application. As shown in fig. 23, the method includes:

2301. the receiving end receives the second bit stream.

The receiving end may be any device needing decoding, such as a network device, a computer device, a terminal device, etc., especially a device adopting FEC technology for decoding. For example, the receiving end is a computer, a desktop computer, a notebook computer, a modem, a router, a network bridge, a TRP, and the like. In the present application, the operations or processes performed by the receiving end (for example, the operations or processes performed by the receiving end in the method flow in fig. 23) may be performed by the receiving end, or may be performed by a chip or a circuit system provided in the receiving end. The circuitry may be, for example, an integrated circuit, a logic circuit. The chip may be, for example, a SoC chip, a baseband modem (modem) chip, a SerDes chip, etc., and is not limited herein. The receiving end will be described below as an example.

The second bit stream is a bit stream which is received by the receiving end and transmitted by the first bit stream transmitted by the transmitting end through a channel. The second bit stream comprises second information bits (corresponding to the first information bits described above) and second redundancy bits (corresponding to the first redundancy bits described above). The second redundancy bits are used to correct a non-consecutive plurality of second bits (corresponding to the plurality of first bits described above) in the second information bits. In the present application, the transmitting end transmits the first bit stream, which is actually a signal for modulating and signal processing the first bit stream. The receiving end receives the second bit stream, which is actually a signal transmitted by the receiving end (i.e. a signal obtained by modulating and processing the first bit stream) through a channel. The receiving of the second bit stream by the receiving end can be understood as: and receiving a second signal, wherein the second signal is a signal which is obtained by modulating and processing a first bit stream by the transmitting end and is received by the receiving end through channel transmission of a first signal transmitted by the transmitting end. One possible implementation of step 2031 is as follows: the receiving end carries out signal processing and demodulation on the received second signal to obtain a second bit stream. Since modulation and signal processing of received signals are conventional techniques in the art, they are not described herein.

In one possible implementation, the second information bits include a first symbol block including an mth encoded symbol in a first codeword and an mth encoded symbol in a second codeword, the plurality of second bits including all or part of the bits in the mth encoded symbol in the first codeword and not including the encoded symbols in the second codeword, the m being an integer greater than 0. The code symbols not included in the second codeword may be any bits in the code symbols not included in the second codeword. Or, any bits in the second codeword are not included. Optionally, the plurality of second bits includes one bit or a discontinuous plurality of bits in an mth encoded symbol of the first codeword. In this implementation, the plurality of second bits includes all or part of the bits in the mth encoded symbol in the first codeword and does not include the encoded symbol in the second codeword; therefore, the burst continuous error codes can be dispersed into different code words, and the effects of reducing the number of error codes in each code word and improving the error correction success probability can be achieved. The second information bits may be regarded as information bits received by the receiving end via the channel transmission of the first information bits.

In one possible implementation manner, the second information bit further includes a second symbol block, where the second symbol block includes an nth encoded symbol in the first codeword and an nth encoded symbol in the second codeword, the encoded symbols in the second symbol block are sequentially an nth encoded symbol in a K-th codeword to an nth encoded symbol in the first codeword, the encoded symbols in the first symbol block are sequentially an mth encoded symbol in the first codeword to an mth encoded symbol in the K-th codeword, and n is an integer greater than 0 and not equal to m, and the kth codeword to the first codeword are used for decoding to obtain the information bit, and K is an integer greater than 1. In this implementation, the ordering of the encoded symbols in the second symbol block is different from the ordering of the encoded symbols in the first codeword, which may increase the probability of dispersing burst errors into different codewords.

2302. And the receiving end decodes the second bit stream to obtain information bits.

The operation of the receiving end to decode the second bit stream to obtain the information bit may be the inverse operation of the transmitting end to encode the information bit to obtain the first bit stream. Optionally, the receiving end outputs the information bits after decoding the information bits. The information bits are output, for example, via an output device (e.g., a display screen, a display, an audio device), etc.

One possible implementation of step 2302 is as follows: the receiving end arranges the second bit stream into a matrix according to columns; performing inner code decoding on each row of the matrix, reserving information bits of each row, and discarding redundant bits; the information bits are derived from the information bits of each row (or each column) of the matrix. Multiplexing the bit stream shown in fig. 14, fig. 14 can be regarded as a second bit stream. Multiplexing the matrix shown in fig. 13, the matrix shown in fig. 13 may be used as a matrix in which the second bit streams are arranged in columns at the receiving end. The receiving end arranges the second bit stream into a matrix according to columns: arranging symbol blocks in the second bit stream in columns in units of symbol blocks, for example, j symbol blocks are arranged in each column; and arranging the inner code redundant parts into a matrix by columns. Arranging the symbol blocks in columns in units of symbol blocks in the second bit stream means that the symbol blocks are regarded as one column instead of one column in the matrix. Referring to FIG. 13, part ₁ 、part ₂ 、…、part _j Can be regarded as a first column obtained by arranging symbol blocks in the second bit stream in columns in units of symbol blocks, r _1,1 、r _2,1 、…、r _i,1 Can be considered as the first column obtained by arranging the inner code redundant parts in columns. For the receiving end, the number, size (i.e. how many code symbols one symbol block comprises), code length of the inner code, symbol length of the inner code in the second bit stream are known The second bit stream may thus be arranged in columns as a matrix. One possible implementation of obtaining information bits from the information bits of each row of the matrix is as follows: de-interleaving an information bit matrix to obtain a plurality of outer code words, wherein the information bit matrix refers to a submatrix containing information bits of an inner code in the matrix, and referring to the submatrix corresponding to the information bits of the inner code word in fig. 13; performing outer code decoding on each outer code word, only reserving outer code information bits after decoding, and discarding redundant bits; and outputting the outer code information bits according to the sequence of the outer code words to obtain the information bits. The operation of de-interleaving the information bit matrix pattern to obtain a plurality of outer code words is an inverse operation of the operation of interleaving the plurality of outer code words according to outer code encoded symbols to obtain a plurality of symbol blocks. Because of the conventional technical means in the art of deinterleaving, details are not provided herein.

One possible implementation of step 2302 is as follows: the receiving end arranges the second bit stream into a matrix according to the rows; performing inner code decoding on each column of the matrix, and reserving information bits of each column; the information bits are derived from the information bits of each column (or each row) of the matrix. The implementation of arranging the second bit streams in rows into a matrix at the receiving end is similar to the implementation of arranging the second bit streams in columns into a matrix. It is not essential for a person skilled in the art that the receiving end arranges the second bit streams in rows into a matrix, and the receiving end arranges the second bit streams in columns into a matrix, which is not described here again. It should be understood that if the transmitting end arranges the plurality of symbol blocks into a matrix by rows, the receiving end arranges the second bit stream into a matrix by rows; if the transmitting end arranges the plurality of symbol blocks into a matrix by columns, the receiving end arranges the second bit stream into a matrix by columns.

Fig. 24 is a flowchart of another decoding method according to an embodiment of the present application. The method flow in fig. 24 is one possible implementation of the method depicted in fig. 23. In the implementation manner, the receiving end arranges the received second bit stream in a matrix manner and decodes the inner code of each row of the matrix; the burst error code and the non-random error code are successfully dispersed into different internal and external codes and internal code words, so that the error correction success probability of a single code word is improved, and the error rate of the whole system is reduced.

As shown in fig. 24, the method includes:

2401. the receiving end arranges the received second bit stream in a matrix mode to obtain a first matrix.

One possible implementation of step 2401 is as follows: the receiving end arranges the second bit stream into a matrix according to columns. Illustratively, the receiving end arranges the symbol blocks in the second bit stream in columns in units of symbol blocks, for example, j symbol blocks are arranged in each column; and arranging the inner code redundant parts into a matrix according to columns, and finally arranging the inner code redundant parts into a first matrix. The matrix shown in fig. 13 may be regarded as an example of the first matrix.

2402. And the receiving end decodes the inner code of each row of the first matrix, and only retains information bits after decoding to obtain a second matrix.

The second matrix is a sub-matrix of the first matrix. The first matrix includes a sub-matrix (i.e., a second matrix) corresponding to the information bits and a sub-matrix corresponding to the redundancy bits. Alternatively, the first matrix may be divided into two parts, one part comprising information bits (or blocks of symbols) and the other part comprising redundancy bits. The meaning of the second matrix is the same as the meaning of the information bit matrix described above.

In one possible implementation, step 2401 is replaced with: and the receiving end decodes the inner code of each column of the first matrix, and only retains information bits after decoding to obtain a second matrix.

2403. The receiving end de-interleaves the second matrix to obtain a plurality of outer code words.

2404. And the receiving end performs outer code decoding on each outer code word, and only retains outer code information bits after decoding.

2405. The receiving end outputs the outer code information bits according to the sequence of the outer code words.

Step 2405 is optional, but not necessary.

In the embodiment of the application, the receiving end arranges the received second bit stream in a matrix mode and decodes the inner code of each row of the matrix; the burst error code and the non-random error code are successfully dispersed into different internal and external codes and internal code words, so that the error correction success probability of a single code word is improved, and the error rate of the whole system is reduced.

The following describes the structure of a communication device capable of implementing the coding transmission method and/or decoding method provided by the embodiment of the present application with reference to the accompanying drawings.

Fig. 25 is a schematic structural diagram of a communication device 2500 according to an embodiment of the present application. The communication device 2500 may correspondingly implement the functions or steps implemented by the transmitting end in the above-described method embodiments, or may correspondingly implement the functions or steps implemented by the receiving end in the above-described method embodiments. The communication device may include a processing module 2510 and a transceiver module 2520. Optionally, a storage unit may be included, which may be used to store instructions (code or programs) and/or data. The processing module 2510 and the transceiver module 2520 may be coupled to the storage unit, for example, the processing module 2510 may read instructions (code or program) and/or data in the storage unit to implement a corresponding method. The units can be independently arranged or partially or fully integrated. For example, transceiver module 2520 may include a transmit module and a receive module. The transmitting module may be a transmitter and the receiving module may be a receiver. The entity corresponding to transceiver module 2520 may be a transceiver or a communication interface.

In some possible embodiments, the communication device 2500 can correspondingly implement the behaviors and functions of the transmitting end in the above method embodiments. For example, communication device 2500 may be a transmitting terminal or a component (e.g., a chip or a circuit) applied to the transmitting terminal. The transceiver module 2520 may be used, for example, to perform all of the receiving or transmitting operations performed by the transmitting end in the embodiments of fig. 6, 15, 16, e.g., step 606 in the embodiment shown in fig. 6, step 1506 in the embodiment shown in fig. 15, step 1607 in the embodiment shown in fig. 16, and/or other processes for supporting the techniques described herein. The processing module 2510 is configured to perform all operations except for the transceiving operations performed by the station in the embodiments of fig. 6, 15 and 16, for example, steps 602 to 605 in the embodiment shown in fig. 6, steps 1501 to 1505 in the embodiment shown in fig. 15, and steps 1601 to 1606 in the embodiment shown in fig. 16.

In some possible embodiments, the communication device 2500 can correspondingly implement the behaviors and functions of the receiving end in the above method embodiments. For example, communication device 2500 may be a receiving end or a component (e.g., a chip or a circuit) applied to the receiving end. Transceiver module 2520 may be used, for example, to perform all of the receiving or transmitting operations performed by the receiving end in the embodiments of fig. 23, 24, such as step 2405 in the embodiment shown in fig. 24, and/or to support other processes for the techniques described herein. The processing module 2510 is configured to perform all operations performed by the receiving end except for the transceiving operations, for example, step 2301 and step 2302 in the embodiment shown in fig. 23, and steps 2401 to 2404 in the embodiment shown in fig. 24.

Fig. 26 is a schematic structural diagram of another communication device 260 according to an embodiment of the present application. The communication device in fig. 26 may be the transmitting end or the receiving end.

As shown in fig. 26, the communication device 260 includes at least one processor 2610 and a transceiver 2620.

In some embodiments of the application, the processor 2610 and the transceiver 2620 may be used to perform functions or operations performed by a transmitting end, etc. The transceiver 2620 performs all the receiving or transmitting operations performed by the transmitting end in the embodiments of fig. 6, 15, 16, for example. The processor 2610 is used, for example, to perform all operations performed by the transmitting end in the embodiments of fig. 6, 15, and 16 except for the transceiving operations.

In some embodiments of the application, the processor 2610 and the transceiver 2620 may be used to perform functions or operations performed by a receiving end, etc. The transceiver 2620 performs all the receiving or transmitting operations performed by the receiving end in the embodiment of fig. 24, for example. The processor 2610 is used for executing all operations executed by the receiving end except for the transceiving operations, for example, step 2301, step 2302 in the embodiment shown in fig. 23, and steps 2401 to 2404 in the embodiment shown in fig. 24.

The transceiver 2620 is used to communicate with other devices/apparatus over a transmission medium. The processor 2610 utilizes the transceiver 2620 to transmit and receive data and/or signaling and is used to implement the methods of the method embodiments described above. The processor 2610 may perform the functions of the processing module 2510 and the transceiver 2620 may perform the functions of the transceiver module 2520.

Alternatively, the transceiver 2620 may include a radio frequency circuit and an antenna, where the radio frequency circuit is mainly used for converting a baseband signal and a radio frequency signal and processing the radio frequency signal. The antenna is mainly used for receiving and transmitting radio frequency signals in the form of electromagnetic waves. Input and output devices, such as touch screens, display screens, keyboards, etc., are mainly used for receiving data input by a user and outputting data to the user.

Optionally, the communication device 260 may also include at least one memory 2630 for storing program instructions and/or data. A memory 2630 is coupled to the processor 2610. The coupling in the embodiments of the present application is an indirect coupling or communication connection between devices, units, or modules, which may be in electrical, mechanical, or other forms for information interaction between the devices, units, or modules. The processor 2610 may operate in conjunction with the memory 2630. The processor 2610 may execute program instructions stored in the memory 2630. At least one of the at least one memory may be included in the processor.

When the communication device 260 is powered on, the processor 2610 may read the software program in the memory 2630, interpret and execute instructions of the software program, and process data of the software program. When data is required to be transmitted wirelessly, the processor 2610 performs baseband processing on the data to be transmitted and outputs a baseband signal to the radio frequency circuit, and the radio frequency circuit performs radio frequency processing on the baseband signal and then transmits the radio frequency signal to the outside in the form of electromagnetic waves through the antenna. When data is transmitted to the communication device, the radio frequency circuit receives a radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor 2610, and the processor 2610 converts the baseband signal into data and processes the data.

In another implementation, the radio frequency circuitry and antenna described above may be provided separately from the processor performing the baseband processing, e.g., in a distributed scenario, the radio frequency circuitry and antenna may be in a remote arrangement from the communication device.

The specific connection medium between the transceiver 2620, the processor 2610 and the memory 2630 is not limited in the embodiment of the present application. In the embodiment of the present application, the memory 2630, the processor 2610 and the transceiver 2620 are connected through a bus 2640, which is shown by a thick line in fig. 26, and the connection manner between other components is only schematically illustrated and not limited thereto. The bus may be classified as an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in fig. 26, but not only one bus or one type of bus.

In the embodiment of the present application, the processor may be a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps and logic blocks disclosed in the embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in the processor for execution.

Fig. 27 is a schematic structural diagram of another communication device 270 according to an embodiment of the present application. As shown in fig. 27, the communication device shown in fig. 27 includes a logic circuit 2701 and an interface 2702. The processing module 2510 in fig. 25 may be implemented with logic circuit 2701, and the transceiver module 2520 in fig. 25 may be implemented with interface 2702. The logic circuit 2701 may be a chip, a processing circuit, an integrated circuit, a system on chip (SoC) chip, or the like, and the interface 2702 may be a communication interface, an input/output interface, or the like. In the embodiment of the application, the logic circuit and the interface can be coupled with each other. The embodiment of the present application is not limited to the specific connection manner of the logic circuit and the interface.

In some embodiments of the present application, the logic and interfaces may be used to perform the functions or operations performed by the sender, etc.

In some embodiments of the present application, the logic and interfaces may be used to perform the functions or operations performed by the receiving end described above, and so on.

The present application also provides a computer-readable storage medium having stored therein a computer program or instructions which, when run on a computer, cause the computer to perform the method of the above-described embodiments.

The application also provides a computer program product comprising instructions or a computer program which, when run on a computer, cause the method of the above embodiments to be performed.

The application also provides a communication system which comprises the sending end and the receiving end.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method of coded transmission, comprising:

according to information bits to be encoded, encoding to obtain a first bit stream, wherein the first bit stream comprises first information bits and first redundant bits, the first bit stream is used for decoding to obtain the information bits, and the first redundant bits are used for correcting a plurality of discontinuous first bits in the first information bits;

and transmitting the first bit stream.

2. The method of claim 1, wherein the first information bits comprise a first symbol block comprising an mth encoded symbol in a first codeword and an mth encoded symbol in a second codeword, wherein the plurality of first bits comprises all or a portion of the mth encoded symbol in the first codeword and no encoded symbol in the second codeword, wherein the first codeword and the second codeword are derived from encoding the information bits, and wherein m is an integer greater than 0.

3. The method of claim 2, wherein the plurality of first bits comprises one bit or a non-contiguous plurality of bits in an mth encoded symbol of the first codeword.

4. A method according to claim 2 or 3, wherein the first information bits further comprise a second symbol block comprising an nth encoded symbol in the first codeword and an nth encoded symbol in the second codeword, the encoded symbols in the second symbol block being in turn an nth encoded symbol in a K-th codeword to an nth encoded symbol in the first codeword, the encoded symbols in the first symbol block being in turn an mth encoded symbol in the first codeword to an mth encoded symbol in the K-th codeword, the n being an integer greater than 0 and not equal to the m, the K-th codeword to the first codeword resulting from encoding the information bits, the K being an integer greater than 1.

5. The method according to any one of claims 1 to 4, wherein the first information bits include a plurality of symbol blocks including a first symbol block including an mth encoded symbol in a first codeword and an mth encoded symbol in a second codeword, and a second symbol block including an nth encoded symbol in the first codeword and an nth encoded symbol in the second codeword, the first redundancy bits being used for correcting any one of a plurality of bit sequences in which the plurality of symbol blocks are arranged in a matrix, the first codeword and the second codeword being obtained by encoding the information bits, the m and the n being integers greater than 0, the m being different from the n.

6. The method according to any one of claims 1 to 5, wherein said encoding the first bit stream from the information bits to be encoded comprises:

performing outer code coding on the information bits to obtain a plurality of outer code words;

interleaving the plurality of outer code words by taking coding symbols as units to obtain a plurality of symbol blocks, wherein the plurality of symbol blocks comprise a first symbol block and a second symbol block, the first symbol block comprises an mth coding symbol in a first code word and an mth coding symbol in a second code word, the second symbol block comprises an nth coding symbol in the first code word and an nth coding symbol in the second code word, the m and the n are integers larger than 0, and the m is different from the n;

arranging the plurality of symbol blocks into a matrix in columns;

performing inner code coding on each row in the matrix to obtain a plurality of groups of redundant bits, wherein the plurality of groups of redundant bits comprise the first redundant bits;

and processing the first bit stream according to the plurality of symbol blocks and the plurality of groups of redundant bits.

7. The method of claim 6, wherein arranging the plurality of symbol blocks in columns into a matrix comprises:

Arranging the plurality of symbol blocks into the matrix with P bits in each row according to columns, wherein P is equal to the product of an inner code length to be adopted for inner code coding and an inner code symbol length, m bits in each coding symbol in the first symbol block are arranged into t columns, t is divided by m, and m, P and t are integers larger than 0.

8. The method of claim 7, wherein each encoded symbol in the symbol blocks of odd columns in the matrix is arranged normally and each encoded symbol in the symbol blocks of even columns in the matrix is arranged inversely; alternatively, each code symbol in the symbol blocks of even columns in the matrix is normally arranged, and each code symbol in the symbol blocks of odd columns in the matrix is inversely arranged.

9. The method according to any one of claims 1 to 5, wherein said encoding the first bit stream from the information bits to be encoded comprises:

performing outer code encoding on the first bit stream to obtain a plurality of outer code words;

Arranging the plurality of symbol blocks into a matrix in rows;

performing inner code coding on each column in the matrix to obtain a plurality of groups of redundant bits, wherein the plurality of groups of redundant bits comprise the first redundant bits;

10. The method of claim 9, wherein the arranging the plurality of symbol blocks in rows into a matrix comprises:

arranging the plurality of symbol blocks into the matrix with P bits in each column according to rows, wherein P is equal to the product of an inner code length to be adopted for inner code coding and an inner code symbol length, m bits in each coding symbol in the first symbol block are arranged into t rows, t is divided by m, and m, P and t are integers larger than 0.

11. The method of claim 10, wherein each encoded symbol in the symbol blocks of the odd rows in the matrix is arranged normally and each encoded symbol in the symbol blocks of the even rows in the matrix is arranged inversely; alternatively, each of the encoded symbols in the symbol blocks of the even rows in the matrix is normally arranged, and each of the encoded symbols in the symbol blocks of the odd rows in the matrix is inversely arranged.

12. A decoding method, comprising:

a receiving end receives a second bit stream, wherein the second bit stream is a bit stream which is received by the receiving end through channel transmission of a first bit stream sent by a sending end, and comprises second information bits and second redundant bits, and the second redundant bits are used for correcting a plurality of discontinuous second bits in the second information bits;

and decoding to obtain information bits according to the second bit stream.

13. The method of claim 12, wherein the second information bits comprise a first symbol block comprising an mth encoded symbol in a first codeword and an mth encoded symbol in a second codeword, wherein the plurality of second bits comprise all or a portion of the bits in the mth encoded symbol in the first codeword and no encoded symbols in the second codeword, and wherein m is an integer greater than 0.

14. The method of claim 13, wherein the plurality of second bits comprises one bit or a non-contiguous plurality of bits in an mth encoded symbol of the first codeword.

15. The method according to claim 13 or 14, wherein the second information bits further comprise a second symbol block, the second symbol block comprising an nth encoded symbol in the first codeword and an nth encoded symbol in the second codeword, the encoded symbols in the second symbol block being in turn an nth encoded symbol in a K-th codeword to an nth encoded symbol in the first codeword, the encoded symbols in the first symbol block being in turn an mth encoded symbol in the first codeword to an mth encoded symbol in the K-th codeword, the n being an integer greater than 0 and not equal to the m, the K-th codeword to the first codeword being used for decoding to obtain the information bits, the K being an integer greater than 1.

16. The method according to any one of claims 12 to 15, wherein the second information bits include a plurality of symbol blocks, the plurality of symbol blocks including a first symbol block including an mth encoded symbol in a first codeword and an mth encoded symbol in a second codeword, the second symbol block including an nth encoded symbol in the first codeword and an nth encoded symbol in the second codeword, the second redundancy bits being used to correct any one of a plurality of bit sequences in which the plurality of symbol blocks are arranged in a matrix, the m and the n being integers greater than 0, the m being different from the n.

17. The method according to any of claims 12 to 16, wherein said decoding information bits from said second bitstream comprises:

the receiving end arranges the second bit stream into a matrix according to columns;

the receiving end decodes the inner code of each row of the matrix and reserves the information bit of each row;

the receiving end obtains the information bits according to the information bits of each row of the matrix.

18. The method according to any of claims 12 to 16, wherein said decoding information bits from said second bitstream comprises:

The receiving end arranges the second bit stream into a matrix according to rows;

the receiving end decodes the inner code of each column of the matrix and reserves the information bit of each column;

the receiving end obtains the information bits according to the information bits of each column of the matrix.

19. A communication device comprising means or units for implementing the method of any one of claims 1 to 11.

20. A communication device comprising means or units for implementing the method of any one of claims 12 to 18.

21. A computer readable storage medium, wherein a computer program is stored in the computer readable storage medium, the computer program comprising program instructions which, when executed, cause a computer to perform the method of any one of claims 1 to 11, or which, when executed, cause a computer to perform the method of any one of claims 12 to 18.

22. A communication device comprising a processor coupled to a memory, the memory storing instructions for executing the instructions to cause the communication device to perform the method of any one of claims 1 to 11 or to cause the communication device to perform the method of any one of claims 12 to 18.