KR20180107703A - Apparatus and method of transmission using harq in communication or broadcasting system - Google Patents

Abstract

The present disclosure relates to a 5^th generation (5G) or pre-5G communication system to support a higher data rate than a 4^th generation (4G) communication system such as LTE. The present invention discloses a method for effective retransmission when HARQ is applied to encoded data using a low density parity check (LDCP) code. The method comprises the steps of: initially transmitting data encoded with an LDPC code to a receiver; receiving a negative acknowledgment (NACK) from the receiver; determining retransmission related information for data retransmission; and retransmitting the data encoded with the LDPC code corresponding to the NACK based on the retransmission related information.

Description

TECHNICAL FIELD [0001] The present invention relates to a method and apparatus for HARQ in a communication or broadcasting system,

The present invention relates to a transmission method and apparatus using HARQ in a communication or broadcasting system.

Efforts are underway to develop an improved 5G or pre-5G communication system to meet the growing demand for wireless data traffic after commercialization of the 4G communication system. For this reason, a 5G communication system or a pre-5G communication system is called a system after a 4G network (Beyond 4G network) communication system or after a LTE system (Post LTE).

To achieve a high data rate, 5G communication systems are being considered for implementation in very high frequency (mmWave) bands (e.g., 60 gigahertz (60GHz) bands). In order to mitigate the path loss of the radio wave in the very high frequency band and to increase the propagation distance of the radio wave, in the 5G communication system, beamforming, massive MIMO, full-dimension MIMO (FD-MIMO ), Array antennas, analog beam-forming, and large scale antenna technologies are being discussed.

In order to improve the network of the system, the 5G communication system has developed an advanced small cell, an advanced small cell, a cloud radio access network (cloud RAN), an ultra-dense network, (D2D), a wireless backhaul, a moving network, cooperative communication, Coordinated Multi-Points (CoMP), and interference cancellation Have been developed.

In addition, in the 5G system, the Advanced Coding Modulation (ACM) scheme, Hybrid FSK and QAM Modulation (FQAM) and Sliding Window Superposition Coding (SWSC), the advanced connection technology, Filter Bank Multi Carrier (FBMC) (non-orthogonal multiple access), and SCMA (sparse code multiple access).

In a communication / broadcasting system, the link performance can be significantly degraded by various noise, fading phenomena and inter-symbol interference (ISI) of the channel. Therefore, in order to realize high-speed digital communication / broadcasting systems requiring high data throughput and reliability such as next-generation mobile communication, digital broadcasting, and portable Internet, it is required to develop a technique for overcoming noise, fading and intersymbol interference. Recently, as a method to overcome the noise, the error correcting code has been actively studied as a method for improving the reliability of the communication by efficiently restoring the information distortion.

 The present invention provides an LDPC encoding and decoding method and apparatus for supporting various codeword lengths from a designed parity check matrix. The present invention also provides an HARQ transmission method and apparatus based on an LDPC code.

According to an aspect of the present invention, there is provided a method of transmitting data encoded with an LDPC (Low Density Parity Check) code to a receiver, the method comprising: receiving a negative acknowledgment (NACK) And retransmitting data encoded with the LDPC code corresponding to the NACK based on the retransmission related information.

A method of receiving data in a receiver, the method comprising receiving data encoded with an LDPC (Low Density Parity Check) code from a transmitter, transmitting a negative acknowledgment (NACK) to the transmitter based on the data decoding result, And re-receiving data encoded with the LDPC code retransmitted according to the NACK based on the retransmission information.

In addition, the transmitter for transmitting data may include a transmitting / receiving unit for transmitting / receiving signals to / from a receiver, data initially encoded with an LDPC (Low Density Parity Check) code to a receiver, receiving a negative acknowledgment (NACK) Determining retransmission related information for data retransmission, and controlling the retransmission of the data encoded with the LDPC code according to the NACK based on the retransmission related information.

The receiver receives data from a transmitter and receives data encoded by an LDPC (Low Density Parity Check) code from the transmitter. The receiver decides whether to perform a false acknowledgment to the transmitter based on the data decoding result NACK), determines retransmission related information for data retransmission, and controls to re-receive data encoded with the LDPC code retransmitted based on the retransmission information in response to the NACK. do.

The present invention can support an HARQ scheme based on an LDPC code applicable to a variable length and a variable rate.

값에 따라 전송되는 비트를 도시한 도면이다.
도 14a는 재전송되는 심볼이 동일한 경우 변조 심볼 매핑 방법을 도시한 도면이다.
도 14b는 재전송되는 심볼이 동일하지 않을 경우 변조 심볼 매핑 방법을 도시한 도면이다.
도 15는 각 심볼마다 순환 쉬프트를 적용하는 방법을 도시한 도면이다.
도 16a는 본 발명을 수행하는 장치를 도시한 블록도이다.
도 16b는 본 발명의 실시예에 따른 변조 심볼 매핑 방법을 도시한 순서도이다.
도 17은 본 발명의 실시예에 따른 데이터 재전송 방법을 도시한 도면이다.
도 18은 본 발명의 일 실시 예에 따른 부호화 장치의 구성을 나타내는 블록도이다.
도 19는 본 발명의 일 실시 예에 따른 복호화 장치의 구성을 나타내는 블록도이다.
도 20은 본 발명의 실시예에 따른 복호화 장치를 도시한 블록도이다.
도 21 및 22는 본 발명의 실시예에 따라 동작할 수 있는 송신기 및 수신기를 도시한 도면이다.
도 23은 본 발명에 따라 신호 전송시 특정 BLER을 만족시키는 SNR 값을 도시한 도면이다.
도 24는 블록 인터리버를 도시한 도면이다.
도 25는 본 발명에 따른 송신 순서를 도시한 도면이다. 1 is a diagram illustrating a systematic LDPC codeword structure.
FIG. 2 shows an example of a parity check matrix H1 of an LDPC code including four rows and eight columns, and a tanner graph. Referring to FIG.
3 is a diagram showing a basic structure of a parity check matrix.
4 is a block diagram of a transmitting apparatus according to an embodiment of the present invention.
5 is a block diagram of a receiving apparatus according to an embodiment of the present invention.
6A and 6B are diagrams illustrating the characteristics of the LDPC parity check matrix used in the present invention.
7A and 7B are diagrams illustrating a message passing operation performed in an arbitrary check node and variable node for LDPC decoding.
8 is a flowchart illustrating a transmission method according to an embodiment of the present invention.
9A and 9B are flowcharts illustrating a transmission method according to an embodiment of the present invention.
FIG. 10 is a diagram showing the positions of LDPC codewords and predetermined bits for the retransmission.
11A and 11B are diagrams showing codewords which are redundant in retransmission according to a coding rate.
11C is a diagram showing codewords transmitted when the interleaver is used differently.
12A and 12B are diagrams illustrating a method for determining a retransmission start point according to an initial code rate.
13A is a flow chart illustrating a method for determining the position of an rv value in accordance with the present invention.
FIG. 13B is a cross-

≪ / RTI > FIG.
14A is a diagram illustrating a modulation symbol mapping method when the retransmitted symbols are the same.
14B is a diagram illustrating a modulation symbol mapping method when the retransmitted symbols are not the same.
15 is a diagram showing a method of applying a cyclic shift for each symbol.
16A is a block diagram illustrating an apparatus for performing the present invention.
16B is a flowchart illustrating a modulation symbol mapping method according to an embodiment of the present invention.
17 is a diagram illustrating a data retransmission method according to an embodiment of the present invention.
18 is a block diagram showing a configuration of an encoding apparatus according to an embodiment of the present invention.
19 is a block diagram showing a configuration of a decoding apparatus according to an embodiment of the present invention.
20 is a block diagram illustrating a decoding apparatus according to an embodiment of the present invention.
21 and 22 are diagrams illustrating a transmitter and a receiver that may operate in accordance with an embodiment of the present invention.
23 is a diagram showing an SNR value satisfying a specific BLER upon signal transmission according to the present invention.
24 is a diagram showing a block interleaver.
25 is a diagram showing a transmission procedure according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions of the present invention, and these may be changed according to the intention of the user, the operator, or the like. Therefore, the definition should be based on the contents throughout this specification.

It is to be understood that the subject matter of the present invention is also applicable to other systems having similar technical backgrounds, with a slight variation not exceeding the scope of the present invention, and it can be done by a person skilled in the art It will be possible.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The Low Density Parity Check (LDPC) code, first introduced by Gallager in the 1960s, has long been forgotten due to the complexity of the technology at the time. However, since turbo codes proposed by Berrou, Glavieux, and Thitimajshima in 1993 showed a performance close to the channel capacity of Shannon, many interpretations on the performance and characteristics of turbo codes were made, iterative decoding, and graph-based channel coding. When the LDPC code is re-studied in the late 1990s, iterative decoding based on a sum-product algorithm is applied on a Tanner graph corresponding to the LDPC code to perform decoding, It has also been found that it has performance close to the capacity of the channel.

An LDPC code can be expressed using a bipartite graph, which is generally defined as a parity-check matrix and is collectively referred to as a tanner graph.

1 is a diagram illustrating a systematic LDPC codeword structure.

(102)를 LDPC 부호화하면, 부호어

(100)가 생성된다. 즉, 부호어는 다수의 비트로 구성되어 있는 비트열이며, 부호어 비트는 부호어를 구성하는 각각의 비트를 의미한다. 또한, 정보어는 다수의 비트로 구성되어 있는 비트열이며, 정보어 비트는 정보어를 구성하는 각각의 비트를 의미한다. 이때, 시스테메틱 부호인 경우, 부호어

로 구성된다. 여기에서,

는 패리티 비트(104)이고, 패리티 비트의 개수 N_parity는 N_parity=N_ldpc - K_ldpc이다. _Referring to FIG. 1, an LDPC code receives an information word 102 composed of K _ldpc bits or symbols and performs LDPC coding to generate a codeword 100 consisting of N _ldpc bits or symbols do. For convenience of explanation, it is assumed that a codeword 100 composed of N _ldpc bits is generated by receiving an information word 102 including K _ldpc bits. That is, K _ldpc input bits

(102) is LDPC-coded, a codeword

(100) is generated. That is, a codeword is a bit string composed of a plurality of bits, and a codeword bit means each bit constituting a codeword. Also, the information word is a bit string composed of a plurality of bits, and the information word bit means each bit constituting the information word. At this time, in the case of a systematic code,

. From here,

Is parity bit 104, and the number N _parity of parity bits is N _parity = N _ldpc - K _ldpc .

The LDPC code is a type of linear block code and includes a process of determining a codeword satisfying the following Equation (1).

[Equation 1]

이다. From here,

to be.

In Equation (1), H denotes a parity check matrix, C denotes a codeword, c _i denotes an i-th bit of a codeword, and N _ldpc denotes a codeword length. Here, h _i denotes an i-th column of the parity check matrix H.

The parity check matrix H is composed of N _ldpc columns equal to the number of bits of the LDPC codeword. Equation 1 means that the sum of the product of the i-th column h _i of the parity check matrix and the i-th codeword bit c _i is '0', so that the i-th column h _i is the i-th codeword bit c _i . < / RTI >

A graphical representation method of an LDPC code will be described with reference to FIG.

FIG. 2 illustrates an example of a parity check matrix H ₁ of an LDPC code including four rows and eight columns, and a diagram thereof as a Tanner graph. Referring to FIG. 2, a parity check matrix H ₁ generates a codeword having a length of 8 because there are eight columns. A code generated through H ₁ means an LDPC code. Bit.

Referring to FIG. 2, a tanner graph of an LDPC code for encoding and decoding based on a parity check matrix H ₁ includes eight variable nodes, that is, x ₁ 202, x ₂ 204, x ₃ 206, x ₄ 208, x ₅ 210, x ₆ 212, x ₇ 214 and x ₈ 216 and four check nodes 218, 220, 222, 224, . Here, the i-th column and the j-th row of the parity check matrix H ₁ of the LDPC code correspond to the variable nodes x _i and j-th check nodes, respectively. The value of 1, that is, a value other than 0 at the intersection of the j-th column and the j-th row of the parity check matrix H ₁ of the LDPC code means that the variable node x _i and the jth check This means that there is an edge connecting the node.

In the Tanner graph of the LDPC code, the degree of the variable node and the check node means the number of segments connected to each node. This means that in the parity check matrix of the LDPC code, 0 Is equal to the number of non-elemental entries. For example, in FIG. 2, variable nodes x ₁ 202, x ₂ 204, x ₃ 206, x ₄ 208, x ₅ 210, x ₆ 212, x ₇ 214 ), the order of the x ₈ (216) are each in sequence 4, 3, 3, 3, 2, 2, 2, and 2, the degree of the check nodes (218, 220, 222, 224) is 6, as each sequence , 5, 5, 5. In addition, the number of non-zero elements in each column of the parity check matrix H ₁ of FIG. 2 corresponding to the variable node of FIG. 2 corresponds to the order 4, 3, 3, 3, 2, 2, And the number of non-zero elements in each row of the parity check matrix H ₁ of FIG. 2 corresponding to the check nodes of FIG. 2 coincides in order with the above-mentioned orders 6, 5, 5 and 5 .

The LDPC code can be decoded using an iterative decoding algorithm based on a sum-product algorithm on the bipartite graph shown in FIG. Here, the summing algorithm is a kind of message passing algorithm, and the message passing algorithm is a method of exchanging messages through an edge on a half-graph and calculating an output message from messages input to a variable node or a check node It shows the algorithm to update.

Here, the value of the i-th encoding bit can be determined based on the message of the i-th variable node. The value of the i-th encoded bit can be either a hard decision or a soft decision. Therefore, the performance of the i-th bit c _i of the LDPC codeword corresponds to the performance of the i-th variable node of the tanner graph, which can be determined according to the position and number of 1s in the i-th column of the parity check matrix. In other words, the performance of the N _ldpc codeword bits of the codeword can be influenced by the position and the number of 1s of the parity check matrix, which indicates that the performance of the LDPC code is greatly affected by the parity check matrix do. Therefore, a method for designing a good parity check matrix is needed to design an LDPC code having excellent performance.

A parity check matrix used in a communication and broadcasting system is typically a quasi-cyclic LDPC code (or QC-LDPC code) using a parity check matrix, .

The QC-LDPC code is characterized by having a parity check matrix composed of a 0-matrix or a circulant permutation matrix having a small square matrix.

More specifically, the QC-LDPC code will be described with reference to the following reference [Myung2006].

Reference [Myung2006]

S. Myung, K. Yang, and Y. Kim, "Lifting Methods for Quasi-Cyclic LDPC Codes," IEEE Communications Letters. vol. 10, pp. 489-491, June 2006.

크기의 순열 행렬(permutation matrix)

을 정의한다. 여기서

는 행렬 상기 행렬 P에서의 i번째 행(row), j번째 열(column)의 원소(entry)를 의미한다.(0 ≤i, j < L) Referring to the reference document [Myung2006], as shown in the following Equation 2

Size permutation matrix

. here

(0? I, j < L) denotes an element of an i-th row and a j-th column in the matrix P,

&Quot; (2) &quot;

(0 ≤ i < L)는

크기의 항등 행렬(identity matrix)의 각 원소들을 i 번 만큼 오른쪽 방향으로 순환 이동(circular shift) 시킨 형태의 순환 순열 행렬임을 알 수 있다. For the permutation matrix P defined above,

(0 < i &lt; L)

It is a circular permutation matrix in which each element of the size identity matrix is circularly shifted to the right by i times.

The parity check matrix H of the simplest QC-LDPC code can be expressed by the following equation (3).

&Quot; (3) &quot;

을

크기의 0-행렬이라 정의할 경우, 상기 수학식 3에서 순환 순열 행렬 또는 0-행렬의 각 지수

는 {-1, 0, 1, 2, ..., L-1} 값 중에 하나를 가지게 된다. 또한 상기 수학식 3의 패리티 검사 행렬 H는 열 블록이 n개, 행 블록이 m개이므로,

크기를 가지게 됨을 알 수 있다. 또한 상기 순환 순열 행렬의 크기는 ZxZ로 표현될수도 있다.if

of

Matrix is defined as a 0-matrix having a size of 0,

Has one of {-1, 0, 1, 2, ..., L-1}. Since the parity check matrix H of Equation (3) has n column blocks and m row blocks,

It is understood that it has a size. The size of the cyclic permutation matrix may be represented by ZxZ.

크기의 이진(binary) 행렬을 패리티 검사 행렬 H의 모행렬(mother matrix) M(H)라 하고, 각 순환 순열 행렬 또는 0-행렬의 지수만을 선택하여 수학식 4와 같이 얻은

크기의 정수 행렬을 패리티 검사 행렬 H의 지수 행렬 E(H)라 한다. Normally, in the parity check matrix of Equation (3), each of the cyclic permutation matrix and the 0-matrix is replaced with 1 and 0,

(H) of the parity check matrix H, and selects only the exponents of the respective cyclic permutation matrixes or the 0-matrices,

The integer matrix of size is called the exponent matrix E (H) of the parity check matrix H.

&Quot; (4) &quot;

Meanwhile, the performance of the LDPC code can be determined according to the parity check matrix. Therefore, it is necessary to design a parity check matrix for an LDPC code having excellent performance. Also, there is a need for an LDPC coding and decoding method capable of supporting various input lengths and coding rates.

In reference to the above reference [Myung2006], a method known as lifting is used for efficient design of a QC-LDPC code. Lifting is a method of efficiently designing a very large parity check matrix by setting a circular permutation matrix or a L value that determines the size of a 0-matrix from a given small mother matrix according to a specific rule. The existing lifting method and QC-LDPC code designed through lifting are briefly summarized as follows.

는

크기의 지수 행렬

을 가지며 각 지수

들은 {-1, 0, 1, 2, ..., L_k - 1} 값 중에 하나로 선택된다. First, S QC-LDPC codes to be designed through a lifting method are C ₁ , ..., C _S when an LDPC code C ₀ is given, and a row block and a column block of a parity check matrix of each QC- The value corresponding to the size of L is called L _k . Here, C ₀ corresponds to the smallest LDPC code having a matrix of C ₁ , ..., C _S as a parity check matrix, and the L ₀ value corresponding to the size of the row block and the column block is 1. For convenience, the parity check matrix of each code _Ck

The

Exponent matrix of size

And each index

Are selected as one of {-1, 0, 1, 2, ..., L _k - 1}.

만 저장하고 있으면 리프팅 방식에 따라 다음 수학식 5를 이용하여 상기 QC-LDPC 부호 C₀, C₁, ..., C_S를 모두 나타낼 수 있다.Looking at the reference [Myung2006], lifting is C ₀ → C ₁ → ... → made of a phase, such as _{C S L k +1 = q k} + 1 L k (q _{k +1} is a positive integer, k = 0, 1, ..., S-1). In addition, the parity check matrix of the C _S by the properties of the lifting process,

The QC-LDPC codes C ₀ , C ₁ , ..., C _S can be represented by the following equation (5) according to the lifting method.

&Quot; (5) &quot;

&Quot; (6) &quot;

In the lifting scheme of Equation (5) or (6), the L _k corresponding to the size of the row block or the column block in the parity check matrix of each QC-LDPC code C _{k has} a multiple relation with each other, Lt; / RTI &gt; The existing lifting method can easily design the QC-LDPC code that improves the error floor characteristics by improving the algebraic or graph characteristics of each parity check matrix designed through lifting.

만을 가질 수 있다. 즉, 리프팅을 10 단계 적용할 경우(S=10) 패리티 검사 행렬은 10개의 크기만을 가질 수 있게 된다. However, since each L _k value is in a multiple relation with each other, the length of each code is severely limited. For example, assuming that a minimum lifting scheme such as L _{k +1} = 2 × L _k is applied to each L _k value, in this case, the size of the parity check matrix of each QC-LDPC code is

. That is, when lifting is applied in 10 steps (S = 10), the parity check matrix can have only 10 sizes.

For this reason, existing lifting schemes have some disadvantages in designing QC-LDPC codes that support various lengths. However, in a commonly used mobile communication system, a very high level of length compatibility is required in consideration of various types of data transmission. For this reason, there is a problem that it is difficult to apply an LDPC code to a mobile communication system in the conventional method.

는

크기의 지수 행렬

을 가진다. 각 지수

들은 {-1, 0, 1, 2, ..., Z-1} 값 중에 하나로 선택된다. (본 발명에서는 편의상 0-행렬을 나타내는 지수를 -1로 표현하고 있지만 시스템의 편의에 따라 다른 값으로 변경될 수 있다.) First, S LDPC codes to be designed through a lifting method are denoted by C ₁ , ..., C _S , and a value corresponding to a size of a row block and a column block of the parity check matrix C _i of each LDPC code is Z . For convenience, the parity check matrix of each code C _i

The

Exponent matrix of size

. Each index

Are selected as one of {-1, 0, 1, 2, ..., Z-1}. (In the present invention, an exponent representing a 0-matrix is represented by -1 for convenience, but may be changed to another value for convenience of the system.)

라 한다. (여기서

는 Z 값 중 최대 값이라 한다) 이 때 Z값이

보다 작을 때에 대한 각 LDPC 부호의 패리티 검사 행렬을 구성하는 순환 순열 행렬 및 0-행렬을 나타내는 지수는 다음과 같은 수학식 7 또는 수학식 8에 따라 결정될 수 있다. Therefore, the exponent matrix of the LDPC code C _S having the largest parity check matrix

. (here

Is the maximum value among the Z values). At this time,

The exponent representing the cyclic permutation matrix and the 0-matrix constituting the parity check matrix of each LDPC code with respect to a smaller size may be determined according to Equation (7) or (8) as follows.

&Quot; (7) &quot;

&Quot; (8) &quot;

는

에 대해 Z로 나눈 나머지를 의미한다.In Equation 7 or Equation 8,

The

&Lt; / RTI &gt;

의 지수 행렬

또는 모행렬

의 열의 개수 n이 36이라 하고, Z의 값을 1, 2, 4, 8, ……, 128과 같은 8 단계 리프팅을 통해 얻을 수 있는 길이의 종류는 36, 72, 144, ……, 4608

이 되어 가장 짧은 길이와 가장 긴 길이의 차이가 매우 크게 된다. However, in [Myung2006], the values of Z are limited to satisfy a multiple relation, so it is not suitable to support various lengths. For example, a parity check matrix

Exponent matrix of

Or a mother matrix

The number n of columns in the matrix is 36, and the value of Z is 1, 2, 4, 8, ... ... , 128 types of lifting, such as 8-stage lifting, 36, 72, 144, ... ... , 4608

So that the difference between the shortest length and the longest length becomes very large.

보다 작을 때에 대해 플로어링 연산에 기반한 리프팅을 적용하여 설계한 패리티 검사 행렬의 지수 변환 방법을 나타낸다.The present invention proposes a method of designing a parity check matrix which can apply the exponent method applied to Equation (9) or Equation (10) without any degradation in performance even when the values of Z are not related to each other. For reference, the method shown in Equation (9) or Equation (10) is an exponential transformation method when a lifting method based on modulo operation is applied. As shown in reference [Myung2006], a method based on a flooring operation or another operation It is obvious that various methods can exist. The following Equation (9) or (10)

The exponential conversion method of the parity check matrix designed by applying lifting based on the flooring operation is shown.

&Quot; (9) &quot;

&Quot; (10) &quot;

Hereinafter, a method of designing a parity check matrix and a method of using the parity check matrix will be described in order to solve the problem of the existing lifting method having a compatibility problem with the length.

In the present invention, the modified lifting process is defined as follows.

1) If the maximum value of Z values is Z _max .

)2) One of the divisors of Z _max is called D. (

)

3) Z is D, 2D, 3D, ... , And SD (= Z _max ).

(For convenience, the parity check matrix corresponding to Z = k x D is _denoted by H _k , and the LDPC code corresponding to the parity check matrix is denoted by C _k .)

In addition to the above-mentioned lifting methods, variable lifting methods can be used to support variable lengths.

Next, the encoding method of the QC-LDPC code will be described in more detail with reference to the reference [Myung2005].

Reference [Myung2005]

S. Myung, K. Yang, and J. Kim, "Quasi-Cyclic LDPC Codes for Fast Encoding," IEEE Transactions on Information Theory, vol. 51, No. 8, pp. 2894-2901, Aug. 2005.

FIG. 3 is a diagram illustrating a basic structure of a parity check matrix proposed in the present invention.

Referring to the reference [Myung2005], a special type of parity check matrix composed of a cyclic permutation matrix is defined as shown in FIG. Also, it is shown that efficient coding can be achieved by satisfying the following Equation (11) or Equation (12) in the parity check matrix of FIG.

&Quot; (11) &quot;

&Quot; (12) &quot;

값은

가 위치하고 있는 행(row)의 위치를 의미한다. In the equations (11) and (12)

The value is

Is the position of the row in which the data is located.

로 정의된 행렬이 항등 행렬이 되어 부호화 과정에서 효율적인 부호화가 가능함이 잘 알려져 있다. When the above Equation (7) and Equation (8) are satisfied, as described in reference document [Myung2005]

It is well known that a matrix defined as an identity matrix can be efficiently encoded in the encoding process.

In the present invention, only one cyclic permutation matrix corresponding to one block is explained. However, the same invention can be applied to a case where a plurality of cyclic permutation matrixes are included in one block.

4 is a block diagram of a transmitting apparatus according to an embodiment of the present invention.

4, the transmission apparatus 400 includes a segmenting unit 410, a zero padding unit 420, an LDPC encoder 430, a rate matching unit 440, And may include a modulator 450.

Here, the components shown in FIG. 4 are components that perform encoding and modulation for variable length input bits, which is an example only, and in some cases, some of the components shown in FIG. 4 May be omitted or changed, and other components may be added.

5 is a block diagram of a receiving apparatus according to an embodiment of the present invention.

5, the receiving apparatus 500 includes a demodulator 510, a rate dematcher 520, an LDPC decoder 530, a zero eliminator 540, and a desegmenter 530 to process variable length information. And a mentation unit 550.

Here, the components shown in Fig. 5 are components that perform the functions corresponding to the components shown in Fig. 4, which are only examples, and in some cases, some of them may be omitted or changed, .

6A and 6B are diagrams illustrating the characteristics of the LDPC parity check matrix used in the present invention.

Embodiments of a parity check matrix designed in consideration of HARQ (Hybrid Automatic Repeat reQuest) scheme based on various coding rates and IR (Incremental Redundancy) are shown in FIGS. 6A and 6B. 6A and 6B, the degree of the parity check matrix corresponding to the incremental redundancy bits is one. In addition, the column blocks having the order of 1 are composed of one cyclic permutation matrix and a '0' matrix. Depending on the type of the parity check matrix, the incremental redundancy bits are generated by a single parity check extension. The incremental redundancy bits may also be transmitted in the initial transmission.

Referring to FIG. 6A, the size of the LDPC parity check matrix used in the present invention varies according to the coding rate. For example, when a high coding rate is applied, the parity check matrix corresponds to sub-matrix 1 (600), which includes a portion for information bits and one bit for parity. However, when the coding rate is lower than that, the parity check matrix corresponds to sub-matrix 2 (610), which is a systematic part for the IR bit and the single parity check code as well as the sub- And the IR bit and the systematic part included in the parity check matrix become larger as the coding rate is lowered.

FIG. 6B is a more detailed view of FIG. 6A. The portion for the information bits of the parity check matrix is composed of K _b column blocks. The sub-matrix 2 consists of N _b column blocks. In this case, the length of the codeword is N _b × Z.

The parity check matrix using the concatenation with a single parity check code is advantageous in that the IR (Incremental Redundancy) technique is applied because it is easy to expand. Since the IR scheme is an important technology for supporting HARQ (Hybrid Automatic Repeat reQuest), an efficient IR scheme with high performance increases the efficiency of the HARQ system. The LDPC codes based on the parity check matrices can be efficiently and efficiently implemented by generating and transmitting new parity using a portion extended by a single parity check code.

It is obvious that LDPC coding having various block lengths and coding rates can be applied if shortening and puncturing are appropriately applied to the LDPC code corresponding to the parity check matrix described in the present invention. In other words, it is possible to support various information word lengths by applying appropriate shortening to the LDPC code corresponding to the parity check matrix, and it is possible to support various coding rates by appropriately applying puncturing, and to generate and transmit a single parity check bit So that an efficient IR technique can be applied.

On the other hand, the LDPC code can be decoded using an iterative decoding algorithm based on the sum algorithm on the half graph shown in FIG. 2, and the summing algorithm is a kind of a message passing algorithm.

Hereinafter, a message passing operation generally used in LDPC decoding will be described with reference to FIGS. 7A and 7B.

7A and 7B are diagrams illustrating a message passing operation performed in an arbitrary check node and variable node for LDPC decoding.

7A shows a plurality of variable nodes 710, 720, 730, 740 connected to the check node m 700 and the check node m 700. In the illustrated example, T _{n ', m} represents a message passed from the variable node n' 710 to the check node m 700, and E _{n, m} represents a message from the check node m 700 to the variable node n 730, The message being passed through. Let N (m) denote the set of all variable nodes connected to the check node m (700) and define N (m) \ n as the set excluding N (m) .

In this case, a message update rule based on the sum-of-product algorithm can be expressed by Equation (13).

&Quot; (13) &quot;

는 하기의 수학식 14와 같이 나타낼 수 있다. Here, Sign (E _{n, m} ) represents the sign of the message E _{n, m} , and | E _{n, m} | represents the magnitude of the message E _{n, m} . Meanwhile,

Can be expressed by the following equation (14).

&Quot; (14) &quot;

7B shows a plurality of check nodes 760, 770, 780 and 790 connected to the variable node x 750 and the variable node x 750. In the illustrated example, E _{y ', x} represents a message passed from the check node y' 760 to the variable node x 750, and T _{y, x} represents the variable node y 780 in the variable node x 750, Message. &Lt; / RTI &gt; Define a set of all variable nodes connected to the variable node x 750 as M (x) and define a set excluding M (x) as the check node y (780) as M (x) \ y . In this case, a message update rule based on the sum-of-product algorithm can be expressed by the following equation (15).

&Quot; (15) &quot;

Here, E _x denotes the initial message value of the variable node x.

When the bit value of the node x is determined, it can be expressed by the following equation (16).

&Quot; (16) &quot;

In this case, the encoding bit corresponding to the node x can be determined according to the P _x value.

7A and 7B, since the above-described method is a general decoding method, a detailed description will be omitted. However, in addition to the methods described in FIGS. 7A and 7B, other methods may be applied to determine the passed message values at variable nodes and check nodes (Frank R. Kschischang, Brendan J. Frey, and Hans-Andrea Loeliger, Factor Graphs and the Sum-Product Algorithm, " IEEE TRANSACTIONS ON INFORMATION THEORY, Vol. 47, No. 2, FEBRUARY 2001, pp 498-519).

Hereinafter, the operation of the transmitter will be described in detail based on FIG.

4, the transmitting apparatus 400 includes a segmenting unit 410, a zero padding unit 420, an LDPC encoder 430, a rate matching unit 440, and a modulation Unit 450 as shown in FIG.

Here, the components shown in FIG. 4 are components for performing encoding and modulation on variable-length input bits, which is only an example, and in some cases, among the components shown in FIG. 4 Some of which may be omitted or changed, and other components may be added.

Meanwhile, the LDPC encoder 430 shown in FIG. 4 can perform operations performed by the LDPC encoder 810 shown in FIG.

On the other hand, the transmitting apparatus 400 receives the necessary parameters (e.g., input bit length, modulation and code rate, parameters for zero padding, code rate / code length of LDPC code, parameters for interleaving, Parameters for repetition, parameters for puncturing, parameters for retransmission, and modulation scheme, etc.), and based on the determined parameters, can be encoded and transmitted to the receiving apparatus 500 of FIG.

In case that the number of input bits is variable, when the number of input bits is larger than a preset value, the input bit may be segmented so as to have a length equal to or less than a predetermined value. Also, each of the segmented blocks may correspond to one LDPC coded block. However, if the number of input bits is less than or equal to a predetermined value, the input bits are not segmented. The input bits may correspond to one LDPC coded block.

By making the lengths of the segmented code blocks the same, the coding and decoding parameters of the LDPC codes of the respective code blocks are made the same, and the implementation complexity can be lowered. In addition, the coding performance can be improved by making the '0' bits of each code block as equal as possible.

Rate matching input bits of the unit 440 are output to the bits of the LDPC encoder _{(430) C = (i 0} , i 1, i 2, ..., i Kldpc -1, p 0, p 1, p ₂ , ... , p _{Nldpc - Kldpc -1} ). i _k (0? k < K _ldpc ) denotes input bits of the LDPC encoding unit 430 and p _k (0? K < N _ldpc - K _ldpc ) denote LDPC parity bits. The rate matching unit 440 includes an interleaver 441 and a puncturing / repetition / zero elimination unit 442.

The modulator 450 modulates the bit stream output from the rate matching unit 440 and transmits the modulated bit stream to a receiving apparatus (e.g., 500 in FIG. 5).

Specifically, the modulator 450 demultiplexes the bits output from the rate matching unit 440 and maps the demultiplexed bits to a constellation.

That is, the modulator 450 can perform serial-to-parallel conversion of the bits output from the rate matching unit 440 to generate a cell having a predetermined number of bits. Here, the number of bits constituting each cell may be equal to the number of bits constituting the modulation symbol mapped to constellation.

Thereafter, the modulator 450 may map the demultiplexed bits to constellation. That is, the modulator 450 modulates the demultiplexed bits through various modulation methods such as QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM to generate modulation symbols You can map to a constellation point. In this case, each cell may be sequentially mapped to a gender point in that demultiplexed bits constitute a cell containing as many bits as the number of modulation symbols.

The modulator 450 may modulate the signal mapped to the constellation and transmit the modulated signal to the receiver 500. [ For example, the modulator 450 may use an Orthogonal Frequency Division Multiplexing (OFDM) scheme to map a signal mapped to the constellation to an OFDM frame and transmit the mapped signal to the receiver 500 through the allocated channel.

On the other hand, the transmission apparatus 400 may store various parameters used for coding, interleaving, and modulation. Here, the parameters used for coding may be information on the code rate of the LDPC code, the codeword length, and the parity check matrix. A parameter used for interleaving may be information on an interleaving rule, and a parameter used for modulation may be information on a modulation scheme. Further, the information on the puncturing can be a puncturing length. In addition, the information about repetition can be the repetition length. The information on the parity check matrix may store the exponent value of the circulation matrix according to Equation (3) and Equation (4) when the parity matrix proposed in the present invention is used.

In this case, each component constituting the transmitting apparatus 400 can perform an operation using these parameters.

Although not shown, the transmitting apparatus 400 may further include a controller (not shown) for controlling the operation of the transmitting apparatus 400 according to circumstances.

In the present invention, the rate matching unit 440 method and apparatus for supporting Hybrid Automatic Repeat reQuest (HARQ) based on the LDPC code will be described.

8 is a flow chart illustrating the operation of the transmitter according to the present invention. Hereinafter, a transmission method based on the LDPC code disclosed in the present invention will be described with reference to FIG.

In step 810, the transmitter determines a modulation order of a modulation symbol for transmission, a transport block size (TBS), and a redundancy version index (rd _idx ) The redundancy version index (rv _idx ) is an integer smaller than a predetermined maximum value as an index value of the redundancy version, and the position of the transmission start bit is determined The number of the rv _idx may be different depending on the system, and in the LTE standard, rv _idx exists in four of 0, 1, 2 or 3. The rv _idx is determined at each transmission in the transmitter, Alternatively, rv _idx can be determined at the receiver and informed to the transmitter, and the transmitter can use the determined rv _idx . _{In the} LTE system, the determination of the rv _idx value in the uplink retransmission is determined in the order of 0, 2, 3, 1, and this value is updated by the modulo 4 operation. Order and rv _idx can be determined in step 860.

In step 820, the transmitter segments a transport block (TB) into a code block (CB) unit based on the determined TBS value. The code block size (CBS) value is determined by the segmentation process. In step 830, the transmitter calculates a K _b value, which is the number of column blocks of the information part of the parity check matrix, according to the determined parameters of the parity check matrix of the CBS and the LDPC code and a cyclic permutation matrix constituting the QC-LDPC code The size Z value of the 0-matrix is determined. In step 840, the transmitter determines the number of column blocks N _b of the parity check matrix considering the retransmission, the exponent value shift values of the respective cyclic permutation matrixes of the parity check matrix (PCM), and the number N _cb of codeword bits considering the retransmission do. The N _cb is the same value as N _b × Z may be determined differently from the N _b × Z by a predetermined rule, and may also be determined in the subsequent step 840. N _b is the number of column blocks of the parity check matrix of the LDPC code, and may be different according to the CBS length. The maximum number of column blocks of the parity check matrix of the LDPC code is determined as N _{b_max} , and N _b is smaller than or equal to N _{b_max} .

The N _cb may differ depending on the maximum value of rv _idx . A particular code rate and a particular UE category (category) or a parity check matrix or the uplink / downlink count and maximum of the range (rv _idx of rv _idx according to at least one element of the length or information word on (UL / DL) ) May be different, so that the actual number of bits to be encoded may differ. N _cb is determined differently depending on at least one element of the specific code rate and the specific UE category or parity check matrix or the uplink / downlink (UL / DL) or the length of the information word irrespective of the rv _idx range. .

[First embodiment of processes 850 and 860]

In step 850, the transmitter performs LDPC encoding and interleaving based on the determined parameters. The interleaving may be performed only when necessary. There may be a plurality of parity check matrices used for the LDPC encoding, and a parity check matrix used for encoding among a plurality of parity check matrices is determined according to a predetermined rule. The size of the parity check matrix used in the LDPC coding may be different according to rv _idx and the coding rate. The actual encoding can be performed up to N _cb or based on the rv _idx value and only for the bits necessary for the current transmission. For example, if rv _idx is 0, the encoding is performed by E or E + Z or E + 2xZ, which is a value obtained by adding the bits (= E) necessary for transmission and the number of bits to be punctured (0 or Z or 2xZ) ). &Lt; / RTI &gt;

를 전송한다. 즉 과정 850의 출력 비트 스트림 W = (w₀, w₁, w₂,…,w_Ncb)과 부호어 비트의 개수 N_cb와 전송 비트의 개수 E와 전송 시작 비트의 index k₀를 기반으로 아래와 같이 비트 스트림이 전송된다. 상기 전송 비트의 개수 E는 할당된 부반송파(subcarrier) 수와 변조 방식에 기반하여 결정되는 값으로 860단계 이전에 결정 할 수 있다. e_k는 w_k 중에서 선택되어 전송되는 비트를 의미한다.In step 860, the transmitter determines a starting position k ₀ of bits to be transmitted among the LDPC coded bits and a number E of transmitted bits. The starting position k ₀ is determined by the rv _idx . In step 870, the transmitter transmits the output bit stream (w ₀ , w ₁ , w ₂ , ..., w _Ncb ) of the process 850

. That is, based on the output bit stream W = (w ₀ , w ₁ , w ₂ , ..., w _Ncb ) of the process 850, the number N _cb of codeword bits, the number E of transmission bits and the index k ₀ of the transmission start bit, The bitstream is transmitted as well. The number of transmission bits E is a value determined based on the number of allocated subcarriers and the modulation scheme, and may be determined before 860 steps. and e _k means a bit selected and transmitted from w _k .

In the above, < NULL > denotes a bit padded with zeros. In addition, the specific bits of the information bits may not always be transmitted.

As another example of step 870, it may be considered that certain bits of the information bits are not always transmitted. The specific bits are referred to as punctured systematic bits.

[Second embodiment of processes 850 and 860]

The output bit streams _{(w 0, w 1, w} 2, ..., w Ncb) of always punctured bit stream information word other than the bits _{(x 0, x 1, x} 2, ..., x Ncb_ext) and code The bit stream is transmitted based on the number of bits N _cb , the number of transmission bits E, and the index k ₀ of the transmission start bit as follows. Ncb_ext = Ncb - Nsym_p where Nsym_p is the number of information bits that are always punctured. For example, when 2 * Z information bits are punctured, Ncb_ext = Ncb -2 * Z. Also, if the shortened Ns bits are excluded, Ncb_ext = Ncb - Nsym_p - Ns. The number of transmission bits E is a value determined based on the number of allocated subcarriers and the modulation scheme, and may be determined before 860 steps. e _k means a bit selected and transmitted from x _k .

or

or

or

Where m is the number of rv_idx. The position (bit index) K ₀ of the bit at which the transmission starts is described in more detail below in various embodiments of the present invention.

[Third embodiment of processes 850 and 860]

The output bit streams _{(w 0, w 1, w} 2, ..., w Ncb) of always punctured bit stream information word other than the bits _{(x 0, x 1, x} 2, ..., x Ncb_ext) and code The bit stream is transmitted based on the number of bits N _cb , the number of transmission bits E, and the index k ₀ of the transmission start bit as follows. Ncb_ext = Ncb - Nsym_p where Nsym_p is the number of information bits that are always punctured. For example, if 2 * Z information bits are punctured, Ncb_ext = Ncb - 2 * Z. Also, if the shortened Ns bits are excluded, Ncb_ext = Ncb - Nsym_p - Ns. The number of transmission bits E is a value determined based on the number of allocated subcarriers and the modulation scheme, and may be determined before 860 steps. e _k means a bit selected and transmitted from x _k .

or

or

or

Where m is the number of rv_idx. The position (bit index) K ₀ of the bit at which the transmission starts is described in more detail below in various embodiments of the present invention.

9 is a diagram illustrating a process of encoding data according to the present invention. 9, in a transmitter, a transport block is segmented into an information block, and an information word block includes a zero padding bit so that the total length is K _b × Z, that is, a multiple of Z . Thereafter, the information word block is LDPC-encoded, and the total length of the codeword is N _b × Z. The codeword bits may be interleaved. The position of k ₀ is determined, and the transmitter removes the zero padded bits and transmits the codeword bits.

According to the present invention, the transmitter determines a k ₀ (= S _idx ) value indicating the position of the transmission start bit from the rv _idx and sequentially transmits the determined codeword from the codeword bit having the determined k ₀ value as an index. Sent in is the rv_idx (= 0, 1, 2 or 3) it is not necessary to determine all S _idx according to, on the basis of rv _idx be transferred by determining the index (i.e. S _idx or k ₀₎ of the transmission start bit have. If the reduction version (RV) is defined as m, then RV = {rv ₀ , rv ₁ , ..., rv _(m-1) } and rv _idx = { _0,1,2 ... , m-1}. rv index of start bit based on _idx S = {s ₀ , s ₁ , ... , s _(m-1) }.

FIG. 9A is a view showing the second embodiment and the third embodiment. And a part of the information bits are always punctured and not input to the circular buffer.

In the present invention, first, a method of determining the order of transmission, that is, the order of Redundancy Version (RV) at the time of data retransmission will be described. The order of the RVs can be set differently according to the index of the modulation and coding scheme (MCS). That is, the order of the redundancy version is defined according to the MCS index (I _MCS ).

The current LTE standard provides the HARQ mode as shown in Table 1 below.

[Table 1]

In the LTE uplink (UL) transmission, in the case of retransmission in the non-adverse HARQ operation, the base station transmits a downlink (DL) physical HARQ channel without transmitting separate downlink control information (DCI, (PHICH), the mobile station automatically performs retransmission in order of Redundancy Version (RV) 0, 2, 3 and 1 at a predetermined point in time.

However, when LDPC codes are used, additional considerations arise because the matrix for LDPC code may change if the code rate is changed during data transmission. The present invention proposes a method for transmitting LDPC codeword bits from a specific bit position based on rv _idx in order to support the IR mode.

FIG. 10 is a diagram showing the positions of LDPC codewords and predetermined bits for the retransmission. According to FIG. 10, the positions of specific bits among the LDPC codeword bits can be designated by rv (redundancy version). In the case of FIG. 8, rv ₀ (1000), rv ₁ (1010), rv ₂ (1020), ... , the position of m specific bits of rv _m-1 (1030) is specified by the value of rv or rv _idx . rv _idx of rv ₀ (1000) of rv _idx is 0 rv _idx of rv ₁ (1010) is 1, and rv _idx of rv ₂ (1020) is 2, rv _m-1 (1030) is the (m-1) . The transmitter can transmit the LDPC codeword from the location indicated by rv. For example, the first bit may be transmitted from the bit indicated by rv ₀ , and in the second transmission, the bit indicated by rv ₁ may be transmitted.

According to the present invention, starting positions according to the initial transmission or retransmission are determined according to a predetermined rule, and in particular, a method of changing a transmission order according to an initial transmission code rate is disclosed. Or a method for changing the order according to the retransmission coding rate. The transmission order is a sequence of rv _idx or a sequence of transmission start bit index.

When data is transmitted from a start position determined by the predetermined rule, additional signaling bits are not needed, thereby reducing system overhead. On the other hand, since the data is transmitted according to a predetermined rule, there may be a limit on the coding gain that can be obtained depending on the coding rate.

11A and 11B are diagrams showing codewords which are redundant in retransmission according to a coding rate. 6A and 6B according to an embodiment of the present invention, when an LDPC code is encoded based on the parity check matrix of the present invention, retransmission is as follows. In FIGS. 6A and 6B, the parity bits in the incremental redundancy bits part of the parity bits encoded based on the parity check matrix have high importance of the front parity bits close to the information bits, so that when the parity bits are selected in order during retransmission A high coding gain can be obtained. Also, as the bit redundancy that occurs during retransmission is reduced, the efficiency increases. That is, a high coding gain can be obtained when the signals are sequentially transmitted without redundancy. That is, a lower error probability.

As shown in FIG. 11A, when the code rate is low, the RV is rv0 (rv _idx = 0) in the initial transmission 1100 and the RV is rv1 (rv _idx = 1) in the first retransmission 1110, When the RV is rv2 (rv _idx = 2) at the retransmission 1120, the encoding gain can not be maximized because there are many bits to be transmitted redundantly. Therefore, when the RV is _{0 in the} initial transmission and the RV of the first retransmission is not rv ₁ , a high coding gain can be obtained.

However, as shown in FIG. 11B, when the code rate is high, the RV is rv0 at the initial transmission 1150, and when the RV at the first retransmission 1160 is rv1, the codeword bits transmitted from the bits indicated by rv0 and rv1 The number of bits to be transmitted redundantly may be less or not as compared with the case of transmission at a low code rate. Therefore, a higher coding gain can be obtained than in the case of Fig. 11A.

Considering this point, a method for determining the transmission order in retransmission according to the present invention is as follows.

First, one of the predetermined transmission orders can be selected and applied according to the initial transmission code rate. For example, if there are four rv values, one of the following four transmission sequences can be selected according to the coding rate.

[Table 2]

Second, a codeword can be transmitted by selecting one of the four transmission sequences according to an allocated modulation and coding scheme (MCS) index, for example, among the methods of specifying the transmission order.

[Table 3]

The code rate may not be specified in the MCS table of Table 3. [

Third, according to the present invention, an effective code rate (R _eff ) determined by an MCS index, a transport block size (TBS) and a number of sub-carriers to which a codeword bit is to be transmitted, ( _{Rth_i} , i = 0, 1, 2,..., N _order -1) for the rate of change in the RV sequence. This method can be performed according to Equation (17) below. R _eff is the number of transport block size (TBS) bits and the ratio of the TBS-based codeword bits transmitted. Method for calculating the actual code rate can vary according to the frame configuration, for example the number of _{(TBS + N CRC) / (} N PRB × ( resource elements (resource element, RE) per PRB - #RE for reference signaling ) X modulation order). Where N _CRC is the number of CRC bits and may be zero. N _PRB denotes the number of allocated resource blocks and # RE for reference signaling denotes the number of resource elements to which reference signaling is allocated. TBS means the number of bits that can be transmitted when a specific I _TBS and N _PRB are applied. Or when the TB (Transport Block) is segmented into a plurality of CBs and retransmitted in CB units or CBGs, R _eff is the size of CB or the number of bits of CBG and CB or CBG are transmitted May be a ratio of the number of codeword bits.

&Quot; (17) &quot;

RV index order indicator = i if R _eff <R _th - i (0? I <N _order )

N _order is the maximum value of the possible RV index order indicators specified in Table 2, which means the maximum number of RV index orders. The R _eff may be determined based on the I _MCS .

When using this method, the transmitter can perform data transmission in a predetermined order even if the receiver does not directly inform the rv _idx value by using signaling such as DCI.

In addition, rv _idx sequences of different patterns can be used for each parity check matrix, or the TBS index or MCS index (I _MCS ) and N _PRB (size of physical resource used in data transmission) determined according to the MCS index and modulation order The rv _idx order can be determined.

Alternatively, according to the present invention, the same effect can be obtained by fixing the non-adoptive rv _idx order, and then using an interleaver according to the initial transmission code rate.

12A and 12B are diagrams illustrating codewords transmitted when the interleaver is used differently. According to FIGS. 12A and 12B, 1200 means that the transmission order is fixed and codewords are transmitted in the order of rv ₀ , rv ₁ , rv ₂ and rv ₃ . At this time, the code word bits _{(= c 0, c 1,} c 2, ..., c N-1) and based on the bits that the S _idx designated by rv _idx the index is divided into bit groups. The first bit group (Bit Group 0) consists of c _s0 to c _{s1-1} . The second bit group (Bit Group 1) consists of c _s1 to c _{{s 2 - 1}} . The third bit group (Bit Group 2) consists of c _s2 to c _{s3-1} . The fourth bit group (Bit Group ₃ ) consists of c _s3 to c _{N} . The fifth bit group (Bit Group 4) consists of c _s0 to c _{s1-1} .

In this case, when the interleaver 1 is applied, the interleaver 1 arranges the bit groups in the order of Bit Group 4, Bit Group 0, Bit Group 2, Bit Group 1 and Bit Group 3 (1210). In this case, Even if the same rv _idx sequence is used, the starting point of the actually transmitted bits can be changed. When the interleaver 3 is applied, the interleaver 3 (1230) arranges the bit groups in the order of bit groups 0, 3, 1, and 2. In this case, even if the transmitter uses the same rv _idx sequence as that when the interleaver is not used, The starting point of the transmitted bit can be changed. Therefore, the same effect as that of using the interleaver according to the coding rate can be obtained by _changing the rv _idx order according to the coding rate as described above. Therefore, as a method for reducing the signaling overhead, the rv _idx sequence is used in a predetermined order and an encoding gain can be obtained using another interleaver according to the initial transmission code rate.

Also, the present invention discloses a method of determining an index of bits designated by rv _idx (redundancy version index), i.e., S _idx value. As described above, the S _idx value is determined from the rv _idx determined when transmitting the codeword bits, and the S _idx value is sequentially transmitted from the bit having the index as the index.

First, the number of codeword bits considering the maximum rv _idx value (= m-1) according to the code rate at the initial transmission can be determined, and the interval of S _idx values referred to by each rv _idx can be adjusted. When the code rate is high at the initial transmission, the code rate at the retransmission based on the maximum rv _idx value may be higher than the minimum code rate that can be supported by the LDPC code. For example, if the code rate at initial transmission is 8/9, the minimum code rate that can be supported is 1/5, and the maximum value (m-1) of rv _idx is 3, the code rate at maximum retransmission is 8/36 (= 8/9 x 1/4), which is higher than 1/5. In this case, if the number of codeword bits (= N _cb ) is determined based on a coding rate of 8/36 and S _idx is set based on the number of codeword bits, the number of codeword bits (= N _cb ) , And a higher coding gain can be obtained than when S _idx is set based on this determination.

According to the present invention, when the maximum value of rv _idx is (m-1), the length N _cb of the codeword bits is set to be equal to or smaller than k / R * m. k is the number of information bits and may be the same as CBS or equal to K _b × Z. The code rate R may be specified as a value according to I _MCS in the MCS table or an effective code rate may be used. The effective sub-efficiency may be changed according to the number of information bits and the number of RBs allocated for transmission (i.e., size of resources).

For example, N _cb may be determined based on Equation (18) below.

&Quot; (18) &quot;

또는,

or,

It may be considered that the Nsym_p bits are not always transmitted among the information bits. The specific bits are referred to as punctured systematic bits.

In this case, the Ncb_ext of the second embodiment is determined based on Equation 18-A below.

&Quot; (18-1) &quot;

Ns is the number of the shortening bits.

The Ncb and Ncb_ext are used to select a smaller value by comparing the values with the limited buffer size when the limited buffer is used.

The N _b is the number of column blocks of the parity check matrix of the LDPC code, and may be varied according to the CBS length. The N _b is equal to or less than the number N _bmax of the maximum column blocks of the parity check matrix. Also, as mentioned above, N _cb may be added to at least one element of the specific code rate and the specific UE category, or whether it is a parity check matrix, uplink or downlink (UL / DL) Can be determined differently. k may be the same value or zero padding on CBS (zero padding) the number of input bits of the LDPC code, a value obtained by adding the number of bits (K _b × Z) and CBS. In this case, 0, 1, ... The index k ₀ of the (m-1) of one of the _idx value S based on rv _idx determined value or transmission start bit may be determined according to Equation 19 below.

&Quot; (19) &quot;

또는,

or,

The m value may be different according to the initial transmission code rate. Or the m value may be different according to the parity check matrix, and may be different depending on the UE category or DL or UL. a denotes the position of S ₀ with rv _idx = 0. a may be the same as the size Z of the sub-matrix of the parity check matrix of the LDPC code, or may be a multiple of Z or 0.

The transmitter may perform up to N _cb when performing the actual encoding, or may only perform up to the bit required for transmission.

Second, the S _idx values, that is, the value of k _0, is a multiple of the lifting value Z for determining the parity check matrix. This is a method for facilitating the decoder operation. FIG. 13A is a diagram illustrating a method of determining a retransmission start point, in particular, an S _idx value determined by rv _idx determined according to the above method. The position of the S _idx value is located at a multiple of Z as shown in FIG. In the present invention, the S _idx values are determined in a state including zero padding bits.

At this time, S _idx can be determined as shown in Equation (20) below.

&Quot; (20) &quot;

또는,

or,

또는,

or,

또는

or

The rv _idx is 0? I <m and the m may vary according to the coding rate. N _cb is the number of codeword bits considering retransmission and can be determined as in Equation (17). Or N _cb = min (N _bmax * Z, N _max ). N _bmax is the maximum number of column blocks of the parity check matrix shown in FIGS. 6A and 6B. N _max is the number of the predetermined maximum encoding bits. If N _max is not set, N _cb = N _bmax x Z can be obtained. Also, as mentioned above, N _cb is determined differently according to at least one element of the specific code rate and the specific UE category or parity check matrix, whether uplink or downlink (UL / DL), or information word length . a denotes the position of S ₀ with rv _idx = 0. a may be the same as the size Z of the sub-matrix of the parity check matrix of the LDPC code, or may be a multiple of Z or 0. The actual encoding may be performed up to N _cb or only for the bit (= E) required for transmission.

Third, the interval between S _idx can be set differently according to the coding rate. Specifically, the position of the transmission start point can be determined by Equation (21) below.

&Quot; (21) &quot;

또는,

or,

는 상위 레이어 시그널링(higher layer signaling, 이는 RRC signaling으로도 해석할 수 있다) 또는 MAC CE 또는 하향링크 물리 계층 신호(L1 DL control)에 의해 미리 설정(configuration)된 값일 수 있고, 또는 직접 송수신기가 계산할 수 있다. 또한 상기

는 부호율 및 정보어 길이(즉 CBS)에 따라 달리 결정될 수 있다. 구체적으로 MCS 인덱스 또는 MCS 인덱스와 변조 차수에 따라 결정된 TBS 인덱스 또는 MCS 인덱스와 N_PRB(데이터 전송시 사용되는 물리 자원의 크기)에 따라 미리 결정되어 있을 수 있다. 일례로

이고 상기 R은 초기 전송 부호율로 MCS 인덱스에 의해 결정될 수 있다. 또한 상기

는 패리티 검사 행렬 및 UE 카테고리에 따라 다를 수 있다. rv_idx는 0≤i<m이고 상기 m은 부호율에 따라 다를 수 있다. N_cb는 재전송을 고려한 부호어 비트의 개수로 상기 수학식 17과 같이 결정될 수 있다. 또는 N_cb = min(N_bmax×Z, N_max)로 결정될 수 있다. 또는 N_cb = min(N_b×Z, N_max)로 결정될 수 있다. N_bmax는 도 6a과 도 6b에서 도시한 패리티 검사 행렬의 열 블록의 최대 개수이고, N_b는 N_bmax보다 작거나 같은 값으로 소정의 규칙에 의해 결정된다. N_max는 기설정된 최대 부호화 비트의 개수이다. N_max를 설정하지 않았을 경우에는 N_cb = N_bmax×Z 또는 N_cb = N_b×Z 로 설정된다. 또한 상기에서 언급한 바와 같이 N_cb는 특정 부호율 및 특정 UE 카테고리(category) 또는 패리티 검사 행렬 또는 상향링크 또는 하향링크(UL/DL) 여부 또는 정보어의 길이 중 적어도 하나의 요소에 따라 다르게 결정될 수 있다. a 는 rv_idx=0인 S₀의 위치를 의미한다. a는 LDPC 부호의 패리티 검사 행렬의 서브 행렬의 크기 Z와 동일 하거나 Z의 배수 혹은 0일 수 있다. 이 때 실제 부호화는 N_cb까지 수행되거나 전송시 필요한 비트(=E, 이는 전송하는 부호어 비트의 개수로 이해될 수 있다)에 대해서만 수행될 수도 있다. 또한 상기 세 번째 방법에 의하여 S_idx를 결정할 경우 작은 idx의 S_idx 값이 큰 idx의 S_idx 보다 더 클 수 있다. 즉 S₁>S₂ 일 수 있다. remind

May be a value preconfigured by higher layer signaling (which may also be interpreted as RRC signaling) or MAC CE or DL physical layer signal (L1 DL control), or may be a value that is directly calculated by the transceiver . Further,

May be determined differently depending on the code rate and the information word length (i.e., CBS). Specifically, it may be determined in advance according to the TBS index or MCS index determined according to the MCS index or the MCS index and the modulation order, and N _PRB (the size of the physical resource used in data transmission). For example

And R may be determined by an MCS index at an initial transmission code rate. Further,

May vary depending on the parity check matrix and the UE category. rv _idx is 0? i <m and m may be different according to the coding rate. N _cb is the number of codeword bits considering retransmission and can be determined as in Equation (17). Or N _cb = min (N _bmax x Z, N _max ). Or N _cb = min (N _b x Z, N _max ). N _bmax is the maximum number of column blocks of the parity check matrix shown in FIGS. 6A and 6B, and N _b is a value less than or equal to N _bmax , and is determined according to a predetermined rule. N _max is the number of the predetermined maximum encoding bits. When N _max is not set, N _cb = N _bmax x Z or N _cb = N _b x Z is set. Also, as mentioned above, N _cb is determined differently depending on at least one element of the specific code rate and the specific UE category or parity check matrix, whether uplink or downlink (UL / DL), or information word length . a denotes the position of S ₀ with rv _idx = 0. a may be the same as the size Z of the sub-matrix of the parity check matrix of the LDPC code, or may be a multiple of Z or 0. In this case, the actual encoding may be performed only for N _cb or for bits required for transmission (= E, which can be understood as the number of codeword bits to be transmitted). Also, when the S _idx is determined by the third method, the S _idx value of the small idx may be larger than the S _idx of the large idx. I.e. S ₁ &gt; S ₂ .

If the RV value is rv _i, that is, rv _idx = i, when the transmitted bits and the RV value are rv _{i + 1,} that is, rv _idx = (i + 1), the same bits It is possible to maximize the coding gain by sequentially using RVs during retransmission.

As described in the second and third embodiments, when the specific information bits are not always transmitted, the Ncb value of Equation (21) can be determined by Equation (18-1). In the case of Embodiment 2, a may be 0 in Equation (21).

에 대해 상세히 설명한다. HARQ-IR 방식을 사용할 경우 상기 기술한 바와 같이 재전송을 통해 최대한 새로운 부호어 비트를 전송해야 부호어 이득을 얻을 수 있다. 그러므로 부호율에 따라 rv값에 따른 전송 시작 비트의 위치를 달리해야 부호어 이득을 최대로 얻을 수 있다. 이 때 구체적인 전송 시작점의 위치는 아래 수학식 22와 같이 특정 값

를 기반으로 하여 패리티 검사 행렬의 순환 순열 행렬의 사이즈의 배수로 결정될 수 있다.Hereinafter,

Will be described in detail. When the HARQ-IR scheme is used, a codeword gain can be obtained by transmitting a new codeword bit as much as possible through retransmission as described above. Therefore, it is necessary to vary the position of the transmission start bit according to the rv value according to the coding rate to obtain the maximum gain of the codeword. At this time, the specific position of the transmission start point is a specific value

The size of the cyclic permutation matrix of the parity check matrix may be determined.

&Quot; (22) &quot;

또는,

or,

The value a may be a predetermined value to the position of the transmission start bit when rv _idx = 0. As mentioned in the second and third embodiments, when the specific information bits are not always transmitted, the Ncb value of Equation (22) can be determined by Equation (18-A). In the case of the second embodiment, a in the equation (22) may be zero.

은 부호율 및 정보어 길이(즉 CBS)에 따라 달라질 수 있다. 구체적으로 MCS 인덱스 또는 MCS 인덱스와 변조 차수에 따라 결정된 TBS 인덱스 또는 MCS 인덱스와 N_PRB(데이터 전송시 사용되는 물리 자원의 크기)에 따라 미리 결정되어 있을 수 있다. 또한 수학식 22의

및 a는 특정 부호율 및 특정 정보어 길이 (TBS(transport block size), CBS(code block size), CBGS(code block group size) 등) 및 특정 UE 카테고리(category) 또는 패리티 검사 행렬 또는 상향링크 또는 햐향링크(UL/DL) 전송 여부 또는 정보어의 길이 중 적어도 하나의 요소에 따라 다르게 결정될 수 있다. 예를 들어 상기 하나의 요소에 의해서

는 항상 고정된 값을 사용할 수 있다. remind

May vary depending on the code rate and the information word length (i.e., CBS). Specifically, it may be determined in advance according to the TBS index or MCS index determined according to the MCS index or the MCS index and the modulation order, and N _PRB (the size of the physical resource used in data transmission). Also,

And a is a specific code rate and a specific information word length (transport block size, code block size (CBS), code block group size (CBGS), etc.) and a specific UE category or parity check matrix, And may be determined differently depending on at least one element of whether to transmit downlink (UL / DL) or length of information word. For example, by one element

Can always use a fixed value.

는 아래 수학식 23과 같을 수 있다. For example,

Can be expressed by Equation 23 below.

&Quot; (23) &quot;

또는

or

The R may be a value set by a higher layer signaling (which may also be interpreted as RRC signaling) or a MAC CE or a DL physical layer signal (L1 DL control) in advance at a coding rate, Or it can be calculated directly by the transceiver. Or may be the value indicated in the MCS table. Or R = f (k / E), which means that R is an arbitrary function with k / E as a variable. k is the number of information bits (length of the information word of the LDPC code, length of the TBS, CBS or CBG bits and CRC bits if necessary), and E is the number of codeword bits to be transmitted. The number E of codeword bits to be transmitted may be determined according to a frame structure in which the information bits are coded and transmitted, the number of layers, the modulation scheme, and the like. K _b denotes the number of column blocks of the information part of the parity check matrix of the LDPC code and depends on the length k of the information word of the LDPC code. For example, K _b = k / Z. Therefore, the value of k _b depends on k and Z. [ And Z is the size of the cyclic permutation matrix of the parity check matrix of the LDPC code. The information word of the LDPC code is a bit string in which zero bits are padded to CB (or a bit string including a CRC in TB).

또는 (1/R)로 정의하도록 한다. 이 때 부호율이 높을수록

값은 작다.Alternatively, the 1 / R value can be used as an integer in the MCS table. That is, a predetermined integer value defined for each MCS index in the MCS table

Or (1 / R). At this time, the higher the coding rate

The value is small.

값은 아래 수학식 24와 같이 정의될 수 있다.or

The value can be defined as shown in Equation 24 below.

&Quot; (24) &quot;

또는

또는

or

or

는 이전 전송의 전송 부호율을 기반으로 결정하는 것이 더 우수한 성능을 보장 할 수 있다. 상기 재전송시 이전 전송(또는 초기 전송)과 전송 부호율이 동일하다는 의미는 재전송시 전송되는 부호화 비트의 개수가 이전 전송(또는 초기 전송)시 전송되는 부호어 비트의 개수와 동일한 경우로, 일 예로 할당된 MCS 인덱스와 서브 캐리어의 개수 (혹은 PRB의 개수)가 동일한 경우를 의미한다. 재전송시의 전송 부호율이 이전 전송(또는 초기 전송)시 전송 부호율과 다를 경우 이전 전송시 전송 부호율 혹은 MCS 인덱스를 기반으로 하여 상기 수학식 23 또는 상기 수학식 24의 R값 또는 I_MCS가 사용될 수 있다. 이 경우 송수신기는 이전 전송시 전송 부호율 또는 전송된 부호어 비트의 개수 또는 MCS 및/또는 N_PRB 등을 저장할 필요가 있다. When determining the transmission start bit based on Equation 21 or Equation 22,

It is possible to guarantee better performance by determining based on the transmission code rate of the previous transmission. When the number of encoded bits transmitted during retransmission is equal to the number of codeword bits transmitted in the previous transmission (or initial transmission), it means that the transmission rate is equal to the previous transmission (or initial transmission) It means that the allocated MCS index and the number of subcarriers (or the number of PRBs) are the same. If the transmission code rate at retransmission is different from the transmission rate at the previous transmission (or initial transmission), the R value or I _MCS of Equation (23) or Equation (24) is calculated based on the transmission code rate or MCS index in the previous transmission Can be used. In this case, the transceiver needs to store the transmission code rate or the number of transmitted codeword bits or MCS and / or N _PRB in the previous transmission.

값을 결정하는 방법을 결정 할 수 있다. 이 때 하향링크에 대한 제어 정보에 포함된 RV 모드 지시자는 초기 전송에서 데이터 전송을 위해 사용한 부호율과 현재 전송(재전송)에서 사용하는 부호율이 같은지 여부를 지시할 수 있고, 상향링크에 대한 제어 정보에 포함된 RV 모드 지시자는 초기 전송에서 데이터 전송을 위해 사용된 부호율과 앞으로 전송할 데이터의 부호율이 같은지 여부를 지시할 수 있다. Or based on an RV mode indicator included in the downlink control information as described below

You can decide how to determine the value. In this case, the RV mode indicator included in the control information for the downlink can indicate whether the code rate used for data transmission in the initial transmission is the same as the code rate used in the current transmission (retransmission) The RV mode indicator included in the information may indicate whether the code rate used for data transmission in the initial transmission is the same as the code rate used for data to be transmitted in the future.

이 결정될 수 있고, 이전 전송과 현재 전송의 파라미터들이 동일하지 않을 경우 (예를 들어 지시자가 1인 경우) 소정의 고정된 값(예를 들어 rv index 개수)을 기반으로

이 결정될 수 있다. If the transmission parameters of the previous transmission and the current transmission are the same (for example, the indicator is 0) according to the indicator, based on the current transmission parameters (for example, the transmission code rate and the information bits)

Can be determined and if the parameters of the previous transmission and the current transmission are not the same (for example, if the indicator is 1), based on a predetermined fixed value (e.g., number of rv index)

Can be determined.

값의 특징을 더 기술한다. 도 13b는

값에 따라 전송되는 비트를 도시한 도면이다. 도 13b에 따르면, k_b, N_b 값이 같더라도 R과

값이 다름에 따라 재전송시 전송되는 비트의 수가 다름을 알 수 있다. 구체적으로 (a)의 경우 부호율 R이 8/9이고 값이 24일 때 3번째 전송시(2번째 재전송시) 전송되는 비트는 1300이 되고, (b)의 경우 R이 1/2이고 값이 44일 때 2번째 전송시 전송되는 비트는 1310이 된다. Below

Describe the characteristics of the value further. Fig.

&Lt; / RTI &gt; FIG. 13B, even if k _b and N _b are the same,

As the values are different, it can be seen that the number of bits transmitted during retransmission is different. Specifically, in the case of (a), when the code rate R is 8/9 and the value is 24, the bits transmitted at the time of the third transmission (at the time of the second retransmission) become 1300, In this case, the bit transmitted at the time of the second transmission is 1310.

는 특정 부호율 범위 내에서는 같은 값을 가질 수 있다. 또는 특정 MCS index 범위 내에서는 같은 값을 가질 수 있다. 일례로, 부호율 5/6부터 8/9에서는

일 수 있다. 상기 부호율 또는

는 설정 가능(configurable)할 수 있으며,

를 결정하는 방법은 상기에서 언급한 바와 같이 특정 부호율 및 특정 정보어 길이(TBS, CBS, CBGS 등) 및 상향링크 또는 하향링크 전송 여부에 따라 혹은 단말 카테고리(UE category) 중 적어도 하나의 요소에 따라 다를 수 있다. remind

Can have the same value within a specific code rate range. Or within the specific MCS index range. For example, in code rates 5/6 through 8/9

Lt; / RTI &gt; The code rate or

Can be configurable,

(TBS, CBS, CBGS, etc.) and whether or not the uplink or downlink transmission is performed, or at least one element of the UE category, as described above, It may be different.

은 부호율과 정보어 길이의 조합에 따라 다르게 사용될 수 있다. 일례로 정보어 길이가 작을 경우 동일 부호율에 대하여

은 정보어의 길이가 길 경우의

보다 클 수 있다. 이는 정보어 길이가 작을 경우의 부호어 비트의 개수 N_cb가 정보어 길이가 길 경우의 N_cb 보다 클 수 있기 때문이다. 이 때 전송되는 LDPC 부호어의 길이가 길면 수신기 측의 복호기 메모리의 사이즈가 증가하여야 하므로 부호어의 길이 (또는 N_cb)는 정보어 길이에 따라 제한할 수 있다. 또한 N_cb 및 N_b는 단말의 버퍼 크기(user buffer size) 및 HARQ 과정(HARQ processing)의 개수에 따라 다를 수 있다. 그러므로 상기 최대 rv index 개수 및

은 UE 카테고리(category)에 따라 다를 수 있다.Further, in Equation 22,

Can be used differently depending on the combination of the code rate and the information word length. For example, if the information word length is small,

When the length of the information word is long

. This is because the number N _cb of codeword bits when the information word length is small can be larger than N _cb when the information word length is long. If the length of the LDPC codeword to be transmitted at this time is long, the size of the decoder memory at the receiver side must increase, so the length (or N _cb ) of the codeword can be limited according to the information word length. N _cb and N _b may be different according to the UE buffer size and the number of HARQ processes. Therefore, the maximum number of rv index and

May vary depending on the UE category.

In another embodiment of the present invention, the positions of the transmission start points may include a specific code rate, a modulation scheme, a bit interleaver, a transport block size (TBS), a code block size (CBS) , A length of a transmission bit, a parity check matrix, a specific UE category, and an uplink or downlink (UL / DL) transmission. When using a higher order modulation scheme, performance may be better if the positions mapped to the modulation symbols are changed while retransmitting some of the bits already transmitted. Therefore, considering the case of retransmitting the same bits when transmitting by the higher order modulation scheme, it is possible to improve the system performance by determining the position of the transmission start point according to the RV mode indicator.

A simple method can be defined as a set having elements corresponding to the number of RV mode indicators including transmission start points. At this time, a set denoting the positions of the transmission start points includes a specific code rate, a modulation scheme, a transport block size (TBS), a code block size (CBS), a code block group size (CBGS) A check matrix, a specific UE category, and whether to transmit UL / UL (UL / DL).

For example, if the number of column blocks of the parity check matrix is 68, and the input bits related to the two column blocks are always punctured and not transmitted, the codeword bits (Ncb) are 66 * Z, The set can be defined as follows. And Z is the size of the cyclic permutation matrix of the parity check matrix of the LDPC code. Hereinafter, the position of the transmission start point means a position from the bits excluding the bits that are always punctured.

Set1 = {0, 17 * Z, 33 * Z, 50 * Z}

Set2 = {0, 25 * Z, 33 * Z, 50 * Z}

Set3 = {0, 28 * Z, 33 * Z, 50 * Z}

If (R> = 0.89 and MOD = 256 QAM) or (R> = 0.89 and MOD = 64 QAM) or (R> = 0.89 and MOD = 16 QAM) then starting positions set is set3

(R > = 0.77 and MOD = QPSK) or (R > = 0.82 and MOD = QPSK) or (R > = 0.82 and MOD = 64QAM) set is set2

else then starting positions set is set1

As another example, when the number of column blocks of the parity check matrix is 68, at least one set of the sets Set 1, set 2, and set 3 is used for all the code rates and modulation schemes.

The set may also be expressed as Set1 = {0, 17, 33, 50}, Set2 = {0, 25, 33, 50}, Set3 = {0, 28, 33, 50}.

As another example, when the number of column blocks of the parity check matrix is 68 and the bits associated with the two column blocks are not always punctured and transmitted, the set indicating the positions of the transmission start points referred to by the RV mode indicator is { 0, 15 * Z, 23 * Z, 37 * Z}. The set can also be expressed as {0, 15, 23, 37}.

In FIG. 23A, when the transmission start point is determined using set 1 and set 3, SNR differences satisfying BLER = 0.01 are indicated according to the coding rate and the modulation method. As shown in the figure, BLER = 0.01 can be satisfied based on lower SNR when different sets are used according to the coding rate and the modulation method.

For example, if the number of column blocks in the parity check matrix is 52 and the input bits associated with the two column blocks are not always punctured and transmitted, the codeword bits (Ncb) are 50 * Z, The set can be defined as follows. And Z is the size of the cyclic permutation matrix of the parity check matrix of the LDPC code. Hereinafter, the position of the transmission start point means the position from the bits excluding the bits that are always punctured.

Set4 = {0, 13 * Z, 25 * Z, 38 * Z}

Set5 = {0, 18 * Z, 25 * Z, 38 * Z}

(R > = 0.62 and MOD = QPSK) or (R > = 0.62 and MOD = 64QAM) or (R > = 0.62 and MOD = 16QAM) is set4

else starting positions set is

Set4 = {0, 13, 25, 38}, Set5 = {0, 18, 25, 38}.

As another example, when the number of column blocks of the parity check matrix is 52, at least one set of the sets Set 1, set 2, and set 3 is used for all the coding rates and modulation schemes.

As another example, when the number of column blocks of the parity check matrix is 52 and the bits related to two column blocks are not always transmitted by puncturing, the set indicating the positions of the transmission start points referred to by the RV mode indicator is { 0, 11 * Z, 16 * Z, 25 * Z}. The set can be expressed as {0, 11, 16, 25}.

In FIG. 23B, when the transmission start point is determined using set 4 and set 5, the SNR difference satisfying BLER = 0.01 is indicated according to the coding rate and the modulation method. As shown in the figure, BLER = 0.01 can be satisfied based on lower SNR when different sets are used according to the coding rate and the modulation method.

Z can be excluded when denoting the set.

In the above embodiments, R is set by a higher layer signaling (which can also be interpreted as RRC signaling) or a MAC CE or a DL physical layer signal (L1 DL control) in advance at a coding rate Value, or it can be calculated directly by the transceiver. Or may be the value indicated in the MCS table. Or R = f (k / E), which means that R is an arbitrary function with k / E as a variable. k is the number of information bits (length of the information word of the LDPC code, length of the TBS, CBS or CBG bits and CRC bits if necessary), and E is the number of codeword bits to be transmitted. The number E of codeword bits to be transmitted may be determined according to a frame structure in which the information bits are coded and transmitted, the number of layers, the modulation scheme, and the like. An information word of an LDPC code is a bit string in which zero bits are padded to CB (or a bit string including a CRC in TB).

The present invention discloses a modulation symbol mapping method and apparatus for performing retransmission. When the codeword bits are transmitted after being converted into the modulation symbols, the LLR (log likelihood ratio) of the bits at the time of decoding may be high or low depending on the positions of the bits constituting the modulation symbols to which the codeword bits are mapped . In this case, if the bits of a position which can have a high LLR are continuously transmitted at the same position and bits of a position capable of having a low LLR are continuously transmitted at the same position in symbol modulation, the bit with low LLR The likelihood of having a low LLR continuously increases. Methods for solving this problem are described below.

14A is a diagram illustrating a modulation symbol mapping method when the same bits are transmitted to the same position among the modulation symbols at the time of retransmission. FIG. 14A illustrates that when the retransmitted symbols are mapped equally, bits at the 1400 position are mapped to the most significant bit (msb) even though the retransmission is performed. In the case of applying the present invention, when a codeword bit is shifted by rv _idx within a bit corresponding to a symbol, 1400 bits become 1410 and a lsb (least significant bit) do. Since the LLRs of msb and lsb are different in symbol modulation, 1400 bit side bits as well as 1400 bits are also transmitted with high and low LLRs in initial transmission and retransmission, so that the performance can be even.

14B is a diagram illustrating a modulation symbol mapping method when the retransmitted symbols are not the same. If the bits constituting the modulation symbol to be mapped at the time of retransmission are not the same, even if the bits at the 1450 position are shifted by rv and become the 1460 position, the bits may become msb as in the initial transmission. In this case, can do. Therefore, in order not to perform the modulation by judging whether the symbols to be retransmitted by the transceiver are the same or not, preferably both of the above methods are applied to perform symbol modulation. Specifically, values obtained by adding the rv index value and the symbol index value are cyclically shifted for each symbol.

15 is a diagram showing a method of applying a cyclic shift for each symbol. According to FIG. 15, when cyclic shift is not applied when 16QAM (Quadrature Amplitude Modulation) is applied, according to (a), codeword bits C ₀ , C ₁ , C ₂ and C ₃ are B ₀ , b ₁ , b ₂ and b ₃ for the _second bit. According to (b), when the value obtained by adding the rv index and the symbol index is 1, the codeword bits C ₃ , C ₀ , C ₁ and C ₂ are set to bits b ₀ , b ₁ , b ₂ and b ₃ for symbol modulation (C) when the sum of the rv index and the symbol index is 2, the codeword bits C ₂ , C ₃ , C _0, and B ₀ are set to bits b ₀ , b ₁ , b ₂ and b ₃ for symbol modulation, C ₁ is substituted.

16A is a block diagram illustrating an apparatus for performing the present invention. According to FIG. 16A, the interleaver 1600 can perform a cyclic shift between bits based on the inputted rv index and symbol index, and the mapper 1610 modulates the shifted bits into symbols.

16B is a flowchart illustrating a modulation symbol mapping method according to an embodiment of the present invention. 16B, the transmitter determines 1650 the redundancy version (RV) or the index rv _idx of the redundancy version and determines 1660 the start position (S _idx or k ₀ ) of the transmission. The transmitter then determines 1670 the mapping order of the bits for the modulation symbols, which is determined based on the rv index and the symbol index. The rv _idx may be a value transmitted by signaling, or may be determined by a predetermined order, or may be determined by a predetermined method according to the present invention.

17 is a diagram illustrating a data retransmission method according to an embodiment of the present invention. 17, the transmitting terminal 1700 initially transmits data to the receiving terminal 1710 (1720). Thereafter, the receiving end transmits a negative acknowledgment (NACK) (negative reception acknowledgment) indicating that data decoding has failed to the transmitting end (1730). The receiving end receives the rv value (rv index) for data retransmission, the position of the transmission start bit, At least one of a number of bits and a cyclic shift value according to a modulation symbol mapping method for retransmission (1740), and performs data retransmission based on the determination (1750). In step 1740, at least one of a maximum transmission bit and a maximum transmission rate may be determined.

Hereinafter, an embodiment will be described in which rv_idx is used according to a predetermined rv_idx order when the parity check matrix is different.

In order to facilitate storing and displaying a plurality of parity check matrices, the same parity check matrix group can be used when the number of blocks Kb of the information bits shown in FIG. 6B is equal to the number of blocks Nb of codeword bits have. That is, the parity check matrices using the exponent values of the cyclic permutation matrix and the size (Z) of the other cyclic permutation matrix based on the same information word block number (Kb) and the codeword block number (Nb) Belongs. For example, a first parity check matrix group (PCM group 1) and a second parity check matrix group (PCM group 2) may be specified according to Kb and Nb as follows.

In this case, if rv_idx is transmitted in a predetermined order without transmitting through a separate signaling, another transmission sequence may be used according to the parity check matrix group as follows.

The present invention discloses yet another embodiment of a modulation symbol mapping method and apparatus. A block interleaver may be present after the puncturing / repetition / zero elimination 442 in the rate matching unit 440 shown in FIG.

As shown in FIG. 4, the output bits of the rate matching unit 440 are input to the modulator 450. The modulator includes a mapper for mapping input bits to bits constituting a modulation symbol. The mapping order may be different according to rv_idx and retransmission. For example, when transmitting based on the same rv_idx as the rv_idx used in the previous transmission, mapping can be performed in the reverse order of the mapping order used in the previous transmission. More specifically, if at least rv_idx is 0, the mapping order is mapped in the reverse order of the mapping order used in the previous transmission in which rv_idx is 0. An example of the case where 256QAM is assumed is shown in FIG. If rv_idx is j in the same i-th transmission, maps bits to symbols based on mapper-1 and uses mapper-2 in at least one case where rv_idx is j among i-th or more transmissions. In this case, performance improvement can be achieved based on different properties of the bits constituting the modulation symbol.

If the same rv_idx is repeated, it is better to repeat rv_idx in the same rv_idx rather than to use different values for rv idx at retransmission.

(Nb) = (22, 68) or (10, 52) in the case of retransmission based on the above method, the LDPC coding / decoding based on the parity check matrix based on the parity check matrix group , The order of {0, 2, 0, 3, 1} is used when retransmitting according to the preset rv_idx. Alternatively, the predetermined rv_idx sequence may be {0, 2, 0, 3}. Alternatively, the predetermined rv_idx sequence may be {0, 2}.

The above procedure was determined by the following method.

One) The first transmission assumes that rv_idx is 0.

2) For (0 < i < N + 1)

A. Based on rv_idx determined up to the (i-1) th transmission, rv_idx having superior performance in various modulation schemes and coding rates is determined in the i th transmission

3) End for

A more specific transmission procedure is shown in Fig.

it is first determined whether rv_idx is signaled. If signaling is not performed and rv_idx is determined based on the predetermined order, it is determined how many transmissions are to be performed. If the number of elements of the rv_idx order set is S and the number of transmissions is i, the value of (i mod S) in the rv_idx order set is determined as rv_idx.

If a parity check matrix belonging to the first parity check matrix group is used, the rv_idx order may be {0 2 1 3}.

If a parity check matrix belonging to the second parity check matrix group is used, the rv_idx order may be {0 2 3 1}.

If reverse mapping is used at least once for the same rv_idx, rv_idx_order may be {0 2 0 3 1}. The codeword bits are mapped to the modulation symbol based on the reverse order of the mapping order used for (i mod 5) = 2 (i mod 5) = 0 with respect to the transmission number i.

Or rv_idx_order may be {0 2 0 3}. The codeword bits are mapped to the modulation symbol based on the reverse order of the mapping order used in the i th transmission satisfying (i mod 4) = 0 when (i mod 4) = 2 with respect to the transmission number i.

Or rv_idx_order may be {0 2}. The codeword bits are mapped to the modulation symbol based on the reverse order of the mapping order used in the i th transmission satisfying (i mod 4) = 0 when (i mod 4) = 2 with respect to the transmission number i. The codeword bits are mapped to the modulation symbol based on the reverse order of the mapping order used in the i th transmission satisfying (i mod 4) = 1 when (i mod 4) = 3.

Although the present invention has been described with respect to data retransmission, it is obvious that the present invention can be applied not only to data but also to all signals transmitted between a base station and a mobile station. Also, the transmitting end and the receiving end of FIG. 17 may be at least one of a base station and a terminal.

18 is a block diagram showing a configuration of an encoding apparatus according to an embodiment of the present invention. In this case, the encoding apparatus 1800 can perform LDPC encoding.

According to FIG. 18, the encoding apparatus 1800 includes an LDPC encoder 1810. The LDPC encoder 1810 may generate LDPC codewords by performing LDPC encoding on the input bits based on the parity check matrix.

)을 구성할 수 있다. LDPC 인코더(1810)는 K_ldpc 개의 LDPC 정보어 비트들을 시스테매틱하게 LDPC 인코딩하여, N_ldpc 개의 비트들로 구성된 LDPC 코드워드 Λ=(c₀,c₁,...,

)=(i₀,i₁,...,

,p₀,p₁,...,

)를 생성할 수 있다. 상기 생성 과정은 상기 수학식 1에서 서술한 바와 같이 상기 LDPC 코드워드와 패리티 검사 행렬의 곱이 제로 벡터가 되도록 부호어를 결정하는 과정을 포함한다. 본 발명의 패리티 검사 행렬은 상기 도 3에서 정의한 패리티 검사 행렬과 동일한 구조를 가질 수 있다.The K _ldpc bits include K _ldpc LDPC information bits I = (i ₀ , i ₁ , ..., k) for the LDPC encoder 1810,

). LDPC encoder 1810 K _ldpc LDPC information bits of the systematic LDPC encoding by the schematic, N _ldpc bits of the LDPC codeword Λ = consisting of _{(c 0, c 1, ...} ,

) = (i ₀ , i ₁ , ...,

, p ₀ , p ₁ , ...,

Can be generated. The generating process includes determining a codeword so that a product of the LDPC codeword and the parity check matrix becomes a zero vector, as described in Equation (1). The parity check matrix of the present invention may have the same structure as the parity check matrix defined in FIG.

In this case, the LDPC encoder 1810 can perform LDPC encoding using a parity check matrix defined differently according to the coding rate (i.e., the coding rate of the LDPC code).

Concrete methods of performing LDPC encoding have been described above.

The encoder 1800 may further include a memory (not shown) for storing information on the code rate, the codeword length, and the parity check matrix of the LDPC code. The LDPC encoder 810 may store the information To perform LDPC coding. The information on the parity check matrix may store information on the exponent value of the circulant matrix when the parity matrix proposed in the present invention is used.

The receiver operation will be described in detail below with reference to FIG.

The demodulation unit 510 demodulates a signal received from the transmission apparatus 400.

The demodulator 510 demodulates a signal received from the transmitter 400 and transmits the demodulated signal to the transmitter 400. The demodulator 510 demodulates the signal received from the transmitter 400, It is possible to generate values corresponding to one bit.

To this end, the receiving apparatus 500 may store information on a modulation scheme modulated according to a mode in the transmitting apparatus 400. Accordingly, the demodulator 510 may demodulate the signal received from the transmitting apparatus 400 according to the mode, and generate values corresponding to the LDPC codeword bits.

Meanwhile, the value corresponding to the bits transmitted from the transmitting apparatus 400 may be a log likelihood ratio (LLR) value. Specifically, the LLR value can be represented by a value obtained by taking a log as a ratio of the probability that the bits transmitted from the transmitting apparatus 400 are zero and the probability of one day. Alternatively, the LLR value may be a bit value itself, and the LLR value may be a representative value determined according to an interval in which the probability that the bit transmitted from the transmitting apparatus 400 is 0 or 1 belongs.

The demodulator 510 includes multiplexing (not shown) with respect to the LLR value. Specifically, it is possible to perform an operation corresponding to a bit demux (not shown) as a component corresponding to a bit demux (not shown) of the transmitting apparatus 400.

To this end, the receiving apparatus 500 may be storing information on parameters that the transmitting apparatus 400 has used for demultiplexing and block interleaving. Accordingly, the MUX (not shown) performs the demultiplexing and the block interleaving operations performed in the bit demux (not shown) with respect to the LLR value corresponding to the cell word, and returns the LLR value corresponding to the cell word in the bit unit Lt; / RTI &gt;

The rate dematching unit 520 may insert an LLR value into the LLR value output from the demodulation unit 510. [ In this case, the rate dematching unit 520 may insert predetermined LLR values between the LLR values output from the demodulation unit 510.

Specifically, the rate dematching unit 520 corresponds to the rate matching unit 440 of the transmission apparatus 400 and includes an interleaver 441, a zero elimination and puncturing / repetition / zero elimination unit 442 ) Can be performed.

First, the rate dematching unit 520 deinterleaves 521 to correspond to the interleaver 441 of the transmitter. The output values of the deinterleaver 521 may insert an LLR value corresponding to zero bits at a position where zero bits are padded in the LDPC codeword in the LLR insertion unit 522. [ In this case, the LLR value corresponding to the padded zero bits, that is, the shortened zero bits, may be ∞ or -∞. However, ∞ or -∞ is the theoretical value and may be substantially the maximum or minimum value of the LLR value used in the receiving apparatus 500.

For this purpose, the receiving apparatus 500 may be storing information on parameters that the transmitting apparatus 400 has used to padd the zero bits. Accordingly, the rate dematching unit 520 can determine the position where the zero bits are padded in the LDPC code word, and insert the LLR value corresponding to the shortened zero bits at the corresponding position.

The LLR insertion unit 522 of the rate dematching unit 520 may insert an LLR value corresponding to the punctured bits at the positions of the punctured bits in the LDPC codeword. In this case, the LLR value corresponding to the punctured bits may be zero.

To this end, the receiving apparatus 500 may store information on parameters used for puncturing in the transmitting apparatus 400. Accordingly, the LLR insertion unit 522 can insert an LLR value corresponding to the position where the LDPC parity bits are punctured.

The LLR combiner 523 may combine or sum the LLR values output from the LLR insertion unit 522 and the demodulation unit 510. Specifically, the LLR combiner 523 is a component corresponding to the puncturing / repetition / zero elimination unit 442 of the transmitting apparatus 400, and performs an operation corresponding to the repetition unit 442 . First, the LLR combiner 523 may combine the LLR value corresponding to the repeated bits with another LLR value. Here, another LLR value may be an LLR value for the bits based on generation of repeated bits in the transmitting apparatus 400, that is, the LDPC parity bits selected for repetition.

That is, as described above, the transmitting apparatus 400 selects the bits from the LDPC parity bits, and repeats them between the LDPC information bits and LDPC parity bits to transmit to the receiving apparatus 500.

Accordingly, the LLR value for the LDPC parity bits is the LLR value for the repaired LDPC parity bits and the LLR value for the unreputed LDPC parity bits, i.e., the LDPC parity bits generated by the encoding Lt; / RTI &gt; Thus, the LLR combiner 523 can combine the LLR values with the same LDPC parity bits.

To this end, the receiving apparatus 500 may store information on parameters used for repetition in the transmitting apparatus 400. [ Accordingly, the LLR combiner 523 can determine the LLR value for the repaired LDPC parity bits and combine it with the LLR value for the LDPC parity bits on which the repetition is based.

In addition, the LLR combiner 523 may combine the LLR values corresponding to the retransmitted or IR (Incremental Redundancy) bits with another LLR value. Here, the different LLR values may be the LLR values for the bits that were selected for generating the LDPC codeword bits based on retransmission or IR generated bits in the transmitting device 400.

That is, as described above, the transmitting apparatus 400 may transmit some or all of the codeword bits to the receiving apparatus 500 when a NACK occurs for HARQ.

Accordingly, the LLR combiner 523 may combine the LLR values for the bits received via retransmission or IR with the LLR values for the LDPC codeword bits received over the previous frame.

To this end, the receiving apparatus 500 may store information on parameters used for retransmission or IR bits generation in the transmitting apparatus 400. Accordingly, the LLR combiner 523 can determine the LLR value for the number of retransmission or IR bits and combine it with the LLR value for the LDPC parity bits based on the generation of the retransmission bits.

The deinterleaver 524 may deinterleave the LLR value output from the LLR combiner 523. [

Specifically, the deinterleaver unit 524 is a component corresponding to the interleaver 441 of the transmission apparatus 400, and can perform an operation corresponding to the interleaver 441. [

To this end, the receiving apparatus 500 may store information on parameters used by the transmitting apparatus 100 for interleaving. Accordingly, the deinterleaver 524 reverses the interleaving operation performed in the interleaver 441 with respect to the LLR value corresponding to the LDPC codeword bits, and deinterleaves the LLR value corresponding to the LDPC codeword bits .

The LDPC decoder 530 may perform LDPC decoding based on the LLR value output from the rate dematching unit 520. [

Specifically, the LDPC decoder 530 is a component corresponding to the LDPC encoder 430 of the transmission apparatus 100, and can perform an operation corresponding to the LDPC encoder 430.

To this end, the receiving apparatus 500 may store information on parameters used for performing LDPC encoding according to a mode in the transmitting apparatus 400. [ Accordingly, the LDPC decoder 530 can perform LDPC decoding based on the LLR value output from the rate dematching unit 520 according to the mode.

For example, the LDPC decoder 530 performs LDPC decoding based on the LLR value output from the rate dematching unit 520 based on an iterative decoding scheme based on a sum-product algorithm, and performs LDPC decoding on the LDPC So that the error-corrected bits can be output.

The zero elimination unit 540 may remove the zero bits from the bits output from the LDPC decoders 2460 and 2560.

Specifically, the zero elimination unit 540 is a component corresponding to the zero padding unit 420 of the transmission apparatus 400 and may perform an operation corresponding to the zero padding unit 420. [

To this end, the receiving apparatus 500 may store information on parameters used for padding the zeroth bits in the transmitting apparatus 400. Accordingly, the zero elimination unit 540 can remove the zero bits padded in the zero padding unit 420 from the bits output from the LDPC decoder 530. [

The demagnetization unit 550 is a component corresponding to the segmentation unit 410 of the transmission apparatus 400 and can perform an operation corresponding to the segmentation unit 410. [

To this end, the receiving apparatus 500 may store information on parameters used by the transmitting apparatus 400 for segmentation. Accordingly, the demagnetization unit 550 may combine the bits output from the zero elimination unit 540, that is, the segments for the variable length input bits, to recover the bits before segmentation.

19 is a block diagram showing a configuration of a decoding apparatus according to an embodiment of the present invention. According to FIG. 19, the decoding apparatus 1900 may include an LDPC decoder 1910. Meanwhile, the decoding apparatus 1900 may further include a memory (not shown) for storing the code rate, the codeword length, and the parity check matrix information of the LDPC code, and the LDPC decoder 1910 may store the information To perform LDPC coding. However, this is only an example, and the information may be provided from the transmitting apparatus side.

The LDPC decoder 1910 performs LDPC decoding on the LDPC codeword based on the parity check matrix.

  For example, the LDPC decoder 1910 may pass LDL (Log Likelihood Ratio) values corresponding to LDPC codeword bits through an iterative decoding algorithm to perform LDPC decoding to generate information word bits.

Here, the LLR value is a channel value corresponding to the LDPC codeword bits, and can be expressed in various ways.

For example, the LLR value can be expressed as a value obtained by taking a log as a ratio of the probability that the bit transmitted through the channel on the transmitting side is 0 and the probability of 1 day. The LLR value may be the bit value itself determined according to the hard decision, and may be a representative value determined according to the interval in which the probability that the bit transmitted from the transmitting side is 0 or 1 belongs.

In this case, the transmitting side can generate the LDPC codeword using the LDPC encoder 1810 as shown in FIG.

Meanwhile, the parity check matrix used in the LDPC decoding may be the same as the parity check matrix shown in FIG.

In this case, the LDPC decoder 1910 can perform LDPC decoding using differently defined parity check matrices according to the coding rate (i.e., the coding rate of the LDPC code).

Meanwhile, as described above, the LDPC decoder 1910 can perform LDPC decoding using an iterative decoding algorithm. In this case, the LDPC decoder 1910 can be configured as shown in FIG. However, in the case of the iterative decoding algorithm, the detailed configuration shown in FIG. 20 is only an example in that it is already known.

20 shows a structure of an LDPC decoder according to another embodiment of the present invention. 20, the decoding apparatus 2000 includes an input processor 2011, a memory 2012, a variable node calculator 2013, a controller 2014, a check node decoder 2015, and an output processor 2016.

The input processor 2011 stores the input value. Specifically, the input processor 2011 may store the LLR value of the received signal received via the wireless channel.

The controller 2014 calculates the number of values input to the variable node calculator 2013 based on the parity check matrix corresponding to the size of the block (that is, the length of the codeword) of the received signal received via the wireless channel, The address value in the memory 2012, the number of values input to the check node operator 2015, and the address value in the memory 2012 are determined.

The memory 2012 stores input data and output data of the variable node operator 2013 and the check node operator 2015.

The variable node operator 2013 receives the data from the memory 2012 according to the address information of the input data and the number information of the input data received from the controller 2014 and performs a variable node operation. Then, the variable node operator 2013 stores the variable node operation results in the memory 2012 based on the address information of the output data input from the controller 2014 and the number information of the output data. The variable node operator 2013 inputs the result of the variable node operation to the output processor 2016 based on the data input from the input processor 2011 and the memory 2012. [ Here, the variable node operation is described above based on Fig.

The check node computing unit 2015 receives data from the memory 2012 based on the address information of the input data and the number information of the input data received from the controller 2014 and performs an inspection node operation. Then, the check node computing unit 2015 stores the variable node computation results in the memory 2012 based on the address information of the output data input from the controller 2014 and the number information of the output data. Here, 7A and 7B.

The output processor 2016 outputs a hard decision result based on the data received from the variable node operator 2013 after determining whether the information bits of the codeword on the transmission side are 0 or 1, 2016 are finally decoded values. 7A and 7B, it is possible to make a hard decision based on the sum of all the message values input to one variable node (initial message value and all message values input from the check node).

21 and 22 are diagrams illustrating a transmitter and a receiver that may operate in accordance with an embodiment of the present invention. The transmitter and the receiver may be either a base station or a terminal. 21, the transmitter 2100 may include a transmitter-receiver unit 2110 and a controller unit 2120. The transmitter-receiver unit transmits and receives information, signals, and messages to and from the receiver, and the control unit controls the transmitter- And can also be controlled to perform embodiments of the present invention. The transmitting apparatus 400 described in the present invention may or may not be included in the control section. The encoding device 1800 may be included in the control unit or not.

22, the receiver 2200 may include a transmitter-receiver unit 2210 and a controller unit 2220. The transmitter-receiver unit transmits and receives information, signals, and messages to and from the transmitter, and the control unit controls the transmitter- And can also be controlled to perform embodiments of the present invention. The receiving apparatus 500 described in the present invention may or may not be included in the control section. The decryption apparatus 1900 may or may not be included in the control unit.

Claims (18)

In a data transmission method of a transmitter,
Comprising the steps of: initially transmitting data encoded with an LDPC (Low Density Parity Check) code to a receiver;
Receiving a negative acknowledgment (NACK) from the receiver;
Determining retransmission related information for data retransmission; And
And retransmitting data encoded with the LDPC code corresponding to the NACK based on the retransmission related information. The method according to claim 1,
Wherein the retransmission related information includes at least one of a rv _idx (redundancy version index) and a transmission start bit position of data to be retransmitted. 3. The method of claim 2,
Wherein the rv _idx is determined based on at least one of a coding rate when data encoded with the LDPC code is initially transmitted, and an MCS (modulation and coding scheme) applied at the time of data transmission. 3. The method of claim 2,
Wherein the transmission start bit position is determined based on a lifting value of a parity check matrix used in data encoding with the LDPC code. 3. The method of claim 2,
Wherein the transmission start bit position is determined based on a parity check matrix used in data encoding with the LDPC code. A method for receiving data in a receiver,
Comprising: receiving data encoded with an LDPC (Low Density Parity Check) code from a transmitter;
Transmitting a negative acknowledgment (NACK) to the transmitter based on the data decoding result;
Determining retransmission related information for data retransmission; And
And re-receiving data encoded with the LDPC code retransmitted according to the NACK based on the retransmission information. The method according to claim 6,
Wherein the retransmission related information includes at least one of a rv _idx (redundancy version index) and a transmission start bit position of data to be retransmitted. 8. The method of claim 7,
Wherein the rv _idx value is determined based on at least one of a coding rate when data encoded with the LDPC code is initially transmitted, and an MCS (modulation and coding scheme) applied at the time of data transmission. 8. The method of claim 7,
Wherein the transmission start bit position is determined based on a lifting value of a parity check matrix used in data encoding with the LDPC code. 8. The method of claim 7,
Wherein the transmission start bit position is determined based on a parity check matrix used in data encoding with the LDPC code. A transmitter for transmitting data,
A transmitting and receiving unit for transmitting and receiving signals to and from a receiver; And
(LDPC) code to a receiver, receives a negative acknowledgment (NACK) from the receiver, determines retransmission related information for data retransmission, and transmits retransmission related information to the receiver based on the retransmission- NACK, and retransmits the data encoded with the LDPC code. 12. The method of claim 11,
Wherein the retransmission related information includes at least one of a rv _idx and a transmission start bit position of data to be retransmitted. 13. The method of claim 12,
Wherein the rv _idx is determined based on at least one of a coding rate at which data encoded with the LDPC code is initially transmitted, and an MCS (modulation and coding scheme) applied at the time of data transmission. 13. The method of claim 12,
Wherein the transmission start bit position is determined based on a lifting value of a parity check matrix used in data encoding with the LDPC code. 13. The method of claim 12,
Wherein the transmission start bit position is determined based on a parity check matrix used in data encoding with the LDPC code. A receiver for receiving data,
A transmitter and receiver for transmitting and receiving signals to and from a transmitter; And
The method includes receiving data encoded with an LDPC (Low Density Parity Check) code from a transmitter, transmitting a negative acknowledgment (NACK) to the transmitter based on the data decoding result, determining retransmission related information for data retransmission, And re-receiving the data encoded with the LDPC code retransmitted based on the NACK information. 17. The method of claim 16,
Wherein the retransmission related information includes at least one of a rv _idx (redundancy version index) of the data to be retransmitted, and a transmission start bit position. 18. The method of claim 17,
The rv _idx is determined based on at least one of a coding rate when data encoded with the LDPC code is initially transmitted, an MCS (modulation and coding scheme) applied at the time of data transmission, and a parity check matrix,
Wherein the transmission start bit position is determined based on a lifting value of a parity check matrix used in data encoding with the LDPC code.

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