KR102509968B1 - Apparatus and method of transmission using harq in communication or broadcasting system - Google Patents

Abstract

The present disclosure relates to a 5G or pre-5G communication system for supporting a higher data rate after a 4G communication system such as LTE. The present invention discloses a method for effective retransmission when HARQ is applied to data encoded using an LDCP code. The present invention includes the steps of initially transmitting data encoded with a low density parity check (LDPC) code to a receiver, receiving a negative acknowledgment (NACK) from the receiver, determining retransmission related information for data retransmission, and the above and retransmitting data encoded with the LDPC code in response to the NACK based on retransmission related information.

Description

Transmission method and apparatus when HARQ is applied in a communication or broadcasting system

The present invention relates to a transmission method and apparatus to which HARQ is applied in a communication or broadcasting system.

Efforts are being made to develop an improved 5G communication system or pre-5G communication system to meet the growing demand for wireless data traffic after the commercialization of the 4G communication system. For this reason, the 5G communication system or pre-5G communication system is being called a system after a 4G network (Beyond 4G Network) communication system or an LTE system (Post LTE).

In order to achieve a high data rate, the 5G communication system is being considered for implementation in a mmWave band (eg, a 60 gigabyte (60 GHz) band). In order to mitigate the path loss of radio waves and increase the propagation distance of radio waves in the ultra-high frequency band, beamforming, massive MIMO, and Full Dimensional MIMO (FD-MIMO) are used in 5G communication systems. ), array antenna, analog beam-forming, and large scale antenna technologies are being discussed.

In addition, to improve the network of the system, in the 5G communication system, an evolved small cell, an advanced small cell, a cloud radio access network (cloud RAN), and an ultra-dense network , Device to Device communication (D2D), wireless backhaul, moving network, cooperative communication, Coordinated Multi-Points (CoMP), and interference cancellation etc. are being developed.

In addition, in the 5G system, advanced coding modulation (Advanced Coding Modulation: ACM) methods FQAM (Hybrid FSK and QAM Modulation) and SWSC (Sliding Window Superposition Coding), advanced access technologies FBMC (Filter Bank Multi Carrier), NOMA (non-orthogonal multiple access), SCMA (sparse code multiple access), and the like are being developed.

In a communication/broadcasting system, link performance can be significantly degraded by various noise, fading, and inter-symbol interference (ISI) of a channel. Therefore, it is required to develop a technology for overcoming noise, fading, and inter-symbol interference in order to implement high-speed digital communication/broadcasting systems that require high data throughput and reliability, such as next-generation mobile communication, digital broadcasting, and portable Internet. As part of research to overcome noise, etc., research on error correcting codes has been actively conducted recently as a method for increasing communication reliability by efficiently restoring distortion of information.

The present invention provides an LDPC encoding and decoding method and apparatus supporting various codeword lengths from a designed parity check matrix. In addition, the present invention provides an HARQ transmission method and apparatus based on an LDPC code.

The present invention for solving the above problems is the step of initially transmitting data encoded with LDPC (Low Density Parity Check) code to a receiver, receiving a negative acknowledgment (NACK) from the receiver, retransmission for data retransmission The method may include determining information, and retransmitting data encoded with the LDPC code in response to the NACK based on the retransmission related information.

In addition, in a method for receiving data by a receiver, receiving data encoded with a low density parity check (LDPC) code from a transmitter, transmitting a negative acknowledgment (NACK) to the transmitter based on a result of decoding the data, Retransmitting data Determining retransmission related information for the retransmission, and retransmitting data encoded with the LDPC code retransmitted in response to the NACK based on the retransmission information.

In addition, in a transmitter for transmitting data, a transmitter and receiver for transmitting and receiving a signal with a receiver and data encoded with an LDPC (Low Density Parity Check) code are initially transmitted to the receiver, and a negative acknowledgment (NACK) is received from the receiver, and a control unit that determines retransmission-related information for data retransmission and controls data encoded with the LDPC code to be retransmitted in response to the NACK based on the retransmission-related information.

In addition, in a receiver for receiving data, a transceiver for transmitting and receiving a signal with a transmitter and receiving data encoded with a low density parity check (LDPC) code from the transmitter, and based on a result of decoding the data, the transmitter confirms negative reception ( NACK), determines retransmission-related information for data retransmission, and controls retransmission of data encoded with the LDPC code retransmitted in response to the NACK based on the retransmission information. do.

The present invention can support a HARQ scheme based on an LDPC code applicable to a variable length and variable rate.

값에 따라 전송되는 비트를 도시한 도면이다.
도 14a는 재전송되는 심볼이 동일한 경우 변조 심볼 매핑 방법을 도시한 도면이다.
도 14b는 재전송되는 심볼이 동일하지 않을 경우 변조 심볼 매핑 방법을 도시한 도면이다.
도 15는 각 심볼마다 순환 쉬프트를 적용하는 방법을 도시한 도면이다.
도 16a는 본 발명을 수행하는 장치를 도시한 블록도이다.
도 16b는 본 발명의 실시예에 따른 변조 심볼 매핑 방법을 도시한 순서도이다.
도 17은 본 발명의 실시예에 따른 데이터 재전송 방법을 도시한 도면이다.
도 18은 본 발명의 일 실시 예에 따른 부호화 장치의 구성을 나타내는 블록도이다.
도 19는 본 발명의 일 실시 예에 따른 복호화 장치의 구성을 나타내는 블록도이다.
도 20은 본 발명의 실시예에 따른 복호화 장치를 도시한 블록도이다.
도 21 및 22는 본 발명의 실시예에 따라 동작할 수 있는 송신기 및 수신기를 도시한 도면이다.
도 23은 본 발명에 따라 신호 전송시 특정 BLER을 만족시키는 SNR 값을 도시한 도면이다.
도 24는 블록 인터리버를 도시한 도면이다.
도 25는 본 발명에 따른 송신 순서를 도시한 도면이다. 1 is a diagram showing a structure of a systematic LDPC codeword.
2 is a diagram showing an example of a parity check matrix H1 of an LDPC code having 4 rows and 8 columns and a Tanner graph thereof.
3 is a diagram showing the basic structure of a parity check matrix.
4 is a block diagram of a transmission device according to an embodiment of the present invention.
5 is a block diagram of a receiving device according to an embodiment of the present invention.
6A and 6B are diagrams describing characteristics of the LDPC parity check matrix used in the present invention.
7A and 7B are diagrams illustrating a message passing operation performed in an arbitrary check node and a variable node for LDPC decoding.
8 is a flowchart illustrating a transmission method according to an embodiment of the present invention.
9a and 9b are flowcharts illustrating a transmission method according to an embodiment of the present invention.
FIG. 10 is a diagram showing positions of LDPC codewords and preset specific bits for the retransmission.
11A and 11B are diagrams illustrating overlapping codewords upon retransmission according to code rates.
11C is a diagram illustrating codewords transmitted when an interleaver is used differently.
12A and 12B are diagrams illustrating a method of determining a retransmission start point according to an initial code rate.
13A is a flowchart illustrating a method for determining the location of an rv value according to the present invention.
Figure 13b is the present invention

It is a diagram showing bits transmitted according to values.
14A is a diagram illustrating a modulation symbol mapping method when retransmitted symbols are the same.
14B is a diagram illustrating a modulation symbol mapping method when retransmitted symbols are not identical.
15 is a diagram illustrating a method of applying a cyclic shift to each symbol.
16A is a block diagram illustrating an apparatus for implementing the present invention.
16B is a flowchart illustrating a modulation symbol mapping method according to an embodiment of the present invention.
17 is a diagram illustrating a data retransmission method according to an embodiment of the present invention.
18 is a block diagram showing the configuration of an encoding device according to an embodiment of the present invention.
19 is a block diagram showing the configuration of a decoding device according to an embodiment of the present invention.
20 is a block diagram illustrating a decryption apparatus according to an embodiment of the present invention.
21 and 22 are diagrams illustrating a transmitter and receiver capable of operating in accordance with an embodiment of the present invention.
23 is a diagram showing SNR values satisfying a specific BLER during signal transmission according to the present invention.
24 is a diagram illustrating a block interleaver.
25 is a diagram showing a transmission sequence according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. And, in describing the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. In addition, terms to be described later are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of a user or operator. Therefore, the definition should be made based on the contents throughout this specification.

The main gist of the present invention can be applied to other systems having similar technical backgrounds with slight modifications within the scope of the present invention, which is the judgment of a person skilled in the art of the present invention. It will be possible.

Advantages and features of the present invention, and methods for achieving them, will become clear with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only the present embodiments make the disclosure of the present invention complete, and common knowledge in the art to which the present invention belongs It is provided to fully inform the holder of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numbers designate like elements throughout the specification.

Low Density Parity Check (LDPC) codes, first introduced by Gallager in the 1960s, have long been forgotten due to complexity that was difficult to implement at the technical level at the time. However, iterative decoding ( A lot of research has been conducted on iterative decoding) and graph-based channel coding. Taking this as an opportunity, as the LDPC code was re-researched in the late 1990s, when decoding is performed by applying iterative decoding based on the sum-product algorithm on the Tanner graph corresponding to the LDPC code, the LDPC code is obtained. It has also been found to have performance approaching Shannon's channel capacity.

An LDPC code is generally defined as a parity-check matrix and can be expressed using a bipartite graph commonly referred to as a Tanner graph.

1 is a diagram showing a structure of a systematic LDPC codeword.

(102)를 LDPC 부호화하면, 부호어

(100)가 생성된다. 즉, 부호어는 다수의 비트로 구성되어 있는 비트열이며, 부호어 비트는 부호어를 구성하는 각각의 비트를 의미한다. 또한, 정보어는 다수의 비트로 구성되어 있는 비트열이며, 정보어 비트는 정보어를 구성하는 각각의 비트를 의미한다. 이때, 시스테메틱 부호인 경우, 부호어

로 구성된다. 여기에서,

는 패리티 비트(104)이고, 패리티 비트의 개수 N_parity는 N_parity=N_ldpc - K_ldpc이다.According to FIG. 1, the LDPC code receives an information word 102 composed of K _ldpc bits or symbols, performs LDPC encoding, and generates a codeword 100 (codeword) composed of N _ldpc bits or symbols do. For convenience of description below, it is assumed that the codeword 100 composed of N _ldpc bits is generated by receiving the information word 102 including K _ldpc bits. That is, an information word that is K _ldpc input bits

If (102) is LDPC-encoded, the codeword

(100) is created. That is, the codeword is a bit string composed of a plurality of bits, and the codeword bits refer to each bit constituting the codeword. In addition, the information word is a bit string composed of a plurality of bits, and the information word bits mean each bit constituting the information word. In this case, in the case of a systematic code, a codeword

consists of From here,

is the parity bit 104, and the number of parity bits N _parity is N _parity = N _ldpc - K _ldpc .

The LDPC code is a type of linear block code and includes a process of determining a codeword that satisfies the condition of Equation 1 below.

[Equation 1]

이다. From here,

am.

In Equation 1, H is a parity check matrix, C is a codeword, c _i is the i th bit of the codeword, and N _ldpc is the length of the codeword. Here, h _i means the i-th column of the parity check matrix H.

The parity check matrix H is composed of N _ldpc columns equal to the number of bits of the LDPC codeword. Equation 1 means that the sum of the products of the ith column (h _i ) of the parity check matrix and the ith codeword bit c _i is '0', so the ith column (h _i ) is the ith codeword bit c It means that there is a relationship with _i .

Referring to FIG. 2, a method of representing a graph of an LDPC code will be described.

2 is a diagram showing an example of a parity check matrix H ₁ of an LDPC code having 4 rows and 8 columns and a Tanner graph thereof. Referring to FIG. 2, since the parity check matrix H ₁ has 8 columns, a codeword having a length of 8 is generated. corresponds to the bit.

Referring to FIG. 2, the Tanner graph of the LDPC code encoded and decoded based on the parity check matrix H ₁ has eight variable nodes, that is, x ₁ (202), x ₂ (204), x ₃ ( 206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214), x ₈ (216) and 4 check nodes (218, 220, 222, 224) is composed of Here, the i-th column and the j-th row of the parity check matrix H ₁ of the LDPC code correspond to the variable node x _i and the j-th check node, respectively. In addition, the value of 1 at the point where the j-th column and the j-th row of the parity check matrix H ₁ of the LDPC code intersect, that is, the meaning of a non-zero value is the variable node x _i and the j-th check on the Tanner graph as shown in FIG. This means that there is an edge connecting the nodes.

The degree of the variable node and the check node in the Tanner graph of the LDPC code means the number of line segments connected to each node, which means that 0 is 0 in the column or row corresponding to the node in the parity check matrix of the LDPC code. equal to the number of non-entries. For example, in FIG. 2, the variable nodes x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214) ), x ₈ The degree of 216 is 4, 3, 3, 3, 2, 2, 2, 2 in order, respectively, and the order of check nodes 218, 220, 222, 224 is 6 in order, respectively. , becomes 5, 5, 5. In addition, the number of non-zero elements in each column of the parity check matrix H ₁ of FIG. 2 corresponding to the variable node of FIG. They match in order, and the number of non-zero elements in each row of the parity check matrix H ₁ of FIG. 2 corresponding to the check nodes of FIG. 2 coincides with the above-mentioned orders 6, 5, 5, and 5 in order. .

The LDPC code can be decoded using an iterative decoding algorithm based on a sum-product algorithm on the bipartite graph listed in FIG. 2 . Here, the multiplication algorithm is a kind of message passing algorithm, and the message passing algorithm is to exchange messages through an edge on a bipartite graph, calculate an output message from messages input to a variable node or check node, and Indicates the update algorithm.

Here, the value of the i-th coded bit may be determined based on the message of the i-th variable node. The value of the i-th coded bit can be both a hard decision and a soft decision. Therefore, the performance of i-th bit c _i of the LDPC codeword corresponds to the performance of the i-th variable node of the Tanner graph, which can be determined according to the position and number of 1s in the i-th column of the parity check matrix. In other words, the performance of the N _ldpc codeword bits of the codeword can be influenced by the location and number of 1s in the parity check matrix, which means that the performance of the LDPC code is greatly affected by the parity check matrix. do. Therefore, in order to design an LDPC code with excellent performance, a method for designing a good parity check matrix is required.

A parity check matrix used in communication and broadcasting systems is a quasi-cyclic LDPC code (or QC-LDPC code, hereinafter QC-LDPC code) that typically uses a quasi-cyclic parity check matrix for ease of implementation. is used a lot

The QC-LDPC code is characterized by having a parity check matrix composed of a zero matrix having a form of a small square matrix or circulant permutation matrices.

The QC-LDPC code will be described in more detail with reference to the following reference [Myung2006].

Reference [Myung2006]

S. Myung, K. Yang, and Y. Kim, "Lifting Methods for Quasi-Cyclic LDPC Codes," IEEE Communications Letters. vol. 10, p. 489-491, June 2006.

크기의 순열 행렬(permutation matrix)

을 정의한다. 여기서

는 행렬 상기 행렬 P에서의 i번째 행(row), j번째 열(column)의 원소(entry)를 의미한다.(0 ≤i, j < L) Looking at the above reference [Myung2006], as shown in Equation 2 below:

size permutation matrix

define here

Means an entry of the i-th row and j-th column in the matrix P of the matrix P. (0 ≤i, j < L)

[Equation 2]

(0 ≤ i < L)는

크기의 항등 행렬(identity matrix)의 각 원소들을 i 번 만큼 오른쪽 방향으로 순환 이동(circular shift) 시킨 형태의 순환 순열 행렬임을 알 수 있다. For the permutation matrix P defined as above

(0 ≤ i < L) is

It can be seen that it is a circular permutation matrix in the form of circular shifting each element of the identity matrix of size i times in the right direction.

The parity check matrix H of the simplest QC-LDPC code can be expressed in the form of Equation 3 below.

[Equation 3]

을

크기의 0-행렬이라 정의할 경우, 상기 수학식 3에서 순환 순열 행렬 또는 0-행렬의 각 지수

는 {-1, 0, 1, 2, ..., L-1} 값 중에 하나를 가지게 된다. 또한 상기 수학식 3의 패리티 검사 행렬 H는 열 블록이 n개, 행 블록이 m개이므로,

크기를 가지게 됨을 알 수 있다. 또한 상기 순환 순열 행렬의 크기는 ZxZ로 표현될수도 있다.if

second

When defined as a 0-matrix of size, each index of the cyclic permutation matrix or 0-matrix in Equation 3 above

has one of the values {-1, 0, 1, 2, ..., L-1}. In addition, since the parity check matrix H of Equation 3 has n column blocks and m row blocks,

It can be seen that it has a size. Also, the size of the cyclic permutation matrix may be expressed as ZxZ.

크기의 이진(binary) 행렬을 패리티 검사 행렬 H의 모행렬(mother matrix) M(H)라 하고, 각 순환 순열 행렬 또는 0-행렬의 지수만을 선택하여 수학식 4와 같이 얻은

크기의 정수 행렬을 패리티 검사 행렬 H의 지수 행렬 E(H)라 한다. Typically obtained by replacing each cyclic permutation matrix and the 0-matrix with 1 and 0 in the parity check matrix of Equation 3 above, respectively.

A binary matrix of the size is referred to as the mother matrix M(H) of the parity check matrix H, and obtained as in Equation 4 by selecting only the index of each cyclic permutation matrix or 0-matrix.

The integer matrix of the size is called the exponent matrix E(H) of the parity check matrix H.

[Equation 4]

Meanwhile, the performance of the LDPC code may be determined according to the parity check matrix. Therefore, it is necessary to design a parity check matrix for an LDPC code having excellent performance. In addition, an LDPC encoding and decoding method capable of supporting various input lengths and code rates is required.

Referring to the above reference [Myung2006], a method known as lifting is used for efficient design of QC-LDPC codes. Lifting is a method of efficiently designing a very large parity check matrix by setting an L value that determines the size of a cyclic permutation matrix or a 0-matrix from a given small parent matrix according to a specific rule. The existing lifting method and the characteristics of the QC-LDPC code designed through lifting are briefly summarized as follows.

는

크기의 지수 행렬

을 가지며 각 지수

들은 {-1, 0, 1, 2, ..., L_k - 1} 값 중에 하나로 선택된다. First, when an LDPC code C ₀ is given, S QC-LDPC codes to be designed through the lifting method are referred to as C ₁ , ..., C _S , row and column blocks of the parity check matrix of each QC-LDPC code The value corresponding to the size of is called L _k . Here, C ₀ corresponds to the smallest LDPC code having the parent matrix of C ₁ , ..., C _S code as a parity check matrix, and the value of L ₀ corresponding to the size of row and column blocks is 1. In addition, for convenience, the parity check matrix of each code C _k

Is

exponential matrix of size

and each index

are selected as one of {-1, 0, 1, 2, ..., L _k - 1} values.

만 저장하고 있으면 리프팅 방식에 따라 다음 수학식 5를 이용하여 상기 QC-LDPC 부호 C₀, C₁, ..., C_S를 모두 나타낼 수 있다.Looking at the reference [Myung2006], lifting is performed in the same steps as C ₀ → C ₁ →...→ C _S and L _{k +1} = q _{k + 1} L _k (q _{k +1} is a positive integer, k=0,1,..., S-1). Also, by the characteristics of the lifting process, the parity check matrix of C _S

If only stored, all of the QC-LDPC codes C ₀ , C ₁ , ..., C _S can be expressed using Equation 5 according to the lifting method.

[Equation 5]

[Equation 6]

In the lifting method of Equation 5 or 6, L _k corresponding to the size of a row block or column block in the parity check matrix of each QC-LDPC code C _k have a multiple relationship with each other, so that the exponential matrix also has a specific method is selected by Such an existing lifting method helps to easily design a QC-LDPC code with improved error floor characteristics by improving the algebraic or graph characteristics of each parity check matrix designed through lifting.

만을 가질 수 있다. 즉, 리프팅을 10 단계 적용할 경우(S=10) 패리티 검사 행렬은 10개의 크기만을 가질 수 있게 된다. However, since each L _k value is in a multiplicative relationship with each other, there is a disadvantage in that the length of each code is greatly limited. For example, assuming that a minimum lifting method such as L _{k +1} = 2 × L _k is applied to each L _k value, in this case, the size of the parity check matrix of each QC-LDPC code is

can only have That is, when 10 steps of lifting are applied (S=10), the parity check matrix can have only 10 sizes.

For this reason, the existing lifting method has somewhat disadvantageous characteristics in designing QC-LDPC codes supporting various lengths. However, a commonly used mobile communication system requires a very high level of length compatibility in consideration of various types of data transmission. For this reason, there is a problem in that it is difficult to apply the LDPC code in the mobile communication system in the conventional method.

는

크기의 지수 행렬

을 가진다. 각 지수

들은 {-1, 0, 1, 2, ..., Z-1} 값 중에 하나로 선택된다. (본 발명에서는 편의상 0-행렬을 나타내는 지수를 -1로 표현하고 있지만 시스템의 편의에 따라 다른 값으로 변경될 수 있다.) First, S LDPC codes to be designed through the lifting method are denoted by C ₁ , ..., C _S , and values corresponding to the size of the row block and column block of the parity check matrix C _i of each LDPC code are denoted by Z . In addition, for convenience, the parity check matrix of each code C _i

Is

exponential matrix of size

have each index

are selected as one of the values {-1, 0, 1, 2, ..., Z-1}. (In the present invention, the exponent representing the 0-matrix is expressed as -1 for convenience, but it can be changed to other values depending on the convenience of the system.)

라 한다. (여기서

는 Z 값 중 최대 값이라 한다) 이 때 Z값이

보다 작을 때에 대한 각 LDPC 부호의 패리티 검사 행렬을 구성하는 순환 순열 행렬 및 0-행렬을 나타내는 지수는 다음과 같은 수학식 7 또는 수학식 8에 따라 결정될 수 있다. Therefore, the exponential matrix of LDPC code C _S having the largest parity check matrix is

say (here

is the maximum value of Z values) At this time, the Z value is

An exponent representing the 0-matrix and the cyclic permutation matrix constituting the parity check matrix of each LDPC code for the case of less than may be determined according to Equation 7 or Equation 8 below.

[Equation 7]

[Equation 8]

는

에 대해 Z로 나눈 나머지를 의미한다.In Equation 7 or Equation 8

Is

is the remainder of division by Z.

의 지수 행렬

또는 모행렬

의 열의 개수 n이 36이라 하고, Z의 값을 1, 2, 4, 8, ……, 128과 같은 8 단계 리프팅을 통해 얻을 수 있는 길이의 종류는 36, 72, 144, ……, 4608

이 되어 가장 짧은 길이와 가장 긴 길이의 차이가 매우 크게 된다. However, [Myung2006] restricts the values of Z so that the multiplicative relationship is satisfied, so it is not suitable for supporting various lengths. For example parity check matrix

exponential matrix of

or parent matrix

Let the number of columns of n be 36, and the value of Z be 1, 2, 4, 8, ... … , the kinds of lengths that can be obtained through 8-step lifting such as 128 are 36, 72, 144, … … , 4608

As a result, the difference between the shortest length and the longest length becomes very large.

보다 작을 때에 대해 플로어링 연산에 기반한 리프팅을 적용하여 설계한 패리티 검사 행렬의 지수 변환 방법을 나타낸다.In the present invention, even when the values of Z are not multiplicative with each other, the exponential method applied to Equation 9 or Equation 10 can be applied as it is, and a method of designing a parity check matrix with little performance degradation is proposed. For reference, the method presented in Equation 9 or Equation 10 is an exponential conversion method when a lifting method based on a modulo operation is applied, and as shown in reference [Myung2006], it is based on a floor operation or other operation. Thus, it is obvious that various methods may exist. The following Equation 9 or Equation 10 shows that the Z value is

It shows the exponential conversion method of the parity check matrix designed by applying the flooring operation-based lifting to the case of less than .

[Equation 9]

[Equation 10]

Hereinafter, a method of designing a parity check matrix and a method of using the parity check matrix to solve the problem of the existing lifting method having a compatibility problem with respect to length will be described.

First, in the present invention, the modified lifting process is defined as follows.

1) The maximum value among Z values is Z _max say

)2) Let D be one of the divisors of Z _max . (

)

3) Z is D, 2D, 3D, … , SD (= Z _max ).

(For convenience, let H _k denote a parity check matrix corresponding to Z = k×D, and denote an LDPC code corresponding to the parity check matrix C _k .)

In addition to the lifting methods mentioned above, various lifting methods can be used to support variable length.

Next, the coding method of the QC-LDPC code will be described in detail with reference to the reference [Myung2005].

Reference [Myung2005]

S. Myung, K. Yang, and J. Kim, " Quasi-Cyclic LDPC Codes for Fast Encoding," IEEE Transactions on Information Theory, vol. 51, No. 8, pp. 51; 2894-2901, Aug. 2005.

3 is a diagram showing the basic structure of a parity check matrix proposed in the present invention.

Referring to the above reference [Myung2005], as shown in FIG. 3, a special type of parity check matrix composed of a cyclic permutation matrix is defined. In addition, it is shown that efficient encoding is possible if the relationship of Equation 11 or Equation 12 is satisfied in the parity check matrix of FIG. 3 .

[Equation 11]

[Equation 12]

값은

가 위치하고 있는 행(row)의 위치를 의미한다. In Equations 11 and 12 above,

value is

It means the position of the row where is located.

로 정의된 행렬이 항등 행렬이 되어 부호화 과정에서 효율적인 부호화가 가능함이 잘 알려져 있다. In this way, when the above Equations 7 and 8 are satisfied, in reference [Myung2005]

It is well known that the matrix defined by becomes an identity matrix, enabling efficient coding in the coding process.

In the present invention, for convenience, only the case of one cyclic permutation matrix corresponding to one block has been described, but it will be clarified that the same invention can be applied to a case in which several cyclic permutation matrices are included in one block.

4 is a block diagram of a transmission device according to an embodiment of the present invention.

Specifically, as shown in FIG. 4, the transmitter 400 includes a segmentation unit 410, a zero padding unit 420, an LDPC encoder 430, a rate matching unit 440, A modulator 450 may be included.

Here, the component shown in FIG. 4 is a component that encodes and modulates variable length input bits, and this is only an example. In some cases, some of the components shown in FIG. 4 It may be omitted or changed, and other components may be further added.

5 is a block diagram of a receiving device according to an embodiment of the present invention.

Specifically, as shown in FIG. 5, the receiving device 500 includes a demodulation unit 510, a rate dematching unit 520, an LDPC decoder 530, a zero removal unit 540, and a deseg to process variable length information. Mention unit 550 may be included.

Here, the component shown in FIG. 5 is a component that performs a function corresponding to the component shown in FIG. 4, which is only an example, and in some cases may be omitted or changed, and other components may be added. It could be.

6A and 6B are diagrams describing characteristics of the LDPC parity check matrix used in the present invention.

Examples of parity check matrices designed in consideration of a hybrid automatic repeat request (HARQ) technique based on various code rates and IR (Incremental Redundancy) are shown in FIGS. 6A and 6B. 6A and 6B, the order of the parity check matrix corresponding to incremental redundancy bits is 1. In addition, the column blocks having an order of 1 are composed of one cyclic permutation matrix and a '0' matrix. According to the shape of the parity check matrix, incremental redundancy bits are generated as a single parity check extension. The incremental redundancy bits may also be transmitted during initial transmission.

According to FIG. 6A, the size of the LDPC parity check matrix used in the present invention varies according to the code rate. For example, when a high code rate is applied, the parity check matrix corresponds to sub-matrix 1 (sub-matrix 1, 600), which includes an information word bit and a part for parity 1 bit. However, when a code rate lower than this is applied, the parity check matrix corresponds to submatrix 2 (610), which includes not only the part included in submatrix 1 but also the systematic part for IR bits and single parity check codes. , and the IR bits and the systematic part included in the parity check matrix become larger as the coding rate decreases.

FIG. 6B shows FIG. 6A in more detail, and the part for the information word bits of the parity check matrix is composed of K _b column blocks. In addition, in the case of submatrix 2, it is composed of N _b column blocks, and in this case, the length of the codeword is N _b × Z.

A parity check matrix using a concatenation method with a single parity check code has an advantage in applying an incremental redundancy (IR) technique because scalability is easy. Since the IR technique is an important technique for supporting HARQ (Hybrid Automatic Repeat request), an efficient IR technique with excellent performance increases the efficiency of the HARQ system. The LDPC codes based on the parity check matrices generate and transmit a new parity using a part extended to a single parity check code, so that an efficient and high-performance IR technique can be applied.

For reference, it is obvious that LDPC encoding techniques having various block lengths and code rates can be applied if shortening and puncturing are appropriately applied to the LDPC codes corresponding to the parity check matrix described in the present invention. In other words, various information word lengths can be supported by appropriately shortening the LDPC code corresponding to the parity check matrix, and various code rates can be supported by appropriately applying puncturing, and a single parity check bit of an appropriate length is generated and transmitted By doing so, an efficient IR technique can be applied.

Meanwhile, the LDPC code can be decoded using an iterative decoding algorithm based on the sum-product algorithm on the bipartite graph listed in FIG. 2, and the sum-product algorithm is a kind of message passing algorithm.

Hereinafter, a message passing operation generally used in LDPC decoding will be described with reference to FIGS. 7A and 7B.

7A and 7B are diagrams illustrating a message passing operation performed in an arbitrary check node and a variable node for LDPC decoding.

7A shows a check node m (700) and a plurality of variable nodes (710, 720, 730, 740) connected to the check node m (700). In addition, shown T _{n ',m} represents a message passed from variable node n' (710) to check node m (700), and E _n,m is from check node m (700) to variable node n (730). Indicates the message passed to . Here, the set of all variable nodes connected to the inspection node m (700) is defined as N(m), and the set excluding the variable node n (730) from N(m) is defined as N(m)\n do it with

In this case, the message update rule based on the sum-product algorithm can be expressed as in Equation 13 below.

[Equation 13]

는 하기의 수학식 14와 같이 나타낼 수 있다. Here, Sign(E _n,m ) represents the sign of the message E _n,m , and |E _n,m | represents the magnitude of the message E _n,m . On the other hand, the function

Can be expressed as in Equation 14 below.

[Equation 14]

Meanwhile, FIG. 7B illustrates a variable node x 750 and a plurality of check nodes 760, 770, 780, and 790 connected to the variable node x 750. In addition, the illustrated E _{y ',x} represents a message passing from the inspection node y' (760) to the variable node x (750), and T _y,x is the variable node x (750) to the variable node y (780) Indicates the message passed to . Here, the set of all variable nodes connected to the variable node x (750) is defined as M(x), and the set excluding the check node y (780) from M(x) is defined as M(x)\y do it with In this case, the message update rule based on the sum-product algorithm can be expressed as Equation 15 below.

[Equation 15]

Here, E _x means the initial message value of variable node x.

In addition, when the bit value of node x is determined, it can be expressed as in Equation 16 below.

[Equation 16]

In this case, the coded bit corresponding to the node x can be determined according to the value of P _x .

Since the method described in FIGS. 7A and 7B is a general decoding method, further detailed description thereof will be omitted. However, in addition to the methods described in FIGS. 7A and 7B, other methods may be applied to determine the values of messages passed through variable nodes and check nodes (Frank R. Kschischang, Brendan J. Frey, and Hans-Andrea Loeliger, " Factor Graphs and the Sum-Product Algorithm," IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 47, NO. 2, FEBRUARY 2001, pp498-519).

Below, the operation of the transmitter will be described in detail based on FIG. 4 .

Specifically, as shown in FIG. 4, the transmitter 400 includes a segmentation unit 410, a zero padding unit 420, an LDPC encoder 430, a rate matching unit 440, and a modulation to process variable length input bits. may include section 450 .

Here, the component shown in FIG. 4 is a component that encodes and modulates variable length input bits, which is only an example, and in some cases, among the components shown in FIG. Some may be omitted or changed, and other components may be further added.

Meanwhile, the LDPC encoder 430 shown in FIG. 4 may perform an operation performed by the LDPC encoder 810 shown in FIG. 8 .

On the other hand, the transmitter 400 provides necessary parameters (eg, input bit length, ModCod (modulation and code rate), parameters for zero padding, code rate/code length of LDPC code, parameters for interleaving, repeati parameters for repetition, parameters for puncturing, parameters for retransmission, modulation schemes, etc.) may be determined, encoded based on the determined parameters, and transmitted to the receiving device 500 of FIG. 5 .

Since the number of input bits is variable, when the number of input bits is greater than a preset value, the input bits may be segmented to have a length less than or equal to the preset value. Also, each segmented block may correspond to one LDPC coded block. However, when the number of input bits is less than or equal to a preset value, the input bits are not segmented. Input bits may correspond to one LDPC coded block.

By making the lengths of the segmented code blocks the same, the implementation complexity can be reduced by making the encoding and decoding parameters of the LDPC code of each code block the same. In addition, encoding performance can be improved by making padded '0' bits of each code block as identical as possible.

The input bits of the rate matching unit 440 are the output bits of the LDPC encoding unit 430, and C = ( i ₀ , i ₁ , i ₂ , ... , i _{Kldpc -1,} p ₀ , p ₁ , p ₂ , ... , p _{Nldpc - Kldpc -1} ). i _k (0≤k< K _ldpc ) means the input bits of the LDPC encoding unit 430 and p _k (0≤k< N _ldpc - K _ldpc ) means LDPC parity bits. The rate matching unit 440 includes an interleaver 441 and a puncturing/repetition/zero removal unit 442.

The modulator 450 modulates the bit string output from the rate matching unit 440 and transmits the modulated bit string to a receiving device (eg, 500 in FIG. 5 ).

Specifically, the modulator 450 may demultiplex the bits output from the rate matching unit 440 and map them to a constellation.

That is, the modulator 450 may serial-to-parallel-convert the bits output from the rate matching unit 440 to generate a cell composed of a certain number of bits. Here, the number of bits constituting each cell may be the same as the number of bits constituting a modulation symbol mapped to a constellation.

Then, the modulator 450 may map the demultiplexed bits to a constellation. That is, the modulator 450 modulates the demultiplexed bits through various modulation schemes such as QPSK, 16-QAM, 64-QAM, 256-QAM, 1024-QAM, and 4096-QAM to generate modulation symbols. It can be mapped to a constellation point. In this case, each cell may be sequentially mapped to a constellation point in that the demultiplexed bits constitute a cell including as many bits as the number of modulation symbols.

Also, the modulator 450 may modulate the signal mapped to the constellation and transmit the modulated signal to the receiving device 500 . For example, the modulator 450 may map a signal mapped to a constellation to an OFMD frame using an orthogonal frequency division multiplexing (OFDM) method and transmit the mapped signal to the receiving device 500 through an assigned channel.

Meanwhile, the transmitter 400 may previously store various parameters used for encoding, interleaving, and modulation. Here, the parameters used for encoding may be information about the code rate of the LDPC code, the codeword length, and the parity check matrix. Also, a parameter used for interleaving may be information about an interleaving rule, and a parameter used for modulation may be information about a modulation method. Also, information about puncturing may be a puncturing length. In addition, the repetition-related information may be the repetition length. The information on the parity check matrix can store exponential values of the circulation matrices according to Equations 3 and 4 when the parity matrix proposed in the present invention is used.

In this case, each component constituting the transmission device 400 may perform an operation using these parameters.

Meanwhile, although not shown, in some cases, the transmitter 400 may further include a controller (not shown) for controlling the operation of the transmitter 400 .

In the present invention, a method and apparatus of the rate matching unit 440 for supporting HARQ (Hybrid Automatic Repeat request) based on the LDPC code are described.

8 is a flowchart illustrating transmitter operation according to the present invention. Hereinafter, an LDPC code-based transmission method disclosed in the present invention will be described based on FIG. 8 .

In step 810, the transmitter determines the modulation order of the modulation symbol for transmission, the transport block size (Transport block size, TBS), and rv _idx (redundancy version index, or redundancy version). The values are control information The redundancy version index (rv _idx ) is an index value of the redundancy version, which is an integer smaller than a preset maximum value, and determines the position of the transmission start bit. The number of rv _idx may vary depending on the system, and in the LTE standard, there are four rv _idx 0, 1, 2, or 3. The rv _idx is determined by the transmitter at every transmission and transmitted to the receiver Alternatively, the rv _idx may be determined by the receiver and notified to the transmitter, and the transmitter may use the determined rv _idx . Alternatively, the rv _idx may be determined according to a preset order and number of retransmissions. Uplink in LTE system During link retransmission, the rv _idx value is determined in the order of 0, 2, 3, and 1, and this value is updated by calculating modulo 4. The modulation order and rv _idx can be determined in step 860.

In step 820, the transmitter segments the transport block (TB) into code block (CB) units based on the determined TBS value. A code block size (CBS) value is determined by the segmentation process. In step 830, the transmitter calculates the K _b value, which is the number of column blocks of the information word part of the parity check matrix, according to the parameters of the parity check matrix of the determined CBS and LDPC codes, and a cyclic permutation matrix constituting the QC-LDPC code, or Determines the size Z value of the 0-matrix. Then, in step 840, the transmitter determines the number N _b of column blocks of the parity check matrix considering retransmission, shift values of exponents of each cyclic permutation matrix of the parity check matrix (PCM), and the number N _cb of codeword bits considering retransmission. do. The N _cb may have the same value as N _b ×Z, may be determined differently from N _b ×Z according to a predetermined rule, and may be determined after step 840. N _b is the number of column blocks of the parity check matrix of the LDPC code, and may vary according to the CBS length. The maximum number of column blocks of the parity check matrix of the LDPC code is determined to be N _{b_max} , and N _b is less than or equal to N _{b_max} .

The N _cb may vary according to the maximum value of rv _idx . The range of rv _idx (the number and maximum value of rv _idx ) according to at least one element of a specific code rate and a specific UE category or parity check matrix or uplink / downlink (UL / DL) or the length of an information word ) may be different, the number of actually encoded bits may be different accordingly. In addition, N _cb is determined differently depending on at least one element of a specific code rate and a specific UE category or parity check matrix or uplink / downlink (UL / DL) or length of an information word, regardless of the rv _idx range It can be.

[First embodiment of processes 850 and 860]

In step 850, the transmitter performs LDPC encoding and interleaving based on the determined parameters. The interleaving may be performed only when necessary. A plurality of parity check matrices used for the LDPC encoding may exist, and a parity check matrix used for encoding is determined from among the plurality of parity check matrices according to a predetermined rule. In addition, the size of the parity check matrix used in the LDPC encoding may differ depending on rv _idx and a code rate. Actual encoding may be performed up to N _cb or performed only on bits necessary for current transmission based on the value of rv _idx . For example, if rv _idx is 0, encoding is E or (E+Z) or (E+2xZ), which is the sum of the bits required for transmission (=E) and the number of bits to be punctured (0 or Z or 2xZ) among the information bits ) can be performed only for

를 전송한다. 즉 과정 850의 출력 비트 스트림 W = (w₀, w₁, w₂,…,w_Ncb)과 부호어 비트의 개수 N_cb와 전송 비트의 개수 E와 전송 시작 비트의 index k₀를 기반으로 아래와 같이 비트 스트림이 전송된다. 상기 전송 비트의 개수 E는 할당된 부반송파(subcarrier) 수와 변조 방식에 기반하여 결정되는 값으로 860단계 이전에 결정 할 수 있다. e_k는 w_k 중에서 선택되어 전송되는 비트를 의미한다.In step 860, the transmitter determines the start position k ₀ of transmitted bits among LDPC coded bits and the number E of transmitted bits. The starting position k ₀ is determined by the rv _idx . In step 870, the transmitter outputs bit streams (w ₀ , w ₁ , w ₂ ,…,w _Ncb ) of process 850.

send That is, based on the output bit stream W = (w ₀ , w ₁ , w ₂ ,…,w _Ncb ) of step 850, the number of codeword bits N _cb , the number of transmission bits E, and the index k ₀ of transmission start bits, the following A bit stream is transmitted as well. The number E of transmission bits is a value determined based on the number of allocated subcarriers and a modulation scheme, and may be determined prior to step 860. e _k denotes a bit selected from among w _k and transmitted.

In the above, <NULL> means a bit padded with zero. In addition, certain bits among the information word bits may not always be transmitted.

As another embodiment of step 870, a case in which specific bits among information word bits are not always transmitted may be considered. The specific bits are referred to as punctured systematic bits.

[Second Embodiment of Process 850 and Process 860]

Among the output bit streams (w ₀ , w ₁ , w ₂ ,... , w _Ncb ), the bit streams (x ₀ , x ₁ , x ₂ ,..., x _{Ncb_ext} ) and the code excluding information word bits that are always punctured A bit stream is transmitted as follows based on the number of bits N _cb , the number of transmission bits E, and the index k ₀ of transmission start bits. Here, Ncb_ext = Ncb - Nsym_p where Nsym_p is the number of information word bits that are always punctured. For example, when 2*Z information bits are punctured, Ncb_ext = Ncb -2*Z. Also, when Ns bits that are shortened are excluded, Ncb_ext = Ncb - Nsym_p - Ns. The number E of transmission bits is a value determined based on the number of allocated subcarriers and a modulation scheme, and may be determined prior to step 860. e _k means a bit selected from x _k and transmitted.

or

or

or

Here, m is the number of rv_idx. K ₀ , which is the position (bit index) of the bit at which the transmission starts, will be described in more detail below in various embodiments of the present invention.

[Third Embodiment of Process 850 and Process 860]

Of the output bit streams (w ₀ , w ₁ , w ₂ ,..., w _Ncb ), the bit streams (x ₀ , x ₁ , x ₂ ,..., x _{Ncb_ext} ) and the code excluding information word bits that are always punctured A bit stream is transmitted as follows based on the number of bits N _cb , the number of transmission bits E, and the index k ₀ of transmission start bits. Here, Ncb_ext = Ncb - Nsym_p where Nsym_p is the number of information word bits that are always punctured. For example, when 2*Z information bits are punctured, Ncb_ext = Ncb - 2*Z. Also, when Ns bits that are shortened are excluded, Ncb_ext = Ncb - Nsym_p - Ns. The number E of transmission bits is a value determined based on the number of allocated subcarriers and a modulation scheme, and may be determined prior to step 860. e _k means a bit selected from x _k and transmitted.

or

or

or

Here, m is the number of rv_idx. K ₀ , which is the position (bit index) of the bit at which the transmission starts, will be described in more detail below in various embodiments of the present invention.

9 is a diagram illustrating a process of encoding data according to the present invention. According to FIG. 9, in the transmitter, a transport block is segmented into an information block, and the information block includes zero padding bits so that the total length is K _b ×Z, that is, a multiple of Z. will become Thereafter, the information word block is LDPC-encoded, and the total length of the codeword becomes N _b ×Z. The codeword bits may be interleaved. The position of the k ₀ value is determined, and the transmitter transmits the codeword bit after removing the zero-padded bits.

According to the present invention, the transmitter determines the k ₀ (=S _idx ) value indicating the position of the transmission start bit from the rv _idx , and sequentially transmits the codeword bit having the determined k ₀ value as an index. When transmitting, it is not necessary to determine all S _idx according to rv_idx (= 0, 1, 2 or 3), and the index of the transmission start bit (i.e., S _idx or k ₀ ) can be determined and transmitted based on rv _idx there is. If m redundancy version (RV) is defined, RV= {rv ₀ , rv ₁ , .., rv _(m-1) } and rv _idx = {0, 1, 2, … , m-1}. Index of start bit based on rv _idx S={s ₀ , s ₁ , … , s _(m-1) }.

9A is a diagram showing the second embodiment and the third embodiment. The case where some of the information word bits are always punctured and not input to the circular buffer is shown.

In the present invention, firstly, a method of determining a transmission order, that is, an order of redundancy versions (RVs) when retransmitting data is described. The order of RVs may be set differently according to the index of a modulation and coding scheme (MCS). That is, the order of redundancy versions is defined according to the MCS index (I _MCS ).

The current LTE standard provides the HARQ mode shown in Table 1 below.

[Table 1]

In particular, in LTE uplink (UL) transmission, in the case of retransmission during non-adpative HARQ operation, the base station does not transmit separate downlink control information (DCI, that is, UL grant) for data scheduling, and downlink (DL) physical HARQ channel When NACK is transmitted on (PHICH), the terminal automatically performs retransmission in the order of RV (Redundancy Version) 0, 2, 3, and 1 at a predetermined time.

However, when the LDPC code is used, additional considerations arise because a matrix for the LDPC code may be changed when a code rate is changed during data transmission. The present invention proposes a method of transmitting LDPC codeword bits from a specific bit position based on rv _idx to support the IR mode.

FIG. 10 is a diagram showing positions of LDPC codewords and preset specific bits for the retransmission. According to FIG. 10, positions of specific bits among LDPC codeword bits may be designated by redundancy version (rv). 8, rv ₀ (1000), rv ₁ (1010), rv ₂ (1020), . , the location of m specific bits of rv _m-1 (1030) is designated by the value of rv or rv _idx . The rv _idx of rv ₀ (1000) is 0, the rv _idx of rv ₁ (1010) is 1, the rv _idx of rv ₂ (1020) is 2, and the rv _idx of rv _m-1 (1030) is (m-1) . After generating the LDPC codeword, the transmitter may transmit it from a position indicated by rv. For example, in the first transmission, the bit indicated by rv ₀ may be transmitted, and in the case of the second transmission, the bit indicated by rv ₁ may be transmitted.

The present invention discloses a method for determining start positions of the initial transmission or retransmission according to a predetermined rule, and in particular, changing the transmission order according to the initial transmission code rate. Alternatively, a method of changing the order according to the retransmission code rate is disclosed. The transmission order means the order of rv _idx or the order of transmission start bit index.

When data is transmitted from the starting position determined by the predetermined rule, system overhead can be reduced because additional signaling bits are not required. On the other hand, since data is transmitted according to a predetermined rule, there may be a limit to the additionally obtainable encoding gain according to the code rate.

11A and 11B are diagrams illustrating overlapping codewords upon retransmission according to code rates. In the case of applying an LDPC code encoded based on the parity check matrices of FIGS. 6A and 6B according to the present invention, the following points should be noted when retransmitting. Among parity bits encoded based on the parity check matrix in FIGS. 6A and 6B, among the parity bits in the incremental redundancy bits part, the first parity bits close to the information word bits have a high importance, so when parity bits are selected in order during retransmission A high coding gain can be obtained. In addition, as bit duplication occurring during retransmission is reduced, the efficiency increases. That is, a high coding gain can be obtained when the signals are sequentially transmitted without overlapping as much as possible. That is, it can be transmitted with a lower error probability.

As shown in FIG. 11A, when the code rate is low, when the transmitter performs initial transmission (1100), RV is rv0 (rv _idx = 0), and during first retransmission (1110), RV is rv1 (rv _idx = 1), and second In retransmission 1120, if RV is rv2 (rv _idx = 2), the maximum encoding gain cannot be obtained because there are many overlapping bits transmitted. Therefore, when RV of initial transmission is rv ₀ and RV of first retransmission uses a value other than rv ₁ , a high coding gain can be obtained.

However, as shown in FIG. 11B, when the code rate is high, if RV is rv0 during initial transmission (1150) and RV is rv1 during first retransmission (1160), codeword bits transmitted starting with the bits indicated by rv0 and rv1 Among them, the number of overlapping bits transmitted may be less or absent compared to the case of transmission with a low code rate. Therefore, a higher encoding gain can be obtained than in the case of FIG. 11A.

Considering this point, the method for determining the transmission order during retransmission proposed in the present invention is as follows.

First, one of the preset transmission sequences may be selected and applied according to the initial transmission code rate. For example, when there are 4 rv values in total, one of the following 4 transmission orders can be selected and applied according to the code rate.

[Table 2]

Second, as an example of a method for specifying the transmission order, a codeword may be transmitted by selecting one of the four transmission orders according to an allocated modulation and coding scheme (MCS) index.

[Table 3]

The code rate may not be specified in the MCS table of Table 3 above.

Thirdly, according to the present invention, the actual code rate (effective code rate, R _eff ) determined by the MCS index, transport block size (TBS), and the number of sub-carriers to which codeword bits will be transmitted and the preset code By comparing threshold values (R _{th_i} , i = 0, 1, 2, ..., N _order -1) for the rate, better performance can be shown by using a specific RV order according to the comparison result. This method may be performed according to Equation 17 below. The R _eff is a ratio between the number of Transport Block Size (TBS) bits and the transmitted TBS-based codeword bits. The method of calculating the actual code rate may vary depending on the frame structure, for example (TBS + N _CRC ) / (N _PRB × (the number of resource elements (RE) per PRB - #RE for reference signaling ) × modulation order). Here, N _CRC is the number of CRC bits and may be 0. N _PRB means the number of allocated resource blocks, and #RE for reference signaling means the number of resource elements to which reference signaling is allocated. TBS means the number of bits that can be transmitted when specific I _TBS and N _PRB are applied. Alternatively, when the TB (Transport Block) is segmented into a plurality of CB (Code Blocks) and retransmitted in CB units or CBG (CB group) units, R _eff is the size of CB or the number of bits of CBG and CB or CBG transmitted It may be a ratio of the number of codeword bits.

[Equation 17]

RV index order indicator = i if R _eff < R _{th_i} ( 0≤ i < N _order )

The N _order is the maximum value of the possible RV index order indicators specified in Table 2, and means the maximum number of branches of the RV index order. The R _eff may be determined based on the I _MCS .

When using this method, the transmitter can perform data transmission in a preset order even if the receiver does not directly inform the rv _idx value using signaling such as DCI.

In addition, different patterns of rv _idx order may be used for each parity check matrix, or according to the TBS index or MCS index (I _MCS ) and N _PRB (size of physical resources used during data transmission) determined according to the MCS index and modulation order The rv _idx order may be determined.

Alternatively, according to the present invention, the same effect can be obtained by fixing the rv _idx order in a non-adaptive manner and then transmitting using an interleaver differently according to the initial transmission code rate.

12A and 12B are diagrams illustrating codewords transmitted when an interleaver is used differently. According to FIGS. 12A and 12B, 1200 means that the transmission order is fixed and codewords are transmitted in the order of rv ₀ , rv ₁ , rv _{2 ,} and rv ₃ . At this time, the codeword bits (= c ₀ , c ₁ , c ₂ , ..., c _N-1 ) are divided into bit groups based on the bits whose index is S _idx designated by rv _idx . The first bit group (Bit Group0) consists of c _s0 to c _{s1-1} . The second bit group (Bit Group1) consists of c _s1 to c _{s2-1} . The third bit group (Bit Group2) consists of c _s2 to c _{s3-1} . The fourth bit group (Bit Group3) consists of c _s3 to c _{N} . The fifth bit group (Bit Group4) consists of c _s0 to c _{s1-1} .

At this time, when interleaver 1 is applied, interleaver 1 arranges bit groups in the order of Bit Group4, Bit Group0, Bit Group2, Bit Group1, and Bit Group3 (1210). Even if the same rv _idx order is used, the starting point of actually transmitted bits can be changed. When interleaver 3 is applied, interleaver 3 (1230) arranges bit groups in the order of bit groups 0, 3, 1, and 2, and in this case, the transmitter also uses the same rv _idx order as when the interleaver is not used, You can change the starting point of transmitted bits. Therefore, it is possible to obtain the same effect as changing the order of rv _idx according to the code rate as described above by using an interleaver according to the code rate. Therefore, as a method for reducing signaling overhead, the order of rv _idx is used in a preset order and a different interleaver is used according to the initial transmission code rate so that a coding gain can be obtained.

In addition, the present invention discloses a method of determining an index of a bit designated as rv redundancy version index (rv _idx ), that is, an S _idx value. As described above, when codeword bits are transmitted, an S _idx value is determined from the determined rv _idx , and the bits having the determined S _idx value as an index are sequentially transmitted.

First, the interval of S _idx values indicated by each rv _idx can be adjusted by determining the number of codeword bits considering the maximum rv _idx value (=m-1) according to the code rate at the time of initial transmission. If the code rate is high at the time of initial transmission, the code rate at the time of retransmission based on the maximum rv _idx value may be higher than the minimum code rate that the LDPC code can support. For example, if the initial transmission code rate is 8/9, the minimum supportable code rate is 1/5, and the maximum value (m-1) of rv _idx is 3, the maximum retransmission code rate is 8/36 (= 8/9×1/4), which is higher than 1/5. In this case, if the number of codeword bits (=N _cb ) is determined based on the code rate 8/36 and S _idx is set based on this, the number of codeword bits (=N _cb ) is determined based on the code rate 1/5 It is possible to obtain a higher encoding gain than when S _idx is set based on this determination.

Also, according to the present invention, when the maximum value of rv _idx is (m-1), the codeword bit length N _cb is set to a value equal to or smaller than k/R*m. k is the number of information word bits and may be equal to CBS or equal to K _b × Z. The code rate R may be specified as a value according to I _MCS in the MCS table or an effective code rate may be used. The effective inefficiency may be changed according to the number of information word bits and the number of RBs allocated for transmission (ie, resource size).

For example, N _cb is determined based on Equation 18 below.

[Equation 18]

또는,

or,

A case in which specific Nsym_p bits among information word bits are not always transmitted may be considered. The specific bits are referred to as punctured systematic bits.

In this case, Ncb_ext of the second embodiment is determined based on Equation 18-A below.

[Equation 18-1]

The Ns is the number of short bits.

When a limited buffer is used, Ncb and Ncb_ext are compared with the limited buffer size to select a smaller value.

N _b is the number of column blocks of the parity check matrix of the LDPC code, and may vary according to the CBS length. The N _b is a value smaller than or equal to N _bmax , the maximum number of column blocks of the parity check matrix. In addition, as mentioned above, N _cb depends on at least one element of whether it belongs to a specific code rate and a specific UE category, a parity check matrix, uplink or downlink (UL/DL), or the length of an information word. may be determined differently. k may be the same value as CBS or the number of input bits (K _b ×Z) of the LDPC code, which is a value obtained by adding the number of zero padding bits to CBS. In this case, 0, 1, … , (m-1), the S _idx value based on rv _idx determined as one of (m-1) or the index k ₀ of the transmission start bit may be determined according to Equation 19 below.

[Equation 19]

또는,

or,

The value of m may be different according to the initial transmission code rate. Alternatively, the value of m may be different according to the parity check matrix, and may be different according to the UE category or DL or UL. a means the position of S ₀ where rv _idx =0. a may be equal to the size Z of the sub-matrix of the parity check matrix of the LDPC code, a multiple of Z, or 0.

When performing actual encoding, the transmitter may perform up to N _cb or may perform only up to bits necessary for transmission.

Second, S _idx values, that is, k ₀ values, are multiplied by a lifting value Z for determining a parity check matrix. This is a method for facilitating a decoder operation. FIG. 13A is a diagram showing a method of determining a retransmission start point, and in particular, an S _idx value determined by rv _idx determined by the above method. As shown in FIG. 13, the position of the S _idx value is located in multiples of Z. In the present invention, for this purpose, S _idx values are determined with zero padding bits included.

At this time, S _idx may be determined as shown in Equation 20 below.

[Equation 20]

또는,

or,

또는,

or,

또는

or

The rv _idx is 0≤i<m, and the m may vary according to the code rate. N _cb is the number of codeword bits considering retransmission and can be determined as shown in Equation 17 above. Alternatively, N _cb = min(N _bmax *Z, N _max ). N _bmax is the maximum number of column blocks of the parity check matrix shown in FIGS. 6A and 6B. N _max is the preset maximum number of coded bits. If N _max is not set, N _cb = N _bmax ×Z can be obtained. In addition, as mentioned above, N _cb is determined differently according to at least one element of a specific code rate, a specific UE category, a parity check matrix, whether uplink or downlink (UL/DL), or the length of an information word. It can be. a means the position of S ₀ where rv _idx =0. a may be equal to the size Z of the sub-matrix of the parity check matrix of the LDPC code, a multiple of Z, or 0. Actual encoding may be performed up to N _cb or performed only for bits (=E) necessary for transmission.

Thirdly, intervals between S _idx can be set differently according to the code rate. Specifically, the location of the transmission start point may be determined as shown in Equation 21 below.

[Equation 21]

또는,

or,

는 상위 레이어 시그널링(higher layer signaling, 이는 RRC signaling으로도 해석할 수 있다) 또는 MAC CE 또는 하향링크 물리 계층 신호(L1 DL control)에 의해 미리 설정(configuration)된 값일 수 있고, 또는 직접 송수신기가 계산할 수 있다. 또한 상기

는 부호율 및 정보어 길이(즉 CBS)에 따라 달리 결정될 수 있다. 구체적으로 MCS 인덱스 또는 MCS 인덱스와 변조 차수에 따라 결정된 TBS 인덱스 또는 MCS 인덱스와 N_PRB(데이터 전송시 사용되는 물리 자원의 크기)에 따라 미리 결정되어 있을 수 있다. 일례로

이고 상기 R은 초기 전송 부호율로 MCS 인덱스에 의해 결정될 수 있다. 또한 상기

는 패리티 검사 행렬 및 UE 카테고리에 따라 다를 수 있다. rv_idx는 0≤i<m이고 상기 m은 부호율에 따라 다를 수 있다. N_cb는 재전송을 고려한 부호어 비트의 개수로 상기 수학식 17과 같이 결정될 수 있다. 또는 N_cb = min(N_bmax×Z, N_max)로 결정될 수 있다. 또는 N_cb = min(N_b×Z, N_max)로 결정될 수 있다. N_bmax는 도 6a과 도 6b에서 도시한 패리티 검사 행렬의 열 블록의 최대 개수이고, N_b는 N_bmax보다 작거나 같은 값으로 소정의 규칙에 의해 결정된다. N_max는 기설정된 최대 부호화 비트의 개수이다. N_max를 설정하지 않았을 경우에는 N_cb = N_bmax×Z 또는 N_cb = N_b×Z 로 설정된다. 또한 상기에서 언급한 바와 같이 N_cb는 특정 부호율 및 특정 UE 카테고리(category) 또는 패리티 검사 행렬 또는 상향링크 또는 하향링크(UL/DL) 여부 또는 정보어의 길이 중 적어도 하나의 요소에 따라 다르게 결정될 수 있다. a 는 rv_idx=0인 S₀의 위치를 의미한다. a는 LDPC 부호의 패리티 검사 행렬의 서브 행렬의 크기 Z와 동일 하거나 Z의 배수 혹은 0일 수 있다. 이 때 실제 부호화는 N_cb까지 수행되거나 전송시 필요한 비트(=E, 이는 전송하는 부호어 비트의 개수로 이해될 수 있다)에 대해서만 수행될 수도 있다. 또한 상기 세 번째 방법에 의하여 S_idx를 결정할 경우 작은 idx의 S_idx 값이 큰 idx의 S_idx 보다 더 클 수 있다. 즉 S₁>S₂ 일 수 있다. remind

May be a value configured in advance by higher layer signaling (which can also be interpreted as RRC signaling) or MAC CE or downlink physical layer signal (L1 DL control), or directly calculated by the transceiver. can Also reminded

may be determined differently depending on the code rate and information word length (ie, CBS). Specifically, it may be predetermined according to the TBS index or MCS index determined according to the MCS index and the modulation order and N _PRB (size of physical resources used during data transmission). as an example

And R is the initial transmission code rate and may be determined by the MCS index. Also reminded

may be different depending on the parity check matrix and UE category. rv _idx is 0≤i<m, and m may be different depending on the code rate. N _cb is the number of codeword bits considering retransmission and can be determined as shown in Equation 17 above. Alternatively, N _cb = min(N _bmax ×Z, N _max ). Alternatively, N _cb = min(N _b ×Z, N _max ). N _bmax is the maximum number of column blocks of the parity check matrix shown in FIGS. 6A and 6B, and N _b is a value smaller than or equal to N _bmax and determined by a predetermined rule. N _max is the preset maximum number of coded bits. If N _max is not set, N _cb = N _bmax ×Z or N _cb = N _b ×Z is set. In addition, as mentioned above, N _cb may be determined differently depending on at least one element of a specific code rate, a specific UE category, a parity check matrix, whether uplink or downlink (UL/DL), or the length of an information word. can a means the position of S ₀ where rv _idx =0. a may be equal to the size Z of the sub-matrix of the parity check matrix of the LDPC code, a multiple of Z, or 0. In this case, actual encoding may be performed up to N _cb or may be performed only for bits necessary for transmission (=E, which may be understood as the number of codeword bits to be transmitted). Also, when the S _idx is determined by the third method, the S _idx value of the small idx may be greater than the S idx value of the large _idx . That is, it may be S ₁ >S ₂ .

In the case of using the above method, the transmitted bits when the RV value is rv _i , that is, rv _idx = i, and the same bits among the transmitted bits when the RV value is rv _{i + 1,} that is, rv _idx = (i + 1) Since the number can be minimized, the coding gain can be maximized by sequentially using RVs during retransmission.

As mentioned in Embodiment 2 and Embodiment 3, when specific information bits are not always transmitted, the Ncb value of Equation 21 can be determined by Equation 18-1. In the case of Example 2, in Equation 21 above, a may be 0.

에 대해 상세히 설명한다. HARQ-IR 방식을 사용할 경우 상기 기술한 바와 같이 재전송을 통해 최대한 새로운 부호어 비트를 전송해야 부호어 이득을 얻을 수 있다. 그러므로 부호율에 따라 rv값에 따른 전송 시작 비트의 위치를 달리해야 부호어 이득을 최대로 얻을 수 있다. 이 때 구체적인 전송 시작점의 위치는 아래 수학식 22와 같이 특정 값

를 기반으로 하여 패리티 검사 행렬의 순환 순열 행렬의 사이즈의 배수로 결정될 수 있다.In the following

explain in detail. In the case of using the HARQ-IR scheme, as described above, a codeword gain can be obtained only when maximum new codeword bits are transmitted through retransmission. Therefore, the position of the transmission start bit according to the rv value must be changed according to the code rate to obtain the maximum codeword gain. At this time, the location of the specific transmission start point is a specific value as shown in Equation 22 below.

It may be determined as a multiple of the size of the cyclic permutation matrix of the parity check matrix based on .

[Equation 22]

또는,

or,

The a may be a value preset as a position of a transmission start bit when rv _idx = 0. As mentioned in Embodiment 2 and Embodiment 3, when specific information bits are not always transmitted, the Ncb value of Equation 22 can be determined by Equation 18-A. In the case of Example 2, a in Equation 22 may be 0.

은 부호율 및 정보어 길이(즉 CBS)에 따라 달라질 수 있다. 구체적으로 MCS 인덱스 또는 MCS 인덱스와 변조 차수에 따라 결정된 TBS 인덱스 또는 MCS 인덱스와 N_PRB(데이터 전송시 사용되는 물리 자원의 크기)에 따라 미리 결정되어 있을 수 있다. 또한 수학식 22의

및 a는 특정 부호율 및 특정 정보어 길이 (TBS(transport block size), CBS(code block size), CBGS(code block group size) 등) 및 특정 UE 카테고리(category) 또는 패리티 검사 행렬 또는 상향링크 또는 햐향링크(UL/DL) 전송 여부 또는 정보어의 길이 중 적어도 하나의 요소에 따라 다르게 결정될 수 있다. 예를 들어 상기 하나의 요소에 의해서

는 항상 고정된 값을 사용할 수 있다. remind

may vary according to the code rate and information word length (ie, CBS). Specifically, the MCS index or TBS index or MCS index determined according to the MCS index and modulation order may be determined in advance according to N _PRB (size of physical resources used during data transmission). Also in Equation 22

And a is a specific code rate and specific information word length (transport block size (TBS), code block size (CBS), code block group size (CBGS), etc.) and a specific UE category or parity check matrix or uplink or It may be determined differently according to at least one element of downlink (UL/DL) transmission or not or the length of an information word. For example, by the above one element

can always use a fixed value.

는 아래 수학식 23과 같을 수 있다. As an example above

May be as shown in Equation 23 below.

[Equation 23]

또는

or

The R may be a code rate and a value configured in advance by higher layer signaling (which can also be interpreted as RRC signaling) or MAC CE or downlink physical layer signal (L1 DL control), Alternatively, the direct transceiver can calculate. Alternatively, it may be a value displayed in the MCS table. Alternatively, R = f (k / E), which means that R is an arbitrary function with k / E as a variable. k is the number of information bits (the length of the information word of the LDPC code, the number of bits of TBS, CBS, or CBG, and the length including CRC bits if necessary), and E means the number of code word bits to be transmitted. The number E of codeword bits to be transmitted may be determined according to a frame structure in which the information bits are encoded and transmitted, the number of layers, a modulation method, and the like. K _b means the number of column blocks of the information word part of the parity check matrix of the LDPC code, and varies according to the length (k) of the information word of the LDPC code. For example, K _b =k/Z. Therefore, the value of k _b depends on k and Z. Z is the size of the cyclic permutation matrix of the parity check matrix of the LDPC code. The information word of the LDPC code means a bit string obtained by padding zero bits to CB (or a bit string including CRC in TB).

또는 (1/R)로 정의하도록 한다. 이 때 부호율이 높을수록

값은 작다.Alternatively, the 1/R value can be integerized and used in the MCS table. That is, a predetermined integer value defined for each MCS index in the MCS table

or (1/R). In this case, the higher the code rate, the

value is small

값은 아래 수학식 24와 같이 정의될 수 있다.or

The value may be defined as in Equation 24 below.

[Equation 24]

또는

또는

or

or

는 이전 전송의 전송 부호율을 기반으로 결정하는 것이 더 우수한 성능을 보장 할 수 있다. 상기 재전송시 이전 전송(또는 초기 전송)과 전송 부호율이 동일하다는 의미는 재전송시 전송되는 부호화 비트의 개수가 이전 전송(또는 초기 전송)시 전송되는 부호어 비트의 개수와 동일한 경우로, 일 예로 할당된 MCS 인덱스와 서브 캐리어의 개수 (혹은 PRB의 개수)가 동일한 경우를 의미한다. 재전송시의 전송 부호율이 이전 전송(또는 초기 전송)시 전송 부호율과 다를 경우 이전 전송시 전송 부호율 혹은 MCS 인덱스를 기반으로 하여 상기 수학식 23 또는 상기 수학식 24의 R값 또는 I_MCS가 사용될 수 있다. 이 경우 송수신기는 이전 전송시 전송 부호율 또는 전송된 부호어 비트의 개수 또는 MCS 및/또는 N_PRB 등을 저장할 필요가 있다. When determining the transmission start bit based on Equation 21 or Equation 22, the

is determined based on the transmission code rate of the previous transmission to ensure better performance. The meaning that the transmission code rate is the same as the previous transmission (or initial transmission) during retransmission means that the number of coded bits transmitted during retransmission is the same as the number of codeword bits transmitted during previous transmission (or initial transmission). For example, This means that the allocated MCS index and the number of subcarriers (or the number of PRBs) are the same. If the transmission code rate during retransmission is different from the transmission code rate during previous transmission (or initial transmission), the R value or I _MCS of Equation 23 or Equation 24 above is based on the transmission code rate or MCS index during previous transmission can be used In this case, the transceiver needs to store the transmission code rate or the number of transmitted codeword bits or MCS and/or N _PRB during previous transmission.

값을 결정하는 방법을 결정 할 수 있다. 이 때 하향링크에 대한 제어 정보에 포함된 RV 모드 지시자는 초기 전송에서 데이터 전송을 위해 사용한 부호율과 현재 전송(재전송)에서 사용하는 부호율이 같은지 여부를 지시할 수 있고, 상향링크에 대한 제어 정보에 포함된 RV 모드 지시자는 초기 전송에서 데이터 전송을 위해 사용된 부호율과 앞으로 전송할 데이터의 부호율이 같은지 여부를 지시할 수 있다. Or based on the RV mode indicator included in the downlink control information as follows

You can decide how to determine the value. At this time, the RV mode indicator included in the downlink control information may indicate whether the code rate used for data transmission in the initial transmission and the code rate used in the current transmission (retransmission) are the same, and control for uplink The RV mode indicator included in the information may indicate whether a code rate used for data transmission in initial transmission and a code rate of data to be transmitted in the future are the same.

이 결정될 수 있고, 이전 전송과 현재 전송의 파라미터들이 동일하지 않을 경우 (예를 들어 지시자가 1인 경우) 소정의 고정된 값(예를 들어 rv index 개수)을 기반으로

이 결정될 수 있다. If the transmission parameters of the previous transmission and the current transmission are the same according to the indicator (for example, when the indicator is 0), based on the current transmission parameter (for example, transmission code rate and information word bit)

can be determined, and if the parameters of the previous transmission and the current transmission are not the same (eg, when the indicator is 1), based on a predetermined fixed value (eg, the number of rv indexes)

this can be determined.

값의 특징을 더 기술한다. 도 13b는

값에 따라 전송되는 비트를 도시한 도면이다. 도 13b에 따르면, k_b, N_b 값이 같더라도 R과

값이 다름에 따라 재전송시 전송되는 비트의 수가 다름을 알 수 있다. 구체적으로 (a)의 경우 부호율 R이 8/9이고 값이 24일 때 3번째 전송시(2번째 재전송시) 전송되는 비트는 1300이 되고, (b)의 경우 R이 1/2이고 값이 44일 때 2번째 전송시 전송되는 비트는 1310이 된다. below

Further characterize the value. Figure 13b

It is a diagram showing bits transmitted according to values. According to FIG. 13B, even if the values of k _b and N _b are the same, R and

As the value is different, it can be seen that the number of bits transmitted during retransmission is different. Specifically, in the case of (a), when the code rate R is 8/9 and the value is 24, the transmitted bit at the third transmission (at the second retransmission) is 1300, and in the case of (b), R is 1/2 and the value When is 44, the bit transmitted in the second transmission is 1310.

는 특정 부호율 범위 내에서는 같은 값을 가질 수 있다. 또는 특정 MCS index 범위 내에서는 같은 값을 가질 수 있다. 일례로, 부호율 5/6부터 8/9에서는

일 수 있다. 상기 부호율 또는

는 설정 가능(configurable)할 수 있으며,

를 결정하는 방법은 상기에서 언급한 바와 같이 특정 부호율 및 특정 정보어 길이(TBS, CBS, CBGS 등) 및 상향링크 또는 하향링크 전송 여부에 따라 혹은 단말 카테고리(UE category) 중 적어도 하나의 요소에 따라 다를 수 있다. remind

may have the same value within a specific code rate range. Alternatively, it may have the same value within a specific MCS index range. For example, in code rates 5/6 to 8/9

can be The code rate or

can be configurable,

As mentioned above, the method for determining is according to a specific code rate, a specific information word length (TBS, CBS, CBGS, etc.) and whether uplink or downlink transmission or to at least one element among UE categories may vary depending on

은 부호율과 정보어 길이의 조합에 따라 다르게 사용될 수 있다. 일례로 정보어 길이가 작을 경우 동일 부호율에 대하여

은 정보어의 길이가 길 경우의

보다 클 수 있다. 이는 정보어 길이가 작을 경우의 부호어 비트의 개수 N_cb가 정보어 길이가 길 경우의 N_cb 보다 클 수 있기 때문이다. 이 때 전송되는 LDPC 부호어의 길이가 길면 수신기 측의 복호기 메모리의 사이즈가 증가하여야 하므로 부호어의 길이 (또는 N_cb)는 정보어 길이에 따라 제한할 수 있다. 또한 N_cb 및 N_b는 단말의 버퍼 크기(user buffer size) 및 HARQ 과정(HARQ processing)의 개수에 따라 다를 수 있다. 그러므로 상기 최대 rv index 개수 및

은 UE 카테고리(category)에 따라 다를 수 있다.In addition, in Equation 22

may be used differently according to a combination of code rate and information word length. For example, when the information word length is small, for the same code rate

When the length of the information word is long

can be bigger This is because the number of codeword bits N _cb when the information word length is small may be greater than N _cb when the information word length is long. At this time, if the length of the transmitted LDPC codeword is long, the size of the decoder memory of the receiver must increase, so the length of the codeword (or N _cb ) can be limited according to the length of the information word. Also, N _cb and N _b may vary depending on the user buffer size of the UE and the number of HARQ processing. Therefore, the maximum rv index number and

may be different depending on the UE category.

In another embodiment of the present invention, the locations of transmission start points are determined by a specific code rate, modulation method, bit interleaver, information word length (transport block size (TBS), code block size (CBS), code block group size (CBGS), etc.) , the length of transmission bits, a parity check matrix, a specific UE category, and uplink or downlink (UL/DL) transmission. In the case of using a higher-order modulation method, performance may be better if a position mapped to a modulation symbol is changed while retransmitting some bits among previously transmitted bits. Therefore, in case of transmission using a high-order modulation scheme, determining the location of the transmission start point according to the RV mode indicator in consideration of retransmission of the same bits can improve system performance.

As a simple method, it can be defined as a set having as many elements as the number of RV mode indicators including transmission start points. At this time, the set indicating the positions of the transmission start point is a specific code rate, modulation method, information word length (TBS (transport block size), CBS (code block size), CBGS (code block group size), etc.), transmission bit length, parity It is determined differently according to at least one element among a check matrix, a specific UE category, and whether uplink or downlink (UL/DL) transmission is performed.

For example, if the number of column blocks of the parity check matrix is 68 and the input bits related to two of the column blocks are always punctured and not transmitted, the codeword bits (Ncb) are 66*Z, and the location of the transmission start point is A set can be defined as: The Z is the size of the cyclic permutation matrix of the parity check matrix of the LDPC code. Hereinafter, the position of the transmission start point means the position from bits excluding the bits that are always punctured.

Set1 = {0, 17*Z, 33*Z, 50*Z}

Set2 = {0, 25*Z, 33*Z, 50*Z}

Set3 = {0, 28*Z, 33*Z, 50*Z}

If (R >= 0.89 and MOD=256 QAM) or (R >= 0.89 and MOD=64QAM) or (R>= 0.89 and MOD=16 QAM) then starting positions set is set3

else if (R >= 0.82 and MOD=256 QAM) or (R >= 0.82 and MOD=64QAM) or (R>= 0.77 and MOD= 16 QAM) or (R>= 0.77 and MOD= QPSK) then starting positions set is set2

else then starting positions set is set1

As another example, when the number of column blocks of the parity check matrix is 68, at least one of the sets set1, set2, and set3 is used for all code rates and modulation schemes.

The set may also be expressed as Set1 = {0, 17, 33, 50}, Set2 = {0, 25, 33, 50}, and Set3 = {0, 28, 33, 50}.

As another example, if the number of column blocks of the parity check matrix is 68 and the bits related to the two column blocks are not always punctured and transmitted, the set indicating the positions of the transmission start points indicated by the RV mode indicator is { 0, 15*Z, 23*Z, 37*Z}. The set may also be expressed as {0, 15, 23, 37}.

In FIG. 23a, when the transmission start point is determined using set 1 and set 3, the SNR difference satisfying BLER = 0.01 is indicated according to the code rate and modulation method. As shown, it can be seen that BLER = 0.01 can be satisfied based on a lower SNR when different sets are used according to the code rate and modulation method.

For example, if the number of column blocks of the parity check matrix is 52 and the input bits related to two of the column blocks are always punctured and not transmitted, the codeword bits (Ncb) are 50*Z, and the location of the transmission start point is A set can be defined as: Z is the size of the cyclic permutation matrix of the parity check matrix of the LDPC code. Hereinafter, the location of the transmission start point means a location from bits excluding the always-punctured bits.

Set4 = {0, 13*Z, 25*Z, 38*Z}

Set5 = {0, 18*Z, 25*Z, 38*Z}

If (R >= 0.62 and MOD=256 QAM) or (R >= 0.62 and MOD=64QAM) or (R>= 0.53 and MOD=16 QAM) or (R>= 0.53 and MOD= QPSK) then starting positions set is set4

else starting positions set is set5

Set4 = {0, 13, 25, 38} and Set5 = {0, 18, 25, 38} may also be expressed.

As another example, when the number of column blocks of the parity check matrix is 52, at least one of the sets set1, set2, and set3 is used for all code rates and modulation schemes.

As another example, if the number of column blocks of the parity check matrix is 52 and the bits related to the two column blocks are always punctured and not transmitted, the set indicating the positions of the transmission start points indicated by the RV mode indicator is { 0, 11*Z, 16*Z, 25*Z}. The set may be expressed as {0, 11, 16, 25}.

In FIG. 23B, when the transmission start point is determined using set 4 and set 5, the SNR difference satisfying BLER = 0.01 is indicated according to the code rate and modulation method. As shown, it can be seen that BLER = 0.01 can be satisfied based on a lower SNR when different sets are used according to the code rate and modulation method.

When expressing the set, Z can be excluded.

In the above embodiments, R is a code rate configured in advance by higher layer signaling (which can also be interpreted as RRC signaling) or MAC CE or downlink physical layer signal (L1 DL control) value, or directly calculated by the transceiver. Alternatively, it may be a value displayed in the MCS table. Alternatively, R = f (k / E), which means that R is an arbitrary function with k / E as a variable. k is the number of information bits (the length of the information word of the LDPC code, the number of bits of TBS, CBS, or CBG, and the length including CRC bits if necessary), and E means the number of code word bits to be transmitted. The number E of codeword bits to be transmitted may be determined according to a frame structure in which the information bits are encoded and transmitted, the number of layers, a modulation method, and the like. The information word of the LDPC code means a bit string obtained by padding zero bits to CB (or a bit string including CRC in TB).

The present invention discloses a modulation symbol mapping method and apparatus when performing retransmission. When the codeword bits are converted into modulation symbols and then transmitted and received, the LLR (log likelihood ratio) of the bits during decoding may be high or low depending on the position of the bits constituting the modulation symbol to which the codeword bits were mapped. . At this time, when the symbol is modulated in the same way, if the bit at the position that can have the high LLR is continuously transmitted at the same position and the bit at the position that can have the low LLR is continuously transmitted at the same position, even if retransmission is performed, the bit with the low LLR In the case of , the possibility of having a continuously low LLR increases. A method for solving this problem is described below.

14A is a diagram illustrating a modulation symbol mapping method when identical bits are transmitted to the same location among modulation symbols during retransmission. (a) of FIG. 14A shows that when retransmitted symbols are identically mapped, the bit at position 1400 is continuously mapped to msb (most significant bit) and transmitted even if retransmission is performed. When the present invention is applied, when a codeword bit is modulated into a symbol, when a shift is performed by rv _idx within a bit corresponding to one symbol, 1400 bits become 1410 positions, and lsb (least significant bit) becomes do. Since the LLRs of msb and lsb are different during symbol modulation, not only 1400 bits but also bits next to 1400 bits are transmitted with high and low LLRs during initial transmission and retransmission, so even performance can be shown.

14B is a diagram illustrating a modulation symbol mapping method when retransmitted symbols are not identical. If the bits constituting the modulation symbols to be mapped during retransmission are not the same, the bit at position 1450 is shifted by rv and even if it is at position 1460, it can be msb as in the initial transmission. can do. Therefore, in order for the transceiver to determine whether or not the retransmitted symbols are the same and not to perform modulation, symbol modulation is performed by applying both of the above methods. Specifically, values obtained by adding the rv index value and the symbol index value are cyclically shifted for each symbol.

15 is a diagram illustrating a method of applying a cyclic shift to each symbol. According to FIG. 15, when 16QAM (Quadrature Amplitude Modulation) is applied, according to (a), when cyclic shift is not applied, codeword bits C ₀ , C ₁ , C ₂ and C ₃ are sequentially symbol-modulated. It is mapped to bits b ₀ , b ₁ , b ₂ and b ₃ for. According to (b), when the value obtained by adding the rv index and the symbol index is 1, codeword bits C ₃ , C ₀ , C ₁ and C ₂ are used as bits b ₀ , b ₁ , b ₂ and b ₃ for symbol modulation. substituted, and according to (c), when the value obtained by adding the rv index and the symbol index is 2, bits b ₀ , b ₁ , b ₂ and b ₃ for symbol modulation are codeword bits C ₂ , C ₃ , C ₀ and C ₁ is substituted.

16A is a block diagram illustrating an apparatus for implementing the present invention. Referring to FIG. 16A, the interleaver 1600 may perform a cyclic shift between bits based on the input rv index and symbol index, and the mapper 1610 modulates the shifted bits into symbols.

16B is a flowchart illustrating a modulation symbol mapping method according to an embodiment of the present invention. According to FIG. 16B, the transmitter determines a redundancy version (RV) or an index (rv _idx ) of the redundancy version (1650) and determines a transmission start position (S _idx or k ₀ ) (1660). Then, the transmitter determines the bit mapping order for the modulation symbol (1670), which is determined based on the rv index and the symbol index. The rv _idx may be a value transmitted by signaling, may be determined according to a preset order, or may be determined by a predetermined method according to the present invention.

17 is a diagram illustrating a data retransmission method according to an embodiment of the present invention. According to FIG. 17, the transmitter 1700 initially transmits data to the receiver 1710 (1720). Thereafter, the receiving end transmits a NACK (negative acknowledgment) indicating that data decoding has failed to the transmitting end (1730), and upon receiving this, the sending end transmits the rv value (rv index) for data retransmission, the position of the transmission start bit, and the codeword. At least one of the number of bits and a cyclic shift value according to a modulation symbol mapping method for retransmission is determined (1740), and data retransmission is performed based on the determination (1750). Also, in step 1740, at least one of a maximum transmission bit and a maximum transmission rate may also be determined.

Hereinafter, an embodiment in which rv_idx is used according to a preset order of rv_idx when parity check matrices are different will be described.

In order to easily store and display a plurality of parity check matrices, when the number of blocks (Kb) of information bits shown in FIG. there is. That is, parity check matrices using different sizes (Z) of cyclic permutation matrices and exponents of cyclic permutation matrices based on the same number of information word blocks (Kb) and number of codeword blocks (Nb) are in the same parity check matrix group. belong For example, the first parity check matrix group (PCM group 1) and the second parity check matrix group (PCM group2) may be specified according to Kb and Nb as follows.

At this time, when rv_idx is transmitted in a predetermined order without transmission through separate signaling, different transmission orders may be used according to parity check matrix groups as follows.

The present invention discloses another embodiment of a modulation symbol mapping method and apparatus. In the rate matching unit 440 shown in FIG. 4, a block interleaver may exist after the puncturing/repetition/zero removal unit 442.

As shown in FIG. 4 , the output bits of the rate matching unit 440 are input to the modulation unit 450 . The modulator includes a mapper that maps input bits to bits constituting a modulation symbol. The mapping order may be different depending on rv_idx and retransmission. For example, when transmission is performed based on the same rv_idx as rv_idx used in previous transmission, mapping may be performed in the reverse order of the mapping order used in previous transmission. More specifically, at least when rv_idx is 0, the mapping order is mapped in the reverse order of the mapping order used in the previous transmission where rv_idx is 0. Assuming 256QAM, an embodiment is shown in FIG. 24. When rv_idx is j in the same ith transmission, bits are mapped to symbols based on mapper-1, and mapper-2 is used in at least one case where rv_idx is j among ith or more transmissions. In this case, performance improvement can be obtained based on the different reliability characteristics of each bit constituting the modulation symbol.

When the same rv_idx is repeated, if the mapping is different, performance can be improved by repeating the same rv_idx rather than using different values for all rv idx during retransmission.

In the case of retransmission based on the above method, LDPC encoding / decoding system based on the parity check matrix group based on the parity check matrix group of (Kb, Nb) = (22, 68) or (10, 52) In , when retransmitted according to the preset rv_idx, the order of {0, 2, 0, 3, 1} is used. Alternatively, the preset order of rv_idx may be {0, 2, 0, 3}. Alternatively, the preset order of rv_idx may be {0, 2}.

The order was determined by the following method.

1) It is assumed that 0 is used for rv_idx in the first transmission.

2) For(0<i<N+1)

A. Based on the rv_idx determined until the (i-1)th transmission, rv_idx with excellent performance in various modulation schemes and code rates is determined during the ith transmission.

3) End for

A more specific transmission sequence is shown in FIG. 25 .

It is first determined whether rv_idx is signaled or not. When rv_idx is determined based on a preset order without being signaled, it is determined what number of transmissions it is. If the number of elements in the rv_idx order set is S and the number of transmissions is i, the value of (i mod S) in the rv_idx order set is determined as rv_idx.

When a parity check matrix belonging to the first parity check matrix group is used, the rv_idx order may be {0 2 1 3}.

When a parity check matrix belonging to the second parity check matrix group is used, the rv_idx order may be {0 2 3 1}.

If mapping in reverse order is used at least once for the same rv_idx, rv_idx_order may be { 0 2 0 3 1 }. For the transmission number i, if (i mod 5) = 2, codeword bits are mapped to modulation symbols based on the reverse order of the mapping sequence used in (i mod 5) = 0.

Alternatively, rv_idx_order may be { 0 2 0 3 }. If (i mod 4) = 2 for transmission number i, codeword bits are mapped to modulation symbols based on the reverse order of the mapping order used in the ith transmission satisfying (i mod 4) = 0.

Alternatively, rv_idx_order may be { 0 2 }. If (i mod 4) = 2 for transmission number i, codeword bits are mapped to modulation symbols based on the reverse order of the mapping order used in the ith transmission satisfying (i mod 4) = 0. In addition, when (i mod 4) = 3, codeword bits are mapped to modulation symbols based on the reverse order of the mapping sequence used in the ith transmission satisfying (i mod 4) = 1.

Although the present invention has been described for the case of data retransmission, it is obvious that it can be applied to all signals transmitted between the base station and the terminal as well as data. Also, the transmitting end and the receiving end of FIG. 17 may be at least one of a base station or a terminal.

18 is a block diagram showing the configuration of an encoding device according to an embodiment of the present invention. In this case, the encoding device 1800 may perform LDPC encoding.

According to FIG. 18, an encoding device 1800 includes an LDPC encoder 1810. The LDPC encoder 1810 may generate an LDPC codeword by performing LDPC encoding on input bits based on the parity check matrix.

)을 구성할 수 있다. LDPC 인코더(1810)는 K_ldpc 개의 LDPC 정보어 비트들을 시스테매틱하게 LDPC 인코딩하여, N_ldpc 개의 비트들로 구성된 LDPC 코드워드 Λ=(c₀,c₁,...,

)=(i₀,i₁,...,

,p₀,p₁,...,

)를 생성할 수 있다. 상기 생성 과정은 상기 수학식 1에서 서술한 바와 같이 상기 LDPC 코드워드와 패리티 검사 행렬의 곱이 제로 벡터가 되도록 부호어를 결정하는 과정을 포함한다. 본 발명의 패리티 검사 행렬은 상기 도 3에서 정의한 패리티 검사 행렬과 동일한 구조를 가질 수 있다.K _ldpc bits are K _ldpc LDPC information bits for the LDPC encoder 1810 I=(i ₀ ,i ₁ ,...,

) can be configured. The LDPC encoder 1810 systematically LDPC-encodes K _ldpc bits of LDPC information, and obtains an LDPC codeword composed of N _ldpc bits Λ=(c ₀ ,c ₁ ,...,

)=(i ₀ ,i ₁ ,...,

,p ₀ ,p ₁ ,...,

) can be created. As described in Equation 1 above, the generation process includes a process of determining a codeword such that the product of the LDPC codeword and the parity check matrix becomes a zero vector. The parity check matrix of the present invention may have the same structure as the parity check matrix defined in FIG. 3 above.

In this case, the LDPC encoder 1810 may perform LDPC encoding using parity check matrices defined differently according to code rates (ie, code rates of LDPC codes).

Meanwhile, since the specific method of performing LDPC encoding has been described above, a detailed redundant description will be omitted.

Meanwhile, the encoding device 1800 may further include a memory (not shown) for pre-storing information about the code rate, codeword length, and parity check matrix of the LDPC code, and the LDPC encoder 810 stores such information LDPC encoding can be performed using Information on the parity check matrix may store information on an exponent value of a circulant matrix when the parity matrix proposed in the present invention is used.

Below, a receiver operation will be described in detail based on FIG. 5 .

The demodulator 510 demodulates the signal received from the transmitter 400 .

Specifically, the demodulation unit 510 is a component corresponding to the modulation unit 450 of the transmission device 400 of FIG. 4, demodulates the signal received from the transmission device 400, and transmits it in the transmission device 400. Values corresponding to one bit can be generated.

To this end, the receiving device 500 may pre-store information about a modulation scheme modulated by the transmitting device 400 according to a mode. Accordingly, the demodulator 510 may demodulate the signal received from the transmitter 400 according to the mode to generate values corresponding to the LDPC codeword bits.

Meanwhile, a value corresponding to the bits transmitted by the transmitter 400 may be a Log Likelihood Ratio (LLR) value. Specifically, the LLR value may be expressed as a value obtained by taking Log of a ratio of a probability that a bit transmitted from the transmitter 400 is 0 and a probability that it is 1. Alternatively, the LLR value may be a bit value itself, and also, the LLR value may be a representative value determined according to a section to which the probability that the bit transmitted by the transmitter 400 is 0 or 1 belongs.

The demodulation unit 510 includes a process of performing multiplexing (not shown) on the LLR value. Specifically, a component corresponding to a bit demux (not shown) of the transmitter 400 may perform an operation corresponding to the bit demux (not shown).

To this end, the receiving device 500 may previously store information on parameters used by the transmitting device 400 for demultiplexing and block interleaving. Accordingly, the mux (not shown) reverses the demultiplexing and block interleaving operations performed in the bit demux (not shown) on the LLR value corresponding to the cell word, and converts the LLR value corresponding to the cell word in bit units. can be multiplexed with

The rate dematching unit 520 may insert the LLR value into the LLR value output from the demodulation unit 510 . In this case, the rate dematching unit 520 may insert prearranged LLR values between the LLR values output from the demodulation unit 510 .

Specifically, the rate dematching unit 520 is a component corresponding to the rate matching unit 440 of the transmitting device 400, and includes the interleaver 441, the zero removal and puncturing/repetition/zero removal unit 442 ) can perform the corresponding operation.

First, the rate dematching unit 520 performs deinterleaving 521 to correspond to the interleaver 441 of the transmitter. In the output values of the deinterleaving 521, the LLR inserter 522 may insert an LLR value corresponding to the zero bits in the position where the zero bits are padded in the LDPC codeword. In this case, an LLR value corresponding to the padded zero bits, ie, the shortened zero bits, may be ∞ or -∞. However, ∞ or -∞ is a theoretical value, and may actually be the maximum or minimum value of the LLR value used in the receiving device 500.

To this end, the receiving device 500 may previously store information on parameters used by the transmitting device 400 to pad zero bits. Accordingly, the rate dematching unit 520 may determine a position where zero bits are padded in the LDPC codeword, and insert an LLR value corresponding to the shortened zero bits at the corresponding position.

In addition, the LLR insertion unit 522 of the rate dematching unit 520 may insert LLR values corresponding to the punctured bits in positions of the punctured bits in the LDPC codeword. In this case, LLR values corresponding to the punctured bits may be 0.

To this end, the receiving device 500 may previously store information on parameters used for puncturing by the transmitting device 400 . Accordingly, the LLR inserter 522 may insert an LLR value corresponding to the punctured position of the LDPC parity bits.

The LLR combiner 523 may combine the LLR values output from the LLR inserter 522 and the demodulator 510, that is, add up. Specifically, the LLR combiner 523 is a component corresponding to the puncturing/repetition/zero removal unit 442 of the transmitter 400, and performs an operation corresponding to the repetition unit 442. can First, the LLR combiner 523 may combine LLR values corresponding to repeated bits with other LLR values. Here, another LLR value may be an LLR value for bits based on the generation of repeated bits in the transmitter 400, that is, LDPC parity bits selected as repetition targets.

That is, as described above, the transmitter 400 selects bits from the LDPC parity bits, repeats them between the LDPC information word bits and the LDPC parity bits, and transmits them to the receiver 500.

Accordingly, the LLR value for the LDPC parity bits is an LLR value for repeated LDPC parity bits and an LLR value for non-repeated LDPC parity bits, that is, LDPC parity bits generated by encoding. can be configured. Accordingly, the LLR combiner 523 may combine the LLR values to the same LDPC parity bits.

To this end, the receiving device 500 may previously store information on parameters used by the transmitting device 400 for repetition. Accordingly, the LLR combiner 523 may determine an LLR value for the repeated LDPC parity bits and combine it with an LLR value for the LDPC parity bits that are the basis of the repetition.

In addition, the LLR combiner 523 may combine LLR values corresponding to retransmitted or IR (Incremental Redundancy) bits with other LLR values. Here, another LLR value may be an LLR value for bits selected for generating LDPC codeword bits based on generating bits retransmitted or IRed by the transmitter 400.

That is, as described above, the transmitter 400 may transmit some or all of the codeword bits to the receiver 500 when a NACK occurs for HARQ.

Accordingly, the LLR combiner 523 may combine LLR values for bits received through retransmission or IR with LLR values for LDPC codeword bits received through a previous frame.

To this end, the receiving device 500 may pre-store information on parameters used for retransmission or generation of IR bits in the transmitting device 400 . Accordingly, the LLR combiner 523 may determine an LLR value for the number of retransmission or IR bits, and combine it with an LLR value for LDPC parity bits based on generation of retransmission bits.

The deinterleaver 524 may deinterleave the LLR values output from the LLR combiner 523.

Specifically, the deinterleaver unit 524 is a component corresponding to the interleaver 441 of the transmitter 400 and may perform an operation corresponding to the interleaver 441 .

To this end, the receiving device 500 may pre-store information on parameters used by the transmitting device 100 for interleaving. Accordingly, the deinterleaver 524 reversely performs the interleaving operation performed by the interleaver 441 on the LLR values corresponding to the LDPC codeword bits to deinterleave the LLR values corresponding to the LDPC codeword bits. can

The LDPC decoder 530 may perform LDPC decoding based on the LLR value output from the rate dematching unit 520.

Specifically, the LDPC decoder 530 is a component corresponding to the LDPC encoder 430 of the transmitter 100 and may perform an operation corresponding to the LDPC encoder 430 .

To this end, the receiving device 500 may previously store information on parameters used by the transmitting device 400 to perform LDPC encoding according to the mode. Accordingly, the LDPC decoder 530 may perform LDPC decoding based on the LLR value output from the rate dematching unit 520 according to the mode.

For example, the LDPC decoder 530 performs LDPC decoding based on the LLR value output from the rate dematching unit 520 based on an iterative decoding scheme based on a sum-product algorithm, and performs LDPC decoding on the LDPC decoding. Accordingly, the error-corrected bits may be output.

The zero remover 540 may remove zero bits from bits output from the LDPC decoders 2460 and 2560 .

Specifically, the zero remover 540 is a component corresponding to the zero padder 420 of the transmitter 400 and may perform an operation corresponding to the zero padder 420 .

To this end, the receiving device 500 may pre-store information about parameters used by the transmitting device 400 to pad zero bits. Accordingly, the zero remover 540 may remove the zero bits padded by the zero padder 420 from the bits output from the LDPC decoder 530 .

The desegmentation unit 550 is a component corresponding to the segmentation unit 410 of the transmission device 400 and may perform an operation corresponding to the segmentation unit 410 .

To this end, the receiving device 500 may pre-store information on parameters used by the transmitting device 400 for segmentation. Accordingly, the desegmentation unit 550 may combine the bits output from the zero removal unit 540, that is, the segments for the variable length input bits, and restore the bits before segmentation.

19 is a block diagram showing the configuration of a decoding device according to an embodiment of the present invention. According to FIG. 19 , a decoding apparatus 1900 may include an LDPC decoder 1910. Meanwhile, the decoding apparatus 1900 may further include a memory (not shown) for pre-storing information about the code rate, codeword length, and parity check matrix of the LDPC code, and the LDPC decoder 1910 stores such information LDPC encoding can be performed using However, this is only an example, and the corresponding information may be provided from the transmitting device side.

The LDPC decoder 1910 performs LDPC decoding on the LDPC codeword based on the parity check matrix.

For example, the LDPC decoder 1910 may generate information word bits by performing LDPC decoding by passing log likelihood ratio (LLR) values corresponding to LDPC codeword bits through an iterative decoding algorithm.

Here, the LLR value is a channel value corresponding to LDPC codeword bits and can be expressed in various ways.

For example, the LLR value may be expressed as a value obtained by taking Log of a ratio of a probability that a bit transmitted through a channel by a transmitter is 0 and a probability that it is 1. In addition, the LLR value may be a bit value itself determined according to the hard decision, or may be a representative value determined according to a section to which the probability that the transmitted bit is 0 or 1 belongs.

In this case, the transmitter may generate an LDPC codeword using the LDPC encoder 1810 as shown in FIG. 18 .

Meanwhile, a parity check matrix used in LDPC decoding may have the same behavior as the parity check matrix shown in FIG. 3 .

In this case, the LDPC decoder 1910 may perform LDPC decoding using parity check matrices defined differently according to code rates (ie, code rates of LDPC codes).

Meanwhile, as described above, the LDPC decoder 1910 may perform LDPC decoding using an iterative decoding algorithm. In this case, the LDPC decoder 1910 may have a structure as shown in FIG. 20 . However, since the iterative decoding algorithm is already known, the detailed configuration shown in FIG. 20 is only an example.

20 shows a structural diagram of an LDPC decoder according to another embodiment of the present invention. According to FIG. 20 , the decoding apparatus 2000 includes an input processor 2011, a memory 2012, a variable node calculator 2013, a controller 2014, a check node repeater 2015, and an output processor 2016.

The input processor 2011 stores input values. Specifically, the input processor 2011 may store an LLR value of a received signal received through a radio channel.

The controller 2014 calculates the number of values input to the variable node calculator 2013 based on the parity check matrix corresponding to the block size (i.e., codeword length) and code rate of the received signal received through the wireless channel. And the address value in the memory 2012, the number of values input to the check node operator 2015, and the address value in the memory 2012 are determined.

The memory 2012 stores input data and output data of the variable node operator 2013 and the check node operator 2015.

The variable node calculator 2013 receives data from the memory 2012 according to address information of the input data received from the controller 2014 and information on the number of input data, and performs variable node calculation. Thereafter, the variable node calculator 2013 stores variable node operation results in the memory 2012 based on the address information of the output data received from the controller 2014 and the number information of the output data. In addition, the variable node operator 2013 inputs a variable node operation result to the output processor 2016 based on data input from the input processor 2011 and the memory 2012. Here, the variable node operation has been described above based on FIG. 18 .

The check node operator 2015 receives data from the memory 2012 based on the address information of the input data received from the controller 2014 and the number information of the input data, and performs a check node operation. Then, the check node calculator 2015 stores variable node operation results in the memory 2012 based on the address information of the output data and the number information of the output data received from the controller 2014. Here, the check node operation is It has been described above based on FIGS. 7A and 7B.

The output processor 2016 makes a hard decision on whether the information word bits of the codeword of the transmission side are 0 or 1 based on the data received from the variable node calculator 2013, and then outputs the hard decision result, and the output processor ( 2016) becomes the final decoded value. 7a and 7b, a hard decision can be made based on the sum of all message values (initial message value and all message values input from the check node) input to one variable node.

21 and 22 are diagrams illustrating a transmitter and receiver capable of operating in accordance with an embodiment of the present invention. The transmitter and receiver may each be either a base station or a terminal. According to FIG. 21, the transmitter 2100 may be composed of a transceiver 2110 and a control unit 2120, the transceiver transmits and receives information, signals, messages, etc. with the receiver, and the control unit causes the transceiver to perform the transmission and reception operation. control, and may also be controlled to perform an embodiment of the present invention. The transmitter 400 described in the present invention may or may not be included in the control unit. Also, the encoding device 1800 may or may not be included in the control unit.

22, the receiver 2200 may be composed of a transceiver 2210 and a control unit 2220, the transceiver transmits and receives information, signals, messages, etc. with the transmitter, and the control unit causes the transceiver to perform the transmission and reception operation control, and may also be controlled to perform an embodiment of the present invention. The receiving device 500 described in the present invention may or may not be included in the control unit. Also, the decoding device 1900 may or may not be included in the control unit.

Claims (18)

In the method of a transmitter of a communication system,
Generating a codeword by performing low density parity check (LDPC) coding on an information bit stream to be transmitted based on a parity check matrix selected from among a plurality of parity check matrices;
Checking an index of a redundancy version (RV) to be applied to the codeword among a plurality of RV indexes;
Generating a bit stream by performing rate matching on the codeword based on the identified RV index,
The bit string is generated by rearranging the codeword to start at one of a plurality of starting points,
Wherein the one starting point is determined based on the checked RV index and a parity check matrix group corresponding to the selected parity check matrix. According to claim 1,
Wherein each of the plurality of starting points corresponds to a specific bit of the codeword. According to claim 1,
Characterized in that the index of the one starting point is a multiple of Z, which is the size of a matrix constituting the selected parity check matrix. According to claim 1,
Each of the plurality of starting points corresponds to one of the plurality of RV indices, and an interval between adjacent starting points is not uniform. According to claim 1,
Characterized in that the order of the plurality of RV indices is determined based on at least one of the parity check matrix group corresponding to the selected parity check matrix or a code rate of an initial transmission of the information bit stream to be transmitted. In the method of a receiver of a communication system,
Checking a plurality of values corresponding to a bit string transmitted by a transmitter based on the received signal;
Checking an RV index to be applied among a plurality of redundancy versions (RVs);
performing de-rate matching on the plurality of values based on the identified RV index; and
Confirming an information bit sequence by performing low parity check matrix (LDPC) decoding on a plurality of de-rate matched values based on a parity check matrix selected from among a plurality of parity check matrices;
The plurality of values start from one of the plurality of starting points, and the one starting point is based on the checked RV index and a parity check matrix group corresponding to the selected parity check matrix. According to claim 6,
Characterized in that the index of the one starting point is a multiple of Z, which is the size of a matrix constituting the selected parity check matrix. According to claim 6,
Each of the plurality of starting points corresponds to one of the plurality of RV indices, and an interval between adjacent starting points is not uniform. According to claim 6,
Characterized in that the order of the plurality of RV indices is determined based on at least one of the parity check matrix group corresponding to the selected parity check matrix or the code rate of the first transmission of the bit stream transmitted by the transmitter. In the transmitter of the communication system,
transceiver; and
Generating a codeword by performing low density parity check (LDPC) coding on an information bit stream to be transmitted based on a parity check matrix selected from among a plurality of parity check matrices;
Checking an index of a redundancy version (RV) to be applied to the codeword among a plurality of RV indices,
A control unit controlling to generate a bit stream by performing rate matching on the codeword based on the identified RV index,
The bit string is generated by rearranging the codeword to start at one of a plurality of starting points,
The one starting point is determined based on the checked RV index and a parity check matrix group corresponding to the selected parity check matrix. According to claim 10,
Wherein each of the plurality of starting points corresponds to a specific bit of the codeword. According to claim 10,
Characterized in that the index of the one starting point is a multiple of Z, which is the size of a matrix constituting the selected parity check matrix. According to claim 10,
Each of the plurality of starting points corresponds to one of the plurality of RV indices, and an interval between adjacent starting points is not uniform. According to claim 10,
The order of the plurality of RV indices is determined based on at least one of the parity check matrix group corresponding to the selected parity check matrix or a code rate of an initial transmission of the information bit stream to be transmitted. In the receiver of the communication system,
transceiver; and
ascertaining a plurality of values corresponding to the bits transmitted by the transmitter based on the received signal;
Check the RV index to be applied among multiple redundancy versions (RVs),
Performing de-rate matching on the plurality of values based on the identified RV index;
A controller for controlling to check an information bit stream by performing LDPC (low parity check matrix) decoding on a plurality of de-rate matched values based on a parity check matrix selected from among a plurality of parity check matrices;
The plurality of values start from one of a plurality of starting points, and the one starting point is based on the checked RV index and a parity check matrix group corresponding to the selected parity check matrix. Receiver. According to claim 15,
The receiver, characterized in that the index of the one starting point is a multiple of Z, which is the size of a matrix constituting the selected parity check matrix. According to claim 15,
Each of the plurality of starting points corresponds to one of the plurality of RV indices, and an interval between adjacent starting points is not uniform. The method of claim 15, wherein the order of the plurality of RV indices is determined based on at least one of the parity check matrix group corresponding to the selected parity check matrix or a code rate of an initial transmission of the bit stream transmitted by the transmitter Receiver characterized in that.

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