KR20210030848A - Apparatus and method for decoding of data in communication or broadcasting system - Google Patents

Abstract

The present disclosure relates to a communication technique, which converges a 5G communication system for supporting a higher data rate after a 4G system with IoT technology, and to a system thereof. According to the present invention, the decoding method of a receiver comprises the steps of: receiving a signal corresponding to an input bit transmitted from a transmitter; checking the number of input bits based on the signal; checking the size of the code block based on the number of input bits; and performing layered decoding based on a parity check matrix corresponding to the size of the code block.

Description

Data decoding method and apparatus in communication or broadcasting system {APPARATUS AND METHOD FOR DECODING OF DATA IN COMMUNICATION OR BROADCASTING SYSTEM}

The present invention relates to a data decoding method and apparatus using an LDPC decoder in a communication or broadcasting system based on an LDPC code.

Efforts are being made to develop an improved 5G communication system or a pre-5G communication system in order to meet the increasing demand for wireless data traffic after the commercialization of 4G communication systems. For this reason, the 5G communication system or the pre-5G communication system is called a communication system after a 4G network (Beyond 4G Network) or a system after an LTE system (Post LTE). In order to achieve a high data rate, the 5G communication system is being considered for implementation in the ultra-high frequency (mmWave) band (eg, such as the 60 Giga (60 GHz) band). In order to mitigate the path loss of radio waves in the ultra-high frequency band and increase the transmission distance of radio waves, 5G communication systems include beamforming, massive MIMO, and Full Dimensional MIMO (FD-MIMO). ), array antenna, analog beam-forming, and large scale antenna technologies are being discussed. In addition, in order to improve the network of the system, in 5G communication system, evolved small cell, advanced small cell, cloud radio access network (cloud RAN), ultra-dense network , Device to Device communication (D2D), wireless backhaul, moving network, cooperative communication, CoMP (Coordinated Multi-Points), and interference cancellation And other technologies are being developed. In addition, in 5G systems, advanced coding modulation (ACM) methods such as Hybrid FSK and QAM Modulation (FQAM) and SWSC (Sliding Window Superposition Coding), advanced access technologies such as Filter Bank Multi Carrier (FBMC), NOMA (non orthogonal multiple access), and sparse code multiple access (SCMA) are being developed.

Meanwhile, the Internet is evolving from a human-centered connection network in which humans create and consume information, to an Internet of Things (IoT) network that exchanges and processes information between distributed components such as objects. IoE (Internet of Everything) technology, which combines IoT technology with big data processing technology through connection with cloud servers, etc., is also emerging. In order to implement IoT, technological elements such as sensing technology, wired/wireless communication and network infrastructure, service interface technology, and security technology are required. , M2M), and MTC (Machine Type Communication) technologies are being studied. In the IoT environment, intelligent IT (Internet Technology) services that create new value in human life by collecting and analyzing data generated from connected objects can be provided. IoT is the field of smart home, smart building, smart city, smart car or connected car, smart grid, healthcare, smart home appliance, advanced medical service, etc. through the convergence and combination of existing IT (information technology) technology and various industries. Can be applied to.

Accordingly, various attempts have been made to apply a 5G communication system to an IoT network. For example, technologies such as sensor network, machine to machine (M2M), and machine type communication (MTC) are implemented by techniques such as beamforming, MIMO, and array antenna. There is. The application of a cloud radio access network (cloud RAN) as the big data processing technology described above can be said as an example of the convergence of 5G technology and IoT technology.

In a communication or broadcasting system, link performance may be significantly degraded due to various noise, fading phenomena, and inter-symbol interference (ISI) of a channel. Therefore, in order to implement high-speed digital communication or broadcasting systems that require high data throughput and reliability, such as next-generation mobile communication, digital broadcasting, and portable Internet, it is required to develop a technology for overcoming noise, fading, and inter-symbol interference. As a part of research to overcome noise, etc., in recent years, research on error-correcting codes has been actively conducted as a method to increase the reliability of communication by efficiently restoring distortion of information.

The present invention provides an apparatus and method for efficiently decoding a low-density parity-check (LDPC) code in a communication or broadcasting system.

In addition, the present invention applies suitable decoding scheduling according to the structural or algebraic characteristics of the LDPC code when decoding the LDPC code using layered scheduling or a method similar thereto, without increasing the decoding complexity. It provides an LDPC decoding apparatus and method for improving decoding performance.

In order to solve the above problems, in a method of performing LDPC decoding by a receiver in a communication system of the present invention, the method comprising: receiving a signal corresponding to a transport block and a code block; And performing LDPC (low-density parity-check) decoding using the signal and a parity check matrix to decode the code block, and the performing of the LDPC decoding may be performed according to a predetermined decoding scheduling rule. It is characterized in that decoding is performed using at least a partial region of the parity check matrix.

Transmitting and receiving unit in the communication system of the present invention for solving the above problems; And receiving a signal corresponding to a transport block and a code block, and performing LDPC (low density parity check) decoding using the signal and a parity check matrix to decode the code block, and performing the LDPC decoding And a controller for controlling to perform decoding using at least a partial region of the parity check matrix according to a predetermined decoding scheduling rule.

In a receiver for receiving and processing a signal corresponding to a transmission block and a code block in a communication system of the present invention to solve the above problems, LDPC information word bits, first parity bits, and first 2 determining values corresponding to parity bits and performing decoding using at least a part of the parity check matrix of the LDPC code, wherein the parity check matrix of the LDPC code corresponds to the LDPC information bits. A first part including a first partial matrix and a second sub-matrix corresponding to the first parity bits and composed of columns of degree 2 and columns of degree 3, and a third corresponding to the LDPC information bits And a second part including a partial matrix, a fourth partial matrix corresponding to the first parity bits, and a fifth partial matrix, which is an identity matrix, corresponding to the second parity bits.

In addition, the decoding method of the receiver of the present invention for solving the above problem includes receiving a signal corresponding to an input bit transmitted from a transmitter, checking the number of input bits based on the signal, and Checking the size of the code block based on the number, and performing layered decoding based on a parity check matrix corresponding to the size of the code block, wherein the layered decoding is a partial matrix corresponding to a column block to be punctured A layer corresponding to at least one of the row blocks of order 1 is decoded with priority.

In addition, the receiver of the present invention for solving the above problem includes a transceiver; And receiving a signal corresponding to the input bit transmitted from the transmitter, checking the number of input bits based on the signal, checking the size of the code block based on the number of input bits, and determining the size of the code block. And a control unit that performs layered decoding based on a corresponding parity check matrix, wherein the layered decoding takes precedence with respect to a layer corresponding to at least one of the row blocks of degree 1 in the partial matrix corresponding to the column block to be punctured. Characterized in that it is decoded.

In addition, the decoding method of the receiver of the present invention for solving the above problem includes the steps of receiving a signal corresponding to an input bit transmitted from the receiver, checking the number of input bits based on the signal, and Checking the size of the code block based on the number; And performing layered decoding based on a parity check matrix corresponding to the size of the code block, wherein the layered decoding is performed based on the following decoding pattern.

Pattern-1:

[42, 40, 26, 34, 37, 45, 30, 32, 22, 28, 38, 44, 41, 20, 27, 25, 31, 36, 39, 13, 33, 35, 24, 29, 43 , 17, 23, 18, 21, 14, 6, 10, 16, 1, 4, 19, 7, 12, 15, 9, 5, 11, 8, 0, 2, 3]

Pattern-2:

[22, 37, 40, 31, 24, 29, 20, 12, 27, 25, 28, 35, 38, 41, 32, 23, 34, 39, 17, 16, 36, 21, 33, 18, 15 , 9, 14, 30, 11, 19, 6, 7, 8, 26, 10, 13, 1, 4, 5, 0, 2, 3].

In addition, in the receiver of the present invention for solving the above problem, the transmission and reception unit; And receiving a signal corresponding to the input bit transmitted from the transmitter, checking the number of input bits based on the signal, checking the size of the code block based on the number of input bits, and determining the size of the code block. It characterized in that it comprises a control unit for performing layered decoding based on a corresponding parity check matrix.

Pattern-1:

[42, 40, 26, 34, 37, 45, 30, 32, 22, 28, 38, 44, 41, 20, 27, 25, 31, 36, 39, 13, 33, 35, 24, 29, 43 , 17, 23, 18, 21, 14, 6, 10, 16, 1, 4, 19, 7, 12, 15, 9, 5, 11, 8, 0, 2, 3]

Pattern-2:

[22, 37, 40, 31, 24, 29, 20, 12, 27, 25, 28, 35, 38, 41, 32, 23, 34, 39, 17, 16, 36, 21, 33, 18, 15 , 9, 14, 30, 11, 19, 6, 7, 8, 26, 10, 13, 1, 4, 5, 0, 2, 3].

According to various embodiments of the present invention, efficient decoding performance may be supported according to LDPC decoding scheduling. In particular, when the LDPC decoding method based on layered scheduling is applied, LDPC decoding performance, that is, improved error-correcting performance or fast decoding convergence performance, can be improved without increasing complexity. .

1 is a structural diagram of a systematic LDPC codeword.
2 is a diagram illustrating a method of representing a graph of an LDPC code.
3A and 3B are exemplary diagrams for explaining cycle characteristics of a QC-LDPC code.
4 is a block diagram of a transmission device according to an embodiment of the present invention.
5 is a block diagram of a receiving device according to an embodiment of the present invention.
6A and 6B are message structure diagrams showing a message passing operation in an arbitrary check node and a variable node for LDPC decoding.
7 is a block diagram illustrating a detailed configuration of an LDPC encoding unit according to an embodiment of the present invention.
8 is a block diagram illustrating a configuration of a decoding apparatus according to an embodiment of the present invention.
9 is a structural diagram of an LDPC decoder according to another embodiment of the present invention.
10 is an exemplary diagram of a decoding process in an LDPC decoding apparatus according to an embodiment of the present invention.
11 is an exemplary diagram of a decoding process based on LDPC and CRC codes according to an embodiment of the present invention.
12 is an exemplary diagram of an LDPC encoding process according to an embodiment of the present invention.
13 is an exemplary diagram of an LDPC decoding process according to an embodiment of the present invention.
14 is an exemplary diagram of a structure diagram of a parity check matrix of an LDPC code.
15 is an exemplary diagram of a parity check matrix for an LDPC code proposed in the present invention.
16 is another exemplary diagram of a parity check matrix for an LDPC code proposed in the present invention.
17A and 17B are exemplary diagrams illustrating a case in which one or two punctured bits are connected to one inspection node, respectively.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, terms to be described later are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of users or operators. Therefore, the definition should be made based on the contents throughout the present specification.

The main subject matter of the present invention can be applied to other systems having a similar technical background with slight modifications without significantly departing from the scope of the present invention, which is determined by a person skilled in the technical field of the present invention. It will be possible. For reference, a communication system is generally a term including the meaning of a broadcasting system, but in the present invention, when a broadcasting service is a major service among communication systems, it may be more clearly named as a broadcasting system.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only these embodiments make the disclosure of the present invention complete, and the general knowledge in the technical field to which the present invention pertains. It is provided to completely inform the scope of the invention to the possessor, and the invention is only defined by the scope of the claims. The same reference numerals refer to the same elements throughout the specification.

In various embodiments of the present disclosure described below, a hardware approach is described as an example. However, since various embodiments of the present disclosure include technology using both hardware and software, various embodiments of the present disclosure do not exclude a software-based approach.

The Low Density Parity Check (LDPC) code, first introduced by Gallager in the 1960s, has long been forgotten due to the complexity that is difficult to implement at the technology level at the time. However, as the turbo code proposed by Berrou, Glavieux, and Thitimajshima in 1993 showed a performance close to the channel capacity of Shannon, many interpretations of the performance and characteristics of the turbo code were made, and iterative decoding ( Iterative decoding) and graph-based channel coding have been studied. As a result of this, when LDPC codes were re-researched in the late 1990s, the LDPC code was decoded by applying iterative decoding based on the sum-product algorithm on the Tanner graph corresponding to the LDPC code. It has also been found to have a performance close to the channel capacity of Chenon.

The LDPC code is generally defined as a parity-check matrix and can be expressed using a bipartite graph commonly referred to as a Tanner graph. In general, LDPC codes are a kind of parity check code, and are called'low-density' parity check codes because the ratio of the number of 1s (i.e., density) in the parity check matrix for the case of very long length is very low. Became. Therefore, for convenience in the present invention, techniques proposed based on LDPC codes can be easily extended to general parity check matrix codes.

1 is a diagram showing the structure of a systematic LDPC codeword.

(102)를 LDPC 부호화하면, 부호어

(100)가 생성된다. 즉, 정보어 및 부호어는 다수의 비트로 구성되어 있는 비트열이며, 정보어 비트 및 부호어 비트는 정보어 및 부호어를 구성하는 각각의 비트를 의미한다. 통상적으로 LDPC 부호화 비트가

와 같이 정보어를 포함하고 있을 경우 시스테메틱(systemetic) 부호라 한다. 여기에서,

는 패리티 비트(104)이고, 패리티 비트의 개수 N_parity는 N_parity=N_ldpc - K_ldpc 로 나타낼 수 있다.1, the LDPC code receives _{an information word 102 composed of K ldpc} bits or symbols and performs encoding to generate a codeword 100 composed of _{N ldpc bits or symbols.} do. For convenience of description below, it is assumed that an information word 102 including _{K ldpc} bits is received and a codeword 100 composed of _{N ldpc bits is generated.} That is, an information word _{that is K ldpc input bits}

If (102) is LDPC coded, the codeword

(100) is generated. That is, the information word and the codeword are a bit string composed of a plurality of bits, and the information word bit and the codeword bit mean respective bits constituting the information word and the codeword. Typically, the LDPC coded bit is

If the information word is included, it is called a systemetic code. From here,

Is a parity bit 104, the number N _parity of the parity bits is N = N _{parity ldpc} - can be represented by K _ldpc.

The LDPC code is a type of linear block code and includes a process of determining a codeword that satisfies the condition as shown in Equation 1 below.

[Equation 1]

이다.From here,

to be.

In Equation 1, H denotes a parity check matrix, c denotes a codeword, c _i denotes the i-th bit of the codeword, and N _ldpc denotes the LDPC codeword length. Here, h _i means the i-th column of the parity check matrix H.

The parity check matrix H is composed of _{N ldpc} columns equal to the number of bits of the LDPC codeword. Equation 1 means that the sum of the products of the i-th column (h _i ) and the i-th codeword bit c _i of the parity check matrix becomes '0', so the i-th column (h _i ) is the i-th codeword bit c _It means that it has a relationship with i.

2 is a diagram illustrating a method of representing a graph of an LDPC code.

A method of representing a graph of an LDPC code will be described with reference to FIG. 2.

FIG. 2 is a diagram illustrating an example _{of a parity check matrix H 1} of an LDPC code consisting of 4 rows and 8 columns, and a Tanner graph. Referring to FIG. 2, _{since there are 8 columns of a parity check matrix H 1} , a codeword having a length of 8 is generated, and a code generated through H1 means an LDPC code, and each column is a coded 8-bit code. Corresponds to.

Referring to FIG. 2, a Tanner graph of an LDPC code encoded and decoded based on a _{parity check matrix H 1 shows eight variable nodes, that is, x 1} (202), x ₂ (204), and x ₃ ( 206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214), x ₈ (216) and 4 check nodes (218, 220, 222, 224) It consists of Here, the i-th column and j-th row of the parity check matrix H _{1 of the LDPC code correspond to the variable nodes x i} and j-th check nodes, respectively. In addition, the value of 1 at the intersection of the i-th column and the j-th row of the parity check matrix H _{1 of the LDPC code, that is, the meaning of a non-zero value, is the variable node x i} and the j-th check on the Tanner graph as shown in FIG. It means that there is an edge connecting the nodes.

In the Tanner graph of the LDPC code, the degree of the variable node and the check node means the number of line segments connected to each node, and this is 0 in the column or row corresponding to the node in the parity check matrix of the LDPC code. It is equal to the number of non-entries. For example, in FIG. 2, variable nodes x ₁ (202), x ₂ (204), x ₃ (206), x ₄ (208), x ₅ (210), x ₆ (212), x ₇ (214 ), x ₈ (216) has the order of 4, 3, 3, 3, 2, 2, 2, 2, respectively, and the order of the test nodes 218, 220, 222, 224 is 6 in order, respectively. , 5, 5, 5. _{In addition, the number of non-zero elements in each column of the parity check matrix H 1} of FIG. 2 corresponding to the variable node of FIG. 2 is determined by the above-described orders 4, 3, 3, 3, 2, 2, 2, 2, and _{The number of non-zero elements in each row of the parity check matrix H 1} of FIG. 2 corresponding to the check nodes of FIG. 2 matches in order with the above-described orders 6, 5, 5, and 5 . For this reason, the degree of each variable node is also referred to as a column degree or column weight, and the order of a check node is also referred to as a row degree or row weight.

In summary, in the parity check matrix of the LDPC code, the order means the number of non-zero elements in a column or row. In addition, in the parity check matrix, the number of non-zero elements in one column may be expressed as the order of the column or the weight of the column, and the number of non-zero elements in one row may be expressed as the order of the row or the weight of the row. In addition, the elements of the parity check matrix or the line segments on the Tanner graph can be expressed as hardware-connected inside the variable node processor (VNU) or check node processor (CNU) in the LDPC decoder. It may be expressed differently in various ways such as a line, a connection line, an edge, an interconnection network, and a shift network. These interconnection networks are used to input/output appropriate values for LDPC decoding between node processors of the LDPC decoder.

The LDPC code may be decoded using an iterative decoding algorithm based on a sum-product algorithm on the bipartite graph listed in FIG. 2. Here, the summation algorithm is a kind of message passing algorithm, and the message passing algorithm exchanges messages through edges on a bipartite graph, and calculates and updates an output message from messages input to a variable node or a check node. Represents the algorithm.

Here, the value of the i-th coded bit may be determined based on the message of the i-th variable node. The value of the i-th coded bit can be both a hard decision and a soft decision. Therefore, the i-th bit of c _i the performance of the LDPC codeword corresponds to a performance of the i-th variable node in a Tanner graph, which can be determined according to the position and number of the i-th column of the first parity check matrix. In other words, _{the performance of the N ldpc} codeword bits of the codeword can be influenced by the position and number of 1 in the parity check matrix, which means that the performance of the LDPC code is greatly affected by the parity check matrix. do. Therefore, in order to design an LDPC code with excellent performance, a method of designing a good parity check matrix is required.

The parity check matrix used in communication and broadcasting systems is a quasi-cyclic LDPC code (or QC-LDPC code, hereinafter QC-LDPC code) using a parity check matrix in a generally quasi-cyclic form for ease of implementation. Is used.

The QC-LDPC code is characterized by having a zero matrix in the form of a small square matrix or a parity check matrix composed of circulant permutation matrices. In this case, the permutation matrix refers to a matrix in which each row or column contains only one 1 and all other elements are 0. In addition, the cyclic permutation matrix refers to a matrix in which each element of the identity matrix is cyclically shifted to the right or left.

Hereinafter, the QC-LDPC code will be described in detail.

크기의 순환 순열 행렬

을 정의한다. 여기서

는 행렬 상기 행렬 P에서의 i번째 행(row), j번째 열(column)의 원소(entry)를 의미한다.(0

i, j < L) First, as in Equation 2

Cyclic permutation matrix of size

Is defined. here

Denotes the entry of the i-th row and the j-th column of the matrix P. (0

i, j <L)

[Equation 2]

(0 ≤ i < L)는

크기의 항등 행렬(identity matrix)의 각 원소들을 i 번 만큼 오른쪽 방향으로 순환 이동(circular shift) 시킨 형태의 순환 순열 행렬임을 알 수 있다. For the permutation matrix P defined as above

(0 ≤ i <L) is

It can be seen that it is a cyclic permutation matrix in a form in which each element of an identity matrix of size is cyclically shifted to the right by i times.

The parity check matrix H of the QC-LDPC code can be expressed in the form of Equation 3 below.

[Equation 3]

을

크기의 0-행렬이라 정의할 경우, 상기 수학식 3에서 순환 순열 행렬 또는 0-행렬의 각 지수

는 {-1, 0, 1, 2, ..., L-1} 값 중에 하나를 가지게 된다. 또한 상기 수학식 3의 패리티 검사 행렬 H는 열 블록(column block)이 n개, 행 블록이 m개이므로,

크기를 가지게 됨을 알 수 있다. if

of

When defined as a 0-matrix of size, each exponent of a cyclic permutation matrix or 0-matrix in Equation 3 above

Has one of the values {-1, 0, 1, 2, ..., L-1}. In addition, since the parity check matrix H of Equation 3 has n column blocks and m row blocks,

You can see that it has a size.

If the parity check matrix of Equation 3 has a full rank, it is obvious that the size of the information word bit of the QC-LDPC code corresponding to the parity check matrix is (n-m)L. For convenience, (n-m) column blocks corresponding to an information word bit are called an information word column block, and m column blocks corresponding to the remaining parity bits are called a parity column block. When the parity check matrix of Equation 3 does not have a perfect coefficient, the information word bit becomes larger than (n-m)L.

크기의 이진(binary) 행렬을 패리티 검사 행렬 H의 모행렬(mother matrix) 또는 기본 행렬 (base matrix) M(H)라 하고, 각 순환 순열 행렬 또는 0-행렬의 지수를 선택하여 수학식 4와 같이 얻은

크기의 정수 행렬을 패리티 검사 행렬 H의 지수 행렬 (exponent matrix) E(H)라 한다. Typically, obtained by replacing each cyclic permutation matrix and 0-matrix with 1 and 0 in the parity check matrix of Equation 3, respectively.

A binary matrix of size is referred to as the mother matrix of the parity check matrix H or the base matrix M(H), and each cyclic permutation matrix or the exponent of the 0-matrix is selected, as shown in Equation 4 Obtained together

An integer matrix of size is referred to as an exponent matrix E(H) of the parity check matrix H.

[Equation 4]

As a result, since one integer included in the exponential matrix corresponds to a cyclic permutation matrix or a zero-matrix in the parity check matrix, the exponent matrix may be expressed as a sequence of integers for convenience. In general, the parity check matrix can be expressed not only by an exponential matrix, but also by various sequences that can express the same characteristics algebraically. In the present invention, for convenience, the parity check matrix is expressed as an exponential matrix or a sequence indicating the position of 1 in the parity check matrix, but a sequence notation method capable of distinguishing the position of 1 or 0 included in the parity check matrix is Since it is diverse, it is not limited to the method expressed in the present specification, and may be expressed in the form of various sequences showing the same effect algebraically. The sequence may be called in various ways, such as an LDPC sequence, an LDPC code sequence, an LDPC matrix sequence, or a parity check matrix sequence in order to distinguish it from other sequences.

In addition, LDPC encoding and decoding may be performed by directly generating the parity check matrix in the transmitting and receiving device on the device, but LDPC encoding and decoding using an exponential matrix or sequence that has the same effect algebraically as the parity check matrix according to implementation characteristics. You can also do Therefore, in the present invention, for convenience, encoding and decoding using a parity check matrix is described, but it should be noted that it is considered that it can be implemented through various methods capable of obtaining the same effect as the parity check matrix on an actual device.

For reference, the algebraically the same effect means that it is possible to explain or convert two or more different expressions that are logically or mathematically identical to each other.

의 합으로 포함되어 있을 때, 그 지수 행렬은 수학식 6과 같이 나타낼 수 있다. 상기 수학식 6을 살펴보면, 상기 복수 개의 순환 순열 행렬 합이 포함된 행 블록 및 열 블록에 대응되는 i 번째 행 및 j 번째 열에 2 개의 정수가 대응되는 행렬임을 알 수 있다. In the present invention, for convenience, only one cyclic permutation matrix corresponding to one block has been described, but the same invention may be applied even when multiple cyclic permutation matrices are included in one block. For example, two cyclic permutation matrices at the positions of one i-th row block and j-th column block as shown in Equation 5 below

When included as the sum of, the exponential matrix can be expressed as in Equation 6. Referring to Equation 6, it can be seen that two integers correspond to the i-th row and the j-th column corresponding to the row block and column block including the sum of the plurality of cyclic permutation matrices.

[Equation 5]

[Equation 6]

크기의 행렬을 순환 행렬(circulant matrix 또는 circulant)이라 한다.In general, as in the above embodiment, in the QC-LDPC code, a plurality of cyclic permutation matrices may correspond to one row block and a column block in the parity check matrix, but in the present invention, one cyclic permutation matrix corresponds to one block. Only the case will be described, but the gist of the invention is not limited thereto. For reference, in this way, a plurality of cyclic permutation matrices are duplicated in one row block and column block.

A matrix of size is called a circulant matrix or circulant.

On the other hand, the parent matrix or the basic matrix for the parity check matrix and the exponential matrix in Equation 5 and Equation 6 is similar to the definition used in Equation 3, and each cyclic permutation matrix and 0-matrix are respectively 1 and 0. It means a binary matrix obtained by replacing, and the sum of a plurality of cyclic permutation matrices included in one block (ie, cyclic matrix) is also simply replaced by 1.

Since the performance of the LDPC code is determined according to the parity check matrix, it is necessary to design a parity check matrix for the LDPC code having excellent performance. In addition, there is a need for an LDPC encoding or decoding method capable of supporting various input lengths and code rates.

Lifting is not only used for efficient design of QC-LDPC codes, but also refers to a method used to generate a parity check matrix of various lengths from a given exponential matrix or to generate an LDPC codeword. That is, the lifting is applied to efficiently design a very large parity check matrix by setting the L value that determines the size of a cyclic permutation matrix or 0-matrix from a given small parent matrix according to a specific rule, or a given exponential matrix or corresponding thereto. It refers to a method of generating a parity check matrix of various lengths or generating an LDPC codeword by applying an appropriate L value to the sequence.

The existing lifting method and the characteristics of the QC-LDPC code designed through this lifting will be briefly described with reference to the following reference [Myung2006].

Reference [Myung2006]

S. Myung, K. Yang, and Y. Kim, "Lifting Methods for Quasi-Cyclic LDPC Codes," IEEE Communications Letters. vol. 10, pp. 489-491, June 2006.

는

크기의 지수 행렬

을 가지며 각 지수

들은 {-1, 0, 1, 2, ..., L_k - 1} 값 중에 하나로 선택된다. First, when the LDPC code C ₀ is given, the S QC-LDPC codes to be designed through the lifting method are C ₁ , ..., C _S , and the row blocks and column blocks of the parity check matrix of each of the QC-LDPC codes. The value corresponding to the size of is called _{L k.} Here, C ₀ corresponds to the smallest LDPC code having the parent matrix of C ₁ , ..., C _{S code as a parity check matrix, and the L 0} value corresponding to the size of the row block and the column block is 1. Also, for convenience, the parity check matrix of _{each code C k}

Is

Exponential matrix of magnitude

And each exponent

Are selected as one of the values {-1, 0, 1, 2, ..., L _k-1}.

만 저장하고 있으면 리프팅 방식에 따라 다음 수학식 7을 이용하여 상기 QC-LDPC 부호 C₀, C₁, ..., C_S를 모두 나타낼 수 있다.Existing lifting method consists of the same steps as _{C 0} -> C ₁ ->...-> C _{S and L k+1} = q _k+1 L _k (q _k+1 is a positive integer, k=0, It has features that satisfy the same conditions as 1,..., S-1). Also, the parity check matrix of _{C s}

If only is stored, all of the QC-LDPC codes C ₀ , C ₁ , ..., C _S can be expressed using Equation 7 below according to the lifting method.

[Equation 7]

or

[Equation 8]

In this way, not only a method of designing a larger QC-LDPC code C ₁ , ..., C _{S from C 0 , but also a small code C i} using an appropriate method such as Equation 7 or Equation 8 from the _{large code C k} The method of creating (i=k-1, k-2,… 1, 0) is called lifting.

In the lifting method of Equation 7 or 8, in _{the parity check matrix of each QC-LDPC code C k , L k} corresponding to the size of the row block or the column block have a multiple relationship with each other, so that the exponential matrix is also a specific method. Is selected by Such an existing lifting method improves the algebraic or graph characteristics of each parity check matrix designed through lifting, thereby helping to easily design a QC-LDPC code with improved error floor characteristics.

라 하고, L 값에 따라 변환된 지수 행렬을

이라 할 때 일반적으로 다음과 수학식 9와 같은 변환식이 적용될 수 있다. In general, lifting may be considered as using the exponential matrix of Equation 4 for LDPC encoding and decoding by changing the values of the elements for various L values. For example, the exponential matrix of Equation 4

And the exponential matrix transformed according to the L value

In this case, in general, a transformation equation such as the following Equation 9 may be applied.

[Equation 9]

는 다양한 형태로 정의할 수 있는데 예를 들면 다음 수학식 10과 같은 정의들을 사용할 수도 있다. In Equation 9

May be defined in various forms, for example, definitions such as the following Equation 10 may be used.

[Equation 10]

In Equation 10, mod(a,b) refers to a modulo-b operation for a, and D refers to a constant that is a positive integer defined in advance.

For reference, the criterion to which the transform equation f is applied in the transform equation of Equation 9 is indicated as 0 for convenience, but the reference value may be set differently according to the value of the block size L to be supported. In addition, when the exponent corresponding to the 0 matrix is excluded from the beginning in the expression of the exponent matrix or the LDPC sequence, the rule for values having an exponent less than 0 in Equation 9 may be omitted.

As another embodiment of the present invention, a case in which LDPC encoding and decoding is applied based on a plurality of exponential matrices or LDPC sequences on one determined basic matrix will be described. That is, the basic matrix is fixed to one, and it is variable by determining an exponential matrix or sequence of LDPC codes defined on the basic matrix, and applying a lifting according to the block size included in each block size group from the exponential matrix or sequence. LDPC encoding and decoding of the length are performed. In this method, elements or numbers constituting an exponent matrix of an LDPC code or an LDPC sequence may have different values, but the positions of the corresponding elements or numbers are accurately matched on the basic matrix. As described above, the exponential matrix or LDPC sequence means the index of the cyclic permutation matrix, that is, a kind of cyclic shift value for bits, and corresponds to the corresponding cyclic permutation matrix by setting the positions of all elements or numbers equally. It is easy to grasp the positions of the bits to be used. For reference, since an exponential matrix or LDPC sequence corresponds to a cyclic shift value of bits corresponding to the block size (Z), the exponent matrix is a shift matrix, a shift value matrix, or a shift sequence. ) Or a shift value sequence.

Let us divide the block size (Z) to be supported into a plurality of block size groups (or sets) as shown in Equation 11 below. Note that the block size (Z) is a value corresponding to the size ZxZ of the cyclic permutation matrix or the cyclic matrix in the parity check matrix of the LDPC code.

[Equation 11]

Z1 = {2, 4, 8, 16, 32, 64, 128, 256}

Z2 = {3, 6, 12, 24, 48, 96, 192, 384}

Z3 = {5, 10, 20, 40, 80, 160, 320}

Z4 = {7, 14, 28, 56, 112, 224}

Z5 = {9, 18, 36, 72, 144, 288}

Z6 = {11, 22, 44, 88, 176, 352}

Z7 = {13, 26, 52, 104, 208}

Z8 = {15, 30, 60, 120, 240}

Equation 11 is only an example, and all block size (Z) values included in the block size group of Equation 11 may be used, or block size values included in an appropriate subset as shown in Equation 12 below may be used. In addition, appropriate values may be added to or excluded from the block size group (or set) of Equation 11 or 12.

[Equation 12]

Z1'= {8, 16, 32, 64, 128, 256}

Z2'= {12, 24, 48, 96, 192, 384}

Z3'= {10, 20, 40, 80, 160, 320}

Z4'= {7, 14, 28, 56, 112, 224}

Z5'= {18, 36, 72, 144, 288}

Z6'= {11, 22, 44, 88, 176, 352}

Z7'= {26, 52, 104, 208}

Z8'= {15, 30, 60, 120, 240}

라 하고, 상기 p번째 그룹에 포함된 Z 값에 대응되는 지수 행렬을

라 할 때, f_p (x,Z) = x (mod Z)를 이용하여 수학식 9와 같은 수열의 변환 방법을 적용한다고 하자. 즉, 예를 들어 블록 크기 Z가 Z = 28와 같이 결정된 경우에는 Z = 28이 포함되어 있는 4번째 블록 크기 그룹에 대응되는 지수 행렬(또는 LDPC 수열)

에 대해서 Z = 28에 대한 지수 행렬(또는 LDPC 수열)

각 원소

를 다음 수학식 13과 같이 얻을 수 있다. The block size groups of Equation 11 and Equation 12 have different granularity, and all the ratios of neighboring block sizes are the same integer. In other words, the block sizes included in one group have a factor or multiple relationship with each other. Each of the exponential matrices corresponding to the p (p = 1, 2, ..., 8) group

And, an exponential matrix corresponding to the Z value included in the p-th group is

In the case of, _{suppose that f p} (x,Z) = x (mod Z) is used to apply the conversion method of a sequence as shown in Equation 9. That is, for example, when the block size Z is determined as Z = 28, the exponential matrix (or LDPC sequence) corresponding to the fourth block size group in which Z = 28 is included.

For Z = 28 exponential matrix (or LDPC sequence)

Each element

Can be obtained as in Equation 13 below.

[Equation 13]

Transformation such as Equation 13 is also simply expressed as Equation 14 below.

[Equation 14]

For reference, above has been described on the assumption that the lifting or transforming of the exponential matrix in Equations 9 and 10 or Equations 11 to 14 is applied to the entire exponential matrix corresponding to the parity check matrix. The exponential matrix can also be partially applied.

For example, in general, a submatrix corresponding to a parity bit of a parity check matrix often has a special structure for efficient encoding. In this case, the coding method or complexity may change due to lifting. Therefore, in order to maintain the same coding method or complexity, lifting is not applied to a part of the exponential matrix for the partial matrix corresponding to the parity in the parity check matrix, or the lifting method applied to the exponential matrix for the partial matrix corresponding to the information bit Other lifting can be applied. In other words, the lifting method applied to the sequence corresponding to the information word bit in the exponential matrix and the lifting method applied to the sequence corresponding to the parity bit may be set differently. In some cases, a part of the sequence corresponding to the parity bit Alternatively, a fixed value may be used without a sequence conversion because no lifting is applied to the whole.

4 is a block diagram of a transmission device according to an embodiment of the present invention.

Specifically, as shown in FIG. 4, the transmission device 400 includes a segmentation unit 410, a zero padding unit 420, an LDPC encoding unit 430, and a rate matching unit 440 to process variable length input bits. ), a modulator 450, and the like. The rate matching unit 440 may include an interleaver 441 and a puncturing/repetition/zero removal unit 442, and the like.

Here, the constituent elements shown in FIG. 4 are constituent elements that encode and modulate variable-length input bits, and this is only an example, and some of the constituent elements shown in FIG. 4 may be omitted or changed in some cases. May be, and other components may be added. As an example of the modulation scheme, any of a QAM scheme such as QPSK, 16-, 64-, 256-, 1024-QAM, or a phase shift keying (PSK) or amplitude and PSK (APSK) scheme may be used.

On the other hand, the transmission device 400 is required parameters (e.g., input bit length, ModCod (modulation and code rate), zero padding (or shortening)) parameters, LDPC code code rate, information word or code The reception device 500 by determining the length of the word, interleaving parameters, parameters for repetition and puncturing, and modulation methods), encoding input bits based on the determined parameters, etc. ).

Since the number of input bits is variable, when the number of input bits is greater than a preset value, the input bits may be segmented to have a length less than or equal to the preset value. In addition, each segmented block may correspond to one LDPC-coded block. However, if the number of input bits is less than or equal to a preset value, segmentation is not performed. Input bits may correspond to one LDPC coded block.

Meanwhile, the transmission device 400 may pre-store various parameters used for encoding, interleaving, and modulation. Here, the parameter used for encoding may include at least one of information on a code rate of an LDPC code, an input bit or information word or code word length, and a parity check matrix. Further, a parameter used for interleaving may include information on an interleaving rule, and a parameter used for modulation may include information on a modulation method. Also, the information on puncturing may include a puncturing length. In addition, the information on the repetition may include the length of the repetition. The information on the parity check matrix may include an index value of a cyclic matrix when the parity matrix presented in the present invention is used.

In this case, each component constituting the transmission device 400 may perform an operation using these parameters.

Meanwhile, although not shown, in some cases, the transmission device 400 may further include a control unit (not shown) for controlling the operation of the transmission device 400.

5 is a block diagram of a receiving device according to an embodiment of the present invention.

Specifically, as shown in FIG. 5, in order to process variable length information, the receiving device 500 includes a demodulation unit 510, a rate dematching unit 520, an LDPC decoding unit 530, a zero removing unit 540, and It may include a desegmentation unit 550 and the like. The rate dematching unit 520 may include a log likelihood ratio (LLR) insertion unit 522, an LLR combiner 523, a deinterleaver 524, and the like. The LLR insertion unit 522 and the LLR combiner 523 may have different names according to values used for decoding. For example, when decoding is performed based on values such as LR (likelihood raito) instead of LLR, a name may be determined based on values used for decoding, such as an LR inserter and an LR combiner. Based on this, the operation may be slightly different.

The operation of the demodulator 510 may be subdivided into various processes and expressed in some cases. For example, after channel estimation based on the received signal, values necessary for FEC decoding corresponding to the codeword bits transmitted from the demodulated signal or symbol based on the result (eg, LLR or LR or It can be subdivided into the process of determining the corresponding value, etc.). In this case, the operation within each demodulator may be subdivided into each channel measurement block and a symbol-to-LLR (symbol-to-LLR) conversion block. Of course, various subdivisions are possible according to the structure of the system.

Here, the components shown in FIG. 5 are components that perform functions corresponding to the components shown in FIG. 5, and this is only an example, and some may be omitted or changed depending on the case, and other components are More may be added.

The parity check matrix in the present invention may be read using a memory, may be given in advance by a transmitting device or a receiving device, or may be directly generated by a transmitting device or a receiving device. In addition, the transmitting device may store or generate a sequence or an exponential matrix corresponding to the parity check matrix and apply it to encoding. Similarly, the receiving device may store or generate a sequence or an exponential matrix corresponding to the parity check matrix and applied to decoding.

Hereinafter, a detailed description of the operation of the receiver will be made based on FIG. 5.

The demodulation unit 510 demodulates the signal received from the transmission device 400.

Specifically, the demodulation unit 510 is a component corresponding to the modulation unit 450 of the transmission device 400, receives and demodulates a signal transmitted from the transmission device 400, and transmits the signal from the transmission device 400. Values (eg, LLR or LR or values corresponding thereto) corresponding to bits may be generated.

To this end, the reception device 500 may pre-store information on a modulation scheme modulated by the transmission device 400 according to a mode. Accordingly, the demodulator 510 may demodulate the signal received from the transmission device 400 according to the mode, and may generate values corresponding to the LDPC codeword bits.

The LR value refers to the ratio of the probability that the bit transmitted from the transmitting device 400 is 0 and the probability of 1, and the LLR value is a log in the ratio of the probability that the bit transmitted from the transmitting device 400 is 0 and the probability of being 1. Can be expressed as the value taken. Alternatively, the LR or LLR value may be hard-determined according to the probability or the ratio of the probability or the log value for the ratio of the probability and expressed as the bit value itself, or the log value for the ratio of the probability or probability or the ratio of the probability It can also be expressed as a representative value defined in advance according to the section to which it belongs. An example of a method of determining a representative value defined in advance according to a section to which the probability or the ratio of the probability or the log value for the ratio of the probability belongs is a method that considers quantization. In addition, various other values corresponding to the probability or the ratio of the probability or the log value for the ratio of the probability may be used.

In the present invention, the operation based on the LLR value is shown for convenience in order to describe the operation of the receiving method and the device, but there is no need to be limited thereto.

The demodulation unit 510 includes a function of performing multiplexing (not shown) on the LLR value. Specifically, the mux (not shown) is a component corresponding to the bit demux (not shown) of the transmission device 400 and may perform an operation corresponding to the bit demux (not shown).

To this end, the receiving device 500 may pre-store information on parameters used by the transmitting device 400 for demultiplexing and block interleaving. Accordingly, the MUX (not shown) performs demultiplexing and block interleaving operations performed in bit demux (not shown) for the LLR value corresponding to the cell word (information representing the received symbol for the LDPC codeword as a vector value). Conversely, the LLR value corresponding to the cell word can be multiplexed in bit units.

The rate dematching unit 520 may additionally insert an LLR value into the LLR values output from the demodulation unit 510. In this case, the rate dematching unit 520 may insert predetermined LLR values between LLR values output from the demodulation unit 510.

Specifically, the rate dematching unit 520 is a component corresponding to the rate matching unit 440 of the transmission device 400, and includes an interleaver 441, zero removal and puncturing/repetition/zero removal unit 442. ) Can be performed.

또는 -

가 될 수 있다. 하지만,

또는 -

는 이론적인 값이며, 실질적으로는 수신 장치(500)에서 이용되는 LLR 값의 최대값 또는 최소값이 될 수 있다.First, the rate dematching unit 520 performs deinterleaving to correspond to the interleaver 441 of the transmitter. LLR values corresponding to the zero bits may be inserted into the output values of the deinterleaver 524 at a position where the zero bits were padded in the LDPC codeword by the LLR insertion unit 522. In this case, the padded zero bits, that is, the LLR values corresponding to the shortened zero bits, are

or -

Can be. But,

or -

Is a theoretical value, and may actually be a maximum value or a minimum value of the LLR value used in the reception device 500.

To this end, the receiving device 500 may pre-store information on a parameter used by the transmitting device 400 to pad the zero bits. Accordingly, the rate dematching unit 520 may determine a position where the zero bits have been padded in the LDPC codeword, and insert an LLR value corresponding to the shortened zero bits in the corresponding position.

In addition, the LLR insertion unit 522 of the rate dematching unit 520 may insert LLR values corresponding to the punctured bits at positions of the punctured bits in the LDPC codeword. In this case, the LLR value corresponding to the punctured bits may be 0 or another predetermined value. In general, when parity bits of order 1 are punctured, there is no effect on performance improvement in the LDPC decoding process, so they may not be used in the LDPC decoding process without LLR insertion in part or all of the corresponding puncturing positions. However, in order to increase the efficiency of the LDPC decoding process based on the parallel process, the LLR insertion unit 522 uses a predetermined LLR at a position corresponding to some or all of the order 1 puncturing bits regardless of the decoding performance improvement. You can insert values.

To this end, the receiving device 500 may pre-store information on a parameter used for puncturing by the transmitting device 400. Accordingly, the LLR inserting unit 522 may insert an LLR value (eg, LLR = 0) corresponding to the LDPC information word bit or the parity bit punctured position. However, this process may be omitted for positions of some punctured parity bits.

The LLR combiner 523 may combine, that is, sum, the LLR values output from the LLR insertion unit 522 and the demodulation unit 510. Specifically, the LLR combiner 523 is a component corresponding to the puncturing/repetition/zero removal unit 442 of the transmission device 400, and performs an operation corresponding to the repeater 442. I can. First, the LLR combiner 523 may combine the LLR values corresponding to the repeated bits with other LLR values. Here, the other LLR value may be bits based on generation of the bits repetitioned by the transmission device 400, that is, an LLR value for an LDPC information word bit or parity bits selected as a repetition target. In addition, according to the 3GPP 5G standard TS 38.212 document, the repetitioned bits may be variously determined based on parameters such as redundancy version (RV) values or code rates set in a retransmission process such as hybrid ARQ (HARQ). have.

That is, as described above, the transmission device 400 selects LDPC coded bits and, if necessary, repeats some of the LDPC information word bits and the LDPC parity bits to transmit to the reception device 500. Accordingly, the LLR values for LDPC coded bits may be composed of LLR values for repetitioned LDPC coded bits and LLR values for non-repeatable LDPC coded bits. The LLR combiner 523 may combine LLR values corresponding to the same LDPC coded bits.

To this end, the reception device 500 may pre-store information on a parameter used by the transmission device 400 for repetition. Accordingly, the LLR combiner 523 may determine an LLR value for the repetitioned LDPC coded bits, and combine this with the LLR value for the LDPC coded bits that are the basis of the repetition.

In addition, the LLR combiner 523 may combine the LLR values corresponding to retransmitted or increment redundancy (IR) bits with other LLR values. Here, the other LLR value may be an LLR value for some or all of the LDPC codeword bits based on the generation of bits retransmitted or IRed by the transmitting device 400.

As described above, when NACK occurs for HARQ, the transmission device 400 may transmit some or all of the codeword bits to the reception device 500.

Accordingly, the LLR combiner 523 may combine an LLR value for bits received through retransmission or IR with an LLR value for LDPC codeword bits received through a previous frame.

To this end, the receiving device 500 may pre-store information on a parameter used by the transmitting device 400 for retransmission or generating an IR bit. Accordingly, the LLR combiner 523 may determine an LLR value for retransmission or IR bits, and combine this with an LLR value for at least some of the LDPC coded bits that are the basis for generation of the retransmission bits.

The deinterleaver 524 may deinterleave the LLR value output from the LLR combiner 523.

Specifically, the deinterleaver 524 is a component corresponding to the interleaver 441 of the transmission device 400 and may perform an operation corresponding to the interleaver 441.

To this end, the receiving device 500 may pre-store information on parameters used by the transmitting device 400 for interleaving. Accordingly, the deinterleaver 524 reversely performs the interleaving operation performed by the interleaver 441 on the LLR values corresponding to the transmitted LDPC coded bits, and obtains the LLR values corresponding to the transmitted LDPC coded bits. Deinterleaving is possible.

The LDPC decoding unit 530 may perform LDPC decoding based on the LLR value output from the rate dematching unit 520.

Specifically, the LDPC decoder 530 is a component corresponding to the LDPC encoder 430 of the transmission device 400 and may perform an operation corresponding to the LDPC encoder 430.

To this end, the receiving device 500 may pre-store information on a parameter used by the transmitting device 400 to perform LDPC encoding according to a mode. Accordingly, the LDPC decoding unit 530 may perform LDPC decoding based on the LLR value output from the rate dematching unit 520 according to the mode.

For example, the LDPC decoding unit 530 performs LDPC decoding based on the LLR value output from the rate dematching unit 520 based on an iterative decoding method based on the sum-multiplication algorithm, and the error is corrected according to the LDPC decoding. Bits can be output.

The zero remover 540 may remove zero bits from bits output from the LDPC decoder 530.

Specifically, the zero removing unit 540 is a component corresponding to the zero padding unit 420 of the transmission device 400 and may perform an operation corresponding to the zero padding unit 420.

To this end, the receiving device 500 may pre-store information on a parameter used by the transmitting device 400 to pad the zero bits. Accordingly, when decoding is performed using the padded bits in the LDPC decoding unit 530, the zero removing unit 540 may remove the zero bits padded by the zero padding unit 420 from output bits. have. The operation of removing the zero padded (or shortened) bit by the zero removing unit 540 may actually mean an operation of removing the padding bits, but the output bits of the LDPC decoding unit 530 are converted to the next desegmentation unit. When transmitting to 550, it may mean an operation of excluding the padded bits. In addition, the zero-padded bits in the transmitting device may not be used in the decoding process because the receiving device accurately knows their positions. In this case, the process of removing the zero-padded bits may be omitted.

The desegmentation unit 550 is a component corresponding to the segmentation unit 410 of the transmission device 400 and may perform an operation corresponding to the segmentation unit 410.

To this end, the receiving device 500 may pre-store information on parameters used by the transmitting device 400 for segmentation. Accordingly, the desegmentation unit 550 may restore bits before segmentation by combining the bits output from the zero removal unit 540, that is, segments of variable length input bits.

Meanwhile, the LDPC code can be decoded using an iterative decoding algorithm based on the sum-multiplication algorithm on the dividing graph listed in FIG. 2, and the sum-product algorithm is a kind of message passing algorithm.

Hereinafter, a message passing operation generally used in LDPC decoding will be described with reference to FIGS. 6A and 6B.

6A and 6B are diagrams illustrating a message passing operation in an arbitrary check node and a variable node for LDPC decoding.

6A illustrates a test node m 600 and a plurality of variable nodes 610, 620, 630 and 640 connected to the test node m 600. In addition, the illustrated Tn',m represents a message that is passed from the variable node n'(610) to the check node m (600), and En,m is the pass from the check node m (600) to the variable node n (630). Indicates a message to be used. Here, the set of all variable nodes connected to the test node m(600) is defined as N(m), and the set except for the variable node n(630) in N(m) is defined as N(m)\n. It should be.

In this case, the message update rule based on the summation algorithm may be expressed as Equation 15 below.

[Equation 15]

는 하기의 수학식 16과 같이 나타낼 수 있다. Here, Sign(E _n,m ) represents the sign of the message E _n,m , and |E _n,m | represents the magnitude of the message E _n,m. Meanwhile, the function

Can be expressed as in Equation 16 below.

[Equation 16]

For reference, the -log(tanh(.)) function of Equation 16 may be more simply expressed as a log(coth(.)) function.

Meanwhile, in FIG. 6B, a plurality of test nodes 660, 670, 680, and 690 connected to the variable node x 650 and the variable node x 650 are illustrated. In addition, the illustrated E _y',x represents a message passed from the check node y'(660) to the variable node x (650), and T _y,x is the check node y (680) from the variable node x (650). Represents a message that is passed by. Here, the set of all test nodes connected to the variable node x(650) is defined as M(x), and the set except for the test node y(680) in M(x) is defined as M(x)\y. It should be. In this case, the message update rule based on the summation algorithm may be expressed as Equation 17 below.

[Equation 17]

Here, E _x means the initial message value of the variable node x.

In addition, when determining the bit value of the node x, it can be expressed as Equation 18 below.

[Equation 18]

In this case, the coded bit corresponding to the node x can be determined according to the Px value.

Since the method described above in FIGS. 6A and 6B is a general decoding method, a detailed description thereof will be omitted. However, in addition to the methods described in FIGS. 6A and 6B, other methods may be applied to determine the values of messages passed in the variable node and the check node, and detailed descriptions related thereto are described in “Frank R. Kschischang, Brendan J. Frey, and Hans-Andrea Loeliger, "Factor Graphs and the Sum-Product Algorithm," IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 47, NO. 2, FEBRUARY 2001, pp498-519). For example, in Equations 15 and 16, the update expression of the check node is expressed in the form of a sum by expressing it based on the -log(tanh(.)) function. It is expressed in the form of a product based on the ^{inverse function tanh -1 (.).} As such, there may be various expression methods that are conceptually identical. In addition, in order to reduce complexity, various simplified decoding methods such as a min-sum algorithm may exist. In the present invention, detailed descriptions of these various decoding algorithms are omitted, but it is obvious that the decoding scheduling scheme proposed in the present invention and the decoding algorithms as well as various other types of decoding algorithms can be combined.

7 is a block diagram illustrating a detailed configuration of an LDPC encoding unit according to an embodiment of the present invention.

)을 구성할 수 있다. LDPC 부호화부(700)는 K_ldpc 개의 LDPC 정보어 비트들을 시스테매틱하게 LDPC 부호화하여, N_ldpc 개의 비트들로 구성된 LDPC 코드워드 C = (c₀,c₁,..., c_Nldpc-1) = (i₀,i₁,..., i_Kldpc-1,p₀,p₁,...,p_{Nldpc-Kldpc-1})를 생성할 수 있다. K _{ldpc bits are K ldpc} LDPC information bits for the LDPC encoder 700 I = (i ₀ ,i ₁ ,...,

) Can be configured. The LDPC encoder 700 systematically performs LDPC encoding of K _ldpc LDPC information bits, and an LDPC codeword consisting of _{N ldpc bits C = (c 0} ,c ₁ ,..., c _Nldpc-1 ) = (i ₀ ,i ₁ ,..., i _Kldpc-1 ,p ₀ ,p ₁ ,...,p _{Nldpc-Kldpc-1} ) can be created.

As described in Equation 1, a codeword is determined such that the product of the LDPC codeword and the parity check matrix becomes a zero vector.

Referring to FIG. 7, the encoding apparatus 700 includes an LDPC encoding unit 710. The LDPC encoder 710 may generate an LDPC codeword by performing LDPC encoding on input bits based on a parity check matrix or an exponential matrix or sequence corresponding thereto. In this case, the LDPC encoder 710 uses a parity check matrix differently defined according to a code rate (that is, a code rate of an LDPC code) or an input bit (or code word or information word) length, or a block length Z. Encoding can be performed.

Meanwhile, the encoding apparatus 700 may further include a memory (not shown) for pre-storing information on a code rate of an LDPC code, an input bit (or information word or code word) length, and a parity check matrix. The encoder 710 may perform LDPC encoding using this information. The information on the parity check matrix may include information on an index value of a cyclic matrix when the parity matrix presented in the present invention is used.

8 is a block diagram illustrating a configuration of a decoding apparatus according to an embodiment of the present invention.

Referring to FIG. 8, the decoding apparatus 800 may include an LDPC decoding unit 810.

The LDPC decoder 810 performs LDPC decoding on an LDPC codeword based on a parity check matrix or an exponential matrix or sequence corresponding thereto.

For example, the LDPC decoder 810 may generate information word bits by performing LDPC decoding by passing LLR values corresponding to LDPC codeword bits through an iterative decoding algorithm. Here, the LLR value is a channel value corresponding to LDPC codeword bits transmitted from the transmitter, and may be expressed in various ways.

In this case, the LDPC decoder 810 may perform LDPC decoding using a parity check matrix defined differently according to a code rate (ie, a code rate of an LDPC code).

9 is a diagram illustrating a structure of an LDPC decoder according to another embodiment of the present invention.

Meanwhile, as described above, the LDPC decoding unit 810 may perform LDPC decoding using an iterative decoding algorithm. In this case, the LDPC decoding unit 810 may have a structure as shown in FIG. 9. However, the detailed configuration shown in FIG. 9 is also only an example.

Referring to FIG. 9, the decoding apparatus 900 includes an input processor 901, a memory 902, a variable node calculator 904, a controller 906, a check node calculator 908, an output processor 910, and the like. .

The input processor 901 stores an input value. Specifically, the input processor 901 may store an LLR value of a received signal received through a wireless channel.

The controller 904 is the number of values input to the variable node operator 904 based on the size of the block of the received signal received through the radio channel (i.e., the length of the codeword) and the parity check matrix corresponding to the code rate. And an address value in the memory 902, the number of values input to the check node operator 908, and an address value in the memory 902 are determined.

The memory 902 stores input data and output data of the variable node operator 904 and the check node operator 908.

The variable node operator 904 receives data from the memory 902 according to address information of input data and information on the number of input data received from the controller 906 and performs a variable node operation. Thereafter, the variable node operator 904 stores the variable node operation results in the memory 902 based on the address information of the output data received from the controller 906 and information on the number of output data. In addition, the variable node operator 904 inputs a variable node operation result to the output processor 910 based on data received from the input processor 901 and the memory 902. Here, the variable node operation has been described above based on FIG. 6.

The check node operator 908 receives data from the memory 902 based on address information of input data and the number of input data received from the controller 906 and performs a check node operation. Thereafter, the test node operator 908 stores the test node operation results in the memory 902 based on address information of the output data received from the controller 906 and information on the number of output data. Here, the check node operation has been described above based on FIG. 6.

The output processor 910 makes a hard decision based on the data received from the variable node operator 904 to determine whether the information word bits of the codeword on the transmitting side were 0 or 1, and then outputs the hard decision result. The output value of 910 becomes the finally decoded value. In this case, a hard decision may be made based on the sum of all message values (initial message values and all message values input from the check node) input to one variable node in FIG. 6.

Meanwhile, the memory 902 of the decoding apparatus 900 may pre-store information on the code rate of the LDPC code, the length of the input bit (or information word or code word), and the parity check matrix, and the LDPC decoder 810 LDPC encoding can be performed using this information. However, this is only an example, and the corresponding information may be provided from the transmitting side.

10 is an exemplary diagram of a decoding process in an LDPC decoding apparatus according to an embodiment of the present invention.

Referring to FIG. 10, in step 1001, a value, referred to as a channel LLR or an intrinsic LLR, of a corresponding bit generated from a received signal is input to each variable node. The input LLR values may be rate de-matched LLR values. In step 1003, the intrinsic LLR of each variable node is transmitted to a neighboring check node, and all check nodes calculate a message corresponding to an extrinsic LLR to be transferred to each variable node based on the received message. In the flooding-type LDPC decoder, all check nodes calculate and update message values, and a message corresponding to the calculated extrinsic LLR is delivered to neighboring variable nodes along a connected connection line.

In step 1005, all variable nodes generate a complete LLR to determine the message and bit values to be delivered to the check nodes based on the message corresponding to the received extrinsic LLR and intrinsic LLR values. do. The final LLR may be referred to as a posterior probability (APP) metric, an APP LLR, or another term having an equivalent technical meaning. In the flooding-type LDPC code decoder, all variable nodes calculate and update message values.

In step 1007, the variable node estimates the bit value by hard-decision on the final LLR before delivering the message to the check node.

In step 1009, it is checked whether the estimated bit value satisfies the syndrome check equation determined by the parity check matrix. When it is confirmed that the syndrome check equation is satisfied, in step 1011, it is determined that the decoding has been successful, and the success of the decoding is output and reported.

If it is determined that the syndrome check equation is not satisfied, in step 1013, it is checked whether the number of repetitive decoding performed so far reaches the maximum number of repetitive decoding previously specified. If the number of repetitive decoding performed so far has not reached the maximum number of repetitive decoding, the series of processes are repeated again. If the result of the decoding does not satisfy the syndrome check equation until the number of repetitive decoding performed so far reaches the maximum number of repetitive decoding, in step 1015, a decoding failure is output and reported.

The layered LDPC decoding refers to a method of dividing check nodes into a plurality of layers, and then sequentially performing decoding from the ordered check nodes.

Referring to FIG. 10, in step 1003, a check node belonging to an ordered layer receives a message from a connected variable node. The check node delivers the calculated and updated message to neighboring variable nodes. In step 1005, variable nodes receiving the updated message calculate and update a message and a final LLR to be transmitted to the check node. A series of operation processes for one layer as described above is referred to as layer processing.

When layer processing is performed for all layers, in step 1007, the receiving end calculates a bit estimate by hard-determining the final LLR calculated by each variable node. In step 1009, the receiving end checks whether the decoding succeeds or fails by performing a syndrome check based on the estimated bit value. In this case, the check nodes of the parity check matrix corresponding to the syndrome check may be all check nodes or some check nodes that are predetermined. (For example, some or all of the check nodes connected to the variable node of degree 1 may be excluded.)

In general, an LDPC code can detect an error through a syndrome, but a CRC code may be additionally applied as an external code to support a higher level of error detection capability. Fig. 11 shows a general example of an FEC decoding operation when a CRC code is applied as an outer code and an LDPC code is applied as an inner code.

11 is an exemplary diagram of a decoding process based on LDPC and CRC codes according to an embodiment of the present invention.

라 하고 복호에 사용된 패리티 검사 행렬을 H라 할 때, 다음 수학식 19와 같이 결정되는 값을 의미한다. As shown in FIG. 11, the receiver generally performs LDPC decoding in step 1110 and then checks or checks the syndrome of the LDPC as in step 1120 to determine whether an error is detected. Here, the LDPC syndrome is a codeword that can be obtained through hard decision after performing LDPC decoding.

When denoted by and the parity check matrix used for decoding is denoted by H, it means a value determined as in Equation 19 below.

[Equation 19]

가 성립하므로, 복호가 성공적으로 수행되었을 경우에는 상기 수학식 19의 신드롬 s 값 또한 0이 되어야 한다. (경우에 따라 LDPC 신드롬 값이 0인 경우를 LDPC 신드롬 값을 확인하여 통과(pass)되었다고 표현할 수도 있다.) 하지만 만일 상기 신드롬 값이 0이 아니라면 (또는 LDPC 신드롬 값이 통과되지 못했다면),

임을 의미한다. If the codeword transmitted from the actual transmitter is c, by Equation 1

Since is established, when decoding is successfully performed, the syndrome s value of Equation 19 should also be 0. (In some cases, when the LDPC syndrome value is 0, it may be expressed that the LDPC syndrome value is checked and passed.) However, if the syndrome value is not 0 (or if the LDPC syndrome value has not passed),

Means

If the LDPC syndrome s value is not 0 in step 1120 of FIG. 11, the receiver immediately makes an exception in step 1150 and determines whether to use the information word bit or code block performed LDPC decoding in the upper layer of the system, or Alternatively, it may be determined whether to discard the information word bit or code block obtained by the LDPC decoding, as determined in advance.

However, even if the LDPC syndrome s value is not 0 in step 1120, the receiver does not immediately process an exception in step 1150 and may perform CRC detection (or confirmation) on the information word bit as in step 1130. The reason is that the codeword decoding failed according to the LDPC decoding result, but since there is a possibility that only the parity bit remains and there is no error in the information word bit after LDPC decoding, CRC detection is performed in step 1130 to determine the information word bit. It is possible to determine whether to detect errors for

In addition, when the LDPC syndrome value according to LDPC decoding is 0, the receiver may perform CRC detection in step 1130.

If it is determined in step 1130 that the information word bit vector has been successfully decoded through CRC detection, the decoding process is terminated. If it is determined in step 1130 that the information word bit vector contains an error as a result of CRC detection, the receiver treats the decoded information word bit vector or code block as an exception as in step 1150, and generates the corresponding information word vector or code block. It is possible to decide whether to use or not use, or to discard (discard) in the upper layer of the.

Note that in the present invention, the meaning of exception handling may mean all operations performed when it is determined that decoding has failed or is likely to fail, in addition to operations to be performed when decoding has been successfully performed in all processes.

In addition, the receiver may generate an instruction or flag regarding whether or not the decoding is successful and transmit it to an upper layer. The upper layer may determine a processing method of decoded information word bits or code blocks based on the instruction or flag. (Example: Resend request decision, etc.)

이지만, 복호된 부호어

가 c와는 다른 부호어인 경우에는 LDPC 신드롬이 0이 될 수도 있다. 이러한 오류는 LDPC 부호를 통해 검출이 불가능하기 때문에(undetected error) 통상적으로 LDPC 복호 후에 CRC 검출을 수행해야 오류를 검출할 수 있다. For reference, in Equation 19

But, the decoded codeword

If is a codeword different from c, the LDPC syndrome may be 0. Since such an error cannot be detected through the LDPC code (undetected error), it is generally necessary to perform CRC detection after LDPC decoding to detect the error.

In addition, the syndrome value s may be obtained (or calculated or determined) through a calculation process based on a parity check matrix and a decoded codeword as shown in Equation 19, but may be easily obtained according to characteristics of the LDPC decoder. For example, in Equation 15, a message used in a decoding process for LDPC decoding can be divided into a size and a code to perform decoding, where the syndrome value s is the operation of + or-signs of the messages. It can be easily obtained (or calculated or determined) through. For example, in an actual decoder implementation, a + sign is mapped to a binary number such as 0 and a-sign is 1, so that a syndrome value can be easily obtained based on an appropriate XOR operation. In particular, it is possible to easily identify whether the syndrome value is 0 or not from an implementation feature in the LDPC iterative decoding process. For reference, the hard decision degree of the actual LDPC-decoded codeword can be easily determined based on the codes of messages for each bit of LDPC decoding.

When checking or confirming the LDPC syndrome in step 1120, it is not necessary to check or confirm all syndromes of the LDPC code, and only some syndrome values may be tested or confirmed. For example, a check node connected to a variable node of degree 1, that is, syndrome values related to a check node corresponding to a parity bit of degree 1 may not be used for checking or checking in step 1120. Since the bits corresponding to the variable node of order 1 have a significantly low probability of correcting an error, it is highly likely to always be detected that an error has occurred even when the LDPC syndrome is checked. Therefore, in order to prevent an erroneous error test result, in many cases, the LDPC syndrome is checked or confirmed for all or part of the test nodes connected only to variable nodes or bits of degree 2 or more.

The LDPC code considered in the present invention is a quasi-circular LDPC code that can be defined as a quasi-circular parity check matrix of FIG. 3, and generally has algebraic characteristics according to a block size expressed by L or Z as shown in Equation 11. Have. For example, the cycle characteristics of the quasi-cyclic LDPC code on the Tanner graph are related to the block size, and if the parity check matrix has complete coefficients, the length of the LDPC information word can also be expressed in the form of a multiple of the block size. Due to this algebraic characteristic, not only encoding but also decoding of the quasi-cyclic LDPC code can be performed more efficiently based on the block length.

However, since a transport block generally has various lengths, the number of information word bits of the LDPC code that can be defined in the parity check matrix of the quasi-cyclic LDPC code, that is, may not appear in the form of a multiple of the specific block size Z. Even after the segmentation described in FIG. 4, it may not appear in the form of a multiple of the block size Z. In this way, information word bits or code blocks that are smaller than the maximum number of LDPC information bits that can perform LDPC encoding on the parity check matrix at one time or that are less than the maximum code block size or that are not multiples of the block size are coded. In this case, for convenience of encoding or decoding, an operation such as zero padding (or shortening) may be additionally performed to satisfy a multiple of the block size.

In the present invention, the maximum number of bits of the LDPC information that can be coded at one time for the parity check matrix of the LDPC code or the basic matrix (or parent matrix) of the parity check matrix is determined for convenience. It can be referred to as a code block size, which _{can be expressed as K cb.}

The maximum number of LDPC information word bits or the maximum code block size may be differently defined for each given parity check matrix or basic matrix. For example, in coding using a parity check matrix defined based on the basic matrix B1, the maximum code block size is _{defined as K cb1} = 8448, and in coding using a parity check matrix defined based on the basic matrix B2, the maximum code The block size can be defined as _{K cb2 = 3840.} In this case, it should be noted that K _cb1 = 8448 and K _cb2 = 3840 must be multiples of the maximum value of the block size Z applicable to each basic matrix.

For example, if the maximum values of the applicable block sizes for the basic matrices B1 and B2 are the same as 384, K _cb1 = 8448 = 22*384 and K _cb2 = 3840 = 10*384, and the information of the basic matrix B1 This means that the partial matrix corresponding to the bit is composed of 22 column blocks, and the partial matrix corresponding to the information word bit of the basic matrix B2 is composed of 10 column blocks.

As described above, in the present invention, since the number of columns of the partial matrix corresponding to the information word bits is a multiple of the block size, LDPC encoding is performed by adding <Null> bits to the transport block to be transmitted for convenience of encoding and decoding. The size of the code block to be applied may be set to be a multiple of the block size Z of the LDPC parity check matrix. <Null> bits may be added irrespective of whether segmentation is applied or not, and may be added to set the size of the code block to be constant. Adding <Null> bits to the information word bits of these LDPC codes is generally called'shortening', and since it is set as the bit value (for example, 0) at the promised position in the transmitter and receiver, it is actually transmitted. It may not be possible, and since the receiver can accurately know the value, decoding may be performed by excluding it from the decoding process, or decoding may be performed by applying a value promised during the decoding process.

For example, if the promised value of the shortened bits is 0, the decoder returns a value corresponding to 1 (e.g., in the case of LLR, the maximum value set in the system corresponding to the infinity value). It can also be applied to perform decoding.

In general, in the case of a system in which a sequence is appropriately transformed and used for a wide variety of block sizes L (or Z) from one LDPC exponential matrix or sequence or parity check matrix, like the lifting method described in Equations 9 to 14, There are many advantages because it only needs to be implemented for one or a small number of sequences. However, as the number of block sizes to be supported increases, it is a very difficult problem to design an LDPC code with good performance for all block sizes.

12 and 13 are flowcharts illustrating an embodiment of an LDPC encoding and decoding process based on a designed basic matrix or an exponential matrix.

12 is a diagram illustrating an embodiment of an LDPC encoding process according to an embodiment of the present invention.

First, as shown in step 1210 of FIG. 12, the transmitter determines the TBS of the transport block size (or transport block size, transport block size) to be transmitted. In step 1220, the transmitter determines whether the TBS is greater than, less than or equal to max CBS, which is the maximum code block size.

If the TBS is greater than max CBS, the transmitter determines a new CBS by segmenting the transport block in step 1230, and if it is less than or equal to the TBS, the segmentation operation is omitted and the TBS is determined as CBS.

In step 1240, the transmitter determines a block size (Z) value to be applied to LDPC encoding based on the CBS.

In step 1250, the transmitter appropriately determines the LDPC index matrix or sequence according to the TBS or CBS or block size (Z) value.

In step 1260, the transmitter performs LDPC encoding based on the determined block size and an exponential matrix or sequence. In some cases, step 1250 may include a process of transforming the determined LDPC index matrix or sequence based on the determined block size. It is obvious that the LDPC exponential matrix or sequence or parity check matrix for LDPC encoding may be determined in various ways based on TBS or CBS depending on the system. For example, it is possible to first determine a basic matrix through TBS, and determine an LDPC exponential matrix or a sequence parity check matrix based on the determined basic matrix and CBS, and various other methods may be applied.

The LDPC decoding process may also be represented as shown in FIG. 13 so as to correspond to the encoding process.

13 is a diagram illustrating an embodiment of an LDPC decoding process according to an embodiment of the present invention.

The receiver may receive a signal corresponding to an input bit or a transmission block or a code block. In the present invention, an input bit may mean an LDPC information word bit, or a TB, or a bit with a CRC added to the TB (TB + CRC), or a code block bit. In step 1310, the receiver determines the number of transmission blocks or input bits based on the signal. In step 1320, the receiver determines whether TBS is greater than max CBS. Here, since the max CBS may vary according to a basic matrix or a parity check matrix used for LDPC encoding, a process (not shown) of determining max CBS according to the TBS or code rate may be additionally required.

If the TBS is greater than max CBS, the receiver determines the size of the segmented CBS in step 1330. If TBS is determined to be less than or equal to max CBS, TBS is immediately determined to be the same as CBS.

In step 1340, the receiver determines a block size (Z) value to be applied to LDPC decoding. Steps 1310 to 1330 are steps of determining a block size and may be expressed as one step.

In step 1350, the receiver determines the LDPC parity check matrix or exponential matrix or sequence based on the TBS or CBS or the block size (Z) value or code rate. In step 1360, the receiver may perform LDPC decoding using the determined block size and parity check matrix, exponential matrix, or sequence. Meanwhile, the step 1350 may include a process of transforming the determined LDPC parity check matrix, exponential matrix, or sequence based on the determined block size in some cases. It is obvious that the LDPC index matrix or sequence or parity check matrix for LDPC decoding may be determined in various ways based on TBS or CBS depending on the system. For example, a basic matrix is first determined based on TBS or code rate, max CBS is determined (or set) based on the determined basic matrix, and CBS is determined based on the determined or set max CBS, and then the above Based on the determined CBS, it is possible to determine the block size Z and LDPC exponential matrix or sequence or parity check matrix, and various other methods can be applied.

According to the above embodiment, the process of determining the exponential matrix or sequence of the LDPC code in steps 1250 and 1350 of FIGS. 12 and 13 is when the exponential matrix or sequence is determined by one of TBS, CBS, or block size (Z). Has been described, but various other methods may be applied.

In an embodiment of the LDPC encoding and decoding process based on the basic matrix and the exponent matrix (or LDPC sequence) of the LDPC code of FIGS. 12 and 13, a part of the information word bit is appropriately shortened for the LDPC code. By puncturing and repeating a part of the codeword bits, LDPC encoding and decoding of various code rates and various lengths may be supported. For example, after applying a shortening to some of the information word bits in the basic matrix or exponential matrix determined for LDPC encoding and decoding in FIGS. 12 and 13, the information word bits corresponding to the first two column blocks in the parity check matrix or When a part of an input bit or a code block is punctured, a part of a parity is punctured, or a part of an LDPC codeword is repeated, various information word lengths (or code block lengths) and various code rates can be supported.

In addition, when a variable information word length or a variable code rate is supported by using shortening or zero padding of the LDPC code, performance of the code may be improved according to the shortening order or shortening method. If the shortening order is set in advance, coding performance can be improved by properly rearranging the order of part or all of the basic matrix. In addition, performance may be improved by appropriately determining the number of column blocks to which a block size or shortening is applied for a specific information word length (or code block length CBS).

In general, for LDPC codes, the code rate can be adjusted by applying puncturing to the codeword bits according to the code rate. When a parity bit corresponding to a column of order 1 is punctured, decoding complexity is reduced because the LDPC decoder can perform decoding without using a part or all of the corresponding part of the parity check matrix. In consideration of coding performance, there is a method for improving the performance of the LDPC code by adjusting the puncturing order of parity bits or the transmission order of the generated LDPC codewords. For example, rather than simply puncturing parity bits to support a variable code rate, better performance can be supported when part of the information word bits and parity bits are properly punctured. In addition, when repeating some LDPC codewords to support a lower code rate, the order of the LDPC codewords may be appropriately determined in advance to improve LDPC coding performance.

Typically, in the LDPC encoding process, the transmitter first determines the number (or size) of input bits (or code blocks) to which LDPC encoding is applied, and then determines the block size (Z) to which the LDPC encoding is applied according to the number. , After determining an appropriate LDPC exponential matrix or sequence according to the block size, LDPC encoding is performed based on the block size (Z) and the determined exponential matrix or LDPC sequence. In this case, the LDPC index matrix or sequence may be applied to LDPC encoding without transformation. In some cases, the LDPC index matrix or sequence may be appropriately transformed according to a block size (Z) to perform LDPC encoding.

Similarly, in the LDPC decoding process, the receiver determines the number (or size) of input bits (or code blocks) for the transmitted LDPC codeword, and then determines the block size (Z) to which LDPC decoding is applied according to the number. After determining an appropriate LDPC exponential matrix or sequence according to the block size, LDPC decoding is performed based on the block size (Z) and the determined exponential matrix or LDPC sequence. In this case, the LDPC exponent matrix or sequence may be applied to LDPC decoding without transformation. In some cases, the LDPC exponent matrix or sequence may be appropriately transformed according to the block size (Z) to perform LDPC decoding.

14 shows a general structure of a parity check matrix of an LDPC code, which is an inner code applied to an FEC encoder and an FEC decoder to be described in the present invention.

Referring to FIG. 14, in the parity check matrix, the number of columns is N and the number of rows is (M ₁ + M ₂ ). In general, when the parity check matrix has a full rank, the number of columns corresponding to information word bits in the parity check matrix is equal to the total number of columns minus the total number of rows. That is, if the parity check matrix of FIG. 13 has a perfect coefficient (M ₁ + M ₂ ), it means that the number of information word bits K is N-(M ₁ + M _{2 ).} In the present invention, for convenience, only the case where the parity check matrix of FIG. 14 has perfect coefficients is described, but it is not necessarily limited thereto.

First, the parity check matrix of FIG. 14 is the first part of parity-check matrix consisting of partial matrices A (1410) and B (1420), and submatrices C (1440) and D (1450). ) And E(1460). The submatrix O(1430) means a 0-matrix of size _{(M 1} Х M _{2 ).} Since the submatrix O 1430 is _{a 0-matrix of (M 1} Х M ₂ ), even if it is included in the first part of the parity check matrix, it does not affect the operation of the matrix. For this reason, in the present invention, for convenience, a matrix composed of partial matrices A(1410) and B(1420) excluding submatrix O(1430), which is a 0-matrix of size _{(M 1} Х M _{2 ), is used as the first part of the parity check matrix.} However, in some cases, the first part of the parity check matrix may include a partial matrix O 1430.

라 하고, 부분 행렬 B(1420) 또는 D(1450)에 대응되는 제1 패리티 비트들(또는 제1 패리티 비트 벡터)를

라 하고, 부분 행렬 E(1460)에 대응되는 제2 패리티 비트들(또는 제2 패리티 비트 벡터)를

라 하면, 수학식 1로부터 다음 수학식 20과 같은 관계식을 얻을 수 있다. The parity check matrix of FIG. 14 is referred to as H for convenience, and information word bits (or information word bit vectors) corresponding to the partial matrix A 1410 or C 1440 are

And first parity bits (or first parity bit vector) corresponding to the partial matrix B (1420) or D (1450)

And second parity bits (or second parity bit vector) corresponding to the partial matrix E 1460

Then, a relational expression such as the following equation (20) can be obtained from equation (1).

[Equation 20]

는 정보어 비트 벡터 i와 패리티 검사 행렬의 제1 파트에 기반하여 획득 (또는 계산 또는 결정)할 수 있다. 또한 상기 패리티 벡터

를 얻은 다음에 정보어 비트 벡터 i, 상기 패리티 벡터

그리고 패리티 검사 행렬 제2 파트에 기반하여 패리티 벡터

를 획득 (또는 계산 또는 결정)할 수 있다. Referring to Equation 20, a first parity vector

May be obtained (or calculated or determined) based on the information word bit vector i and the first part of the parity check matrix. Also the parity vector

After obtaining the information word bit vector i, the parity vector

And a parity vector based on the second part of the parity check matrix

Can be obtained (or calculated or determined).

,

,

는 각각 정보어 비트 벡터, 제1 패리티 벡터, 제2 패리티 벡터의 LDPC 복호 결과에 대한 경판정 결과 값을 의미한다.)As described above, the error probability for each bit of the LDPC code varies depending on the order. In particular, when the order is 2 or more, the bit error rate (BER, bit error rate, or bit error ratio) has a characteristic that sharply decreases compared to the bit with the order 1. In particular, when the information word bits are successfully decoded, codeword bits with degree 2 or more hardly cause an error, but codeword bits with order 1 (especially parity bits) will be transmitted even if the information word bits are successfully decoded. It may contain a large number of bit errors. For this reason, in the communication system to which LDPC encoding and decoding based on the parity check matrix of FIG. 14 is applied, a syndrome corresponding to the second part of the parity check matrix consisting of partial matrices C (1440), D (1450) and E (1460) Some of the values may not have a value of 0 with a very high probability regardless of whether an error occurs in the information word bit. That is, the first part (partial matrix O 1430 may also be included) and partial matrix C 1440 of the parity check matrix composed of partial matrices A 1410 and B 1420 of the parity check matrix of FIG. 14, The syndrome values determined based on the second part of the parity check matrix composed of D(1450) and E(1460) are respectively the first part of LDPC syndrome s ₁ and the second part of the syndrome (the Second part of LDPC syndrome) When s _{2 , the value of s 2} has a non-zero vector value with a very high probability, regardless of the decoding result, as shown in Equation 21 below. (In Equation 21

,

,

Denotes a hard decision result value for the LDPC decoding result of the information word bit vector, the first parity vector, and the second parity vector, respectively.)

[Equation 21]

As a result, although the overall LDPC syndrome may be used to determine the success or failure of the LDPC decoding of the first part rows or more of degree 2 in the parity check matrix as s ₁ and the order of the syndrome independently of the first parity bit Whether or not decoding is successful may be determined using a syndrome based on the partial matrix [A 1410 or B 1420] of rows or at least a portion thereof. (Even if the first part of the parity check matrix includes a 0-matrix such as partial matrix O(1430), the actual syndrome values are based on partial matrices A(1410) and B(1420) composed of columns of degree 2 or more. It is decided.)

A specific embodiment having the structure of the parity check matrix of FIG. 14 is shown in FIGS. 15 and 16.

15 and 16 are exemplary diagrams of a parity check matrix for an LDPC code proposed in the present invention.

Referring to FIG. 15, the matrix shown in FIG. 15 is _{an example in the case of K = 22*Z, M 1} = 4*Z, M ₂ = 7*Z in FIG. 14, and referring to FIG. 16, The matrix shown in FIG. 16 is _{an example in the case of K = 10 * Z, M 1} = 4 * Z, and M ₂ = 6 * Z in FIG. 14.

Here, Z denotes the block size defined in Equations 9 to 14, and since the parity check matrices of FIGS. 15 and 16 represent the exponential matrix of the quasi-cyclic parity check matrix, the cyclic permutation matrices of Equation 2 When expressed as an exponential matrix as shown in Equation 4, the size of the cyclic permutation matrices corresponds to _{In FIG. 14, a partial matrix consisting of M 2} columns with order 1 of the column corresponding to E (1460) can be regarded as a partial matrix corresponding to the parity of a single parity-check code, and can be easily extended ( extension) is possible. That is, portions corresponding to C (1440), D (1450) and E (1460) of FIG. 14 can be configured in a form of extending the parity check matrix of a single parity check code, and N = K + M ₁ + Since it is M _{2 , as M 2} increases, the codeword length N may also increase.

Since the code rate of the LDPC code corresponding to the parity check matrix of FIGS. 14, 15, and 16 is K/N, a codeword having a lower code rate may be generated as _{M 2 increases.} In other words, LDPC encoding and decoding may be performed based on a parity check matrix capable of supporting a lower code rate by further extending columns having a degree 1 including FIGS. 15 and 16.

The exponential matrix shown in FIGS. 15 and 16 can be expressed in various forms. For example, the exponential matrix may be expressed using a sequence as shown in Equations 22 to 23 below. Equations 22 and 23 represent each element of the 11x33-sized exponential matrix of FIG. 15 and the 10x20-sized exponent matrix of FIG. 16 for each row. In the exponential matrix, specific element values (eg -1) corresponding to the ZxZ-sized zero matrix can be excluded. For example, in Equation 22, the meaning of the fourth value 63 of the second sequence is the exponent value of the second cyclic permutation matrix (or bit cyclic) that does not correspond to the ZxZ-sized zero matrix in the second row of the exponent matrix of FIG. Shift value) is 63. (In the above example, the starting order of the elements in the sequence and matrix was considered to start from 0.)

[Equation 22]

250 69 226 159 100 10 59 229 110 191 9 195 23 190 35 239 31 1 0

2 239 117 124 71 222 104 173 220 102 109 132 142 155 255 28 0 0 0

106 111 185 63 117 93 229 177 95 39 142 225 225 245 205 251 117 0 0

121 89 84 20 150 131 243 136 86 246 219 211 240 76 244 144 12 1 0

157 102 0

205 236 194 231 28 123 115 0

183 22 28 67 244 11 157 211 0

220 44 159 31 167 104 0

112 4 7 211 102 164 109 241 90 0

103 182 109 21 142 14 61 216 0

98 149 167 160 49 58 0

[Equation 23]

9 117 204 26 189 205 0 0

167 166 253 125 226 156 224 252 0 0

81 114 44 52 240 1 0 0

8 58 158 104 209 54 18 128 0 0

179 214 71 0

231 41 194 159 103 0

155 228 45 28 158 0

129 147 140 3 116 0

142 94 230 0

203 205 61 247 0

The exponential matrix shown in FIGS. 15 and 16, that is, the basic matrix for the exponential matrix represented by Equation 22 and Equation 23, can also be expressed in various forms. As an example, a sequence such as Equation 24 and Equation 25 is used. You can also express it. Equation 24 shows the position of element 1 for each row in the basic matrix corresponding to the exponential matrix of FIGS. 15 and 22. Equation 25 shows the position of a column in which element 1 is located in the basic matrix corresponding to the exponential matrix of FIGS. 16 and 23 for each row. For example, in Equation 24, the meaning of the 3rd value 4 of the 2nd sequence means that the element 1 is in the 4th column of the 2nd row in the basic matrix. (In the above example, the starting order of the elements in the sequence and matrix was considered to start from 0.)

[Equation 24]

0: 0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23

1: 0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24

2: 0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25

3: 0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25

4: 0 1 26

5: 0 1 3 12 16 21 22 27

6: 0 6 10 11 13 17 18 20 28

7: 0 1 4 7 8 14 29

8: 0 1 3 12 16 19 21 22 24 30

9: 0 1 10 11 13 17 18 20 31

10: 1 2 4 7 8 14 32

[Equation 25]

0: 0 1 2 3 6 9 10 11

1: 0 3 4 5 6 7 8 9 11 12

2: 0 1 3 4 8 10 12 13

3: 1 2 4 5 6 7 8 9 10 13

4: 0 1 11 14

5: 0 1 5 7 11 15

6: 0 5 7 9 11 16

7: 1 5 7 11 13 17

8: 0 1 12 18

9: 1 8 10 11 19

In the LDPC encoding/decoding process using the parity check matrix shown in FIGS. 15 and 16 and Equations 22 to 25, various code block lengths and code rates may be supported by applying shortening and puncturing. In addition, in the case of an LDPC code, when a part of an information word bit (ie, a part of a code block) is properly punctured, error correction and error floor performance may be improved. For this reason, it is possible to improve LDPC encoding/decoding performance by always puncturing, modulating and transmitting a part of an information word bit or a part of a code block regardless of a code rate.

For example, as shown in FIG. 15(1506) or FIG. 16(1606), in the parity check matrix of the LDPC code, information word bits of size 2*Z corresponding to two column blocks or a part of the code block are code rate or allocated. Regardless of the size of the resource, a method of not transmitting to the receiving side by always puncturing may be considered.

The transmitter does not transmit the punctured bits, but the receiver can regard the bits that have been transmitted through a channel but lose information, that is, bits that have been erased. Since the receiver cannot substantially distinguish between the probability of 0 and 1 for the lost bits, it determines that the probability of 0 is 1/2 and the probability of 1 is 1/2. Accordingly, the receiver may determine that the lost bit (or punctured bit) is 1 when expressed as an LR value, and as 0 when expressed as an LLR value. In the present invention, for convenience of explanation, a case where the LLR value is used in the LDPC decoder is described, but may be expressed as different values according to the requirements of the LDPC decoder.

These punctured bits correspond to 0 as message values of the LDPC decoder, and can be processed differently by the LDPC decoder according to the order of the punctured LDPC codeword bits. For example, when LDPC encoding and decoding are performed using a parity check matrix corresponding to FIGS. 15 and 16 or Equations 22 to 25, when parity bits having a degree of 1 are punctured, the LLR values are set to 0. Decoding can be performed by setting, but in general, if parity bits with order 1 are punctured, the LLR values corresponding to the punctured bits will not be used in the decoding process because there is no effect of improving performance even if repetitive decoding is performed. May be. However, in some cases, for efficient parallel processing, the LLR values of parity bits of order 1 partially punctured may be set to 0 and used for decoding. For example, when the parallel processing unit of the LDPC decoder is Z, some parity bits having a punctured degree of 1 may be used so that the number of LLR values corresponding to bits used for LDPC decoding is a multiple of Z.

When performing LDPC encoding and decoding using a parity check matrix corresponding to FIGS. 15 and 16 or Equations 22 to 25, information word bits corresponding to two column blocks as shown in (1506) or (1606) Alternatively, features of the decoding process when a part of the code block is punctured are simply shown in FIGS. 17A and 17B.

17A and 17B are exemplary diagrams illustrating a case in which one or two punctured bits are connected to one inspection node, respectively.

17A is a diagram illustrating a Tanner graph corresponding to a first row block in the parity check matrix of FIGS. 15 and 16. In Fig. 17A, for convenience, eight variable nodes and one check node 1710 are shown. However, since the parity check matrices of Figs. 15 and 16 represent quasi-cyclic LDPC codes having a block size of Z, actually 8*Z number of nodes are shown. It can be easily extended to a case consisting of a variable node and Z check nodes.

If two or more variable nodes perforated as shown in (1701) and (1702) of FIG. 17A are connected to one test node, the LLR value corresponding to the variable node is set to 0, and these values are set to the variable node. Each connected line 1720 is transmitted to the test node 1710, respectively. In other words, in the case of applying the update equation based on the method described in Equations 15 and 16, the check node processor must have one or more cases in which the value diverges to infinity in the decoding operation process. The operation of becomes meaningless. Similarly, references Frank R. Kschischang, Brendan J. Frey, and Hans-Andrea Loeliger, "Factor Graphs and the Sum-Product Algorithm," IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 47, NO. 2, FEBRUARY 2001, pp498-519)”, tanh(0) = 0 in the update formula when the decoding update formula based on the product rule using the tanh(.) function is applied, so tanh(0) = One or more cases of 0 must occur, and thus the multiplication expression is always 0, and the LLR value is not updated even if decoding is performed on any variable node.

17B is a diagram illustrating a Tanner graph corresponding to a second row block in the parity check matrix of FIGS. 15 and 16. In FIG. 17B, for convenience, 10 variable nodes and one check node 1740 are shown. However, since the parity check matrices of FIGS. 15 and 16 represent quasi-cyclic LDPC codes having a block size of Z, in fact, 10 * Z It can be easily extended to a case consisting of a variable node and Z check nodes.

If only one variable node perforated as shown in (1731) of FIG. 17B is connected to one test node, the LLR value corresponding to the variable node is set to 0, and this value is set according to the line (1750). It is transmitted to the check node 1740. In other words, in the process of calculating the updated LLR value corresponding to the other lines except for the line 1750, the check node processor applies the update method based on Equation 15 and Equation 16. When LLR = 0, the operation value diverges to infinity, or when the decoding update formula based on the multiplication rule using the tanh(.) function is applied, since tanh(0) = 0, the multiplication expression becomes 0 and the ( 1731), LLR values are not updated for bits corresponding to variable nodes. However, in order to calculate the updated LLR corresponding to the line 1750, the LLR value for the bit corresponding to the variable node 1731 is 0 because it is updated based on values corresponding to lines excluding the line 1750. It can be updated to a value other than that

In the case of the punctured information word bit, the LLR value may or may not be restored immediately after layered decoding is performed on a specific layer or a specific row block according to the structure of the parity check matrix. Meanwhile, in the present invention, a layer may consist of at least one row block. In addition, layered decoding refers to an operation of sequentially performing decoding for each layer. Accordingly, decoding may be sequentially performed in units of one row block, or decoding may be performed by configuring a plurality of row blocks into one layer. Also, depending on the structure of one parity check matrix, some layers may be configured as one row block and other layers may be configured as a plurality of row blocks.

In general, row blocks having orthogonal or quasi-orhtogonal characteristics may be regarded as one layer. Here, when cyclic permutation matrices included in two or more row blocks are located in different column blocks, the row blocks are said to have orthogonal characteristics. In other words, when one row block is generated by adding row blocks with orthogonal characteristics in block units, a cyclic permutation matrix is not overlapped in each column block of the generated row block, and one cyclic permutation matrix Or 0-matrix. In addition, when defined in terms of a basic matrix, it means that there is no case where the weight 1 is duplicated and added when the rows corresponding to the row blocks having the orthogonal characteristic are added. For example, in FIG. 15, the sixth row block and the last tenth row block have orthogonal characteristics to each other. (The first row block was regarded as the 0th row block.)

In addition, the row blocks satisfying the quasi-orthogonal characteristic means a case in which the orthogonal characteristic is satisfied only for the remaining column blocks except for the column blocks at the same position in each row block. For example, in FIG. 15, the fifth row block and the sixth row block have quasi-orthogonal characteristics because all column blocks except for the 0-th column block satisfy orthogonal characteristics. In FIG. 16, the 7th row block and the 8th row block also have quasi-orthogonal characteristics because they satisfy the orthogonal characteristic for the remaining column blocks except for the 1st column block.

In general, for convenience of implementation, layered decoding is performed by setting one row block or a continuous or preset plurality of row blocks having an orthogonal characteristic or quasi-orthogonal characteristic as one layer, but having an orthogonal characteristic or a quasi-orthogonal characteristic Non-contiguous row blocks can also be set as one layer. When row blocks satisfying quasi-orthogonal characteristics are set as one layer, implementation complexity increases as the number of column blocks that do not satisfy quasi-orthogonal characteristics increases. Therefore, a layer can be set in consideration of the complexity allowed in the system. For this reason, row blocks that satisfy the orthogonal characteristic for the remaining column blocks except for one or two or less column blocks are typically set as one layer, but there is no need to be limited thereto. In addition, in order to reduce the wait time for a plurality of row blocks satisfying the orthogonal or quasi-orthogonal characteristic, a plurality of row blocks may be simultaneously processed, but sequentially or consecutively according to a predetermined order. It can also be handled successively.

The meaning of sequentially performing decoding for each layer means performing decoding for the first selected layer and then performing decoding for other layers, and the order of the layers for decoding may be changed. That is, a method of performing decoding on the fourth layer after decoding on the first layer and then decoding on the second layer is also possible. Meanwhile, in the following embodiments, for convenience of description, it is assumed that one row block constitutes one layer.

For example, in a communication system in which a part of an information word bit or a code block corresponding to the 0th and 1st column blocks is punctured for the parity check matrix corresponding to the exponential matrix of FIG. 15, the receiver performs the first layered decoding for LDPC decoding. Even if one of the 0, 2, 3, 4, 5, 7, 8, and 9th row blocks is selected and performed, or layered decoding is successively performed on the row blocks, each bit is not updated. Therefore, the first layered decoding or the continuous layered decoding has no effect.

On the other hand, if one of the 1st, 6th, and 10th row blocks is selected and the first layered decoding is performed, the punctured information word bit corresponding to the 0th or 1st column block or the LLR values corresponding to the code block are updated. After that, even if layered decoding is performed on any row block, LLR values are updated for at least some of the information word bits. In particular, if layered decoding is performed sequentially for the first row block and the tenth row block or the sixth row block and the tenth row block, the LLR values for the transmitted information word bits and parity bits are all meaningful values. Therefore, in the subsequent layered decoding process, it is performed as if all codeword bits were not punctured.

Applying decoding scheduling that can restore LLR values from the first layered decoding in consideration of the punctured information word bits or code blocks, has a very high code rate and the information throughput per time that the system wants to support. If) is high, this is an important issue. In general, when a system wants to transmit data corresponding to several hundred Mbps to several Gbps, not only the channel environment must be good, but also a high LDPC coding rate is applied, and the number of repetitive decoding performed by the receiver is not large. This is because the number of repetitive decoding is generally in inverse proportion to the amount of decoding information per time of the receiver, and thus, the smaller the number of repetitive decoding, the greater the amount of information throughput can be supported. In particular, when a very high throughput of decoding information per time is required, the number of repetitive decoding is often reduced. In this case, the first few invalid layered decoding processes may have a great influence on the reduction of the throughput of information per time. Accordingly, it is possible to increase decoding efficiency by appropriately setting the scheduling for layered decoding in consideration of the structure of the information word bits or code blocks punctured and the parity check matrix.

In order to set the scheduling for the layered decoder, it is important not only to quickly restore the LLR values corresponding to the information word bits or code blocks punctured by the receiver, but also to optimize the decoding performance in consideration of an appropriate order distribution. In general, since LDPC codes have an irregular order distribution, performance may vary depending on how layered decoding is performed on a row block having a certain order distribution.

In order to optimize the performance of layered decoding, the present invention proposes a method of determining the order of a layer to be decoded (or a row block when a layer is composed of one row block) and a specific embodiment thereof. To this end, various factors to be considered in order to determine the order of layers to be decoded are examined, and a specific method of setting appropriate decoding scheduling by combining these factors is proposed. In addition, in the present invention, for convenience of explanation, a specific embodiment is shown only when a quasi-cyclic LDPC code is used, but it is noted that it can be easily extended to a general LDPC code.

<Conditions for determining layered decoding scheduling>

Condition 1) When a part of the information word bit (or code block) is punctured and transmitted, the order or weight is 0 or 1 in a partial matrix consisting only of columns or column blocks corresponding to the punctured information word bit in the basic matrix. The initial decoding of the row block corresponding to the row is prioritized. If there is no information word perforation, condition 1) is ignored.

Condition 2) Prioritize decoding of row blocks for which theoretical decoding performance is maximized in consideration of order or weight distribution or modulation order or methods. In many cases, in the initial decoding process, the lower the order of the check node, that is, the row weight, the better the decoding performance can be. In addition, since the reliability or bit error rate of each bit constituting the modulation symbol is different according to the modulation method, an optimized scheduling method may vary according to the modulation method. For theoretical performance, various methods, such as density evolution analysis or EXIT chart analysis, can be applied.

Condition 3) A row block to be decoded is prioritized in consideration of a basic matrix or parity check matrix of an LDPC code that is substantially used in decoding or affects performance according to code rate or rate matching. That is, the order of layers to be decoded may be changed according to code rate or rate matching.

Condition 4) The row block to be decoded is prioritized in consideration of the basic matrix or parity check matrix of the LDPC code that is actually used depending on the TBS or CBS or affects the performance. That is, the order of layers to be decoded may be changed according to the TBS size.

Condition 1) is a condition for fast LLR restoration in consideration of a substantially limited number of repetitive decoding. In the present invention, for convenience of explanation, since it is assumed that encoding/decoding based on LDPC code having a parity check matrix having a structure of FIGS. 14 to 16 or an exponential matrix of Equations 22 to 25 or a basic matrix is assumed, in the condition 1), Only the perforation to the information word bit is described. In general, in the case of the LDPC code having the structure of FIGS. 14 to 16 or the exponential matrix or the basic matrix of Equations 22 to 25, the puncture of the parity part is variable and corresponds to the case where the parity of order 1 is punctured. This is because there is no problem even if decoding is performed by excluding the parity check matrix part from the decoding process. However, in general, condition 1 may be applied in consideration of both the information word bit as well as the parity bit puncture.

As a specific example of determining the order of layers to be decoded for layered decoding in consideration of condition 1), in FIG. 15, the row block to be decoded first may be determined as one of the 1st, 6th, or 10th row blocks, and , The remaining row blocks can also be used for initial decoding. (Note that the first row block is regarded as the 0th row block.) In the case of FIG. 16, decoding can be performed first on one of the first or third or sixth or seventh or ninth row blocks. In addition, the remaining row blocks can also be used for initial decoding.

In the case of condition 2), it is considered that sufficient repetitive decoding has been performed and the theoretical performance is maximized. In general, the higher the degree of the variable node and the lower the order of the test node, the greater the performance improvement effect. However, in general, since the order of the variable node and the order of the check node increase or decrease at the same time on average, the performance of the LDPC code greatly differs depending on how the order distribution of the LDPC code is set. Since the present invention assumes a layered decoding method, there is a possibility that the performance improvement effect is large to first decode a row block having a low order in the initial decoding process.

As a specific embodiment, in the case of the parity check matrix corresponding to FIGS. 15 and 16, the order or weight of the 0, 1, 2, and 3 rows is considerably larger than the order or weight of the fourth and subsequent rows from the perspective of the basic matrix. . Therefore, initial decoding performance may be better to perform decoding on a row block corresponding to a subsequent row including the fourth row of the basic matrix in the initial decoding. If considered together with condition 1), in FIG. 15, using the 6th row block or 10th row blocks for initial decoding may have a large performance improvement effect, and in FIG. 16, the 6th, 7th, or 9th row blocks are Using it for initial decoding can have a great effect on improving performance.

In the case of applying a higher-order modulation scheme such as 16-QAM, 64-QAM, 256-QAM, 1024-QAM, ..., each bit constituting a modulation symbol has different reliability. For example, the most significant bits (MSBs) in each modulation symbol typically have a low bit error rate, that is, high reliability, and the least significant bits (LSBs) typically have a high bit error rate, that is, low reliability. Therefore, depending on how the LDPC codeword bits to be transmitted are mapped to the modulation symbols, there may be a large difference in LDPC decoding performance. When a rule mapped to a modulation symbol is determined in advance, the order of layers to be initially decoded may be changed in order to maximize performance according to a modulation method (or order) and the mapping rule.

In a communication system that applies appropriate rate matching to support variable code rates, since the partial matrix of the parity check matrix corresponding to the rate matching substantially affects performance, the condition 3) is added to reflect this characteristic. I did. For example, if the LDPC encoding/decoding system supports a very high code rate close to 1 by using the exponential matrix of FIGS. 15 and 16 or the parity check matrix corresponding to the exponential matrix and the basic matrix of Equations 22 to 25, 15 and 16, in partial matrices 1502 and 1602 corresponding to parity bits, some of the parity bits corresponding to the last two column blocks may be punctured through rate matching. If a situation in which parity bits corresponding to the first two column blocks in the partial matrices 1502 and 1602 are punctured, it means a case where the code rate is greater than 1, so if it is not a special situation occurring in the system, In the partial matrices 1502 and 1602, parity bits corresponding to the first two column blocks are not punctured. In this case, an invalid decoding process can be minimized only when initial decoding is performed on the first row block.

On the other hand, if a code rate of 22/27 for FIG. 15 or a code rate of 10/15 for FIG. 16 is supported, parity bits corresponding to the 6th row block are transmitted. When initial decoding is preferentially applied to the sixth row block, the best encoding/decoding performance can be supported.

If the code rate supported by the system is not significantly variable, and the code rate is determined to be different from the above examples, since the optimal decoding scheduling order is determined for the given parity check matrix, the first row block, 6 Performance may be optimized only when initial decoding is performed on a th row block and another row block.

In this way, the size and range of the partial matrix that affects the performance in the parity check matrix varies according to the code rate, so if one fixed layered decoding scheduling method is applied, it is easy to implement, but performance may be slightly lost. . Therefore, when implementation is possible, coding/decoding performance is improved when variable decoding scheduling is applied based on all or part of a supported maximum code rate, a minimum code rate, or an actual supported code rate.

For reference, the code rate used in condition 3) may use an effective code rate in which the number of information word bits or the code block size is divided by the number of transmitted bits, and system information related to MCS or channel quality indicator (CQI) ( For example, a code rate defined from an MCS index or a CQI index) may be used. While the effective code rate has the advantage of defining a scheduling sequence or pattern that enables more accurate performance prediction, an additional process of calculating the effective code rate may be required. In the case of using the code rate defined in the MCS or CQI, an additional operation may not be required, but since it may be different from the code rate optimized for a predetermined scheduling order or pattern, there is a possibility that some performance deterioration may occur.

The condition 4) may be applied when the basic matrix or parity check matrix of the LDPC code that is substantially used for decoding or affecting performance according to the TBS or CBS is different. In fact, according to the 3GPP 5G standard TS 38.212 document, when a code block (or information word bit) is mapped from a parity check matrix to a partial matrix corresponding to an information word, the range is set differently according to the CBS. For example, when coding is performed based on the second basic matrix BG2 defined in TS 38.212 (in TS 38.212, the basic matrix is expressed as a basic graph), when CBS or TBS length is greater than 640, K _b = 10 If it is less than 640 or less than 560, select K _b = 9 column blocks, if less than 560 and more than 192, K _b = 8 column blocks, and if less than 192 _{, select K b} = 6 column blocks, and then the above Coding is performed based on K _{b column blocks.} Accordingly, in the partial matrix of the parity check matrix corresponding to the information word bit or the code block, _{the remaining column blocks except for the K b} column blocks may not be used in the encoding process. In this way, not using a part of the given parity check matrix in the coding process is the same as shortening, which means that the order distribution that affects the actual performance is changed. Therefore, as mentioned in the above condition 2), since the theoretical performance of the LDPC code may be greatly affected, the optimal scheduling order or pattern may vary according to the TBS or CBS length.

Hereinafter, a specific embodiment of an efficient decoding scheduling method applicable to a receiver is proposed by simultaneously considering the four conditions presented in <Conditions for Determining Layered Decoding Scheduling>, or at the same time. For convenience of explanation, in a system using a parity check matrix corresponding to a basic matrix such as Equation 26 and Equation 27 below, information word bits or a part of a code block corresponding to the first column block and the first column block are Suppose you are perforating. However, the contents of the present invention may also be applied to an embodiment in which a part of an information word bit or a code block corresponding to a second or subsequent column block is punctured. In addition, the block size is expressed as Z, and the basic matrix of Equation 26 is expressed as BM1, and the basic matrix of Equation 27 is expressed as BM2.

[Equation 26]

0: 0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23

1: 0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24

2: 0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25

3: 0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25

4: 0 1 26

5: 0 1 3 12 16 21 22 27

6: 0 6 10 11 13 17 18 20 28

7: 0 1 4 7 8 14 29

8: 0 1 3 12 16 19 21 22 24 30

9: 0 1 10 11 13 17 18 20 31

10: 1 2 4 7 8 14 32

11: 0 1 12 16 21 22 23 33

12: 0 1 10 11 13 18 34

13: 0 3 7 20 23 35

14: 0 12 15 16 17 21 36

15: 0 1 10 13 18 25 37

16: 1 3 11 20 22 38

17: 0 14 16 17 21 39

18: 1 12 13 18 19 40

19: 0 1 7 8 10 41

20: 0 3 9 11 22 42

21: 1 5 16 20 21 43

22: 0 12 13 17 44

23: 1 2 10 18 45

24: 0 3 4 11 22 46

25:1 6 7 14 47

26: 0 2 4 15 48

27: 1 6 8 49

28: 0 4 19 21 50

29: 1 14 18 25 51

30: 0 10 13 24 52

31: 1 7 22 25 53

32: 0 12 14 24 54

33: 1 2 11 21 55

34: 0 7 15 17 56

35: 1 6 12 22 57

36: 0 14 15 18 58

37: 1 13 23 59

38: 0 9 10 12 60

39: 1 3 7 19 61

40: 0 8 17 62

41: 1 3 9 18 63

42: 0 4 24 64

43: 1 16 18 25 65

44: 0 7 9 22 66

45: 1 6 10 67

[Equation 27]

0: 0 1 2 3 6 9 10 11

1: 0 3 4 5 6 7 8 9 11 12

2: 0 1 3 4 8 10 12 13

3: 1 2 4 5 6 7 8 9 10 13

4: 0 1 11 14

5: 0 1 5 7 11 15

6: 0 5 7 9 11 16

7: 1 5 7 11 13 17

8: 0 1 12 18

9: 1 8 10 11 19

10: 0 1 6 7 20

11: 0 7 9 13 21

12: 1 3 11 22

13: 0 1 8 13 23

14: 1 6 11 13 24

15: 0 10 11 25

16: 1 9 11 12 26

17: 1 5 11 12 27

18: 0 6 7 28

19: 0 1 10 29

20: 1 4 11 30

21: 0 8 13 31

22: 1 2 32

23: 0 3 5 33

24: 1 2 9 34

25: 0 5 35

26: 2 7 12 13 36

27: 0 6 37

28: 1 2 5 38

29: 0 4 39

30: 2 5 7 9 40

31: 1 13 41

32: 0 5 12 42

33: 2 7 10 43

34: 0 12 13 44

35: 1 5 11 45

36: 0 2 7 46

37: 10 13 47

38: 1 5 11 48

39: 0 7 12 49

40: 2 10 13 50

41: 1 5 11 51

For reference, the receiver determines the block size shown in Equation 11 or 12, and performs decoding based on the block size, the basic matrix BM1 of [Equation 26], and a sequence (or exponential matrix) such as Equation 28 below. It is possible to determine a parity check matrix of the LDPC code required for this. Similarly, the receiver determines the block size shown in Equation 11 or 12, and performs decoding based on the block size, the basic matrix BM2 of [Equation 27], and a sequence (or exponential matrix) as shown in Equation 29 below. It is possible to determine the parity check matrix of the LDPC code required for this. In this case, the method of Equations 8 to 10 may be applied to the process of determining the parity check matrix.

[Equation 28]

0: 250, 69, 226, 159, 100, 10, 59, 229, 110, 191, 9, 195, 23, 190, 35, 239, 31, 1, 0,

1: 2, 239, 117, 124, 71, 222, 104, 173, 220, 102, 109, 132, 142, 155, 255, 28, 0, 0, 0,

2: 106, 111, 185, 63, 117, 93, 229, 177, 95, 39, 142, 225, 225, 245, 205, 251, 117, 0, 0,

3: 121, 89, 84, 20, 150, 131, 243, 136, 86, 246, 219, 211, 240, 76, 244, 144, 12, 1, 0,

4: 157, 102, 0,

5: 205, 236, 194, 231, 28, 123, 115, 0,

6: 183, 22, 28, 67, 244, 11, 157, 211, 0,

7: 220, 44, 159, 31, 167, 104, 0,

8: 112, 4, 7, 211, 102, 164, 109, 241, 90, 0,

9: 103, 182, 109, 21, 142, 14, 61, 216, 0,

10: 98, 149, 167, 160, 49, 58, 0,

11: 77, 41, 83, 182, 78, 252, 22, 0,

12: 160, 42, 21, 32, 234, 7, 0,

13: 177, 248, 151, 185, 62, 0,

14: 206, 55, 206, 127, 16, 229, 0,

15: 40, 96, 65, 63, 75, 179, 0,

16: 64, 49, 49, 51, 154, 0,

17: 7, 164, 59, 1, 144, 0,

18: 42, 233, 8, 155, 147, 0,

19: 60, 73, 72, 127, 224, 0,

20: 151, 186, 217, 47, 160, 0,

21: 249, 121, 109, 131, 171, 0,

22: 64, 142, 188, 158, 0,

23: 156, 147, 170, 152, 0,

24: 112, 86, 236, 116, 222, 0,

25: 23, 136, 116, 182, 0,

26: 195, 243, 215, 61, 0,

27: 25, 104, 194, 0,

28: 128, 165, 181, 63, 0,

29: 86, 236, 84, 6, 0,

30: 216, 73, 120, 9, 0,

31: 95, 177, 172, 61, 0,

32: 221, 112, 199, 121, 0,

33: 2, 187, 41, 211, 0,

34: 127, 167, 164, 159, 0,

35: 161, 197, 207, 103, 0,

36: 37, 105, 51, 120, 0,

37: 198, 220, 122, 0,

38: 167, 151, 157, 163, 0,

39: 173, 139, 149, 0, 0,

40: 157, 137, 149, 0,

41: 167, 173, 139, 151, 0,

42: 149, 157, 137, 0,

43: 151, 163, 173, 139, 0,

44: 139, 157, 163, 173, 0,

45: 149, 151, 167, 0

[Equation 29]

0: 9, 117, 204, 26, 189, 205, 0, 0,

1: 167, 166, 253, 125, 226, 156, 224, 252, 0, 0,

2: 81, 114, 44, 52, 240, 1, 0, 0,

3: 8, 58, 158, 104, 209, 54, 18, 128, 0, 0,

4: 179, 214, 71, 0,

5: 231, 41, 194, 159, 103, 0,

6: 155, 228, 45, 28, 158, 0,

7: 129, 147, 140, 3, 116, 0,

8: 142, 94, 230, 0,

9: 203, 205, 61, 247, 0,

10: 11, 185, 0, 117, 0,

11: 11, 236, 210, 56, 0,

12: 63, 111, 14, 0,

13: 83, 2, 38, 222, 0,

14: 115, 145, 3, 232, 0,

15: 51, 175, 213, 0,

16: 203, 142, 8, 242, 0,

17: 254, 124, 114, 64, 0,

18: 220, 194, 50, 0,

19: 87, 20, 185, 0,

20: 26, 105, 29, 0,

21: 76, 42, 210, 0,

22: 222, 63, 0,

23: 23, 235, 238, 0,

24: 46, 139, 8, 0,

25: 228, 156, 0,

26: 29, 143, 160, 122, 0,

27: 8, 151, 0,

28: 98, 101, 135, 0,

29: 18, 28, 0,

30: 71, 240, 9, 84, 0,

31: 106, 1, 0,

32: 242, 44, 166, 0,

33: 132, 164, 235, 0,

34: 147, 85, 36, 0,

35: 57, 40, 63, 0,

36: 140, 38, 154, 0,

37: 219, 151, 0,

38: 31, 66, 38, 0,

39: 239, 172, 34, 0,

40: 0, 75, 120, 0,

41: 129, 229, 118, 0

Example 1

According to the first embodiment, a row block that is always used for decoding in a parity check matrix may be determined regardless of a code rate in consideration of the maximum code rate Rmax substantially supported by the system. The supportable maximum code rate Rmax is a structural characteristic of the parity check matrix of the LDPC code when it is assumed that codeword bits transmitted after all rate matching are normally received under the assumption that there is no retransmission, and may mean the maximum code rate that can be decoded by itself. In addition, such as code rate 1, it may mean a simple maximum code rate theoretically possible regardless of the parity check matrix of the LDPC code.

LLR from when the first layered decoding is applied while satisfying condition 1) of <Condition for determining layered decoding scheduling> even when parity puncture occurs in consideration of the maximum code rate Rmax among the row blocks always used for decoding. Select a block of rows whose values can be restored. In this case, the row block in which the LLR value can be restored may mean a row block of degree 1 (ie, there is only one cyclic permutation matrix) in the partial matrix corresponding to the column block to be punctured, as described above.

For example, when Rmax is close to 1, the first row block in BM1 or BM2 can always be LLR updated, so the first row block may be selected as the first row block of the layered decoding order or pattern. . For example, when the decoding order or pattern is composed of the indexes of the row blocks according to the order of the row blocks performing decoding, the first number of the decoding order or pattern may be 1. If layered decoding is sequentially performed on other row blocks after layered decoding of the first row block, the layered decoding order or pattern is [1, 0, 2, 3, 4, ... 45], BM2 for BM1. For can be expressed in the form [1, 0, 2, 3, 4, ..., 41].

As described above, if the layered decoding order or pattern is fixed, the basic matrix of Equations 26 and 27, or the order of the row blocks of the exponent matrix or parity check matrix corresponding thereto, is changed and stored, and then layered decoding may be performed. have. For example, in Equation 26, the first two row blocks of BM1, that is, the 0-th row block and the first row block, may be swapped and stored as follows, and then layered decoding may be sequentially performed.

0: 0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24

1: 0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23

Similarly, for BM2, the 0th row block and the 1st row block may be swapped and stored as follows, and then layered decoding may be sequentially performed.

0: 0 1 2 3 6 9 10 11

1: 0 3 4 5 6 7 8 9 11 12

Meanwhile, in the first embodiment, an example of decoding a first row block with priority has been described, but the embodiment of the present invention is not limited thereto. That is, it is obvious that an arbitrary row block or a row block satisfying a predetermined criterion among row blocks having a degree of 1 in the partial matrix corresponding to the column block to be punctured may be decoded with priority.

In addition, the layered decoding may be decoded based on a layer corresponding to the row block to be decoded with priority. In this case, the layer may preferentially include a row block to be decoded and a row block having orthogonality or quasi-orthogonality among row blocks adjacent to the row block.

Example 2

Similar to the first embodiment, the first row block is set as the row block to be decoded.

After performing layered decoding on the first row block to improve performance by reflecting the characteristics of condition 2) of <Conditions for determining layered decoding scheduling>, the remaining row blocks are in reverse order. Decoding can be performed.

To this end, after performing a desegmentation process including a process of determining a TBS or CBS value, a process of determining which of the basic matrices BM1 and BM2 is used, and a process of determining a block size (Z), the determined value and It is possible to determine the codeword bit Er transmitted after rate matching for the r-th code block in consideration of the allocated resource and the modulation method. However, in the 3GPP 5G communication system, when transmission is required when the number of ACK or NACK bits, which is an acknowledgment signal, is 1 or 2, some of the CSI-part2 and/or (and/or) UL-SCH (data) are punctured. Because the same effect may occur, some of the Er bits may not be actually transmitted, but the receiver considers that the corresponding transmission codeword bits are also transmitted, but the codeword bits at the corresponding position are set to LLR = 0 and processed as punctured bits can do. In other words, the transmitted codeword bit Er value may mean a bit physically actually transmitted by the transmitter, but may mean a codeword bit size that can be determined to have been transmitted by the receiver in some cases.

를 수학식 30과 같이 구할 수 있다. If the number of transmitted codeword bits Er is checked, the number of row blocks of the parity check matrix that is valid (or actually affects performance) in the encoding/decoding process or the number of rows of the basic matrix

Can be obtained as in Equation 30.

[Equation 30]

Here, K _b is the number of column blocks actually used while corresponding to the information word bits in the parity check matrix for LDPC encoding of the given code block in the basic matrix, and K _punc is the information word bits or puncturing among the code blocks. It means the number of column blocks corresponding to the bits.

이 된다. 즉, 패리티 검사 행렬에서 총 10개의 행 블록이 실질적으로 LDPC 부호화/복호화 성능에 영향을 준다. As a specific example, if referring to 3GPP standard document TS 38.212, it is assumed that the input bit (TB + CRC) is 5632 bits, the code rate according to the MCS index is greater than 2/3, and Er = 7632. In this condition, BM1 is determined as a basic matrix for LDPC encoding, and the block size is also determined as Z = 5632/22 = 256. In the case of the 3GPP standard TS 38.212, K _punc = 2 is fixed, and when BM1 is used, K _b is always 22.

Becomes. That is, a total of 10 row blocks in the parity check matrix substantially affect the LDPC encoding/decoding performance.

이 된다. 즉, 패리티 검사 행렬에서 총 21개의 행 블록이 실질적으로 LDPC 부호화/복호화 성능에 영향을 준다. 참고로 상기 3GPP 표준 규격 TS 38.212에 따르면, TBS 및 부호율에 따라 사용할 기본 행렬이 결정되며, 특히 기본 행렬 BM2가 사용될 경우에는 입력 비트의 수에 따라 K_b 값이 결정되기 때문에 (K_b - K_punc) 값 또한 입력 비트의 수에 따라 결정 될 수 있다. 예를 들어, 입력 비트 수가 640 보다 큰 경우에는 K_b = 10이므로, (K_b - K_punc) = 8이 되며, 입력 비트 수가 560 보다 크며 640 보다 작거나 같은 경우에는 K_b = 9이므로, (K_b - K_punc) = 7이 되며, 입력 비트 수가 192 보다 크며 560 보다 작거나 같은 경우에는 K_b = 8이므로, (K_b - K_punc) = 6이 되며, 그 이외의 경우에는(otherwise) K_b = 6이므로, (K_b - K_punc) = 4가 된다. 따라서 사용될 행 블록의 개수는 TBS 및 부호율에 따라 다른 값을 이용해 결정해야 한다. As another specific example, if referring to 3GPP standard document TS 38.212, it is assumed that the input bit (TB + CRC) is 3840 bits, the code rate according to the MCS index is less than 2/3, and Er = 11072. In this condition, BM2 is determined as a basic matrix for LDPC encoding, and it is determined that the block size is Z = 384. In the case of the 3GPP standard TS 38.212, K _punc = 2 is fixed, and in the case of 3840, the number of input bits is K _b = 10.

Becomes. That is, a total of 21 row blocks in the parity check matrix substantially affect the LDPC encoding/decoding performance. For reference, according to the 3GPP standard TS 38.212, the basic matrix to be used is determined according to the TBS and the code rate. In particular, when the basic matrix BM2 is used, the value of _{K b is determined according to the number of input bits (K b} -K _punc ) value can also be determined according to the number of input bits. For example, if the number of input bits is greater than 640, K _b = 10, so (K _b -K _punc ) = 8, and if the number of input bits is greater than 560 and less than or equal to 640 _{, since K b} = 9, ( K _b -K _punc ) = 7, and if the number of input bits is greater than 192 and less than or equal to 560, then K _b = 8, so (K _b -K _punc ) = 6, otherwise (otherwise) Since K _b = 6, (K _b -K _punc ) = 4. Therefore, the number of row blocks to be used must be determined using different values depending on the TBS and the code rate.

,

, ..., 3, 2, 0]과 같이 나타낼 수 있다. As a result, when layered decoding is first performed for the first row block and decoding is performed in reverse order for the remaining row blocks, the layered scheduling order or pattern is [1,

,

, ..., 3, 2, 0].

번째 행 블록의 일부에 대응되는 패리티 비트들이 천공된 경우에는 상기 천공된 패리티 비트들과 태너 그래프 상에서 연결되어 있는 정보어 비트들을 레이어드 디코딩이 처음 적용되었을 때 즉시 복호가 되지는 않는다. 따라서 경우에 따라서 상기 순서 또는 패턴은 [1,

,

,

, ... 3, 2, 0]과 같이 다소 변형된 형태로 적용될 수도 있다. In some cases, the last Er value is not a multiple of the block size Z value.

When parity bits corresponding to a part of the th row block are punctured, the punctured parity bits and information word bits connected on the Tanner graph are not immediately decoded when layered decoding is first applied. Therefore, in some cases, the sequence or pattern is [1,

,

,

, ... 3, 2, 0].

In the present invention, a general definition of reverse-order layered decoding is to prioritize at least one of "row blocks or layers corresponding to parity bits of order 1", first apply layered decoding, and reverse order to the remaining row blocks or layers. It means performing decryption with each other. If there is no parity bit of order 1, this means that decoding is performed in reverse order from the last row block or layer of the parity check matrix. Meanwhile, in the case of an LDPC system using basic matrices such as BM1 of Equation 26 and BM2 of Equation 27, the order or pattern modified as follows by additionally considering <Condition for determining layered decoding scheduling> Condition 1). Can be applied.

개의 행 블록들], ..., 3, 2, 0][1, [corresponding to parity bit of order 1

Row blocks], ..., 3, 2, 0]

개의 행 블록들], 0, 2, 3] 또는 [1, 0, [차수가 1인 패리티 비트에 대응되는

개의 행 블록들], 2, 3] 또는 [1, 0, 2, [차수가 1인 패리티 비트에 대응되는

개의 행 블록들], 3] 또는 [1, 0, 2, 3, [차수가 1인 패리티 비트에 대응되는

개의 행 블록들]].When applying reverse-order layered decoding, the decoding order or pattern may be determined in advance for some specific row blocks. For example, in a communication system based on the basic matrix of Equation 26 or 27, if the decoding order of the parity bits corresponding to a column block of order other than 1 is defined in advance according to a requirement condition, the reverse order pattern Can be modified in various ways. More specifically, when the order of the first four row blocks in the basic matrix of Equations 26 and 27 is always set to satisfy the order of [1, 0, 2, 3], the reverse order pattern is It can be transformed as follows: [1, [corresponding to parity bit of degree 1

Row blocks], 0, 2, 3] or [1, 0, [order 1 parity bit corresponding to

Row blocks], 2, 3] or [1, 0, 2, [order 1 parity bit corresponding to

Row blocks], 3] or [1, 0, 2, 3, [corresponding to parity bits of order 1]

Blocks of rows]].

Meanwhile, in the first embodiment, an example of decoding a first row block with priority has been described, but the embodiment of the present invention is not limited thereto. In other words, it is obvious that in the partial matrix corresponding to the column block to be punctured, an arbitrary row block or a row block satisfying a predetermined criterion among row blocks having a degree of 1 can be decoded with priority.

In addition, the layered decoding may be decoded based on a layer corresponding to the row block to be decoded with priority. In this case, the layer may preferentially include a row block to be decoded and a row block having orthogonality or quasi-orthogonality among row blocks adjacent to the row block.

Example 3

After performing the desegmentation process including the process of determining the TBS or CBS value, the process of determining which of the basic matrices BM1, BM2 is used, and the process of determining the block size (Z), When BM1 is determined as the basic matrix, when the code rate R is larger (or greater than or equal to) than the _{reference code rate R BM(1) , the first row block to be decoded is X BM(1)} -th row block Can be set. If BM2 is determined, if the code rate R is larger (or greater than or equal to) than the _{reference code rate R BM(2) , the X BM(2)} th row block can be set as the first row block to be decoded. have. Here, R _BM(1) and R _BM(2) may have the same value or different values. (For convenience, the basic matrices BM1 and BM2 are also denoted BM(i), i=1, 2.)

When BM1 is used for LDPC encoding/decoding, when the code rate R is _{smaller than or equal to (or smaller than) the reference code rate R BM(1)} , conditions 1) and conditions of <Conditions for determining layered decoding scheduling> Considering 2) at the same time, _{it is possible to set the Y BM(1)} th row block as the row block to be decoded first. Likewise, when BM2 is used for LDPC encoding/decoding, when the code rate R is smaller than or equal to (or smaller than _{) the reference code rate R BM(2) , the Y BM (2)} th row block is the first to be decoded. Row blocks can be set.

In this way, the position of the first layered decoding start row block can be variably applied according to the code rate, and in summary, the layered decoding order or pattern can be defined as follows:

i) in case R> R _BM(i) (or _{R> R BM(i)} ); [X _BM(i) , ...],

ii) in case R≦R _BM(i) (or R<R _BM(i) ); [Y _BM(i) , ...].

At this time, the values of X _BM(1) , X _BM(2) , Y _BM(1) and Y _BM(2) are the row blocks with weight or degree 1 in the 0th and 1st column blocks to which the perforation is applied. It can be determined by any one of them. _{For example, Y BM(1)} selected when the code rate R is smaller than the reference code rate is the order or weight of the entire row block compared to _{X BM(1)} among the row blocks with degree 1 in the corresponding column block. Can be determined by the index of the small row block. However, the embodiment of the present invention is not limited thereto, and Y _{BM(1) selected when the code rate R is smaller than the reference code rate is X BM(1)} among the row blocks of degree 1 in the corresponding column block. Compared to, it may be determined by the order of the entire row block or the index of the row block having a larger weight. The _{method of determining Y BM(1)} and X _BM(1) may be predetermined or may be set in the receiver. In this case, the method may be determined in consideration of the stability and efficiency of decoding.

을 그 기준 부호율 R_BM(1)으로 정의하고, 만일 R > 22/27을 만족하면, 레이어드 디코딩 순서 또는 패턴을 [1, ...]과 같이 정의하고, 그렇지 않은 경우에는 [6, ...]과 같은 순서 또는 패턴을 적용할 수 있다. (상기 순서 또는 패턴 [1, ...], [6, ...] 등은 첫 번째 행 블록 이후에 대한 패턴에 대해 역순서 패턴과 같은 다른 패턴이 적용될 수도 있다.)As a specific embodiment, referring to the exponential matrix of FIG. 15 or the basic matrix of Equation 24 corresponding thereto, or the basic matrix of Equation 26 including Equation 24, information word bit (or code block) puncturing is always applied. Row blocks with weight 1 in the 0th and 1st column blocks are the 1st and 6th row blocks. Therefore, the Er value that all 7 row blocks are not used or the code rate corresponding to it

Is defined as the reference code rate R _BM(1) , and if R> 22/27 is satisfied, the layered decoding order or pattern is defined as [1, ...]. Otherwise, [6,. The same sequence or pattern as [..] can be applied. (For the above order or patterns [1, ...], [6, ...], other patterns such as reverse order patterns may be applied to patterns after the first row block.)

을 그 기준 부호율 R_BM(2)로 정의하고, 만일 R > 10/15를 만족하면, 레이어드 디코딩 순서 또는 패턴을 [1, ...]과 같이 정의하고, 그렇지 않은 경우에는 [6, ...]과 같은 순서 또는 패턴을 적용할 수 있다. As a specific embodiment, referring to the exponential matrix of FIG. 16 or the basic matrix of Equation 25 corresponding thereto, or the basic matrix of Equation 27 including Equation 25, information word bit (or code block) puncturing is always applied. Row blocks with weight 1 in the 0th and 1st column blocks are the 1st and 6th row blocks. Therefore, the Er value that all 7 row blocks are not used or the maximum value of the corresponding code rate

Is defined as the reference code rate R _BM(2) , and if R> 10/15 is satisfied, the layered decoding order or pattern is defined as [1, ...]; otherwise, [6,. The same sequence or pattern as [..] can be applied.

In the order or patterns of the specific embodiments, various patterns such as the reverse order pattern described in Embodiment 2) may be applied as the order or pattern after the first row block as follows.

in case R> R _BM(i) (or _{R> R BM(i)} );

,

, ..., (X_BM(i) + 1), (X_BM(i) - 1), ...],[X _BM(i) ,

,

, ..., (X _BM(i) + 1), (X _BM(i) -1), ...],

in case R < R _BM(i) (or R &lt _{; R BM(i)} );

,

, ..., (Y_BM(i) + 1), (Y_BM(i) - 1) ...],[Y _BM(i) ,

,

, ..., (Y _BM(i) + 1), (Y _BM(i) -1) ...],

값이 7인 경우에 [1, 6, 5, 4, 3, 2, 0]과 같은 디코딩 순서 또는 패턴이 적용될 수 있으며, R ≤ 22/27인 경우에는 [6, 5, 4, 3, 2,1, 0]과 같은 디코딩 순서 또는 패턴이 적용될 수 있다. 일반적으로

이 8인 경우에는 [6, 7, 5, 4, 3, 2, 1, 0]이며, 8 보다 큰 경우에는 [6,

,

, ..., 7,5,4,3,2,1,0]과 같이 적용될 수 있다. When describing a specific example for BM1 in Equation 26, if R> 22/27,

When the value is 7, a decoding order or pattern such as [1, 6, 5, 4, 3, 2, 0] can be applied, and when R ≤ 22/27, [6, 5, 4, 3, 2 ,1, 0] may be applied in a decoding order or pattern. Generally

If this is 8, it is [6, 7, 5, 4, 3, 2, 1, 0], and if it is greater than 8, it is [6,

,

, ..., 7,5,4,3,2,1,0].

In the present embodiment, for convenience of explanation, the case where the reference code rate is 1 has been described, but the reference code rate can be set to a plurality, and the layered decoding order or pattern may be set differently accordingly. (Not all need to be different, but at least two different sequences or patterns can be defined.)

나 Er 값 등을 기준으로 설정할 수도 있다. BM(i)에 대해서 행 블록의 개수에 대한 기준

등과 같은 기준 값을을 정하고,

의 값과 비교하여 순서 또는 패턴을 가변 적용할 수 있다. In the present embodiment, a case in which the code rate is set as the criterion for changing the layered decoding order or pattern, but it is not necessarily limited thereto. For example, as in Example 2, the number of row blocks actually used in the basic matrix or the parity check matrix

Or it can be set based on the value of Er. Criteria for the number of row blocks for BM(i)

Set a reference value such as,

The order or pattern can be variably applied by comparing with the value of.

가 가변일 경우에는 LDPC 부호화 및 복호화를 위해 패리티 검사 행렬에서 실제로 사용되는 부분 행렬이 다르게 되므로, 성능이 최적화된 레이어드 디코딩 순서 또는 패턴이 다를 수 있으며, 따라서 TBS 또는 CBS에 따라 서로 다른 레이어드 디코딩 순서 또는 패턴을 적용할 수 있다. 또한 TBS에 따라

값이 다르게 정의되는 경우에는 본 실시예에서 제시한 기준 부호율이 TBS에 따라 변경될 수도 있으며, 사전에 정의된 특정 값을 기준 부호율로 정의할 수도 있다.The number of column blocks actually used among the partial matrices corresponding to the information word part in the parity check matrix according to TBS or CBS, as in the case of using BM2 for LDPC encoding in 3GPP 5G standard

When is variable, since the partial matrix actually used in the parity check matrix for LDPC encoding and decoding is different, the layered decoding order or pattern optimized for performance may be different. Patterns can be applied. Also according to TBS

If the value is defined differently, the reference code rate suggested in the present embodiment may be changed according to the TBS, and a specific value defined in advance may be defined as the reference code rate.

In addition, the layered decoding may be decoded based on a layer corresponding to the row block to be decoded with priority. In this case, the layer may preferentially include a row block to be decoded and a row block having orthogonality or quasi-orthogonality among row blocks adjacent to the row block.

Example 4

A row block having a weight of 0 in the column block corresponding to the information word bits (or code block) to which puncturing is applied may exist according to the basic matrix. These row blocks can be LLR updated even when layered decoding is performed for the first time. Accordingly, when determining the layered decoding scheduling order or pattern, such row blocks may be prioritized to perform decoding.

값을 결정한 다음,

개의 행 블록 중에서 상기 천공을 적용할 정보어 비트들에 대응되는 열 블록 내의 무게가 0인 행 블록들에 대해 레이어드 복호를 모두 수행한 후 (상기 행 블록들에 대해서는 역순서 방향 레이어드 복호를 수행할 수도 있고, 순방향 레이어드 복호를 수행할 수도 있다), 나머지 행 블록들에 대해서 상기 실시예 1), 실시예 2), 실시예 3에서 제시한 방법들 중 적어도 하나를 함께 결합하여 레이어드 디코딩을 적용할 수도 있다. 또한, 상기 레이어드 디코딩은 상기 우선하여 디코딩할 행 블록에 상응하는 레이어에 기반하여 디코딩될 수 있다. 이 때, 레이어는 우선하여 디코딩할 행 블록과 인접한 행 블록들 중 직교성 또는 준직교성을 갖는 행 블록을 포함할 수 있다.In this case, from Equation 30

After determining the value,

After performing layered decoding on all of the row blocks having a weight of 0 in the column block corresponding to the information word bits to which the puncturing is to be applied, (reverse-order layered decoding is performed for the row blocks). Alternatively, forward layered decoding may be performed), and layered decoding may be applied to the remaining row blocks by combining at least one of the methods suggested in the first embodiment, the second embodiment, and the third embodiment. May be. In addition, the layered decoding may be decoded based on a layer corresponding to the row block to be decoded with priority. In this case, the layer may preferentially include a row block to be decoded and a row block having orthogonality or quasi-orthogonality among row blocks adjacent to the row block.

Example 5

In fact, the optimal layered decoding order or pattern may be different from each other according to the number of row blocks actually used for decoding in the parity check matrix. However, in general, when the code rate is low, the performance difference decreases, and when the code rate is high, the performance difference is relatively large. Therefore, the layered decoding order or pattern is optimized for a high code rate using a greedy algorithm. Next, if the order or pattern for a lower code rate is optimized based on the result, a semi-optimized order or pattern can be derived as a simple sequence. In the present invention, although the complexity increases slightly, as a method of maximizing performance according to the transmitted codeword length Er, the layered decoding order or pattern is stored using a sequence having a nested structure (or a nested structure), and then the NSA ( Nested-Sequence Approach) We propose a layered decoding method.

Nested structure decoding that shows stable performance according to TBS or code rate when properly used greed algorithm while considering all conditions 1), 2), 3), and 4) of <Conditions for Determining Layered Decoding Scheduling> You can decide the order or pattern.

As a specific example, the following sequence is defined as a layered decoding order or pattern based on the basic matrix BM1 corresponding to Equation 26:

Pattern 5-1:

[42, 40, 26, 34, 37, 45, 30, 32, 22, 28, 38, 44, 41, 20, 27, 25, 31, 36, 39, 13, 33, 35, 24, 29, 43 , 17, 23, 18, 21, 14, 6, 10, 16, 1, 4, 19, 7, 12, 15, 9, 5, 11, 8, 0, 2, 3]

Similarly, the following sequence is defined as a layered decoding order or pattern based on the basic matrix BM2 corresponding to Equation 27:

Pattern 5-2:

[22, 37, 40, 31, 24, 29, 20, 12, 27, 25, 28, 35, 38, 41, 32, 23, 34, 39, 17, 16, 36, 21, 33, 18, 15 , 9, 14, 30, 11, 19, 6, 7, 8, 26, 10, 13, 1, 4, 5, 0, 2, 3]

However, the decoding order or pattern of the nested structure of the present invention is not limited to the above order or pattern. That is, it is obvious that the embodiment of the present invention can be applied to the decoding order or pattern of the nested structure generated using the greedy algorithm.

Also, the numbers included in the order or pattern may correspond to an index of a row block of a parity check matrix or a row index of a basic matrix.

Hereinafter, methods of using the patterns-1 and 2 will be described in detail.

를 결정한다 (본 발명에서는 수학식 30에 기반하여 결정하는 것으로 설명하지만, 다른 방식으로 결정할 수 있다). 그 다음에 상기 패턴-1 또는 패턴-2의 수열에서

보다 작은 값들을 가지는 수열만 선택한 다음에 선택된 수열을 실제 디코딩에 사용하는 레이어드 디코딩 순서 또는 패턴으로 적용한다. 이와 같은 방식을 편의상 NSA 레이어드 디코딩 방법이라 한다. First, the number of row blocks that are actually used in a given basic matrix or a parity check matrix corresponding to it or affect performance based on Equation 30

(In the present invention, it is described as determining based on Equation 30, but it can be determined in a different way). Then, in the sequence of pattern-1 or pattern-2

After selecting only sequences having smaller values, the selected sequence is applied as a layered decoding order or pattern used for actual decoding. For convenience, this method is referred to as an NSA layered decoding method.

이 된다. 즉, 패리티 검사 행렬에서 총 21개의 행 블록이 실질적으로 LDPC 부호화/복호화 성능에 영향을 준다. 이 때, 상기 패턴-2 수열에서 상기

값 21 보다 작은 숫자들로만 구성된 수열을 선택한다. 즉, 패턴-2 수열에서 유효한 행 블록의 인덱스로만 구성된 수열 (또는 패턴)을 결정할 수 있다. As a specific embodiment, for the case of performing LDPC decoding based on the basic matrix of Equation 27, the input bit (TB+CRC) is 3840 bits (including CRC 16 bits), and the code rate according to the MCS index is less than 2/3. Small, and assume Er = 11072. In the case of 3GPP standard TS 38.212, under this condition, BM2 is determined as a basic matrix for LDPC encoding, and the block size is also determined as Z = 384, and K _punc = 2 is fixed. _{Also, since K b} = 10 in the case of 3840, the number of input bits

Becomes. That is, a total of 21 row blocks in the parity check matrix substantially affect the LDPC encoding/decoding performance. At this time, in the pattern-2 sequence,

Select a sequence consisting only of numbers less than the value 21. That is, in the pattern-2 sequence, a sequence (or pattern) composed of only the indexes of valid row blocks can be determined.

The index of the effective row block in the pattern-2 sequence is as shown below.

[22, 37, 40, 31, 24, 29, 20 , 12 , 27, 25, 28, 35, 38, 41, 32, 23, 34, 39, 17 , 16 , 36, 21, 33, 18 , 15 , 9 , 14 , 30, 11 , 19 , 6 , 7 , 8 , 26, 10 , 13 , 1 , 4 , 5 , 0 , 2 , 3 ]

Accordingly, the order or pattern determined based on the index of the effective row block in the pattern-2 sequence is as follows.

[20, 12, 17, 16, 18, 15, 9, 14, 11, 19, 6, 7, 8, 10, 13, 1, 4, 5, 0, 2, 3]

The selected sequence [20, 12, 17, 16, 18, 15, 9, 14, 11, 19, 6, 7, 8, 10, 13, 1, 4, 5, 0, 2, 3] in the LDPC decoder It means a layered decoding pattern to be applied, which means performing one cycle of repetitive decoding by sequentially performing layered decoding starting with the layered decoding for the 20th row block and then up to the 3rd row block.

번째 행 블록에 대응되는 패리티 비트의 일부는 LLR = 0 값에 대응되기 때문에 상기 NSA 레이어드 디코딩 방식을 위해

보다 작은 숫자들로만 이루어진 수열을 선택하여 해당 레이어드 디코딩을 수행하되, 상기

번째 행 블록은 사전에 정의된 순서에 레이어드 디코딩을 수행할 수도 있다. 예를 들어,

번째 행 블록의 경우에는 항상 i 번째로 레이어드 디코딩을 적용한다고 가정할 경우에는

보다 작은 숫자들로만 이루어진 수열로 구성된 순서 또는 패턴에서 (i-1) 번째 수와 i번째 수 사이에

값이 적용될 수 있다. The NSA layered decoding method can be modified in various forms as well as the above embodiment. For example, in Equation 30, if the Er value is not a multiple of Z, the last

Since some of the parity bits corresponding to the th row block correspond to the LLR = 0 value, for the NSA layered decoding method

Selecting a sequence consisting of only smaller numbers and performing the corresponding layered decoding,

The th row block may perform layered decoding in a predefined order. E.g,

In the case of the first row block, assuming that the i th layered decoding is always applied,

Between the (i-1)th number and the ith number in a sequence or pattern of sequences of only smaller numbers

Values can be applied.

번째 행 블록을 항상 0 번째 레이어드 디코딩 이후 1 번째에 적용된다고 시스템에서 약속되어 있는 경우를 가정한다. 상술한 실시예와 동일하게 TBS = 3840 비트이고 (CRC 16 비트 포함), MCS index에 따른 부호율이 2/3 보다 작으며, Er = 11072이라 가정한 경우에 [20, 12, 17, 16, 18, 15, 9, 14, 11, 19, 6, 7, 8, 10, 13, 1, 4, 5, 0, 2, 3]을 레이어드 디코딩 순서 또는 패턴으로 적용하는 것이 아니라

번째 행 블록인 행 블록 20을 1 번째에 적용하기 위해 [12, 20, 17, 16, 18, 15, 9, 14, 11, 19, 6, 7, 8, 10, 13, 1, 4, 5, 0, 2, 3]과 같이 20의 위치가 바뀔 수도 있다. As a specific example, if the last

Assume that the system promises that the first row block is always applied to the first after the 0th layered decoding. In the same manner as in the above-described embodiment, when TBS = 3840 bits (including CRC 16 bits), the code rate according to the MCS index is less than 2/3, and Er = 11072, [ 20 , 12, 17, 16, 18, 15, 9, 14, 11, 19, 6, 7, 8, 10, 13, 1, 4, 5, 0, 2, 3] are not applied as a layered decoding order or pattern.

[12, 20 , 17, 16, 18, 15, 9, 14, 11, 19, 6, 7, 8, 10, 13, 1, 4, 5 , 0, 2, 3], the position of 20 may be changed.

The method described above is only an example, and there may be an NSA layered decoding method appropriately combined with other techniques based on a sequence of various nested structures.

Example 6

In the above embodiment, it is assumed that some of the information word bits (or code blocks) are always punctured. However, if the information word bit puncturing may not be applied depending on the situation in the system, the order or pattern for the proposed layered decoding scheduling may not be optimal.

For example, if puncturing is not applied, the LLR value is updated no matter which layer is initially decoded, so reverse-order layered decoding is performed in consideration of condition 2) of <Conditions for determining layered decoding scheduling>. And, if the perforation is applied, various methods proposed in the above embodiment and the like can be applied.

In conclusion, performance may be improved by applying layered decoding based on the first pattern when punctured, and the second pattern when not punctured according to whether the information word bit or the code block is partially punctured.

Example 7

If implementation complexity is not a problem, a layered decoding method may be applied using a plurality of sequences or patterns optimized based on a basic matrix or code rate or modulation order of each LDPC code.

For example, in the case of a system using an LDPC basic matrix corresponding to the basic matrix BM2 corresponding to Equation 27 and using some of the modulation schemes such as QPSK, 16QAM, 64QAM, 256QAM, and 1024QAM, each modulation used LDPC decoding may be performed by applying the following sub-optimal layered decoding order or pattern (or sequence) according to the method:

Pattern 7-1: sequence or pattern for QPSK or 4QAM

[37, 40, 29, 27, 25, 22, 31, 28, 36, 33, 32, 34, 24, 41, 38, 21, 20, 35, 18, 12, 23, 39, 17, 30, 16 , 15, 9, 14, 7, 11, 19, 6, 8, 26, 13, 10, 1, 4, 5, 0, 2, 3]

Pattern 7-2: sequence or pattern for 16-QAM

[37, 40, 29, 27, 25, 22, 31, 34, 28, 33, 36, 24, 21, 32, 39, 20, 41, 38, 35, 18, 12, 23, 17, 16, 30 , 15, 9, 14, 6, 11, 7, 19, 10, 8, 26, 1, 4, 5, 13, 0, 2, 3]

Pattern 7-3: sequence or pattern for 64-QAM

[37, 40, 33, 29, 25, 27, 32, 23, 22, 36, 31, 28, 24, 26, 34, 20, 18, 21, 39, 12, 41, 38, 35, 17, 30 , 16, 14, 11, 15, 6, 7, 9, 19, 10, 8, 13, 1, 4, 5, 0, 2, 3]

Pattern 7-4: sequence or pattern for 256-QAM

[40, 37, 33, 32, 30, 29, 28, 41, 27, 26, 25, 39, 23, 22, 24, 38, 36, 21, 20, 18, 12, 35, 31, 17, 15 , 9, 14, 34, 16, 6, 11, 7, 19, 10, 8, 1, 4, 5, 13, 0, 2, 3]

Pattern 7-5: sequence or pattern for 1024-QAM

[41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 18, 15, 12 , 17, 11, 9, 16, 14, 6, 7, 1, 19, 10, 13, 4, 8, 5, 0, 2, 3]

The transmitter can transmit data bits according to each modulation scheme or order. The receiver may appropriately demodulate the received signal according to each modulation method or order, determine an LLR value for each received data bit, and then perform layered decoding based on the LLR value and the patterns.

Meanwhile, for convenience of description, the patterns or 7-1 to 7-5 have been described as being defined for a specific modulation method, but embodiments of the present invention are not limited thereto. That is, it is obvious that the patterns or procedures 7-1 to 7-5 can be applied to each modulation method or order according to the settings of the transmitter or the receiver.

Meanwhile, as described above, the embodiment of the present invention can be applied even when decoding is performed based on a layer composed of one or more row blocks. For example, in the first or second embodiment, when a row block to be decoded with priority is determined among row blocks of order 1, decoding may be performed on a layer corresponding to the row block to be decoded with priority. Specifically, if a row block adjacent to the determined row block has a characteristic that is orthogonal to or quasi-orthogonal to the row block, decoding may be performed based on a layer including the row blocks. In addition, it is obvious that layered decoding can be performed by configuring one layer of row blocks having orthogonality or quasi-orthogonality even when sequential decoding is performed later or when reverse order decoding is performed.

In addition, it is apparent that the layered decoding composed of the at least two or more row blocks may be performed in the above-described embodiments 3 to 6 as well. In addition, when at least one layer is composed of two or more row blocks, the layered decoding order or patterns may be defined as a sequence shorter than the total number of row blocks. You may need additional information about whether the blocks have been combined.

Meanwhile, the above-described layered decoding may be implemented in various ways such as block parallel decoding and row-block parallel decoding (or row parallel decoding).

Here, the block parallel decoding is a layered decoding method typically performed on the basis of one or a plurality of blocks in the parity check matrix, that is, a cyclic permutation matrix having a size of Z*Z. In addition, row block parallel decoding (or row parallel decoding) is a layered decoding method typically performed on the basis of one row block.

The row block parallel decoding method can be viewed as an extension of the block parallel decoding method in a broad sense because decoding is performed on all blocks (cyclic permutation matrices) included in a given row block or a layer composed of a plurality of row blocks. Further, compared to the block parallel decoding method based on one block (cyclic permutation matrix), implementation complexity may increase, but higher decoding information throughput may be supported.

Block parallel decoding may be performed based on one block (cyclic permutation matrix), but may generally be performed based on a plurality of blocks. In addition, it may be performed on a standard smaller than one block. In this case, block parallel decoding may be performed based on a factor of the block size Z in general. In performing block parallel decoding, when a layered decoder is implemented based on a plurality of blocks, implementation complexity increases, but decoding information throughput also increases.

The operation of the receiver according to the embodiment of the present invention is summarized as follows. That is, in a decoding method of a receiver in a communication system, receiving a signal corresponding to an input bit transmitted from a transmitter, determining the number of input bits based on the signal, and a code based on the number of input bits Checking the size of the block; And performing layered decoding based on a parity check matrix corresponding to the size of the code block, wherein the layered decoding is performed on at least one of the row blocks of degree 1 in the partial matrix corresponding to the column block to be punctured. It is characterized in that it is decoded in preference to a corresponding layer. In addition, the layered decoding may be performed by combining various embodiments of the present invention described above.

In addition, the method of the receiver according to an embodiment of the present invention is also, the decoding method of the receiver of the present invention for solving the above problem includes the steps of receiving a signal corresponding to an input bit transmitted from a transmitter, Checking the number of input bits based on the number of input bits, checking the size of the code block based on the number of input bits; And performing layered decoding based on a parity check matrix corresponding to the size of the code block, wherein the layered decoding is performed based on the following decoding order or pattern.

Pattern 5-1:

[42, 40, 26, 34, 37, 45, 30, 32, 22, 28, 38, 44, 41, 20, 27, 25, 31, 36, 39, 13, 33, 35, 24, 29, 43 , 17, 23, 18, 21, 14, 6, 10, 16, 1, 4, 19, 7, 12, 15, 9, 5, 11, 8, 0, 2, 3]

Pattern 5-2:

[22, 37, 40, 31, 24, 29, 20, 12, 27, 25, 28, 35, 38, 41, 32, 23, 34, 39, 17, 16, 36, 21, 33, 18, 15 , 9, 14, 30, 11, 19, 6, 7, 8, 26, 10, 13, 1, 4, 5, 0, 2, 3].

In addition, the decoding method of the receiver of the present invention for solving the above problem includes receiving a signal corresponding to an input bit transmitted from a transmitter, checking the number of input bits based on the signal, and Checking the size of the code block based on the number, and performing layered decoding based on the basic matrix of the LDPC code corresponding to the number of input bits and the code rate or the parity check matrix corresponding to the size of the code block Including, the layered decoding is characterized in that it is performed based on at least one of the following decoding order or pattern in consideration of a modulation order or a code rate.

Pattern 7-1: sequence or pattern for QPSK or 4QAM

[37, 40, 29, 27, 25, 22, 31, 28, 36, 33, 32, 34, 24, 41, 38, 21, 20, 35, 18, 12, 23, 39, 17, 30, 16 , 15, 9, 14, 7, 11, 19, 6, 8, 26, 13, 10, 1, 4, 5, 0, 2, 3]

Pattern 7-2: sequence or pattern for 16-QAM

[37, 40, 29, 27, 25, 22, 31, 34, 28, 33, 36, 24, 21, 32, 39, 20, 41, 38, 35, 18, 12, 23, 17, 16, 30 , 15, 9, 14, 6, 11, 7, 19, 10, 8, 26, 1, 4, 5, 13, 0, 2, 3]

Pattern 7-3: sequence or pattern for 64-QAM

[37, 40, 33, 29, 25, 27, 32, 23, 22, 36, 31, 28, 24, 26, 34, 20, 18, 21, 39, 12, 41, 38, 35, 17, 30 , 16, 14, 11, 15, 6, 7, 9, 19, 10, 8, 13, 1, 4, 5, 0, 2, 3]

Pattern 7-4: sequence or pattern for 256-QAM

[40, 37, 33, 32, 30, 29, 28, 41, 27, 26, 25, 39, 23, 22, 24, 38, 36, 21, 20, 18, 12, 35, 31, 17, 15 , 9, 14, 34, 16, 6, 11, 7, 19, 10, 8, 1, 4, 5, 13, 0, 2, 3]

Pattern 7-5: sequence or pattern for 1024-QAM

[41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 18, 15, 12 , 17, 11, 9, 16, 14, 6, 7, 1, 19, 10, 13, 4, 8, 5, 0, 2, 3]

The modulation order may be determined by the MCS index. Also, the code rate can be determined by the MCS index. Alternatively, the code rate may be determined based on an effective code rate value, and the effective code rate value may be determined based on the number of bits Er actually transmitted through an allocated resource.

Meanwhile, as described above, the layered decoding order or pattern is not limited to a specific modulation order.

Meanwhile, in the present invention, an order or pattern for determining a layered decoding order based on each of the basic matrix (or parity check matrix) or code rate (or the number of used row blocks) or modulation order of the LDPC code may be determined and used. , The order or pattern may be determined based on two or more conditions. In addition, embodiments of the present invention may be applied independently of each other or combined with each other in a hybrid manner, and all different decoding orders or patterns are applied according to each basic matrix, modulation order, and code rate (or the number of used row blocks). In this case, performance can be optimized, but complexity can increase, so the same pattern can be applied in some cases.

For example, in the layered decoding pattern for the modulation order, it may be set to use any one pattern or order of a predetermined pattern or order for each modulation order when it is less than or equal to a predetermined modulation order.

On the other hand, in the drawings for explaining the method of the present invention, the order of description does not necessarily correspond to the order of execution, and the relationship between precedence and after may be changed or may be executed in parallel.

Alternatively, in the drawings for explaining the method of the present invention, some components may be omitted and only some components may be included within a range that does not impair the essence of the present invention.

In addition, the method of the present invention may be implemented by combining some or all of the contents included in each embodiment within a range not impairing the essence of the present invention.

Although the present invention has been described as a preferred embodiment, various changes and modifications may be suggested to those skilled in the art. Such changes and modifications are intended to be included in the appended claims. In addition, for convenience of description in the operation flow chart of the present invention, operations represented by different blocks may be implemented separately in a plurality of processors in an actual system, but it is obvious that they may be integrated and implemented as one processor.

Claims (17)

In the decoding method of a receiver in a communication system,
Receiving a signal corresponding to an input bit transmitted from a transmitter;
Checking the number of input bits based on the signal;
Checking the size of the code block based on the number of input bits; And
And performing layered decoding based on a parity check matrix corresponding to the size of the code block,
The layered decoding is characterized in that in the partial matrix corresponding to a column block corresponding to a part of the code block to be punctured, the layer corresponding to at least one of the row blocks of degree 1 is decoded with priority. The method of claim 1,
The step of performing the layered decoding,
Performing decoding in preference to a layer corresponding to one of the row blocks of the order 1;
And sequentially decoding a layer corresponding to the remaining row blocks. The method of claim 1,
The step of performing the layered decoding,
Checking the number of valid row blocks in the parity check matrix;
Performing decoding in preference to a layer corresponding to one of the row blocks of the order 1;
And performing decoding on a layer corresponding to the remaining row blocks in reverse order based on the number of valid row blocks. The method of claim 1,
And at least one of the row blocks having the order 1 is determined based on a code rate for the decoding and a reference code rate. The method of claim 1,
The layered decoding,
When there is a row block having a degree of 0 in the partial matrix corresponding to the column block to be punctured, a layer corresponding to the row block having the order of 0 is decoded with the highest priority. The method of claim 1,
The layered decoding is characterized in that it is performed based on a predetermined decoding order based on a basic matrix of the parity check matrix,
The method of claim 1, wherein the decoding order includes the following order.
[22, 37, 40, 31, 24, 29, 20, 12, 27, 25, 28, 35, 38, 41, 32, 23, 34, 39, 17, 16, 36, 21, 33, 18, 15 , 9, 14, 30, 11, 19, 6, 7, 8, 26, 10, 13, 1, 4, 5, 0, 2, 3]. The method of claim 6,
The layered decoding,
A method characterized in that the method is performed based on a decoding order based on an index of a valid row block among indices of a row block included in a predetermined decoding order. In a receiver for decoding in a communication system,
A transmission/reception unit; And
Receive a signal corresponding to the input bit transmitted from the transmitter,
Check the number of input bits based on the signal,
Check the size of the code block based on the number of input bits,
And a control unit for performing layered decoding based on a parity check matrix corresponding to the size of the code block,
Wherein the layered decoding is decoded in preference to a layer corresponding to at least one of a row block having a degree 1 in a partial matrix corresponding to a column block corresponding to a part of a code block to be punctured. The method of claim 8,
The control unit,
Prioritizing decoding is performed on a layer corresponding to one of the row blocks of the order 1,
A receiver, characterized in that for sequentially performing decoding on a layer corresponding to the remaining row blocks. The method of claim 8,
The control unit,
Check the number of valid row blocks in the parity check matrix,
Decoding a layer corresponding to one of the row blocks of the order 1,
And decoding a layer corresponding to the remaining row blocks in reverse order based on the number of valid row blocks. The method of claim 8,
And at least one of the row blocks having the order 1 is determined based on a code rate for decoding and a reference code rate. The method of claim 8,
The layered decoding,
And when there is a row block having a degree of 0 in the partial matrix corresponding to the column block to be punctured, a layer corresponding to the row block having the order of 0 is decoded with the highest priority. The method of claim 8,
The layered decoding is characterized in that it is performed based on a predetermined decoding order based on a basic matrix of the parity check matrix,
The decoding order comprises the following order.
[22, 37, 40, 31, 24, 29, 20, 12, 27, 25, 28, 35, 38, 41, 32, 23, 34, 39, 17, 16, 36, 21, 33, 18, 15 , 9, 14, 30, 11, 19, 6, 7, 8, 26, 10, 13, 1, 4, 5, 0, 2, 3]. The method of claim 13,
The layered decoding,
A receiver, characterized in that it is performed based on a decoding order based on an index of a valid row block among indices of a row block included in a predetermined decoding order. In the decoding method of a receiver in a communication system,
Receiving a signal corresponding to an input bit transmitted from a receiver;
Checking the number of input bits based on the signal;
Checking the size of the code block based on the number of input bits; And
And performing layered decoding based on a parity check matrix corresponding to the size of the code block,
The layered decoding method, characterized in that it is performed based on the following decoding order.
[22, 37, 40, 31, 24, 29, 20, 12, 27, 25, 28, 35, 38, 41, 32, 23, 34, 39, 17, 16, 36, 21, 33, 18, 15 , 9, 14, 30, 11, 19, 6, 7, 8, 26, 10, 13, 1, 4, 5, 0, 2, 3]. In a receiver in a communication system,
A transmission/reception unit; And
Receive a signal corresponding to the input bit transmitted from the transmitter,
Check the number of input bits based on the signal,
Check the size of the code block based on the number of input bits,
And a control unit for performing layered decoding based on a parity check matrix corresponding to the size of the code block,
The layered decoding is performed based on the following decoding order.
[22, 37, 40, 31, 24, 29, 20, 12, 27, 25, 28, 35, 38, 41, 32, 23, 34, 39, 17, 16, 36, 21, 33, 18, 15 , 9, 14, 30, 11, 19, 6, 7, 8, 26, 10, 13, 1, 4, 5, 0, 2, 3]. In a receiver in a communication system,
A transmission/reception unit; And
Receive a signal corresponding to the input bit transmitted from the transmitter,
Check the number of input bits based on the signal,
Check the size of the code block based on the number of input bits,
And a control unit for performing layered decoding based on a parity check matrix corresponding to the size of the code block,
The layered decoding is performed based on a value determined by demodulating the signal,
The layered decoding is performed based on the following decoding order.
[37, 40, 29, 27, 25, 22, 31, 28, 36, 33, 32, 34, 24, 41, 38, 21, 20, 35, 18, 12, 23, 39, 17, 30, 16 , 15, 9, 14, 7, 11, 19, 6, 8, 26, 13, 10, 1, 4, 5, 0, 2, 3]

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